From: Jelly Jia <Jelly.Jia@cixtech.com>
To: vkoul@kernel.org, robh@kernel.org, krzk+dt@kernel.org,
conor+dt@kernel.org, robin.murphy@arm.com
Cc: devicetree@vger.kernel.org, Frank.Li@kernel.org,
cix-kernel-upstream@cixtech.com, dmaengine@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, Jelly.Jia@cixtech.com
Subject: [PATCH v4 5/5] arm64: dts: cix: Describe the Sky1 FCH DMA-350 integration
Date: Fri, 23 Oct 2026 17:30:17 +0800 [thread overview]
Message-ID: <20261023093017.3248454-6-Jelly.Jia@cixtech.com> (raw)
In-Reply-To: <20261023093017.3248454-1-Jelly.Jia@cixtech.com>
The FCH DMA-350 master accesses the CPU physical peripheral window at
0x040b0000 through DMA address 0x040a0000. Describe this fixed translation
and the reachable DRAM windows with dma-ranges on the parent simple-bus.
The CPU register address view remains unchanged.
Keep the existing controller register region and eight interrupt
specifiers, and add its SCMI bus clock.
Signed-off-by: Jelly Jia <Jelly.Jia@cixtech.com>
---
arch/arm64/boot/dts/cix/sky1.dtsi | 36 ++++++++++++++++++++-----------
1 file changed, 24 insertions(+), 12 deletions(-)
diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sky1.dtsi
index 0a820f45feb9..cd498ee7e9a7 100644
--- a/arch/arm64/boot/dts/cix/sky1.dtsi
+++ b/arch/arm64/boot/dts/cix/sky1.dtsi
@@ -518,18 +518,30 @@ iomuxc: pinctrl@4170000 {
reg = <0x0 0x04170000 0x0 0x1000>;
};
- fch_dmac: dma-controller@4190000 {
- compatible = "arm,dma-350";
- reg = <0x0 0x4190000 0x0 0x10000>;
- interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>;
- #dma-cells = <1>;
+ fch-dma-bus {
+ compatible = "simple-bus";
+ ranges;
+ #address-cells = <2>;
+ dma-ranges = <0x0 0x040a0000 0x0 0x040b0000 0x0 0x00040000>,
+ <0x0 0x80000000 0x0 0x80000000 0x8 0x00000000>,
+ <0x80 0x00000000 0x80 0x00000000 0x80 0x00000000>;
+ #size-cells = <2>;
+
+ fch_dmac: dma-controller@4190000 {
+ compatible = "arm,dma-350";
+ reg = <0x0 0x04190000 0x0 0x10000>;
+ clocks = <&scmi_clk CLK_TREE_FCH_DMA_ACLK>;
+ #dma-cells = <1>;
+ interrupts =
+ <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>;
+ };
};
mbox_ap2se: mailbox@5060000 {
--
2.54.0
prev parent reply other threads:[~2026-10-23 9:30 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-23 9:30 [PATCH v4 0/5] dmaengine: arm-dma350: Add slave support and Sky1 integration Jelly Jia
2026-10-23 9:30 ` [PATCH v4 1/5] dmaengine: arm-dma350: Fix source trigger bit Jelly Jia
2026-10-23 9:30 ` [PATCH v4 2/5] dmaengine: arm-dma350: Add slave and cyclic transfer support Jelly Jia
2026-10-23 9:30 ` [PATCH v4 3/5] dt-bindings: dma: arm,dma-350: Document optional clocks and resets Jelly Jia
2026-10-23 9:30 ` [PATCH v4 4/5] dmaengine: arm-dma350: Support integration " Jelly Jia
2026-10-23 9:30 ` Jelly Jia [this message]
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