Re: [PATCH v2 12/24] dt-bindings: PCI: Add ZTE ZX279128S host controller

[Rob Herring <robh@kernel.org>]

On Wed, Oct 14, 2026 at 08:20:52AM +0100, Navid Ghahremani wrote:
> Add Device Tree binding for the DesignWare PCIe host controller on the
> ZTE ZX279128S SoC, using standard clocks, resets, and phys properties.
> 
> Signed-off-by: Navid Ghahremani <ghahramani.navid@gmail.com>
> ---
>  .../bindings/pci/zte,zx279128s-pcie.yaml      | 121 ++++++++++++++++++
>  1 file changed, 121 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pci/zte,zx279128s-pcie.yaml
> 
> diff --git a/Documentation/devicetree/bindings/pci/zte,zx279128s-pcie.yaml b/Documentation/devicetree/bindings/pci/zte,zx279128s-pcie.yaml
> new file mode 100644
> index 0000000000..dc0214511f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/zte,zx279128s-pcie.yaml
> @@ -0,0 +1,121 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/zte,zx279128s-pcie.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: ZTE zx279128s PCIe host controller
> +
> +maintainers:
> +  - Navid Ghahremani <ghahramani.navid@gmail.com>
> +
> +description:
> +  The ZTE zx279128s has two PCIe host controllers based on the Synopsys
> +  DesignWare PCIe IP, each with one lane. Their clocks, resets and PHYs are
> +  controlled through the SoC's Top CRM blocks.
> +
> +allOf:
> +  - $ref: /schemas/pci/pci-host-bridge.yaml#
> +  - $ref: /schemas/pci/snps,dw-pcie-common.yaml#
> +
> +properties:
> +  compatible:
> +    const: zte,zx279128s-pcie
> +
> +  reg:
> +    items:
> +      - description: Data Bus Interface (DBI) registers
> +      - description: Controller wrapper registers
> +      - description: PCIe configuration space region
> +
> +  reg-names:
> +    items:
> +      - const: dbi
> +      - const: ctrl
> +      - const: config
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  clocks:
> +    items:
> +      - description: PCIe controller clock
> +
> +  clock-names:
> +    items:
> +      - const: pcie

Drop. No point in -names for 1 entry.

> +
> +  resets:
> +    items:
> +      - description: PCIe controller reset
> +
> +  reset-names:
> +    items:
> +      - const: core

Drop

> +
> +  phys:
> +    maxItems: 1
> +
> +  phy-names:
> +    items:
> +      - const: pcie

Drop

> +
> +  reset-gpios:
> +    maxItems: 1
> +    description: Optional board GPIO reset line for downstream endpoints.

Is this for PERST#? If so, make that clear.

> +
> +  enable-gpios:
> +    maxItems: 1
> +    description: Optional second board GPIO enable line driven together with reset-gpios.
> +
> +required:
> +  - reg
> +  - reg-names
> +  - interrupts
> +  - '#interrupt-cells'
> +  - interrupt-map
> +  - interrupt-map-mask
> +  - clocks
> +  - clock-names
> +  - resets
> +  - reset-names
> +  - phys
> +  - phy-names
> +
> +unevaluatedProperties: false