[PATCH v1 1/6] arm64: cpufeature: Remove Neoverse-V3/AE from the BBML3 allow list

[Ryan Roberts <ryan.roberts@arm.com>]

Neoverse-V3 and Neoverse-V3AE erratum 3053180 can cause a load or store
to livelock when mapping size changes without break-before-make or when
contiguous hints are programmed inconsistently.

The erratum was previously reported as fixed in r0p2. On that basis,
commit 5aa4b625762e ("arm64: Add BBM Level 2 cpu feature") allowed
Neoverse-V3 from r0p2, and commit 8fca3852e33d ("arm64: cpufeature: add
Neoverse-V3AE to BBML2 allow list") did the same for Neoverse-V3AE.

The updated SDENs, MP168 v11 for Neoverse-V3 and MP172 v12 for
Neoverse-V3AE, dated 9 June 2026, list r0p0, r0p1 and r0p2 as affected
and the erratum as open. There is no fixed revision on which to base
either allow-list entry.

Remove both entries so these CPUs observe break-before-make, and record
the workaround in the silicon errata registry.

Cc: stable@vger.kernel.org
Link: https://support.arm.com/documentation/109231/11-0/?lang=en
Link: https://support.arm.com/documentation/109704/12-0/?lang=en
Signed-off-by: Ryan Roberts <ryan.roberts@arm.com>
---
 Documentation/arch/arm64/silicon-errata.rst | 4 ++++
 arch/arm64/kernel/cpufeature.c              | 2 --
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst
index afe109afe692..9ad965d3e1ea 100644
--- a/Documentation/arch/arm64/silicon-errata.rst
+++ b/Documentation/arch/arm64/silicon-errata.rst
@@ -243,10 +243,14 @@ stable kernels.
 +----------------+-----------------+-----------------+-----------------------------+
 | ARM            | Neoverse-V2     | #4193787        | ARM64_ERRATUM_4118414       |
 +----------------+-----------------+-----------------+-----------------------------+
+| ARM            | Neoverse-V3     | #3053180        | N/A                         |
++----------------+-----------------+-----------------+-----------------------------+
 | ARM            | Neoverse-V3     | #3312417        | ARM64_ERRATUM_3194386       |
 +----------------+-----------------+-----------------+-----------------------------+
 | ARM            | Neoverse-V3     | #4193784        | ARM64_ERRATUM_4118414       |
 +----------------+-----------------+-----------------+-----------------------------+
+| ARM            | Neoverse-V3AE   | #3053180        | N/A                         |
++----------------+-----------------+-----------------+-----------------------------+
 | ARM            | Neoverse-V3AE   | #3312417        | ARM64_ERRATUM_3194386       |
 +----------------+-----------------+-----------------+-----------------------------+
 | ARM            | Neoverse-V3AE   | #4193784        | ARM64_ERRATUM_4118414       |
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 34c5c03c0c9b..b15619690f42 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -2012,8 +2012,6 @@ bool cpu_supports_bbml3(void)
 	/* CPUs that support BBML3 but dont advertise through ID_AA64MMFR2_EL1 */
 	static const struct midr_range supports_bbml3_list[] = {
 		MIDR_REV_RANGE(MIDR_CORTEX_X4, 0, 3, 0xf),
-		MIDR_REV_RANGE(MIDR_NEOVERSE_V3, 0, 2, 0xf),
-		MIDR_REV_RANGE(MIDR_NEOVERSE_V3AE, 0, 2, 0xf),
 		MIDR_ALL_VERSIONS(MIDR_NVIDIA_OLYMPUS),
 		MIDR_ALL_VERSIONS(MIDR_NVIDIA_RIGEL),
 		MIDR_ALL_VERSIONS(MIDR_AMPERE1),
-- 
2.43.0