From: Ryan Roberts <ryan.roberts@arm.com>
To: Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Linu Cherian <linu.cherian@arm.com>
Cc: Ryan Roberts <ryan.roberts@arm.com>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: [PATCH v1 6/6] arm64: cpufeature: Enable BBML3 on Cortex-A320, A520 and A720
Date: Fri, 13 Nov 2026 14:50:20 +0000 [thread overview]
Message-ID: <20261113145022.2592454-7-ryan.roberts@arm.com> (raw)
In-Reply-To: <20261113145022.2592454-1-ryan.roberts@arm.com>
Cortex-A320, Cortex-A520 and Cortex-A720 advertise BBML2 and are known
not to raise conflict aborts for mapping-granularity changes. They can
therefore use the BBML3 semantics, but their MIDRs are missing from the
allow list.
Commit a7ac60414475 ("arm64: cpufeature: Extend bbml2_noabort support
list") named A520(AE) and A720(AE), but added only the AE MIDRs. The
non-AE CPUs have distinct MIDRs and need their own entries. Cortex-A320
can now be identified using its new MIDR definition.
Add all revisions of these three CPUs to the allow list. The reviewed
SDENs identify no BBML3 exclusion erratum for them.
Cortex-A510 remains excluded because it can raise conflict aborts.
Link: https://support.arm.com/documentation/SDEN-2877630/0000?lang=en&rev=0000-06
Link: https://support.arm.com/documentation/SDEN-2444153/0000?lang=en&rev=0000-12
Link: https://support.arm.com/documentation/SDEN-2439421/0000?lang=en&rev=0000-17
Signed-off-by: Ryan Roberts <ryan.roberts@arm.com>
---
arch/arm64/kernel/cpufeature.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index aa6f4c8c1052..de2d2bd686d8 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -2015,11 +2015,14 @@ bool cpu_supports_bbml3(void)
MIDR_ALL_VERSIONS(MIDR_NVIDIA_RIGEL),
MIDR_ALL_VERSIONS(MIDR_AMPERE1),
MIDR_ALL_VERSIONS(MIDR_AMPERE1A),
+ MIDR_ALL_VERSIONS(MIDR_CORTEX_A320),
+ MIDR_ALL_VERSIONS(MIDR_CORTEX_A520),
MIDR_ALL_VERSIONS(MIDR_CORTEX_A520AE),
#ifndef CONFIG_ARM64_ERRATUM_3696244
MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
#endif
MIDR_ALL_VERSIONS(MIDR_CORTEX_A715),
+ MIDR_ALL_VERSIONS(MIDR_CORTEX_A720),
MIDR_ALL_VERSIONS(MIDR_CORTEX_A720AE),
MIDR_ALL_VERSIONS(MIDR_CORTEX_A725),
#ifndef CONFIG_ARM64_ERRATUM_3696244
--
2.43.0
prev parent reply other threads:[~2026-11-13 14:50 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-13 14:50 [PATCH v1 0/6] arm64: BBML3 errata workarounds and cleanup Ryan Roberts
2026-11-13 14:50 ` [PATCH v1 1/6] arm64: cpufeature: Remove Neoverse-V3/AE from the BBML3 allow list Ryan Roberts
2026-11-13 14:50 ` [PATCH v1 2/6] arm64: cpufeature: Remove Cortex-X4 " Ryan Roberts
2026-11-13 14:50 ` [PATCH v1 3/6] arm64: cputype: Add Cortex-A320 definitions Ryan Roberts
2026-11-13 14:50 ` [PATCH v1 4/6] arm64: cputype: Add C2-Ultra definitions Ryan Roberts
2026-11-13 14:50 ` [PATCH v1 5/6] arm64: cpufeature: Track BBML3 exclusions with erratum options Ryan Roberts
2026-11-13 14:50 ` Ryan Roberts [this message]
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