From: Ryan Roberts <ryan.roberts@arm.com>
To: Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Linu Cherian <linu.cherian@arm.com>
Cc: Ryan Roberts <ryan.roberts@arm.com>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: [PATCH v1 3/6] arm64: cputype: Add Cortex-A320 definitions
Date: Fri, 13 Nov 2026 14:50:17 +0000 [thread overview]
Message-ID: <20261113145022.2592454-4-ryan.roberts@arm.com> (raw)
In-Reply-To: <20261113145022.2592454-1-ryan.roberts@arm.com>
Add the Cortex-A320 part number and MIDR definition. The MIDR_EL1
description in the Cortex-A320 Technical Reference Manual specifies
implementer 0x41 and part number 0xd8f.
These definitions will be used to identify Cortex-A320 in the BBML3
allow list.
Link: https://support.arm.com/documentation/109551/0002?lang=en&rev=0002-04
Signed-off-by: Ryan Roberts <ryan.roberts@arm.com>
---
arch/arm64/include/asm/cputype.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index 6002d1d5f55f..abff1ba1c305 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -103,6 +103,7 @@
#define ARM_CPU_PART_C1_NANO 0xD8A
#define ARM_CPU_PART_C1_PRO 0xD8B
#define ARM_CPU_PART_C1_PREMIUM 0xD90
+#define ARM_CPU_PART_CORTEX_A320 0xD8F
#define APM_CPU_PART_XGENE 0x000
#define APM_CPU_VAR_POTENZA 0x00
@@ -200,6 +201,7 @@
#define MIDR_C1_NANO MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_NANO)
#define MIDR_C1_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_PRO)
#define MIDR_C1_PREMIUM MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_PREMIUM)
+#define MIDR_CORTEX_A320 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A320)
#define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)
--
2.43.0
next prev parent reply other threads:[~2026-11-13 14:50 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-13 14:50 [PATCH v1 0/6] arm64: BBML3 errata workarounds and cleanup Ryan Roberts
2026-11-13 14:50 ` [PATCH v1 1/6] arm64: cpufeature: Remove Neoverse-V3/AE from the BBML3 allow list Ryan Roberts
2026-11-13 14:50 ` [PATCH v1 2/6] arm64: cpufeature: Remove Cortex-X4 " Ryan Roberts
2026-11-13 14:50 ` Ryan Roberts [this message]
2026-11-13 14:50 ` [PATCH v1 4/6] arm64: cputype: Add C2-Ultra definitions Ryan Roberts
2026-11-13 14:50 ` [PATCH v1 5/6] arm64: cpufeature: Track BBML3 exclusions with erratum options Ryan Roberts
2026-11-13 14:50 ` [PATCH v1 6/6] arm64: cpufeature: Enable BBML3 on Cortex-A320, A520 and A720 Ryan Roberts
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