* [PATCH 1/1] arm64: dts: imx8mp: Add coresight trace components
@ 2023-05-05 19:51 Frank Li
2023-06-09 8:20 ` Alexander Stein
2023-07-04 15:20 ` Suzuki K Poulose
0 siblings, 2 replies; 5+ messages in thread
From: Frank Li @ 2023-05-05 19:51 UTC (permalink / raw)
To: imx, Rob Herring, Krzysztof Kozlowski, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
open list
Cc: coresight
Add coresight trace components (ETM, ETF, ETB and Funnel).
┌───────┐ ┌───────┐ ┌───────┐
│ CPU0 ├─►│ ETM0 ├─►│ │
└───────┘ └───────┘ │ │
│ │
┌───────┐ ┌───────┐ │ ATP │
│ CPU1 ├─►│ ETM1 ├─►│ │
└───────┘ └───────┘ │ │
│ FUNNEL│
┌───────┐ ┌───────┐ │ │
│ CPU2 ├─►│ ETM2 ├─►│ │
└───────┘ └───────┘ │ │ ┌─────┐ ┌─────┐
│ │ │ │ │ │
┌───────┐ ┌───────┐ │ │ │ M7 │ │ DSP │
│ CPU3 ├─►│ ETM3 ├─►│ │ │ │ │ │
└───────┘ └───────┘ └───┬───┘ └──┬──┘ └──┬──┘ AXI
│ │ │ ▲
▼ ▼ ▼ │
┌───────────────────────────┐ ┌─────┐ ┌─┴──┐
│ ATP FUNNEL ├──►│ETF ├─► │ETR │
└───────────────────────────┘ └─────┘ └────┘
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 179 ++++++++++++++++++++++
1 file changed, 179 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index a19224fe1a6a..0fa74477b9e1 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -304,6 +304,185 @@ soc: soc@0 {
nvmem-cells = <&imx8mp_uid>;
nvmem-cell-names = "soc_unique_id";
+ etm0: etm@28440000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0x28440000 0x10000>;
+ arm,primecell-periphid = <0xbb95d>;
+ cpu = <&A53_0>;
+ clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
+ clock-names = "apb_pclk";
+ out-ports {
+ port {
+ etm0_out_port: endpoint {
+ remote-endpoint = <&ca_funnel_in_port0>;
+ };
+ };
+ };
+ };
+
+ etm1: etm@28540000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0x28540000 0x10000>;
+ arm,primecell-periphid = <0xbb95d>;
+ cpu = <&A53_1>;
+ clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
+ clock-names = "apb_pclk";
+ out-ports {
+ port {
+ etm1_out_port: endpoint {
+ remote-endpoint = <&ca_funnel_in_port1>;
+ };
+ };
+ };
+ };
+
+ etm2: etm@28640000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0x28640000 0x10000>;
+ arm,primecell-periphid = <0xbb95d>;
+ cpu = <&A53_2>;
+ clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
+ clock-names = "apb_pclk";
+ out-ports {
+ port {
+ etm2_out_port: endpoint {
+ remote-endpoint = <&ca_funnel_in_port2>;
+ };
+ };
+ };
+ };
+
+ etm3: etm@28740000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0x28740000 0x10000>;
+ arm,primecell-periphid = <0xbb95d>;
+ cpu = <&A53_3>;
+ clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
+ clock-names = "apb_pclk";
+ out-ports {
+ port {
+ etm3_out_port: endpoint {
+ remote-endpoint = <&ca_funnel_in_port3>;
+ };
+ };
+ };
+ };
+
+ funnel {
+ /*
+ * non-configurable funnel don't show up on the AMBA
+ * bus. As such no need to add "arm,primecell".
+ */
+ compatible = "arm,coresight-static-funnel";
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ ca_funnel_in_port0: endpoint {
+ remote-endpoint = <&etm0_out_port>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ ca_funnel_in_port1: endpoint {
+ remote-endpoint = <&etm1_out_port>;
+ };
+ };
+ port@2 {
+ reg = <2>;
+ ca_funnel_in_port2: endpoint {
+ remote-endpoint = <&etm2_out_port>;
+ };
+ };
+ port@3 {
+ reg = <3>;
+ ca_funnel_in_port3: endpoint {
+ remote-endpoint = <&etm3_out_port>;
+ };
+ };
+ };
+ out-ports {
+ port {
+ ca_funnel_out_port0: endpoint {
+ remote-endpoint = <&hugo_funnel_in_port0>;
+ };
+ };
+ };
+ };
+
+ funnel@28c03000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x28c03000 0x1000>;
+ clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
+ clock-names = "apb_pclk";
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ hugo_funnel_in_port0: endpoint {
+ remote-endpoint = <&ca_funnel_out_port0>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ hugo_funnel_in_port1: endpoint {
+ /* M7 input */
+ };
+ };
+ port@2 {
+ reg = <2>;
+ hugo_funnel_in_port2: endpoint {
+ /* DSP input */
+ };
+ };
+ /* the other input ports are not connect to anything */
+ };
+ out-ports {
+ port {
+ hugo_funnel_out_port0: endpoint {
+ remote-endpoint = <&etf_in_port>;
+ };
+ };
+ };
+ };
+
+ etf@28c04000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x28c04000 0x1000>;
+ clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
+ clock-names = "apb_pclk";
+ in-ports {
+ port {
+ etf_in_port: endpoint {
+ remote-endpoint = <&hugo_funnel_out_port0>;
+ };
+ };
+ };
+ out-ports {
+ port {
+ etf_out_port: endpoint {
+ remote-endpoint = <&etr_in_port>;
+ };
+ };
+ };
+ };
+
+ etr@28c06000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x28c06000 0x1000>;
+ clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
+ clock-names = "apb_pclk";
+ in-ports {
+ port {
+ etr_in_port: endpoint {
+ remote-endpoint = <&etf_out_port>;
+ };
+ };
+ };
+ };
+
aips1: bus@30000000 {
compatible = "fsl,aips-bus", "simple-bus";
reg = <0x30000000 0x400000>;
--
2.34.1
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^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH 1/1] arm64: dts: imx8mp: Add coresight trace components 2023-05-05 19:51 [PATCH 1/1] arm64: dts: imx8mp: Add coresight trace components Frank Li @ 2023-06-09 8:20 ` Alexander Stein 2023-06-12 18:53 ` Frank Li 2023-07-04 15:20 ` Suzuki K Poulose 1 sibling, 1 reply; 5+ messages in thread From: Alexander Stein @ 2023-06-09 8:20 UTC (permalink / raw) To: imx, Rob Herring, Krzysztof Kozlowski, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, open list Cc: coresight, Frank Li Hi, Am Freitag, 5. Mai 2023, 21:51:51 CEST schrieb Frank Li: > Add coresight trace components (ETM, ETF, ETB and Funnel). > > ┌───────┐ ┌───────┐ ┌───────┐ > │ CPU0 ├─►│ ETM0 ├─►│ │ > └───────┘ └───────┘ │ │ > │ │ > ┌───────┐ ┌───────┐ │ ATP │ > │ CPU1 ├─►│ ETM1 ├─►│ │ > └───────┘ └───────┘ │ │ > │ FUNNEL│ > ┌───────┐ ┌───────┐ │ │ > │ CPU2 ├─►│ ETM2 ├─►│ │ > └───────┘ └───────┘ │ │ ┌─────┐ ┌─────┐ > │ │ │ │ │ │ > ┌───────┐ ┌───────┐ │ │ │ M7 │ │ DSP │ > │ CPU3 ├─►│ ETM3 ├─►│ │ │ │ │ │ > └───────┘ └───────┘ └───┬───┘ └──┬──┘ └──┬──┘ AXI > │ │ │ ▲ > ▼ ▼ ▼ │ > ┌───────────────────────────┐ ┌─────┐ ┌─┴──┐ > │ ATP FUNNEL ├──►│ETF ├─► │ETR │ > └───────────────────────────┘ └─────┘ └────┘ > > Signed-off-by: Frank Li <Frank.Li@nxp.com> > --- > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 179 ++++++++++++++++++++++ > 1 file changed, 179 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi > b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index > a19224fe1a6a..0fa74477b9e1 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi > @@ -304,6 +304,185 @@ soc: soc@0 { > nvmem-cells = <&imx8mp_uid>; > nvmem-cell-names = "soc_unique_id"; > > + etm0: etm@28440000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0x28440000 0x10000>; > + arm,primecell-periphid = <0xbb95d>; > + cpu = <&A53_0>; > + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; > + clock-names = "apb_pclk"; > + out-ports { > + port { > + etm0_out_port: endpoint { > + remote-endpoint = <&ca_funnel_in_port0>; > + }; > + }; > + }; > + }; > + > + etm1: etm@28540000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0x28540000 0x10000>; > + arm,primecell-periphid = <0xbb95d>; > + cpu = <&A53_1>; > + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; > + clock-names = "apb_pclk"; > + out-ports { > + port { > + etm1_out_port: endpoint { > + remote-endpoint = <&ca_funnel_in_port1>; > + }; > + }; > + }; > + }; > + > + etm2: etm@28640000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0x28640000 0x10000>; > + arm,primecell-periphid = <0xbb95d>; > + cpu = <&A53_2>; > + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; > + clock-names = "apb_pclk"; > + out-ports { > + port { > + etm2_out_port: endpoint { > + remote-endpoint = <&ca_funnel_in_port2>; > + }; > + }; > + }; > + }; > + > + etm3: etm@28740000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0x28740000 0x10000>; > + arm,primecell-periphid = <0xbb95d>; > + cpu = <&A53_3>; > + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; > + clock-names = "apb_pclk"; > + out-ports { > + port { > + etm3_out_port: endpoint { > + remote-endpoint = <&ca_funnel_in_port3>; > + }; > + }; > + }; > + }; > + > + funnel { > + /* > + * non-configurable funnel don't show up on the AMBA > + * bus. As such no need to add "arm,primecell". > + */ > + compatible = "arm,coresight-static-funnel"; > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + port@0 { > + reg = <0>; > + ca_funnel_in_port0: endpoint { > + remote-endpoint = <&etm0_out_port>; > + }; > + }; > + port@1 { > + reg = <1>; > + ca_funnel_in_port1: endpoint { > + remote-endpoint = <&etm1_out_port>; > + }; > + }; > + port@2 { > + reg = <2>; > + ca_funnel_in_port2: endpoint { > + remote-endpoint = <&etm2_out_port>; > + }; > + }; > + port@3 { > + reg = <3>; > + ca_funnel_in_port3: endpoint { > + remote-endpoint = <&etm3_out_port>; > + }; > + }; > + }; > + out-ports { > + port { > + ca_funnel_out_port0: endpoint { > + remote-endpoint = <&hugo_funnel_in_port0>; > + }; > + }; > + }; > + }; > + > + funnel@28c03000 { > + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; > + reg = <0x28c03000 0x1000>; > + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; > + clock-names = "apb_pclk"; > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + port@0 { > + reg = <0>; > + hugo_funnel_in_port0: endpoint { > + remote-endpoint = <&ca_funnel_out_port0>; > + }; > + }; > + port@1 { > + reg = <1>; > + hugo_funnel_in_port1: endpoint { > + /* M7 input */ > + }; > + }; > + port@2 { > + reg = <2>; > + hugo_funnel_in_port2: endpoint { > + /* DSP input */ > + }; > + }; > + /* the other input ports are not connect to anything */ > + }; > + out-ports { > + port { > + hugo_funnel_out_port0: endpoint { > + remote-endpoint = <&etf_in_port>; > + }; > + }; > + }; > + }; > + > + etf@28c04000 { The reference manual states "CXTMC_ETB" for this address. I don't have much knowledge about coresight, but ETB is not the same as ETF, right? Which one is correct? Best regards, Alexander > + compatible = "arm,coresight-tmc", "arm,primecell"; > + reg = <0x28c04000 0x1000>; > + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; > + clock-names = "apb_pclk"; > + in-ports { > + port { > + etf_in_port: endpoint { > + remote-endpoint = <&hugo_funnel_out_port0>; > + }; > + }; > + }; > + out-ports { > + port { > + etf_out_port: endpoint { > + remote-endpoint = <&etr_in_port>; > + }; > + }; > + }; > + }; > + > + etr@28c06000 { > + compatible = "arm,coresight-tmc", "arm,primecell"; > + reg = <0x28c06000 0x1000>; > + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; > + clock-names = "apb_pclk"; > + in-ports { > + port { > + etr_in_port: endpoint { > + remote-endpoint = <&etf_out_port>; > + }; > + }; > + }; > + }; > + > aips1: bus@30000000 { > compatible = "fsl,aips-bus", "simple-bus"; > reg = <0x30000000 0x400000>; -- TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany Amtsgericht München, HRB 105018 Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider http://www.tq-group.com/ _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/1] arm64: dts: imx8mp: Add coresight trace components 2023-06-09 8:20 ` Alexander Stein @ 2023-06-12 18:53 ` Frank Li 0 siblings, 0 replies; 5+ messages in thread From: Frank Li @ 2023-06-12 18:53 UTC (permalink / raw) To: Alexander Stein Cc: imx, Rob Herring, Krzysztof Kozlowski, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, open list, coresight On Fri, Jun 09, 2023 at 10:20:16AM +0200, Alexander Stein wrote: > > + }; > > + }; > > + > > + etf@28c04000 { > > The reference manual states "CXTMC_ETB" for this address. I don't have much > knowledge about coresight, but ETB is not the same as ETF, right? Which one is > correct? > > Best regards, > Alexander > coresight tmc driver can auto detect etb and etf according to register value. Frank > > + compatible = "arm,coresight-tmc", > "arm,primecell"; > > + reg = <0x28c04000 0x1000>; > > + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; > > + clock-names = "apb_pclk"; > > + in-ports { > > + port { > > + etf_in_port: endpoint { > > + remote-endpoint = _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/1] arm64: dts: imx8mp: Add coresight trace components 2023-05-05 19:51 [PATCH 1/1] arm64: dts: imx8mp: Add coresight trace components Frank Li 2023-06-09 8:20 ` Alexander Stein @ 2023-07-04 15:20 ` Suzuki K Poulose 2023-07-05 20:40 ` Frank Li 1 sibling, 1 reply; 5+ messages in thread From: Suzuki K Poulose @ 2023-07-04 15:20 UTC (permalink / raw) To: Frank Li, imx, Rob Herring, Krzysztof Kozlowski, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, open list Cc: coresight On 05/05/2023 20:51, Frank Li wrote: > Add coresight trace components (ETM, ETF, ETB and Funnel). > > ┌───────┐ ┌───────┐ ┌───────┐ > │ CPU0 ├─►│ ETM0 ├─►│ │ > └───────┘ └───────┘ │ │ > │ │ > ┌───────┐ ┌───────┐ │ ATP │ > │ CPU1 ├─►│ ETM1 ├─►│ │ > └───────┘ └───────┘ │ │ > │ FUNNEL│ > ┌───────┐ ┌───────┐ │ │ > │ CPU2 ├─►│ ETM2 ├─►│ │ > └───────┘ └───────┘ │ │ ┌─────┐ ┌─────┐ > │ │ │ │ │ │ > ┌───────┐ ┌───────┐ │ │ │ M7 │ │ DSP │ > │ CPU3 ├─►│ ETM3 ├─►│ │ │ │ │ │ > └───────┘ └───────┘ └───┬───┘ └──┬──┘ └──┬──┘ AXI > │ │ │ ▲ > ▼ ▼ ▼ │ > ┌───────────────────────────┐ ┌─────┐ ┌─┴──┐ > │ ATP FUNNEL ├──►│ETF ├─► │ETR │ > └───────────────────────────┘ └─────┘ └────┘ > > Signed-off-by: Frank Li <Frank.Li@nxp.com> > --- > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 179 ++++++++++++++++++++++ > 1 file changed, 179 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi > index a19224fe1a6a..0fa74477b9e1 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi > @@ -304,6 +304,185 @@ soc: soc@0 { > nvmem-cells = <&imx8mp_uid>; > nvmem-cell-names = "soc_unique_id"; > > + etm0: etm@28440000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0x28440000 0x10000>; > + arm,primecell-periphid = <0xbb95d>; Why is this needed (and for all the ETMs) ? Suzuki _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/1] arm64: dts: imx8mp: Add coresight trace components 2023-07-04 15:20 ` Suzuki K Poulose @ 2023-07-05 20:40 ` Frank Li 0 siblings, 0 replies; 5+ messages in thread From: Frank Li @ 2023-07-05 20:40 UTC (permalink / raw) To: Suzuki K Poulose Cc: imx, Rob Herring, Krzysztof Kozlowski, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, open list, coresight On Tue, Jul 04, 2023 at 04:20:18PM +0100, Suzuki K Poulose wrote: > On 05/05/2023 20:51, Frank Li wrote: > > Add coresight trace components (ETM, ETF, ETB and Funnel). > > > > ┌───────┐ ┌───────┐ ┌───────┐ > > │ CPU0 ├─►│ ETM0 ├─►│ │ > > └───────┘ └───────┘ │ │ > > │ │ > > ┌───────┐ ┌───────┐ │ ATP │ > > │ CPU1 ├─►│ ETM1 ├─►│ │ > > └───────┘ └───────┘ │ │ > > │ FUNNEL│ > > ┌───────┐ ┌───────┐ │ │ > > │ CPU2 ├─►│ ETM2 ├─►│ │ > > └───────┘ └───────┘ │ │ ┌─────┐ ┌─────┐ > > │ │ │ │ │ │ > > ┌───────┐ ┌───────┐ │ │ │ M7 │ │ DSP │ > > │ CPU3 ├─►│ ETM3 ├─►│ │ │ │ │ │ > > └───────┘ └───────┘ └───┬───┘ └──┬──┘ └──┬──┘ AXI > > │ │ │ ▲ > > ▼ ▼ ▼ │ > > ┌───────────────────────────┐ ┌─────┐ ┌─┴──┐ > > │ ATP FUNNEL ├──►│ETF ├─► │ETR │ > > └───────────────────────────┘ └─────┘ └────┘ > > > > Signed-off-by: Frank Li <Frank.Li@nxp.com> > > --- > > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 179 ++++++++++++++++++++++ > > 1 file changed, 179 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi > > index a19224fe1a6a..0fa74477b9e1 100644 > > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi > > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi > > @@ -304,6 +304,185 @@ soc: soc@0 { > > nvmem-cells = <&imx8mp_uid>; > > nvmem-cell-names = "soc_unique_id"; > > + etm0: etm@28440000 { > > + compatible = "arm,coresight-etm4x", "arm,primecell"; > > + reg = <0x28440000 0x10000>; > > + arm,primecell-periphid = <0xbb95d>; > > Why is this needed (and for all the ETMs) ? Reg size is wrong set to 64k(should be 4k), so crash when call amba_read_periphid(). let me send out a fixed patch. Thank you for found it. Frank > > Suzuki > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2023-07-06 1:55 UTC | newest] Thread overview: 5+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2023-05-05 19:51 [PATCH 1/1] arm64: dts: imx8mp: Add coresight trace components Frank Li 2023-06-09 8:20 ` Alexander Stein 2023-06-12 18:53 ` Frank Li 2023-07-04 15:20 ` Suzuki K Poulose 2023-07-05 20:40 ` Frank Li
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