* [PATCH v2 2/3] arm64: perf: Expose some new events via sysfs
2020-05-05 4:16 [PATCH v2 1/3] arm64: perf: Add support caps in sysfs Shaokun Zhang
@ 2020-05-05 4:16 ` Shaokun Zhang
2020-05-05 4:16 ` [PATCH v2 3/3] arm64: perf: Correct the event index in sysfs Shaokun Zhang
` (2 subsequent siblings)
3 siblings, 0 replies; 6+ messages in thread
From: Shaokun Zhang @ 2020-05-05 4:16 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Shaokun Zhang, Mark Rutland, Will Deacon
Some new PMU events can been detected by PMCEID1_EL0, but it can't
be listed, Let's expose these through sysfs.
Cc: Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
---
arch/arm64/include/asm/perf_event.h | 27 +++++++++++++++++++++++++++
arch/arm64/kernel/perf_event.c | 19 +++++++++++++++++++
2 files changed, 46 insertions(+)
diff --git a/arch/arm64/include/asm/perf_event.h b/arch/arm64/include/asm/perf_event.h
index e7765b62c712..2c2d7dbe8a02 100644
--- a/arch/arm64/include/asm/perf_event.h
+++ b/arch/arm64/include/asm/perf_event.h
@@ -72,6 +72,13 @@
#define ARMV8_PMUV3_PERFCTR_LL_CACHE_RD 0x36
#define ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD 0x37
#define ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS_RD 0x38
+#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_LMISS_RD 0x39
+#define ARMV8_PMUV3_PERFCTR_OP_RETIRED 0x3A
+#define ARMV8_PMUV3_PERFCTR_OP_SPEC 0x3B
+#define ARMV8_PMUV3_PERFCTR_STALL 0x3C
+#define ARMV8_PMUV3_PERFCTR_STALL_SLOT_BACKEND 0x3D
+#define ARMV8_PMUV3_PERFCTR_STALL_SLOT_FRONTEND 0x3E
+#define ARMV8_PMUV3_PERFCTR_STALL_SLOT 0x3F
/* Statistical profiling extension microarchitectural events */
#define ARMV8_SPE_PERFCTR_SAMPLE_POP 0x4000
@@ -79,6 +86,26 @@
#define ARMV8_SPE_PERFCTR_SAMPLE_FILTRATE 0x4002
#define ARMV8_SPE_PERFCTR_SAMPLE_COLLISION 0x4003
+/* AMUv1 architecture events */
+#define ARMV8_AMU_PERFCTR_CNT_CYCLES 0x4004
+#define ARMV8_AMU_PERFCTR_STALL_BACKEND_MEM 0x4005
+
+/* long-latency read miss events */
+#define ARMV8_PMUV3_PERFCTR_L1I_CACHE_LMISS 0x4006
+#define ARMV8_PMUV3_PERFCTR_L2D_CACHE_LMISS_RD 0x4009
+#define ARMV8_PMUV3_PERFCTR_L2I_CACHE_LMISS 0x400A
+#define ARMV8_PMUV3_PERFCTR_L3D_CACHE_LMISS_RD 0x400B
+
+/* additional latency from alignment events */
+#define ARMV8_PMUV3_PERFCTR_LDST_ALIGN_LAT 0x4020
+#define ARMV8_PMUV3_PERFCTR_LD_ALIGN_LAT 0x4021
+#define ARMV8_PMUV3_PERFCTR_ST_ALIGN_LAT 0x4022
+
+/* Armv8.5 Memory Tagging Extension events */
+#define ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED 0x4024
+#define ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_RD 0x4025
+#define ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_WR 0x4026
+
/* ARMv8 recommended implementation defined event types */
#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD 0x40
#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR 0x41
diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index 5f2ac87e4b91..32c87cd48cbe 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -222,10 +222,29 @@ static struct attribute *armv8_pmuv3_event_attrs[] = {
ARMV8_EVENT_ATTR(ll_cache_rd, ARMV8_PMUV3_PERFCTR_LL_CACHE_RD),
ARMV8_EVENT_ATTR(ll_cache_miss_rd, ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD),
ARMV8_EVENT_ATTR(remote_access_rd, ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS_RD),
+ ARMV8_EVENT_ATTR(l1d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L1D_CACHE_LMISS_RD),
+ ARMV8_EVENT_ATTR(op_retired, ARMV8_PMUV3_PERFCTR_OP_RETIRED),
+ ARMV8_EVENT_ATTR(op_SPEC, ARMV8_PMUV3_PERFCTR_OP_SPEC),
+ ARMV8_EVENT_ATTR(stall, ARMV8_PMUV3_PERFCTR_STALL),
+ ARMV8_EVENT_ATTR(stall_slot_backend, ARMV8_PMUV3_PERFCTR_STALL_SLOT_BACKEND),
+ ARMV8_EVENT_ATTR(stall_slot_frontend, ARMV8_PMUV3_PERFCTR_STALL_SLOT_FRONTEND),
+ ARMV8_EVENT_ATTR(stall_slot, ARMV8_PMUV3_PERFCTR_STALL_SLOT),
ARMV8_EVENT_ATTR(sample_pop, ARMV8_SPE_PERFCTR_SAMPLE_POP),
ARMV8_EVENT_ATTR(sample_feed, ARMV8_SPE_PERFCTR_SAMPLE_FEED),
ARMV8_EVENT_ATTR(sample_filtrate, ARMV8_SPE_PERFCTR_SAMPLE_FILTRATE),
ARMV8_EVENT_ATTR(sample_collision, ARMV8_SPE_PERFCTR_SAMPLE_COLLISION),
+ ARMV8_EVENT_ATTR(cnt_cycles, ARMV8_AMU_PERFCTR_CNT_CYCLES),
+ ARMV8_EVENT_ATTR(stall_backend_mem, ARMV8_AMU_PERFCTR_STALL_BACKEND_MEM),
+ ARMV8_EVENT_ATTR(l1i_cache_lmiss, ARMV8_PMUV3_PERFCTR_L1I_CACHE_LMISS),
+ ARMV8_EVENT_ATTR(l2d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L2D_CACHE_LMISS_RD),
+ ARMV8_EVENT_ATTR(l2i_cache_lmiss, ARMV8_PMUV3_PERFCTR_L2I_CACHE_LMISS),
+ ARMV8_EVENT_ATTR(l3d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L3D_CACHE_LMISS_RD),
+ ARMV8_EVENT_ATTR(ldst_align_lat, ARMV8_PMUV3_PERFCTR_LDST_ALIGN_LAT),
+ ARMV8_EVENT_ATTR(ld_align_lat, ARMV8_PMUV3_PERFCTR_LD_ALIGN_LAT),
+ ARMV8_EVENT_ATTR(st_align_lat, ARMV8_PMUV3_PERFCTR_ST_ALIGN_LAT),
+ ARMV8_EVENT_ATTR(mem_access_checked, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED),
+ ARMV8_EVENT_ATTR(mem_access_checked_rd, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_RD),
+ ARMV8_EVENT_ATTR(mem_access_checked_wr, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_WR),
NULL,
};
--
2.7.4
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v2 3/3] arm64: perf: Correct the event index in sysfs
2020-05-05 4:16 [PATCH v2 1/3] arm64: perf: Add support caps in sysfs Shaokun Zhang
2020-05-05 4:16 ` [PATCH v2 2/3] arm64: perf: Expose some new events via sysfs Shaokun Zhang
@ 2020-05-05 4:16 ` Shaokun Zhang
2020-05-05 4:29 ` Shaokun Zhang
2020-05-18 3:18 ` [PATCH v2 1/3] arm64: perf: Add support caps " Shaokun Zhang
2020-05-27 12:31 ` Shaokun Zhang
3 siblings, 1 reply; 6+ messages in thread
From: Shaokun Zhang @ 2020-05-05 4:16 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Shaokun Zhang, Mark Rutland, Will Deacon
When PMU event ID is equal or greater than 0x4000, it will be reduced
by 0x4000 and it is not the raw number in the sysfs. Let's correct it
and obtain the right event ID.
Before this patch:
cat /sys/bus/event_source/devices/armv8_pmuv3_0/events/sample_feed
event=0x001
After this patch:
cat /sys/bus/event_source/devices/armv8_pmuv3_0/events/sample_feed
event=0x4001
Cc: Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
---
arch/arm64/kernel/perf_event.c | 13 ++++++++-----
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index 32c87cd48cbe..bd73e7f0e652 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -155,7 +155,7 @@ armv8pmu_events_sysfs_show(struct device *dev,
pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
- return sprintf(page, "event=0x%03llx\n", pmu_attr->id);
+ return sprintf(page, "event=0x%04llx\n", pmu_attr->id);
}
#define ARMV8_EVENT_ATTR(name, config) \
@@ -263,10 +263,13 @@ armv8pmu_event_attr_is_visible(struct kobject *kobj,
test_bit(pmu_attr->id, cpu_pmu->pmceid_bitmap))
return attr->mode;
- pmu_attr->id -= ARMV8_PMUV3_EXT_COMMON_EVENT_BASE;
- if (pmu_attr->id < ARMV8_PMUV3_MAX_COMMON_EVENTS &&
- test_bit(pmu_attr->id, cpu_pmu->pmceid_ext_bitmap))
- return attr->mode;
+ if (pmu_attr->id > ARMV8_PMUV3_EXT_COMMON_EVENT_BASE) {
+ u64 id = pmu_attr->id - ARMV8_PMUV3_EXT_COMMON_EVENT_BASE;
+
+ if (id < ARMV8_PMUV3_MAX_COMMON_EVENTS && test_bit(id,
+ cpu_pmu->pmceid_ext_bitmap))
+ return attr->mode;
+ }
return 0;
}
--
2.7.4
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH v2 3/3] arm64: perf: Correct the event index in sysfs
2020-05-05 4:16 ` [PATCH v2 3/3] arm64: perf: Correct the event index in sysfs Shaokun Zhang
@ 2020-05-05 4:29 ` Shaokun Zhang
0 siblings, 0 replies; 6+ messages in thread
From: Shaokun Zhang @ 2020-05-05 4:29 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Mark Rutland, Will Deacon
Hi Will,
On 2020/5/5 12:16, Shaokun Zhang wrote:
> When PMU event ID is equal or greater than 0x4000, it will be reduced
> by 0x4000 and it is not the raw number in the sysfs. Let's correct it
> and obtain the right event ID.
>
> Before this patch:
> cat /sys/bus/event_source/devices/armv8_pmuv3_0/events/sample_feed
> event=0x001
> After this patch:
> cat /sys/bus/event_source/devices/armv8_pmuv3_0/events/sample_feed
> event=0x4001
>
> Cc: Will Deacon <will@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
> ---
> arch/arm64/kernel/perf_event.c | 13 ++++++++-----
> 1 file changed, 8 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
> index 32c87cd48cbe..bd73e7f0e652 100644
> --- a/arch/arm64/kernel/perf_event.c
> +++ b/arch/arm64/kernel/perf_event.c
> @@ -155,7 +155,7 @@ armv8pmu_events_sysfs_show(struct device *dev,
>
> pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
>
> - return sprintf(page, "event=0x%03llx\n", pmu_attr->id);
> + return sprintf(page, "event=0x%04llx\n", pmu_attr->id);
> }
>
> #define ARMV8_EVENT_ATTR(name, config) \
> @@ -263,10 +263,13 @@ armv8pmu_event_attr_is_visible(struct kobject *kobj,
> test_bit(pmu_attr->id, cpu_pmu->pmceid_bitmap))
> return attr->mode;
>
> - pmu_attr->id -= ARMV8_PMUV3_EXT_COMMON_EVENT_BASE;
> - if (pmu_attr->id < ARMV8_PMUV3_MAX_COMMON_EVENTS &&
> - test_bit(pmu_attr->id, cpu_pmu->pmceid_ext_bitmap))
> - return attr->mode;
> + if (pmu_attr->id > ARMV8_PMUV3_EXT_COMMON_EVENT_BASE) {
Apologies that this shall be:
if (pmu_attr->id >= ARMV8_PMUV3_EXT_COMMON_EVENT_BASE) {
Thanks,
Shaokun
> + u64 id = pmu_attr->id - ARMV8_PMUV3_EXT_COMMON_EVENT_BASE;
> +
> + if (id < ARMV8_PMUV3_MAX_COMMON_EVENTS && test_bit(id,
> + cpu_pmu->pmceid_ext_bitmap))
> + return attr->mode;
> + }
>
> return 0;
> }
>
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2 1/3] arm64: perf: Add support caps in sysfs
2020-05-05 4:16 [PATCH v2 1/3] arm64: perf: Add support caps in sysfs Shaokun Zhang
2020-05-05 4:16 ` [PATCH v2 2/3] arm64: perf: Expose some new events via sysfs Shaokun Zhang
2020-05-05 4:16 ` [PATCH v2 3/3] arm64: perf: Correct the event index in sysfs Shaokun Zhang
@ 2020-05-18 3:18 ` Shaokun Zhang
2020-05-27 12:31 ` Shaokun Zhang
3 siblings, 0 replies; 6+ messages in thread
From: Shaokun Zhang @ 2020-05-18 3:18 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Mark Rutland, Catalin Marinas, Will Deacon
Hi Will/Mark,
Any comments on v2?
Thanks,
Shaokun
On 2020/5/5 12:16, Shaokun Zhang wrote:
> ARMv8.4-PMU introduces the PMMIR_EL1 registers and some new PMU events,
> like STALL_SLOT etc, are related to it. Let's add a caps directory to
> /sys/bus/event_source/devices/armv8_pmuv3_0/ and support slots from
> PMMIR_EL1 registers in this entry. The user programs can get the slots
> from sysfs directly.
>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
> ---
> Hi Will,
>
> I send another patch[3/3] arm64: perf: Correct the event index in sysfs
> meanwhile because it is dependent on patch2.
>
> ChangeLog in v2:
> * Add caps entry in sysfs
> * Fix the PMU events typos
> * Add one new patch to correct event ID in sysfs
>
> arch/arm64/include/asm/sysreg.h | 2 +
> arch/arm64/kernel/perf_event.c | 87 +++++++++++++++++++++++++++++++----------
> include/linux/perf/arm_pmu.h | 1 +
> 3 files changed, 69 insertions(+), 21 deletions(-)
>
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index c4ac0ac25a00..aa14083de466 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -314,6 +314,8 @@
> #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1)
> #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2)
>
> +#define SYS_PMMIR_EL1 sys_reg(3, 0, 9, 14, 6)
> +
> #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0)
> #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0)
>
> diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
> index 4d7879484cec..5f2ac87e4b91 100644
> --- a/arch/arm64/kernel/perf_event.c
> +++ b/arch/arm64/kernel/perf_event.c
> @@ -277,6 +277,51 @@ static struct attribute_group armv8_pmuv3_format_attr_group = {
> .attrs = armv8_pmuv3_format_attrs,
> };
>
> +static inline int armv8pmu_get_pmu_version(void)
> +{
> + int pmuver;
> + u64 dfr0;
> +
> + dfr0 = read_sysreg(id_aa64dfr0_el1);
> + pmuver = cpuid_feature_extract_unsigned_field(dfr0,
> + ID_AA64DFR0_PMUVER_SHIFT);
> +
> + return pmuver;
> +}
> +
> +static umode_t
> +armv8pmu_caps_attr_is_visible(struct kobject *kobj, struct attribute *attr,
> + int unused)
> +{
> + int pmuver = armv8pmu_get_pmu_version();
> +
> + if (pmuver >= ID_AA64DFR0_PMUVER_8_4)
> + return attr->mode;
> +
> + return 0;
> +}
> +
> +static ssize_t slots_show(struct device *dev, struct device_attribute *attr,
> + char *buf)
> +{
> + int slots = read_sysreg_s(SYS_PMMIR_EL1) & 0xFF;
> +
> + return snprintf(buf, PAGE_SIZE, "%d\n", slots);
> +}
> +
> +static DEVICE_ATTR_RO(slots);
> +
> +static struct attribute *armv8_pmuv3_caps_attrs[] = {
> + &dev_attr_slots.attr,
> + NULL,
> +};
> +
> +static struct attribute_group armv8_pmuv3_caps_attr_group = {
> + .name = "caps",
> + .attrs = armv8_pmuv3_caps_attrs,
> + .is_visible = armv8pmu_caps_attr_is_visible,
> +};
> +
> /*
> * Perf Events' indices
> */
> @@ -940,14 +985,11 @@ static void __armv8pmu_probe_pmu(void *info)
> {
> struct armv8pmu_probe_info *probe = info;
> struct arm_pmu *cpu_pmu = probe->pmu;
> - u64 dfr0;
> u64 pmceid_raw[2];
> u32 pmceid[2];
> int pmuver;
>
> - dfr0 = read_sysreg(id_aa64dfr0_el1);
> - pmuver = cpuid_feature_extract_unsigned_field(dfr0,
> - ID_AA64DFR0_PMUVER_SHIFT);
> + pmuver = armv8pmu_get_pmu_version();
> if (pmuver == 0xf || pmuver == 0)
> return;
>
> @@ -994,7 +1036,8 @@ static int armv8pmu_probe_pmu(struct arm_pmu *cpu_pmu)
> static int armv8_pmu_init(struct arm_pmu *cpu_pmu, char *name,
> int (*map_event)(struct perf_event *event),
> const struct attribute_group *events,
> - const struct attribute_group *format)
> + const struct attribute_group *format,
> + const struct attribute_group *caps)
> {
> int ret = armv8pmu_probe_pmu(cpu_pmu);
> if (ret)
> @@ -1019,6 +1062,8 @@ static int armv8_pmu_init(struct arm_pmu *cpu_pmu, char *name,
> events : &armv8_pmuv3_events_attr_group;
> cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = format ?
> format : &armv8_pmuv3_format_attr_group;
> + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_CAPS] = caps ?
> + caps : &armv8_pmuv3_caps_attr_group;
>
> return 0;
> }
> @@ -1026,97 +1071,97 @@ static int armv8_pmu_init(struct arm_pmu *cpu_pmu, char *name,
> static int armv8_pmuv3_init(struct arm_pmu *cpu_pmu)
> {
> return armv8_pmu_init(cpu_pmu, "armv8_pmuv3",
> - armv8_pmuv3_map_event, NULL, NULL);
> + armv8_pmuv3_map_event, NULL, NULL, NULL);
> }
>
> static int armv8_a34_pmu_init(struct arm_pmu *cpu_pmu)
> {
> return armv8_pmu_init(cpu_pmu, "armv8_cortex_a34",
> - armv8_pmuv3_map_event, NULL, NULL);
> + armv8_pmuv3_map_event, NULL, NULL, NULL);
> }
>
> static int armv8_a35_pmu_init(struct arm_pmu *cpu_pmu)
> {
> return armv8_pmu_init(cpu_pmu, "armv8_cortex_a35",
> - armv8_a53_map_event, NULL, NULL);
> + armv8_a53_map_event, NULL, NULL, NULL);
> }
>
> static int armv8_a53_pmu_init(struct arm_pmu *cpu_pmu)
> {
> return armv8_pmu_init(cpu_pmu, "armv8_cortex_a53",
> - armv8_a53_map_event, NULL, NULL);
> + armv8_a53_map_event, NULL, NULL, NULL);
> }
>
> static int armv8_a55_pmu_init(struct arm_pmu *cpu_pmu)
> {
> return armv8_pmu_init(cpu_pmu, "armv8_cortex_a55",
> - armv8_pmuv3_map_event, NULL, NULL);
> + armv8_pmuv3_map_event, NULL, NULL, NULL);
> }
>
> static int armv8_a57_pmu_init(struct arm_pmu *cpu_pmu)
> {
> return armv8_pmu_init(cpu_pmu, "armv8_cortex_a57",
> - armv8_a57_map_event, NULL, NULL);
> + armv8_a57_map_event, NULL, NULL, NULL);
> }
>
> static int armv8_a65_pmu_init(struct arm_pmu *cpu_pmu)
> {
> return armv8_pmu_init(cpu_pmu, "armv8_cortex_a65",
> - armv8_pmuv3_map_event, NULL, NULL);
> + armv8_pmuv3_map_event, NULL, NULL, NULL);
> }
>
> static int armv8_a72_pmu_init(struct arm_pmu *cpu_pmu)
> {
> return armv8_pmu_init(cpu_pmu, "armv8_cortex_a72",
> - armv8_a57_map_event, NULL, NULL);
> + armv8_a57_map_event, NULL, NULL, NULL);
> }
>
> static int armv8_a73_pmu_init(struct arm_pmu *cpu_pmu)
> {
> return armv8_pmu_init(cpu_pmu, "armv8_cortex_a73",
> - armv8_a73_map_event, NULL, NULL);
> + armv8_a73_map_event, NULL, NULL, NULL);
> }
>
> static int armv8_a75_pmu_init(struct arm_pmu *cpu_pmu)
> {
> return armv8_pmu_init(cpu_pmu, "armv8_cortex_a75",
> - armv8_pmuv3_map_event, NULL, NULL);
> + armv8_pmuv3_map_event, NULL, NULL, NULL);
> }
>
> static int armv8_a76_pmu_init(struct arm_pmu *cpu_pmu)
> {
> return armv8_pmu_init(cpu_pmu, "armv8_cortex_a76",
> - armv8_pmuv3_map_event, NULL, NULL);
> + armv8_pmuv3_map_event, NULL, NULL, NULL);
> }
>
> static int armv8_a77_pmu_init(struct arm_pmu *cpu_pmu)
> {
> return armv8_pmu_init(cpu_pmu, "armv8_cortex_a77",
> - armv8_pmuv3_map_event, NULL, NULL);
> + armv8_pmuv3_map_event, NULL, NULL, NULL);
> }
>
> static int armv8_e1_pmu_init(struct arm_pmu *cpu_pmu)
> {
> return armv8_pmu_init(cpu_pmu, "armv8_neoverse_e1",
> - armv8_pmuv3_map_event, NULL, NULL);
> + armv8_pmuv3_map_event, NULL, NULL, NULL);
> }
>
> static int armv8_n1_pmu_init(struct arm_pmu *cpu_pmu)
> {
> return armv8_pmu_init(cpu_pmu, "armv8_neoverse_n1",
> - armv8_pmuv3_map_event, NULL, NULL);
> + armv8_pmuv3_map_event, NULL, NULL, NULL);
> }
>
> static int armv8_thunder_pmu_init(struct arm_pmu *cpu_pmu)
> {
> return armv8_pmu_init(cpu_pmu, "armv8_cavium_thunder",
> - armv8_thunder_map_event, NULL, NULL);
> + armv8_thunder_map_event, NULL, NULL, NULL);
> }
>
> static int armv8_vulcan_pmu_init(struct arm_pmu *cpu_pmu)
> {
> return armv8_pmu_init(cpu_pmu, "armv8_brcm_vulcan",
> - armv8_vulcan_map_event, NULL, NULL);
> + armv8_vulcan_map_event, NULL, NULL, NULL);
> }
>
> static const struct of_device_id armv8_pmu_of_device_ids[] = {
> diff --git a/include/linux/perf/arm_pmu.h b/include/linux/perf/arm_pmu.h
> index 5b616dde9a4c..1e129b57d51a 100644
> --- a/include/linux/perf/arm_pmu.h
> +++ b/include/linux/perf/arm_pmu.h
> @@ -73,6 +73,7 @@ enum armpmu_attr_groups {
> ARMPMU_ATTR_GROUP_COMMON,
> ARMPMU_ATTR_GROUP_EVENTS,
> ARMPMU_ATTR_GROUP_FORMATS,
> + ARMPMU_ATTR_GROUP_CAPS,
> ARMPMU_NR_ATTR_GROUPS
> };
>
>
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^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH v2 1/3] arm64: perf: Add support caps in sysfs
2020-05-05 4:16 [PATCH v2 1/3] arm64: perf: Add support caps in sysfs Shaokun Zhang
` (2 preceding siblings ...)
2020-05-18 3:18 ` [PATCH v2 1/3] arm64: perf: Add support caps " Shaokun Zhang
@ 2020-05-27 12:31 ` Shaokun Zhang
3 siblings, 0 replies; 6+ messages in thread
From: Shaokun Zhang @ 2020-05-27 12:31 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Mark Rutland, Catalin Marinas, Will Deacon
Hi Will,
A gentle ping, or shall I send another version to fix [PATCH 3/3] mistake?
Thanks,
Shaokun
On 2020/5/5 12:16, Shaokun Zhang wrote:
> ARMv8.4-PMU introduces the PMMIR_EL1 registers and some new PMU events,
> like STALL_SLOT etc, are related to it. Let's add a caps directory to
> /sys/bus/event_source/devices/armv8_pmuv3_0/ and support slots from
> PMMIR_EL1 registers in this entry. The user programs can get the slots
> from sysfs directly.
>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
> ---
> Hi Will,
>
> I send another patch[3/3] arm64: perf: Correct the event index in sysfs
> meanwhile because it is dependent on patch2.
>
> ChangeLog in v2:
> * Add caps entry in sysfs
> * Fix the PMU events typos
> * Add one new patch to correct event ID in sysfs
>
> arch/arm64/include/asm/sysreg.h | 2 +
> arch/arm64/kernel/perf_event.c | 87 +++++++++++++++++++++++++++++++----------
> include/linux/perf/arm_pmu.h | 1 +
> 3 files changed, 69 insertions(+), 21 deletions(-)
>
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index c4ac0ac25a00..aa14083de466 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -314,6 +314,8 @@
> #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1)
> #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2)
>
> +#define SYS_PMMIR_EL1 sys_reg(3, 0, 9, 14, 6)
> +
> #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0)
> #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0)
>
> diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
> index 4d7879484cec..5f2ac87e4b91 100644
> --- a/arch/arm64/kernel/perf_event.c
> +++ b/arch/arm64/kernel/perf_event.c
> @@ -277,6 +277,51 @@ static struct attribute_group armv8_pmuv3_format_attr_group = {
> .attrs = armv8_pmuv3_format_attrs,
> };
>
> +static inline int armv8pmu_get_pmu_version(void)
> +{
> + int pmuver;
> + u64 dfr0;
> +
> + dfr0 = read_sysreg(id_aa64dfr0_el1);
> + pmuver = cpuid_feature_extract_unsigned_field(dfr0,
> + ID_AA64DFR0_PMUVER_SHIFT);
> +
> + return pmuver;
> +}
> +
> +static umode_t
> +armv8pmu_caps_attr_is_visible(struct kobject *kobj, struct attribute *attr,
> + int unused)
> +{
> + int pmuver = armv8pmu_get_pmu_version();
> +
> + if (pmuver >= ID_AA64DFR0_PMUVER_8_4)
> + return attr->mode;
> +
> + return 0;
> +}
> +
> +static ssize_t slots_show(struct device *dev, struct device_attribute *attr,
> + char *buf)
> +{
> + int slots = read_sysreg_s(SYS_PMMIR_EL1) & 0xFF;
> +
> + return snprintf(buf, PAGE_SIZE, "%d\n", slots);
> +}
> +
> +static DEVICE_ATTR_RO(slots);
> +
> +static struct attribute *armv8_pmuv3_caps_attrs[] = {
> + &dev_attr_slots.attr,
> + NULL,
> +};
> +
> +static struct attribute_group armv8_pmuv3_caps_attr_group = {
> + .name = "caps",
> + .attrs = armv8_pmuv3_caps_attrs,
> + .is_visible = armv8pmu_caps_attr_is_visible,
> +};
> +
> /*
> * Perf Events' indices
> */
> @@ -940,14 +985,11 @@ static void __armv8pmu_probe_pmu(void *info)
> {
> struct armv8pmu_probe_info *probe = info;
> struct arm_pmu *cpu_pmu = probe->pmu;
> - u64 dfr0;
> u64 pmceid_raw[2];
> u32 pmceid[2];
> int pmuver;
>
> - dfr0 = read_sysreg(id_aa64dfr0_el1);
> - pmuver = cpuid_feature_extract_unsigned_field(dfr0,
> - ID_AA64DFR0_PMUVER_SHIFT);
> + pmuver = armv8pmu_get_pmu_version();
> if (pmuver == 0xf || pmuver == 0)
> return;
>
> @@ -994,7 +1036,8 @@ static int armv8pmu_probe_pmu(struct arm_pmu *cpu_pmu)
> static int armv8_pmu_init(struct arm_pmu *cpu_pmu, char *name,
> int (*map_event)(struct perf_event *event),
> const struct attribute_group *events,
> - const struct attribute_group *format)
> + const struct attribute_group *format,
> + const struct attribute_group *caps)
> {
> int ret = armv8pmu_probe_pmu(cpu_pmu);
> if (ret)
> @@ -1019,6 +1062,8 @@ static int armv8_pmu_init(struct arm_pmu *cpu_pmu, char *name,
> events : &armv8_pmuv3_events_attr_group;
> cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = format ?
> format : &armv8_pmuv3_format_attr_group;
> + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_CAPS] = caps ?
> + caps : &armv8_pmuv3_caps_attr_group;
>
> return 0;
> }
> @@ -1026,97 +1071,97 @@ static int armv8_pmu_init(struct arm_pmu *cpu_pmu, char *name,
> static int armv8_pmuv3_init(struct arm_pmu *cpu_pmu)
> {
> return armv8_pmu_init(cpu_pmu, "armv8_pmuv3",
> - armv8_pmuv3_map_event, NULL, NULL);
> + armv8_pmuv3_map_event, NULL, NULL, NULL);
> }
>
> static int armv8_a34_pmu_init(struct arm_pmu *cpu_pmu)
> {
> return armv8_pmu_init(cpu_pmu, "armv8_cortex_a34",
> - armv8_pmuv3_map_event, NULL, NULL);
> + armv8_pmuv3_map_event, NULL, NULL, NULL);
> }
>
> static int armv8_a35_pmu_init(struct arm_pmu *cpu_pmu)
> {
> return armv8_pmu_init(cpu_pmu, "armv8_cortex_a35",
> - armv8_a53_map_event, NULL, NULL);
> + armv8_a53_map_event, NULL, NULL, NULL);
> }
>
> static int armv8_a53_pmu_init(struct arm_pmu *cpu_pmu)
> {
> return armv8_pmu_init(cpu_pmu, "armv8_cortex_a53",
> - armv8_a53_map_event, NULL, NULL);
> + armv8_a53_map_event, NULL, NULL, NULL);
> }
>
> static int armv8_a55_pmu_init(struct arm_pmu *cpu_pmu)
> {
> return armv8_pmu_init(cpu_pmu, "armv8_cortex_a55",
> - armv8_pmuv3_map_event, NULL, NULL);
> + armv8_pmuv3_map_event, NULL, NULL, NULL);
> }
>
> static int armv8_a57_pmu_init(struct arm_pmu *cpu_pmu)
> {
> return armv8_pmu_init(cpu_pmu, "armv8_cortex_a57",
> - armv8_a57_map_event, NULL, NULL);
> + armv8_a57_map_event, NULL, NULL, NULL);
> }
>
> static int armv8_a65_pmu_init(struct arm_pmu *cpu_pmu)
> {
> return armv8_pmu_init(cpu_pmu, "armv8_cortex_a65",
> - armv8_pmuv3_map_event, NULL, NULL);
> + armv8_pmuv3_map_event, NULL, NULL, NULL);
> }
>
> static int armv8_a72_pmu_init(struct arm_pmu *cpu_pmu)
> {
> return armv8_pmu_init(cpu_pmu, "armv8_cortex_a72",
> - armv8_a57_map_event, NULL, NULL);
> + armv8_a57_map_event, NULL, NULL, NULL);
> }
>
> static int armv8_a73_pmu_init(struct arm_pmu *cpu_pmu)
> {
> return armv8_pmu_init(cpu_pmu, "armv8_cortex_a73",
> - armv8_a73_map_event, NULL, NULL);
> + armv8_a73_map_event, NULL, NULL, NULL);
> }
>
> static int armv8_a75_pmu_init(struct arm_pmu *cpu_pmu)
> {
> return armv8_pmu_init(cpu_pmu, "armv8_cortex_a75",
> - armv8_pmuv3_map_event, NULL, NULL);
> + armv8_pmuv3_map_event, NULL, NULL, NULL);
> }
>
> static int armv8_a76_pmu_init(struct arm_pmu *cpu_pmu)
> {
> return armv8_pmu_init(cpu_pmu, "armv8_cortex_a76",
> - armv8_pmuv3_map_event, NULL, NULL);
> + armv8_pmuv3_map_event, NULL, NULL, NULL);
> }
>
> static int armv8_a77_pmu_init(struct arm_pmu *cpu_pmu)
> {
> return armv8_pmu_init(cpu_pmu, "armv8_cortex_a77",
> - armv8_pmuv3_map_event, NULL, NULL);
> + armv8_pmuv3_map_event, NULL, NULL, NULL);
> }
>
> static int armv8_e1_pmu_init(struct arm_pmu *cpu_pmu)
> {
> return armv8_pmu_init(cpu_pmu, "armv8_neoverse_e1",
> - armv8_pmuv3_map_event, NULL, NULL);
> + armv8_pmuv3_map_event, NULL, NULL, NULL);
> }
>
> static int armv8_n1_pmu_init(struct arm_pmu *cpu_pmu)
> {
> return armv8_pmu_init(cpu_pmu, "armv8_neoverse_n1",
> - armv8_pmuv3_map_event, NULL, NULL);
> + armv8_pmuv3_map_event, NULL, NULL, NULL);
> }
>
> static int armv8_thunder_pmu_init(struct arm_pmu *cpu_pmu)
> {
> return armv8_pmu_init(cpu_pmu, "armv8_cavium_thunder",
> - armv8_thunder_map_event, NULL, NULL);
> + armv8_thunder_map_event, NULL, NULL, NULL);
> }
>
> static int armv8_vulcan_pmu_init(struct arm_pmu *cpu_pmu)
> {
> return armv8_pmu_init(cpu_pmu, "armv8_brcm_vulcan",
> - armv8_vulcan_map_event, NULL, NULL);
> + armv8_vulcan_map_event, NULL, NULL, NULL);
> }
>
> static const struct of_device_id armv8_pmu_of_device_ids[] = {
> diff --git a/include/linux/perf/arm_pmu.h b/include/linux/perf/arm_pmu.h
> index 5b616dde9a4c..1e129b57d51a 100644
> --- a/include/linux/perf/arm_pmu.h
> +++ b/include/linux/perf/arm_pmu.h
> @@ -73,6 +73,7 @@ enum armpmu_attr_groups {
> ARMPMU_ATTR_GROUP_COMMON,
> ARMPMU_ATTR_GROUP_EVENTS,
> ARMPMU_ATTR_GROUP_FORMATS,
> + ARMPMU_ATTR_GROUP_CAPS,
> ARMPMU_NR_ATTR_GROUPS
> };
>
>
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^ permalink raw reply [flat|nested] 6+ messages in thread