From: "Jason-JH Lin (林睿祥)" <Jason-JH.Lin@mediatek.com>
To: "Bibby Hsieh (謝濟遠)" <Bibby.Hsieh@mediatek.com>,
"chunkuang.hu@kernel.org" <chunkuang.hu@kernel.org>,
"djkurtz@chromium.org" <djkurtz@chromium.org>,
"Shawn Sung (宋孝謙)" <Shawn.Sung@mediatek.com>,
"Nancy Lin (林欣螢)" <Nancy.Lin@mediatek.com>,
"daniel@ffwll.ch" <daniel@ffwll.ch>,
"p.zabel@pengutronix.de" <p.zabel@pengutronix.de>,
"CK Hu (胡俊光)" <ck.hu@mediatek.com>,
"airlied@gmail.com" <airlied@gmail.com>,
"me@adamthiede.com" <me@adamthiede.com>,
"matthias.bgg@gmail.com" <matthias.bgg@gmail.com>,
"littlecvr@chromium.org" <littlecvr@chromium.org>,
"AngeloGioacchino Del Regno"
<angelogioacchino.delregno@collabora.com>
Cc: "YT Shen (沈岳霆)" <Yt.Shen@mediatek.com>,
"dri-devel@lists.freedesktop.org"
<dri-devel@lists.freedesktop.org>,
"linux-mediatek@lists.infradead.org"
<linux-mediatek@lists.infradead.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v3 13/14] drm/mediatek: Support DRM plane alpha in OVL
Date: Wed, 2 Oct 2024 07:50:25 +0000 [thread overview]
Message-ID: <272b47f0c9e27268d29b58c341e0b48bce7e8e25.camel@mediatek.com> (raw)
In-Reply-To: <5975b361-c1b4-4c57-89d4-0d247ae99d8c@adamthiede.com>
> >> > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> >> > > b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> >> > > index 943db4f1bd6b..4b370bc0746d 100644
> >> > > --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> >> > > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> >> > > @@ -458,8 +458,10 @@ void mtk_ovl_layer_config(struct device
> >> > > *dev, unsigned int idx,
> >> > > }
> >> > >
> >> > > con = ovl_fmt_convert(ovl, fmt);
> >> > > -if (state->base.fb && state->base.fb->format->has_alpha)
> >> > > -con |= OVL_CON_AEN | OVL_CON_ALPHA;
> >> > > +if (state->base.fb) {
> >> > > +con |= OVL_CON_AEN;
> >> > > +con |= state->base.alpha & OVL_CON_ALPHA;
> >
> > Hi Adam,
> >
> > Could you print out the "fmt", "state->base.fb->format-
> >>has_alpha", "state->base.alpha" and "con" here?
> >
> > pr_info("fmt:0x%x, has_alpha:0x%x, alpha:0x%x, con:0x%x \n",
> > fmt, state->base.fb->format->has_alpha,
> > state->base.alpha, con);
> >
> > I'm not sure if it's the color format setting problem, maybe there
> is
> > something wire configuration here, such as XRGB8888 with alpha or
> > ARGB8888 without alpha.
> >
> > So I want these information to compare with my MT8188. Thanks!
> >
> > Regards,
> > Jason-JH.Lin
> >
> Jason, thank you for your timely reply. I added the code you provided
> to
> my patch, and now get this line on endless repeat in dmesg:
>
> fmt:0x34325258, has_alpha:0x0, alpha:0xffff, con:0x2000
>
This function is used to configure the 4 OVL hardware layer per-frame,
so it may be called 4 times in every VSYNC. If your display device is
60fps, then this line would be called N layers times in every 16.66ms.
> This line also shows up sometimes in there, but I have no idea what
> triggers it.
>
> fmt:0x34325241, has_alpha:0x1, alpha:0xffff, con:0x21ff
>
From the DRM color format definition here:
https://elixir.bootlin.com/linux/v6.11.1/source/include/uapi/drm/drm_fourcc.h#L198
We can see the MACROs:
#define fourcc_code(a, b, c, d) \
(((uint32_t)(a) << 0) | ((uint32_t)(b) << 8) | \
((uint32_t)(c) << 16) | ((uint32_t)(d) << 24))
...
#define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4')
...
#define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4')
Given the fourcc_code macro as previously described,
the DRM_FORMAT_XRGB8888 macro would translate the characters
'X', 'R', '2', '4' into a 32-bit integer value, with each character
occupying 8 bits in the order from least significant byte to most
significant byte.
Here are the ASCII values for these characters:
'A' has an ASCII value of 65 (0x41)
'X' has an ASCII value of 88 (0x58)
'R' has an ASCII value of 82 (0x52)
'2' has an ASCII value of 50 (0x32)
'4' has an ASCII value of 52 (0x34)
Therefore, the integer value of XR24 with hex format would be:
0x34325258, and AR24 would be: 0x34325241
> Does that help?
>
> -Adam
Here is the translation from your logs :
fmt:0x34325258, has_alpha:0x0, alpha:0xffff, con:0x2000
- DRM color format=XRGB8888
- user set has_alpha=0
- user set alpha value=0xff
- configure value to OVL hardware=0x2000
fmt:0x34325241, has_alpha:0x1, alpha:0xffff, con:0x21ff
- DRM color format=ARGB8888
- user set has_alpha=1
- user set alpha value=0xff
- configure value to OVL hardware=0x21ff
Could you tell me in which log you can see and not see the text on the
tty?
Here is some of my analysis:
In original condition:
if (state->base.fb && state->base.fb->format->has_alpha)
con |= OVL_CON_AEN | OVL_CON_ALPHA;
- XRGB8888 will get con = 0x2000
- ARGB8888 will get con = 0x21ff
In current condition:
if (state->base.fb) {
con |= OVL_CON_AEN;
con |= state->base.alpha & OVL_CON_ALPHA;
}
- XRGB8888 will get con = 0x21ff
- ARGB8888 will get con = 0x21ff
But then XRGB8888 will set the ignore_pixel_alpha by the code below:
/* CONST_BLD must be enabled for XRGB formats although the alpha
channel
* can be ignored, or OVL will still read the value from memory.
* For RGB888 related formats, whether CONST_BLD is enabled or not
won't
* affect the result. Therefore we use !has_alpha as the condition.
*/
if ((state->base.fb && !state->base.fb->format->has_alpha) ||
blend_mode == DRM_MODE_BLEND_PIXEL_NONE)
ignore_pixel_alpha = OVL_CONST_BLEND;
Does your code include this patch?
https://patchwork.kernel.org/project/linux-mediatek/patch/20240620-igt-v3-3-a9d62d2e2c7e@mediatek.com/
If you have included this patch, I would then check with the OVL
hardware designers whether the MT8173 supports OVL_CONST_BLEND.
Regards,
Jason-JH.Lin
next prev parent reply other threads:[~2024-10-02 7:54 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-19 16:38 [PATCH v3 00/14] This series fixes the errors of MediaTek display driver found by IGT Hsiao Chien Sung via B4 Relay
2024-06-19 16:38 ` [PATCH v3 01/14] drm/mediatek: Add missing plane settings when async update Hsiao Chien Sung via B4 Relay
2024-06-19 16:38 ` [PATCH v3 02/14] drm/mediatek: Use 8-bit alpha in ETHDR Hsiao Chien Sung via B4 Relay
2024-06-19 16:38 ` [PATCH v3 03/14] drm/mediatek: Fix XRGB setting error in OVL Hsiao Chien Sung via B4 Relay
2024-06-19 16:38 ` [PATCH v3 04/14] drm/mediatek: Fix XRGB setting error in Mixer Hsiao Chien Sung via B4 Relay
2024-10-07 11:36 ` Markus Elfring
2024-10-09 6:27 ` Shawn Sung (宋孝謙)
2024-06-19 16:38 ` [PATCH v3 05/14] drm/mediatek: Fix destination alpha error in OVL Hsiao Chien Sung via B4 Relay
2024-06-19 16:38 ` [PATCH v3 06/14] drm/mediatek: Turn off the layers with zero width or height Hsiao Chien Sung via B4 Relay
2024-06-19 16:38 ` [PATCH v3 07/14] drm/mediatek: Add OVL compatible name for MT8195 Hsiao Chien Sung via B4 Relay
2024-06-19 16:38 ` [PATCH v3 08/14] drm/mediatek: Add DRM_MODE_ROTATE_0 to rotation property Hsiao Chien Sung via B4 Relay
2024-10-24 20:47 ` Doug Anderson
2024-10-25 1:32 ` Shawn Sung (宋孝謙)
2024-10-25 16:35 ` Doug Anderson
2024-10-26 4:10 ` Shawn Sung (宋孝謙)
2024-06-19 16:38 ` [PATCH v3 09/14] drm/mediatek: Add new color format MACROs in OVL Hsiao Chien Sung via B4 Relay
2024-06-19 16:38 ` [PATCH v3 10/14] drm/mediatek: Set DRM mode configs accordingly Hsiao Chien Sung via B4 Relay
2024-06-19 16:38 ` [PATCH v3 11/14] drm/mediatek: Support more 10bit formats in OVL Hsiao Chien Sung via B4 Relay
2024-06-19 16:38 ` [PATCH v3 12/14] drm/mediatek: Support RGBA8888 and RGBX8888 in OVL on MT8195 Hsiao Chien Sung via B4 Relay
2024-06-19 16:38 ` [PATCH v3 13/14] drm/mediatek: Support DRM plane alpha in OVL Hsiao Chien Sung via B4 Relay
2024-09-30 17:48 ` Adam Thiede
2024-10-01 8:55 ` CK Hu (胡俊光)
2024-10-01 18:02 ` Jason-JH Lin (林睿祥)
2024-10-01 19:51 ` Adam Thiede
2024-10-02 7:50 ` Jason-JH Lin (林睿祥) [this message]
2024-10-02 15:28 ` Adam Thiede
2024-10-03 5:17 ` Jason-JH Lin (林睿祥)
2024-10-03 15:29 ` Adam Thiede
2024-10-05 5:54 ` Yassine Oudjana
2024-10-05 6:33 ` Yassine Oudjana
2024-10-05 10:02 ` Jason-JH Lin (林睿祥)
2024-10-05 17:32 ` Adam Thiede
2024-10-07 7:22 ` Jason-JH Lin (林睿祥)
2024-10-07 10:54 ` Adam Thiede
2024-10-07 14:38 ` Jason-JH Lin (林睿祥)
2024-06-19 16:38 ` [PATCH v3 14/14] drm/mediatek: Support DRM plane alpha in Mixer Hsiao Chien Sung via B4 Relay
2024-06-20 14:16 ` [PATCH v3 00/14] This series fixes the errors of MediaTek display driver found by IGT Chun-Kuang Hu
2024-06-21 1:52 ` Shawn Sung (宋孝謙)
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