* [PATCH 1/2] arm64: dts: freescale: imx8-ss-dma: Fix edma3's location
@ 2023-12-19 12:34 Alexander Stein
2023-12-19 12:34 ` [PATCH 2/2] arm64: dts: imx8: Fix lpuart DMA channel order Alexander Stein
0 siblings, 1 reply; 4+ messages in thread
From: Alexander Stein @ 2023-12-19 12:34 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Fabio Estevam
Cc: Alexander Stein, Pengutronix Kernel Team, NXP Linux Team,
devicetree, linux-arm-kernel
Sort nodes by base address. edma3 comes later in the memory map.
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
---
.../arm64/boot/dts/freescale/imx8-ss-dma.dtsi | 46 +++++++++----------
1 file changed, 23 insertions(+), 23 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
index b0bb77150adc..a180893ac81e 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
@@ -192,29 +192,6 @@ edma2: dma-controller@5a1f0000 {
<&pd IMX_SC_R_DMA_2_CH15>;
};
- edma3: dma-controller@5a9f0000 {
- compatible = "fsl,imx8qm-edma";
- reg = <0x5a9f0000 0x90000>;
- #dma-cells = <3>;
- dma-channels = <8>;
- interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&pd IMX_SC_R_DMA_3_CH0>,
- <&pd IMX_SC_R_DMA_3_CH1>,
- <&pd IMX_SC_R_DMA_3_CH2>,
- <&pd IMX_SC_R_DMA_3_CH3>,
- <&pd IMX_SC_R_DMA_3_CH4>,
- <&pd IMX_SC_R_DMA_3_CH5>,
- <&pd IMX_SC_R_DMA_3_CH6>,
- <&pd IMX_SC_R_DMA_3_CH7>;
- };
-
spi0_lpcg: clock-controller@5a400000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5a400000 0x10000>;
@@ -460,6 +437,29 @@ flexcan3: can@5a8f0000 {
status = "disabled";
};
+ edma3: dma-controller@5a9f0000 {
+ compatible = "fsl,imx8qm-edma";
+ reg = <0x5a9f0000 0x90000>;
+ #dma-cells = <3>;
+ dma-channels = <8>;
+ interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&pd IMX_SC_R_DMA_3_CH0>,
+ <&pd IMX_SC_R_DMA_3_CH1>,
+ <&pd IMX_SC_R_DMA_3_CH2>,
+ <&pd IMX_SC_R_DMA_3_CH3>,
+ <&pd IMX_SC_R_DMA_3_CH4>,
+ <&pd IMX_SC_R_DMA_3_CH5>,
+ <&pd IMX_SC_R_DMA_3_CH6>,
+ <&pd IMX_SC_R_DMA_3_CH7>;
+ };
+
i2c0_lpcg: clock-controller@5ac00000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5ac00000 0x10000>;
--
2.34.1
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^ permalink raw reply related [flat|nested] 4+ messages in thread* [PATCH 2/2] arm64: dts: imx8: Fix lpuart DMA channel order
2023-12-19 12:34 [PATCH 1/2] arm64: dts: freescale: imx8-ss-dma: Fix edma3's location Alexander Stein
@ 2023-12-19 12:34 ` Alexander Stein
2024-01-29 17:17 ` Frank Li
0 siblings, 1 reply; 4+ messages in thread
From: Alexander Stein @ 2023-12-19 12:34 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Fabio Estevam
Cc: Alexander Stein, Pengutronix Kernel Team, NXP Linux Team,
devicetree, linux-arm-kernel
Bindings say DMA channels are in order Rx, Tx. Adjust the DT nodes
accordingly.
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
---
arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
index a180893ac81e..0f48796e32b2 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
@@ -93,8 +93,8 @@ lpuart0: serial@5a060000 {
assigned-clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <80000000>;
power-domains = <&pd IMX_SC_R_UART_0>;
- dma-names = "tx","rx";
- dmas = <&edma2 9 0 0>, <&edma2 8 0 1>;
+ dma-names = "rx", "tx";
+ dmas = <&edma2 8 0 0>, <&edma2 9 0 1>;
status = "disabled";
};
@@ -107,8 +107,8 @@ lpuart1: serial@5a070000 {
assigned-clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <80000000>;
power-domains = <&pd IMX_SC_R_UART_1>;
- dma-names = "tx","rx";
- dmas = <&edma2 11 0 0>, <&edma2 10 0 1>;
+ dma-names = "rx", "tx";
+ dmas = <&edma2 10 0 0>, <&edma2 11 0 1>;
status = "disabled";
};
@@ -121,8 +121,8 @@ lpuart2: serial@5a080000 {
assigned-clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <80000000>;
power-domains = <&pd IMX_SC_R_UART_2>;
- dma-names = "tx","rx";
- dmas = <&edma2 13 0 0>, <&edma2 12 0 1>;
+ dma-names = "rx", "tx";
+ dmas = <&edma2 12 0 0>, <&edma2 13 0 1>;
status = "disabled";
};
@@ -135,8 +135,8 @@ lpuart3: serial@5a090000 {
assigned-clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <80000000>;
power-domains = <&pd IMX_SC_R_UART_3>;
- dma-names = "tx","rx";
- dmas = <&edma2 15 0 0>, <&edma2 14 0 1>;
+ dma-names = "rx", "tx";
+ dmas = <&edma2 14 0 0>, <&edma2 15 0 1>;
status = "disabled";
};
--
2.34.1
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^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [PATCH 2/2] arm64: dts: imx8: Fix lpuart DMA channel order
2023-12-19 12:34 ` [PATCH 2/2] arm64: dts: imx8: Fix lpuart DMA channel order Alexander Stein
@ 2024-01-29 17:17 ` Frank Li
2024-02-06 7:50 ` Alexander Stein
0 siblings, 1 reply; 4+ messages in thread
From: Frank Li @ 2024-01-29 17:17 UTC (permalink / raw)
To: Alexander Stein
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Fabio Estevam, Pengutronix Kernel Team,
NXP Linux Team, devicetree, linux-arm-kernel
On Tue, Dec 19, 2023 at 01:34:39PM +0100, Alexander Stein wrote:
> Bindings say DMA channels are in order Rx, Tx. Adjust the DT nodes
> accordingly.
>
> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> ---
> arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi | 16 ++++++++--------
> 1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
> index a180893ac81e..0f48796e32b2 100644
> --- a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
> @@ -93,8 +93,8 @@ lpuart0: serial@5a060000 {
> assigned-clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>;
> assigned-clock-rates = <80000000>;
> power-domains = <&pd IMX_SC_R_UART_0>;
> - dma-names = "tx","rx";
> - dmas = <&edma2 9 0 0>, <&edma2 8 0 1>;
> + dma-names = "rx", "tx";
> + dmas = <&edma2 8 0 0>, <&edma2 9 0 1>;
edma device bind header file already merged.
Please include <dt-binding/dma/fsl-edma.h>
Change "1" to "FSL_EDMA_RX".
Frank
> status = "disabled";
> };
>
> @@ -107,8 +107,8 @@ lpuart1: serial@5a070000 {
> assigned-clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>;
> assigned-clock-rates = <80000000>;
> power-domains = <&pd IMX_SC_R_UART_1>;
> - dma-names = "tx","rx";
> - dmas = <&edma2 11 0 0>, <&edma2 10 0 1>;
> + dma-names = "rx", "tx";
> + dmas = <&edma2 10 0 0>, <&edma2 11 0 1>;
> status = "disabled";
> };
>
> @@ -121,8 +121,8 @@ lpuart2: serial@5a080000 {
> assigned-clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>;
> assigned-clock-rates = <80000000>;
> power-domains = <&pd IMX_SC_R_UART_2>;
> - dma-names = "tx","rx";
> - dmas = <&edma2 13 0 0>, <&edma2 12 0 1>;
> + dma-names = "rx", "tx";
> + dmas = <&edma2 12 0 0>, <&edma2 13 0 1>;
> status = "disabled";
> };
>
> @@ -135,8 +135,8 @@ lpuart3: serial@5a090000 {
> assigned-clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>;
> assigned-clock-rates = <80000000>;
> power-domains = <&pd IMX_SC_R_UART_3>;
> - dma-names = "tx","rx";
> - dmas = <&edma2 15 0 0>, <&edma2 14 0 1>;
> + dma-names = "rx", "tx";
> + dmas = <&edma2 14 0 0>, <&edma2 15 0 1>;
> status = "disabled";
> };
>
> --
> 2.34.1
>
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^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH 2/2] arm64: dts: imx8: Fix lpuart DMA channel order
2024-01-29 17:17 ` Frank Li
@ 2024-02-06 7:50 ` Alexander Stein
0 siblings, 0 replies; 4+ messages in thread
From: Alexander Stein @ 2024-02-06 7:50 UTC (permalink / raw)
To: Frank Li
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Fabio Estevam, Pengutronix Kernel Team,
NXP Linux Team, devicetree, linux-arm-kernel
Hi,
Am Montag, 29. Januar 2024, 18:17:37 CET schrieb Frank Li:
> On Tue, Dec 19, 2023 at 01:34:39PM +0100, Alexander Stein wrote:
> > Bindings say DMA channels are in order Rx, Tx. Adjust the DT nodes
> > accordingly.
> >
> > Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> > ---
> >
> > arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi | 16 ++++++++--------
> > 1 file changed, 8 insertions(+), 8 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
> > b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi index
> > a180893ac81e..0f48796e32b2 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
> > @@ -93,8 +93,8 @@ lpuart0: serial@5a060000 {
> >
> > assigned-clocks = <&clk IMX_SC_R_UART_0
IMX_SC_PM_CLK_PER>;
> > assigned-clock-rates = <80000000>;
> > power-domains = <&pd IMX_SC_R_UART_0>;
> >
> > - dma-names = "tx","rx";
> > - dmas = <&edma2 9 0 0>, <&edma2 8 0 1>;
> > + dma-names = "rx", "tx";
> > + dmas = <&edma2 8 0 0>, <&edma2 9 0 1>;
>
> edma device bind header file already merged.
> Please include <dt-binding/dma/fsl-edma.h>
>
> Change "1" to "FSL_EDMA_RX".
Thanks, I was not aware of that change. Meanwhile I noticed in my patch the
flags were not switched as well.
Best regards,
Alexander
> Frank
>
> > status = "disabled";
> >
> > };
> >
> > @@ -107,8 +107,8 @@ lpuart1: serial@5a070000 {
> >
> > assigned-clocks = <&clk IMX_SC_R_UART_1
IMX_SC_PM_CLK_PER>;
> > assigned-clock-rates = <80000000>;
> > power-domains = <&pd IMX_SC_R_UART_1>;
> >
> > - dma-names = "tx","rx";
> > - dmas = <&edma2 11 0 0>, <&edma2 10 0 1>;
> > + dma-names = "rx", "tx";
> > + dmas = <&edma2 10 0 0>, <&edma2 11 0 1>;
> >
> > status = "disabled";
> >
> > };
> >
> > @@ -121,8 +121,8 @@ lpuart2: serial@5a080000 {
> >
> > assigned-clocks = <&clk IMX_SC_R_UART_2
IMX_SC_PM_CLK_PER>;
> > assigned-clock-rates = <80000000>;
> > power-domains = <&pd IMX_SC_R_UART_2>;
> >
> > - dma-names = "tx","rx";
> > - dmas = <&edma2 13 0 0>, <&edma2 12 0 1>;
> > + dma-names = "rx", "tx";
> > + dmas = <&edma2 12 0 0>, <&edma2 13 0 1>;
> >
> > status = "disabled";
> >
> > };
> >
> > @@ -135,8 +135,8 @@ lpuart3: serial@5a090000 {
> >
> > assigned-clocks = <&clk IMX_SC_R_UART_3
IMX_SC_PM_CLK_PER>;
> > assigned-clock-rates = <80000000>;
> > power-domains = <&pd IMX_SC_R_UART_3>;
> >
> > - dma-names = "tx","rx";
> > - dmas = <&edma2 15 0 0>, <&edma2 14 0 1>;
> > + dma-names = "rx", "tx";
> > + dmas = <&edma2 14 0 0>, <&edma2 15 0 1>;
> >
> > status = "disabled";
> >
> > };
--
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^ permalink raw reply [flat|nested] 4+ messages in thread
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2023-12-19 12:34 [PATCH 1/2] arm64: dts: freescale: imx8-ss-dma: Fix edma3's location Alexander Stein
2023-12-19 12:34 ` [PATCH 2/2] arm64: dts: imx8: Fix lpuart DMA channel order Alexander Stein
2024-01-29 17:17 ` Frank Li
2024-02-06 7:50 ` Alexander Stein
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