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From: zl020895  <zl020895@163.com>
To: "Andy Shevchenko" <andriy.shevchenko@linux.intel.com>
Cc: longzhao@ambarella.com, "Arnd Bergmann" <arnd@arndb.de>,
	"Krzysztof Kozlowski" <krzk@kernel.org>,
	"Alexandre Belloni" <alexandre.belloni@bootlin.com>,
	soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
	"Rob Herring" <robh@kernel.org>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Michael Turquette" <mturquette@baylibre.com>,
	"Stephen Boyd" <sboyd@kernel.org>,
	"Jerome Brunet" <jbrunet@baylibre.com>,
	"Linus Walleij" <linusw@kernel.org>,
	"Bartosz Golaszewski" <brgl@kernel.org>,
	"Greg Kroah-Hartman" <gregkh@linuxfoundation.org>,
	"Jiri Slaby" <jirislaby@kernel.org>,
	"Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>,
	"Catalin Marinas" <catalin.marinas@arm.com>,
	"Will Deacon" <will@kernel.org>, "Lee Jones" <lee@kernel.org>,
	mfd@lists.linux.dev, devicetree@vger.kernel.org,
	linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org,
	linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re:Re: Re: [PATCH v7 12/15] pinctrl: ambarella: add CV75 pin controller
Date: Thu, 17 Sep 2026 20:55:15 +0800 (CST)	[thread overview]
Message-ID: <4bd10649.9ba9.1a0af6f7ffd.Coremail.zl020895@163.com> (raw)
In-Reply-To: <aqvbfCQ6cxfGYJeC@ashevche-desk.local>

Thanks, Andy.

PINCTRL_PINGROUP only carries pin numbers. The IOMUX alt is not the
pinctrl function: the same pin is in several groups with different
alts, and a few groups mix alts.

In v8 I will switch the group tables to PINCTRL_PINGROUP and pass a
per-pin alt array as group data for set_mux(). PINCTRL_PINFUNCTION
stays as it is.

Best regards,
Long Zhao

At 2026-09-17 20:22:20, "Andy Shevchenko" <andriy.shevchenko@linux.intel.com> wrote:
>On Thu, Sep 17, 2026 at 05:06:45PM +0800, zl020895 wrote:
>> Thanks for the review. The small comments will be in v8,
>> including pinconf set via regmap_assign_bits.
>> 
>> PINCTRL_PINGROUP does not fit here: groups carry
>> AMBA_PINMUX(pin, alt), not a pin-number list, so I will keep
>> CV75_GROUP.
>
>I didn't get. It takes a pin as a parameter and adds the function on top
>of it. It is a combo, but I think it still fits the purpose. Please, use
>existing data structure and a macro.
>
>> At 2026-09-16 18:49:58, "Andy Shevchenko" <andriy.shevchenko@linux.intel.com> wrote:
>> >On Tue, Sep 15, 2026 at 07:15:42PM +0800, Long Zhao via B4 Relay wrote:
>
>...
>
>> >> +#define AMBA_PINMUX(pin, alt)		(((alt) << 12) | (pin))
>> >> +#define AMBA_PINMUX_TO_PIN(mux)		((mux) & 0xfff)
>> >> +#define AMBA_PINMUX_TO_ALT(mux)		(((mux) >> 12) & 0x7)
>> >> +
>> >> +struct amb_pinmux_group {
>> >> +	const char *name;
>> >> +	const u32 *mux;
>> >> +	unsigned int nmux;
>> >> +};
>
>^^^ left for the context.
>
>
>-- 
>With Best Regards,
>Andy Shevchenko
>

  reply	other threads:[~2026-09-17 12:56 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-15 11:15 [PATCH v7 00/15] Ambarella CV75 SoC minimal bring-up Long Zhao via B4 Relay
2026-09-15 11:15 ` [PATCH v7 01/15] dt-bindings: arm: add Ambarella CV75 platforms Long Zhao via B4 Relay
2026-09-15 11:15 ` [PATCH v7 02/15] dt-bindings: mfd: syscon: add Ambarella CV75 secure scratchpad Long Zhao via B4 Relay
2026-09-15 11:15 ` [PATCH v7 03/15] dt-bindings: clock: add Ambarella CV75 RCT Long Zhao via B4 Relay
2026-09-15 11:15 ` [PATCH v7 04/15] dt-bindings: pinctrl: add Ambarella CV75 pinctrl Long Zhao via B4 Relay
2026-09-15 11:15 ` [PATCH v7 05/15] dt-bindings: gpio: pl061: add Ambarella CV75 variant Long Zhao via B4 Relay
2026-09-18  7:15   ` Krzysztof Kozlowski
2026-09-18  8:33     ` zl020895
2026-09-15 11:15 ` [PATCH v7 06/15] dt-bindings: serial: snps-dw-apb-uart: add ambarella,cv75-uart Long Zhao via B4 Relay
2026-09-15 11:15 ` [PATCH v7 07/15] clk: ambarella: add CV75 RCT clock controller Long Zhao via B4 Relay
2026-09-15 13:24   ` Uwe Kleine-König
2026-09-15 13:27   ` Andy Shevchenko
2026-09-15 11:15 ` [PATCH v7 08/15] gpiolib: regmap: add write_data_after_dir quirk Long Zhao via B4 Relay
2026-09-15 15:07   ` Andy Shevchenko
2026-09-16  4:47     ` zl020895
2026-09-20 22:02   ` Linus Walleij
2026-09-21  3:52     ` zl020895
2026-09-21 12:59   ` Michael Walle
2026-09-15 11:15 ` [PATCH v7 09/15] gpiolib: regmap: add gpio_regmap_get_chip() Long Zhao via B4 Relay
2026-09-15 15:30   ` Andy Shevchenko
2026-09-16  4:49     ` zl020895
2026-09-21 12:48   ` Michael Walle
2026-09-22  4:22     ` zl020895
2026-09-23  6:57       ` Michael Walle
2026-09-15 11:15 ` [PATCH v7 10/15] gpio: pl061: convert to gpio-regmap and a custom irqchip Long Zhao via B4 Relay
2026-09-16 10:21   ` Andy Shevchenko
2026-09-21 13:16   ` Michael Walle
2026-09-15 11:15 ` [PATCH v7 11/15] gpio: pl061: add Ambarella register-layout variant Long Zhao via B4 Relay
2026-09-16 10:51   ` Andy Shevchenko
2026-09-20 22:24   ` Linus Walleij
2026-09-15 11:15 ` [PATCH v7 12/15] pinctrl: ambarella: add CV75 pin controller Long Zhao via B4 Relay
2026-09-16 10:49   ` Andy Shevchenko
2026-09-17  9:06     ` zl020895
2026-09-17 12:22       ` Andy Shevchenko
2026-09-17 12:55         ` zl020895 [this message]
2026-09-15 11:15 ` [PATCH v7 13/15] serial: 8250_dw: add Ambarella CV75 quirks Long Zhao via B4 Relay
2026-09-15 11:47   ` Ilpo Järvinen
2026-09-15 13:21   ` Andy Shevchenko
2026-09-15 11:15 ` [PATCH v7 14/15] arm64: ambarella: add ARCH_AMBARELLA and CV75 EVK DT Long Zhao via B4 Relay
2026-09-15 11:15 ` [PATCH v7 15/15] MAINTAINERS: add ARM/AMBARELLA SoC support Long Zhao via B4 Relay
2026-09-16  9:14 ` [PATCH v7 00/15] Ambarella CV75 SoC minimal bring-up Bartosz Golaszewski
     [not found]   ` <CAD++jLnRL_s9zPNkSj2UnHWPx+QHAXV19DA7dEmGZu0AkxxyaA@mail.gmail.com>
2026-09-16 10:23     ` Andy Shevchenko
2026-09-16 11:01       ` zl020895
2026-09-16 15:20         ` Andy Shevchenko
2026-09-17  9:05           ` zl020895
2026-09-21 12:46 ` Michael Walle
2026-09-22  4:19   ` zl020895
2026-09-22  7:30 ` Linus Walleij
2026-09-22  8:43   ` zl020895
2026-09-22  8:52     ` Linus Walleij
2026-09-22  9:02       ` zl020895

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