From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: longzhao@ambarella.com
Cc: "Arnd Bergmann" <arnd@arndb.de>,
"Krzysztof Kozlowski" <krzk@kernel.org>,
"Alexandre Belloni" <alexandre.belloni@bootlin.com>,
soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Michael Turquette" <mturquette@baylibre.com>,
"Stephen Boyd" <sboyd@kernel.org>,
"Jerome Brunet" <jbrunet@baylibre.com>,
"Linus Walleij" <linusw@kernel.org>,
"Bartosz Golaszewski" <brgl@kernel.org>,
"Greg Kroah-Hartman" <gregkh@linuxfoundation.org>,
"Jiri Slaby" <jirislaby@kernel.org>,
"Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>,
"Catalin Marinas" <catalin.marinas@arm.com>,
"Will Deacon" <will@kernel.org>, "Long Zhao" <zl020895@163.com>,
"Lee Jones" <lee@kernel.org>,
mfd@lists.linux.dev, devicetree@vger.kernel.org,
linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org,
linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v7 12/15] pinctrl: ambarella: add CV75 pin controller
Date: Wed, 16 Sep 2026 13:49:58 +0300 [thread overview]
Message-ID: <aqp0VlwWotnuK9t7@ashevche-desk.local> (raw)
In-Reply-To: <20260915-cv75-v5-v7-12-3297d3fbc9c0@ambarella.com>
On Tue, Sep 15, 2026 at 07:15:42PM +0800, Long Zhao via B4 Relay wrote:
> Add an Ambarella pinmux-only pinctrl driver with CV75 function/group
> tables. GPIO is handled by the PL061 driver.
...
> +#define CV75_GROUP(_name) \
> + { \
> + .name = #_name, \
> + .mux = cv75_##_name##_pinmux, \
> + .nmux = ARRAY_SIZE(cv75_##_name##_pinmux), \
> + }
Can't we use PICTRL_PINGROUP()? Why not?
...
> +#define CV75_FUNCTION(_name) \
> + PINCTRL_PINFUNCTION(#_name, cv75_##_name##_groups, \
> + ARRAY_SIZE(cv75_##_name##_groups))
I would dare to make it a single line.
...
> +#include <linux/array_size.h>
> +#include <linux/bits.h>
> +#include <linux/device.h>
> +#include <linux/err.h>
> +#include <linux/errno.h>
I don't see the need to use errno.h, err.h provides the basic ones.
> +#include <linux/init.h>
> +#include <linux/io.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +#include <linux/slab.h>
> +#include <linux/spinlock.h>
> +#include <linux/types.h>
...
> +static void amb_pinmux_set_altfunc(struct amb_pinctrl *ipc, u32 bank,
> + u32 offset, u32 altfunc)
> +{
> + if (bank >= ipc->data->nr_banks)
> + return;
> +
> + for (unsigned int i = 0; i < 3; i++) {
> + u32 data;
> +
> + data = readl_relaxed(ipc->iomux_base + IOMUX_REG(bank, i));
> + data &= ~BIT(offset);
> + data |= ((altfunc >> i) & 1U) << offset;
data |= ((altfunc & BIT(i)) >> i) << offset;
Or even
unsigned long data;
...
__assign_bit(offset, &data, altfunc & BIT(i));
> + writel_relaxed(data, ipc->iomux_base + IOMUX_REG(bank, i));
> + }
> +}
...
> +static int amb_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
> + unsigned long *configs, unsigned int num_configs)
> +{
> + struct amb_pinctrl *ipc = pinctrl_dev_get_drvdata(pctldev);
> + u32 bank = PINID_TO_BANK(pin);
> + u32 offset = PINID_TO_OFFSET(pin);
> + int ret;
> +
> + if (bank >= ipc->data->nr_banks)
> + return -EINVAL;
> +
> + for (unsigned int i = 0; i < num_configs; i++) {
> + enum pin_config_param param = pinconf_to_config_param(configs[i]);
> + u32 arg = pinconf_to_config_argument(configs[i]);
> + int ds;
> +
> + switch (param) {
> + case PIN_CONFIG_BIAS_DISABLE:
> + ret = regmap_update_bits(ipc->pull_regmap,
> + ipc->data->pull_en[bank], BIT(offset), 0);
> + if (ret)
> + return ret;
> + break;
> + case PIN_CONFIG_BIAS_PULL_DOWN:
> + case PIN_CONFIG_BIAS_PULL_UP:
> + ret = regmap_update_bits(ipc->pull_regmap,
> + ipc->data->pull_dir[bank], BIT(offset),
> + (param == PIN_CONFIG_BIAS_PULL_UP) ?
> + BIT(offset) : 0);
_assign_bits()?
Ditto for the rest of the similar cases.
> + if (ret)
> + return ret;
> + ret = regmap_update_bits(ipc->pull_regmap,
> + ipc->data->pull_en[bank], BIT(offset),
> + BIT(offset));
> + if (ret)
> + return ret;
> + break;
> + case PIN_CONFIG_DRIVE_STRENGTH:
> + ds = amb_drive_strength_to_reg(ipc, arg);
> + if (ds < 0)
> + return ds;
> + if (ipc->data->have_ds2) {
> + ret = regmap_update_bits(ipc->ds_regmap,
> + ipc->data->ds0[bank], BIT(offset),
> + (ds & BIT(0)) ? BIT(offset) : 0);
> + if (ret)
> + return ret;
> + ret = regmap_update_bits(ipc->ds_regmap,
> + ipc->data->ds1[bank], BIT(offset),
> + (ds & BIT(1)) ? BIT(offset) : 0);
> + if (ret)
> + return ret;
> + ret = regmap_update_bits(ipc->ds_regmap,
> + ipc->data->ds2[bank], BIT(offset),
> + (ds & BIT(2)) ? BIT(offset) : 0);
> + if (ret)
> + return ret;
> + } else {
> + ret = regmap_update_bits(ipc->ds_regmap,
> + ipc->data->ds0[bank], BIT(offset),
> + (ds & BIT(1)) ? BIT(offset) : 0);
> + if (ret)
> + return ret;
> + ret = regmap_update_bits(ipc->ds_regmap,
> + ipc->data->ds1[bank], BIT(offset),
> + (ds & BIT(0)) ? BIT(offset) : 0);
> + if (ret)
> + return ret;
> + }
> + break;
> + default:
> + return -EOPNOTSUPP;
Is it indeed what we use in pin control? I think the correct one here is
ENOTSUPP (and in that case errno.h is required, yes). Yeah, some drivers
has a mixture and they probably didn't get how this error code is used.
> + }
> + }
> +
> + return 0;
> +}
...
> +static int amb_pinconf_get(struct pinctrl_dev *pctldev,
> + unsigned int pin, unsigned long *config)
> +{
> + struct amb_pinctrl *ipc = pinctrl_dev_get_drvdata(pctldev);
> + enum pin_config_param param = pinconf_to_config_param(*config);
> + u32 bank = PINID_TO_BANK(pin);
> + u32 offset = PINID_TO_OFFSET(pin);
> + u32 pull_en, pull_dir, ds0, ds1, ds2, ds;
> + int ret, strength;
> +
> + if (bank >= ipc->data->nr_banks)
> + return -EINVAL;
> +
> + switch (param) {
> + case PIN_CONFIG_BIAS_DISABLE:
> + case PIN_CONFIG_BIAS_PULL_DOWN:
> + case PIN_CONFIG_BIAS_PULL_UP:
> + ret = regmap_read(ipc->pull_regmap, ipc->data->pull_en[bank],
> + &pull_en);
> + if (ret)
> + return ret;
> +
> + ret = regmap_read(ipc->pull_regmap, ipc->data->pull_dir[bank],
> + &pull_dir);
> + if (ret)
> + return ret;
> + pull_en = (pull_en >> offset) & 1;
> + pull_dir = (pull_dir >> offset) & 1;
Seems to me they can be boolean?
In any case, use ' & BIT(offset)' instead of the above.
> + if (param == PIN_CONFIG_BIAS_DISABLE) {
> + if (pull_en)
> + return -EINVAL;
> + *config = pinconf_to_config_packed(param, 0);
> + return 0;
> + }
> +
> + if (!pull_en)
> + return -EINVAL;
> + if (param == PIN_CONFIG_BIAS_PULL_UP && !pull_dir)
> + return -EINVAL;
> + if (param == PIN_CONFIG_BIAS_PULL_DOWN && pull_dir)
> + return -EINVAL;
> +
> + *config = pinconf_to_config_packed(param, 1);
> + return 0;
> +
> + case PIN_CONFIG_DRIVE_STRENGTH:
> + ret = regmap_read(ipc->ds_regmap, ipc->data->ds0[bank], &ds0);
> + if (ret)
> + return ret;
> +
> + ret = regmap_read(ipc->ds_regmap, ipc->data->ds1[bank], &ds1);
> + if (ret)
> + return ret;
> +
> + ds0 = (ds0 >> offset) & 1;
> + ds1 = (ds1 >> offset) & 1;
> + if (ipc->data->have_ds2) {
> + ret = regmap_read(ipc->ds_regmap, ipc->data->ds2[bank],
> + &ds2);
> + if (ret)
> + return ret;
> +
> + ds2 = (ds2 >> offset) & 1;
> + ds = (ds2 << 2) | (ds1 << 1) | ds0;
> + } else {
> + ds = (ds0 << 1) | ds1;
> + }
Same here, use BIT(offset). For example,
ds2 = !!(ds2 & BIT(offset));
> + strength = amb_reg_to_drive_strength(ipc, ds);
> + if (strength < 0)
> + return strength;
> +
> + *config = pinconf_to_config_packed(param, strength);
> + return 0;
> +
> + default:
> + return -EOPNOTSUPP;
Same Q about the error code.
> + }
> +}
...
> + for (unsigned int pin = 0; pin < ipc->data->npins; pin++) {
> + pindesc[pin].number = pin;
> + pindesc[pin].name = devm_kasprintf(ipc->dev, GFP_KERNEL,
> + "io%u", pin);
> + if (!pindesc[pin].name)
> + return -ENOMEM;
> + }
Use devm_kasprintf_strarray().
...
> +static int amb_pinctrl_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct amb_pinctrl *ipc;
> + int ret;
> +
> + ipc = devm_kzalloc(dev, sizeof(*ipc), GFP_KERNEL);
> + if (!ipc)
> + return -ENOMEM;
> +
> + ipc->dev = dev;
> + ipc->data = device_get_match_data(dev);
> + if (!ipc->data)
> + return dev_err_probe(dev, -EINVAL, "missing SoC data\n");
-ENODATA
> + if (!ipc->data->nr_banks || ipc->data->nr_banks > AMBA_MAX_BANKS ||
> + !ipc->data->npins ||
> + !ipc->data->groups || !ipc->data->ngroups ||
> + !ipc->data->functions || !ipc->data->nfunctions)
> + return dev_err_probe(dev, -EINVAL, "invalid SoC data\n");
> +
> + ipc->iomux_base = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(ipc->iomux_base))
> + return PTR_ERR(ipc->iomux_base);
> +
> + ipc->ds_regmap = syscon_regmap_lookup_by_phandle(dev_of_node(dev),
> + "ambarella,drive-strength-syscon");
> + if (IS_ERR(ipc->ds_regmap))
> + return dev_err_probe(dev, PTR_ERR(ipc->ds_regmap),
> + "missing drive-strength syscon\n");
> +
> + ipc->pull_regmap = syscon_regmap_lookup_by_phandle(dev_of_node(dev),
> + "ambarella,pull-syscon");
> + if (IS_ERR(ipc->pull_regmap))
> + return dev_err_probe(dev, PTR_ERR(ipc->pull_regmap),
> + "missing pull syscon\n");
> +
> + spin_lock_init(&ipc->lock);
> +
> + ret = amb_pinctrl_register(ipc);
> + if (ret)
> + return dev_err_probe(dev, ret, "failed to register pinctrl\n");
> +
> + platform_set_drvdata(pdev, ipc);
> +
> + return 0;
> +}
...
> +#include <linux/types.h>
> +#include <linux/pinctrl/pinctrl.h>
Not really used. Can be replaced with forward declarations.
> +#define AMBA_MAX_BANKS 8
> +
> +#define AMBA_PINMUX(pin, alt) (((alt) << 12) | (pin))
> +#define AMBA_PINMUX_TO_PIN(mux) ((mux) & 0xfff)
> +#define AMBA_PINMUX_TO_ALT(mux) (((mux) >> 12) & 0x7)
> +
> +struct amb_pinmux_group {
> + const char *name;
> + const u32 *mux;
> + unsigned int nmux;
> +};
> +
> +struct amb_pinctrl_data {
> + const struct amb_pinmux_group *groups;
> + const struct pinfunction *functions;
> + unsigned int ngroups;
> + unsigned int nfunctions;
> + unsigned int nr_banks;
> + unsigned int npins;
> + unsigned int ds0[AMBA_MAX_BANKS];
> + unsigned int ds1[AMBA_MAX_BANKS];
> + unsigned int ds2[AMBA_MAX_BANKS];
> + unsigned int pull_en[AMBA_MAX_BANKS];
> + unsigned int pull_dir[AMBA_MAX_BANKS];
> + bool have_ds2;
> +};
> +
> +extern const struct amb_pinctrl_data ambarella_cv75_pinctrl_data;
--
With Best Regards,
Andy Shevchenko
next prev parent reply other threads:[~2026-09-16 10:50 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-15 11:15 [PATCH v7 00/15] Ambarella CV75 SoC minimal bring-up Long Zhao via B4 Relay
2026-09-15 11:15 ` [PATCH v7 01/15] dt-bindings: arm: add Ambarella CV75 platforms Long Zhao via B4 Relay
2026-09-15 11:15 ` [PATCH v7 02/15] dt-bindings: mfd: syscon: add Ambarella CV75 secure scratchpad Long Zhao via B4 Relay
2026-09-15 11:15 ` [PATCH v7 03/15] dt-bindings: clock: add Ambarella CV75 RCT Long Zhao via B4 Relay
2026-09-15 11:15 ` [PATCH v7 04/15] dt-bindings: pinctrl: add Ambarella CV75 pinctrl Long Zhao via B4 Relay
2026-09-15 11:15 ` [PATCH v7 05/15] dt-bindings: gpio: pl061: add Ambarella CV75 variant Long Zhao via B4 Relay
2026-09-18 7:15 ` Krzysztof Kozlowski
2026-09-18 8:33 ` zl020895
2026-09-15 11:15 ` [PATCH v7 06/15] dt-bindings: serial: snps-dw-apb-uart: add ambarella,cv75-uart Long Zhao via B4 Relay
2026-09-15 11:15 ` [PATCH v7 07/15] clk: ambarella: add CV75 RCT clock controller Long Zhao via B4 Relay
2026-09-15 13:24 ` Uwe Kleine-König
2026-09-15 13:27 ` Andy Shevchenko
2026-09-15 11:15 ` [PATCH v7 08/15] gpiolib: regmap: add write_data_after_dir quirk Long Zhao via B4 Relay
2026-09-15 15:07 ` Andy Shevchenko
2026-09-16 4:47 ` zl020895
2026-09-20 22:02 ` Linus Walleij
2026-09-21 3:52 ` zl020895
2026-09-21 12:59 ` Michael Walle
2026-09-15 11:15 ` [PATCH v7 09/15] gpiolib: regmap: add gpio_regmap_get_chip() Long Zhao via B4 Relay
2026-09-15 15:30 ` Andy Shevchenko
2026-09-16 4:49 ` zl020895
2026-09-21 12:48 ` Michael Walle
2026-09-22 4:22 ` zl020895
2026-09-23 6:57 ` Michael Walle
2026-09-15 11:15 ` [PATCH v7 10/15] gpio: pl061: convert to gpio-regmap and a custom irqchip Long Zhao via B4 Relay
2026-09-16 10:21 ` Andy Shevchenko
2026-09-21 13:16 ` Michael Walle
2026-09-15 11:15 ` [PATCH v7 11/15] gpio: pl061: add Ambarella register-layout variant Long Zhao via B4 Relay
2026-09-16 10:51 ` Andy Shevchenko
2026-09-20 22:24 ` Linus Walleij
2026-09-15 11:15 ` [PATCH v7 12/15] pinctrl: ambarella: add CV75 pin controller Long Zhao via B4 Relay
2026-09-16 10:49 ` Andy Shevchenko [this message]
2026-09-17 9:06 ` zl020895
2026-09-17 12:22 ` Andy Shevchenko
2026-09-17 12:55 ` zl020895
2026-09-15 11:15 ` [PATCH v7 13/15] serial: 8250_dw: add Ambarella CV75 quirks Long Zhao via B4 Relay
2026-09-15 11:47 ` Ilpo Järvinen
2026-09-15 13:21 ` Andy Shevchenko
2026-09-15 11:15 ` [PATCH v7 14/15] arm64: ambarella: add ARCH_AMBARELLA and CV75 EVK DT Long Zhao via B4 Relay
2026-09-15 11:15 ` [PATCH v7 15/15] MAINTAINERS: add ARM/AMBARELLA SoC support Long Zhao via B4 Relay
2026-09-16 9:14 ` [PATCH v7 00/15] Ambarella CV75 SoC minimal bring-up Bartosz Golaszewski
[not found] ` <CAD++jLnRL_s9zPNkSj2UnHWPx+QHAXV19DA7dEmGZu0AkxxyaA@mail.gmail.com>
2026-09-16 10:23 ` Andy Shevchenko
2026-09-16 11:01 ` zl020895
2026-09-16 15:20 ` Andy Shevchenko
2026-09-17 9:05 ` zl020895
2026-09-21 12:46 ` Michael Walle
2026-09-22 4:19 ` zl020895
2026-09-22 7:30 ` Linus Walleij
2026-09-22 8:43 ` zl020895
2026-09-22 8:52 ` Linus Walleij
2026-09-22 9:02 ` zl020895
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