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From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: Yabin Cui <yabinc@google.com>, Leo Yan <leo.yan@arm.com>
Cc: Mike Leach <mike.leach@linaro.org>,
	James Clark <james.clark@linaro.org>,
	Alexander Shishkin <alexander.shishkin@linux.intel.com>,
	coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 1/3] coresight: catu: Introduce refcount and spinlock for enabling/disabling
Date: Fri, 4 Apr 2025 10:46:24 +0100	[thread overview]
Message-ID: <69f3429a-57ba-4c02-b1a7-bbf95b2b19db@arm.com> (raw)
In-Reply-To: <CALJ9ZPMx7vqjgkn8OApLBAPwF35v=enHc07A==LXG0C+922rag@mail.gmail.com>

On 03/04/2025 18:53, Yabin Cui wrote:
> On Wed, Apr 2, 2025 at 6:01 AM Leo Yan <leo.yan@arm.com> wrote:
>>
>> Hi Yabin,
>>
>> On Tue, Apr 01, 2025 at 06:21:59PM -0700, Yabin Cui wrote:
>>
>> [...]
>>
>>>> @@ -486,12 +491,17 @@ static int catu_disable_hw(struct catu_drvdata *drvdata)
>>>>
>>>>   static int catu_disable(struct coresight_device *csdev, void *__unused)
>>>>   {
>>>> -       int rc;
>>>> +       int rc = 0;
>>>>          struct catu_drvdata *catu_drvdata = csdev_to_catu_drvdata(csdev);
>>>> +       guard(raw_spinlock_irqsave)(&catu_drvdata->spinlock);
>>>>
>>>> -       CS_UNLOCK(catu_drvdata->base);
>>>> -       rc = catu_disable_hw(catu_drvdata);
>>>> -       CS_LOCK(catu_drvdata->base);
>>>> +       if (--csdev->refcnt == 0) {
>>>> +               CS_UNLOCK(catu_drvdata->base);
>>>> +               rc = catu_disable_hw(catu_drvdata);
>>>> +               CS_LOCK(catu_drvdata->base);
>>>> +       } else {
>>>> +               rc = -EBUSY;
>>
>> This is not an error if the decremented reference counter is not zero.
>> It should return 0.  Otherwise, the change looks good to me.
> 
> In coresight_disable_helpers(), the return value of catu_disable()
> isn't checked.
> The -EBUSY return was used for consistency with other refcounted
> disable functions
> like tmc_disable_etf_sink() and tmc_disable_etr_sink(). I'm happy to
> change it back
> to 0 if you believe that would be the more accurate return value here.

Please stick to 0 here. This indicates there was no errors w.r.t the 
current session. This is similar to what we do for TMC ETR for e.g.

Suzuki


> 
>>
>> Thanks,
>> Leo



  reply	other threads:[~2025-04-04  9:55 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-04-02  1:18 [PATCH v2 0/3] coresight: catu: Introduce refcount and spinlock for enabling/disabling Yabin Cui
2025-04-02  1:18 ` [PATCH v2 1/3] " Yabin Cui
2025-04-02  1:21   ` Yabin Cui
2025-04-02 13:01     ` Leo Yan
2025-04-03 17:53       ` Yabin Cui
2025-04-04  9:46         ` Suzuki K Poulose [this message]
2025-04-02  1:18 ` [PATCH v2 2/3] coresight: catu: Prevent concurrent PERF and SYSFS mode enablement Yabin Cui
2025-04-02 13:47   ` Leo Yan
2025-04-03 17:58     ` Yabin Cui
2025-04-02  1:18 ` [PATCH v2 3/3] coresight: core: Disable helpers for devices that fail to enable Yabin Cui
2025-04-02  1:22   ` Yabin Cui
2025-04-02 13:32     ` Leo Yan
2025-04-02 13:50       ` Mike Leach
2025-04-02 14:12         ` Leo Yan
2025-04-03  0:53           ` Jie Gan
2025-04-03 18:28             ` Yabin Cui

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