Re: [PATCH] arm64: perf: Do not write event type for cycle counter

From: Julien Thierry <julien.thierry@arm.com>
To: Will Deacon <will.deacon@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>,
	Peter Zijlstra <peterz@infradead.org>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Jiri Olsa <jolsa@redhat.com>,
	Arnaldo Carvalho de Melo <acme@kernel.org>,
	Alexander Shishkin <alexander.shishkin@linux.intel.com>,
	Ingo Molnar <mingo@redhat.com>,
	huawei.libin@huawei.com, guohanjun@huawei.com,
	Namhyung Kim <namhyung@kernel.org>,
	liwei391@huawei.com, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH] arm64: perf: Do not write event type for cycle counter
Date: Wed, 3 Apr 2019 15:09:49 +0100	[thread overview]
Message-ID: <75317146-138f-bdab-e656-6c55bb067152@arm.com> (raw)
In-Reply-To: <20190403135405.GB16611@fuggles.cambridge.arm.com>

On 03/04/2019 14:54, Will Deacon wrote:
> On Wed, Apr 03, 2019 at 08:26:20AM +0100, Julien Thierry wrote:
>> On 03/04/2019 04:10, Mark Rutland wrote:
>>> On Tue, Apr 02, 2019 at 04:42:58PM +0100, Julien Thierry wrote:
>>>> On 01/04/2019 09:02, Mark Rutland wrote:
>>>>> On Thu, Mar 28, 2019 at 09:49:05AM +0000, Julien Thierry wrote:
>>>> Now, I'm thinking what we need is to use a different mask than
>>>> EVTYPE_MASK (one that excludes the event bits) when setting
>>>> PMCCFILTR_EL0, but still do that when enabling an event using the cycle
>>>> counter.
>>>>
>>>> Does that approach sound correct? Or am I missing something that would
>>>> allow us to only set that upon reset?
>>>
>>> That sounds right to me!
>>>
>>> It would perhaps be nicer if we could configure event->hwc.config_base to be
>>> the raw register value in all cases, but it looks like that's going to be more
>>> painful than special-casing the cycle counter here.
>>>
>>
>> Right, I'm gonna need to special case the cycle counter to adapt the
>> event type writing to this patch[1]. But since this is not as
>> critical/beneficial as I initially thought, I'll just incorporate the
>> special-casing to the PMU interrupt as NMI series.
> 
> I'm confused as to what we're actually fixing here. PMCCFILTR_EL0 and
> PMEVTYPER<n>_EL0 have the same layout, modulo some RES0 bits, so the
> existing code should work fine afaict.
> 
> What's the problem?
> 

None at the moment, I failed to realize that PMSELR did allow to select
the counter register. But issues start to arise once we try to replace
the "select + access" register with the "direct access" registers for
counter and evtype. But that is another story that fits into another
patch series.

Sorry for the confusion.

Thanks,

-- 
Julien Thierry

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