[PATCH 2/2] pxa: enable L2 if present in XSC3

[PATCH 2/2] pxa: enable L2 if present in XSC3

[Haojian Zhuang]

[PATCH 2/2] pxa: enable L2 if present in XSC3

[Eric Miao]

On Wed, Dec 30, 2009 at 3:28 PM, Haojian Zhuang
<haojian.zhuang@gmail.com> wrote:
> From 2c4a7d0e907df9a762c5c9f0ec48b3b7860e1f7c Mon Sep 17 00:00:00 2001
> From: Haojian Zhuang <haojian.zhuang@marvell.com>
> Date: Wed, 30 Dec 2009 10:02:57 -0500
> Subject: [PATCH] [ARM] pxa: enable L2 if present in XSC3
>
> Check whether L2 is present or not in XSC3. If it's present, enable L2
> immediately.
>
> Disabling L2 after L2 is enabled that would result in unpredicatable behavior
> of XSC3 processor.
>

You may want to enclose this with #ifdef CONFIG_CACHE_XSC3L2 .. #endif
at least, to allow L2 to remain disabled even if L2 is present.

> Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
> ---
> ?arch/arm/mm/proc-xsc3.S | ? ?5 +++++
> ?1 files changed, 5 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
> index 33515c2..8fbe21f 100644
> --- a/arch/arm/mm/proc-xsc3.S
> +++ b/arch/arm/mm/proc-xsc3.S
> @@ -406,6 +406,11 @@ __xsc3_setup:
>
> ? ? ? ?adr ? ? r5, xsc3_crval
> ? ? ? ?ldmia ? r5, {r5, r6}
> +
> + ? ? ? mrc ? ? p15, 1, r0, c0, c0, 1 ? ? ? ? ? @ get L2 present information
> + ? ? ? ands ? ?r0, r0, #0xf8
> + ? ? ? orrne ? r6, r6, #(1 << 26) ? ? ? ? ? ? ?@ enable L2 if present
> +
> ? ? ? ?mrc ? ? p15, 0, r0, c1, c0, 0 ? ? ? ? ? @ get control register
> ? ? ? ?bic ? ? r0, r0, r5 ? ? ? ? ? ? ? ? ? ? ?@ ..V. ..R. .... ..A.
> ? ? ? ?orr ? ? r0, r0, r6 ? ? ? ? ? ? ? ? ? ? ?@ ..VI Z..S .... .C.M (mmu)
> --
> 1.5.6.5
>

[PATCH 2/2] pxa: enable L2 if present in XSC3

[Haojian Zhuang]

On Wed, Dec 30, 2009 at 3:50 AM, Eric Miao <eric.y.miao@gmail.com> wrote:

>>
>> Check whether L2 is present or not in XSC3. If it's present, enable L2
>> immediately.
>>
>> Disabling L2 after L2 is enabled that would result in unpredicatable behavior
>> of XSC3 processor.
>>
>
> You may want to enclose this with #ifdef CONFIG_CACHE_XSC3L2 .. #endif
> at least, to allow L2 to remain disabled even if L2 is present.
>

Updated this patch.

Thanks
Haojian
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[PATCH 2/2] pxa: enable L2 if present in XSC3

[Nicolas Pitre]

On Wed, 30 Dec 2009, Eric Miao wrote:

> On Wed, Dec 30, 2009 at 3:28 PM, Haojian Zhuang
> <haojian.zhuang@gmail.com> wrote:
> > From 2c4a7d0e907df9a762c5c9f0ec48b3b7860e1f7c Mon Sep 17 00:00:00 2001
> > From: Haojian Zhuang <haojian.zhuang@marvell.com>
> > Date: Wed, 30 Dec 2009 10:02:57 -0500
> > Subject: [PATCH] [ARM] pxa: enable L2 if present in XSC3
> >
> > Check whether L2 is present or not in XSC3. If it's present, enable L2
> > immediately.
> >
> > Disabling L2 after L2 is enabled that would result in unpredicatable behavior
> > of XSC3 processor.
> >
> 
> You may want to enclose this with #ifdef CONFIG_CACHE_XSC3L2 .. #endif
> at least, to allow L2 to remain disabled even if L2 is present.

Also... might be a good idea to invalidate L2 before enabling it.


Nicolas

[PATCH 2/2] pxa: enable L2 if present in XSC3

[Haojian Zhuang]

On Wed, Dec 30, 2009 at 1:06 PM, Nicolas Pitre <nico@fluxnic.net> wrote:
> On Wed, 30 Dec 2009, Eric Miao wrote:
>
>> On Wed, Dec 30, 2009 at 3:28 PM, Haojian Zhuang
>> <haojian.zhuang@gmail.com> wrote:
>> > From 2c4a7d0e907df9a762c5c9f0ec48b3b7860e1f7c Mon Sep 17 00:00:00 2001
>> > From: Haojian Zhuang <haojian.zhuang@marvell.com>
>> > Date: Wed, 30 Dec 2009 10:02:57 -0500
>> > Subject: [PATCH] [ARM] pxa: enable L2 if present in XSC3
>> >
>> > Check whether L2 is present or not in XSC3. If it's present, enable L2
>> > immediately.
>> >
>> > Disabling L2 after L2 is enabled that would result in unpredicatable behavior
>> > of XSC3 processor.
>> >
>>
>> You may want to enclose this with #ifdef CONFIG_CACHE_XSC3L2 .. #endif
>> at least, to allow L2 to remain disabled even if L2 is present.
>
> Also... might be a good idea to invalidate L2 before enabling it.
>

XSC3 supports these L2 operations in below.
1) invalidate L2 cache line (parameter is MVA)
2) clean L2 cache line (parameter is MVA)
3) clean L2 cache line (parameter is set/way)
4) clean and invalidate L2 cache line (parameter is set/way)

The most important thing is we couldn't call these L2 operations while
L2 is disabled.

"The behavior of these operations is unpredictable if the L2 cache is
disabled. If the L2 is not present, these operations performs no-ops."

I copied above words from XSC3 core spec at here. My opinion is that
not perform any L2 operations if L2 is disabled.

Thanks
Haojian

[PATCH 2/2] pxa: enable L2 if present in XSC3

[Nicolas Pitre]

On Wed, 30 Dec 2009, Haojian Zhuang wrote:

> On Wed, Dec 30, 2009 at 1:06 PM, Nicolas Pitre <nico@fluxnic.net> wrote:
> > On Wed, 30 Dec 2009, Eric Miao wrote:
> >
> >> On Wed, Dec 30, 2009 at 3:28 PM, Haojian Zhuang
> >> <haojian.zhuang@gmail.com> wrote:
> >> > From 2c4a7d0e907df9a762c5c9f0ec48b3b7860e1f7c Mon Sep 17 00:00:00 2001
> >> > From: Haojian Zhuang <haojian.zhuang@marvell.com>
> >> > Date: Wed, 30 Dec 2009 10:02:57 -0500
> >> > Subject: [PATCH] [ARM] pxa: enable L2 if present in XSC3
> >> >
> >> > Check whether L2 is present or not in XSC3. If it's present, enable L2
> >> > immediately.
> >> >
> >> > Disabling L2 after L2 is enabled that would result in unpredicatable behavior
> >> > of XSC3 processor.
> >> >
> >>
> >> You may want to enclose this with #ifdef CONFIG_CACHE_XSC3L2 .. #endif
> >> at least, to allow L2 to remain disabled even if L2 is present.
> >
> > Also... might be a good idea to invalidate L2 before enabling it.
> >
> 
> XSC3 supports these L2 operations in below.
> 1) invalidate L2 cache line (parameter is MVA)
> 2) clean L2 cache line (parameter is MVA)
> 3) clean L2 cache line (parameter is set/way)
> 4) clean and invalidate L2 cache line (parameter is set/way)
> 
> The most important thing is we couldn't call these L2 operations while
> L2 is disabled.

Well... The idea behind invalidating L2 before enabling it is to make 
sure it doesn't contain random stuff.  But if this is impossible to 
perform while L2 is disabled then we can only assume it is always going 
to be in a coherent state when it is enabled.  Furthermore there is no 
way to only invalidate the entire L2.


Nicolas

[PATCH 2/2] pxa: enable L2 if present in XSC3

[Eric Miao]

On Wed, Dec 30, 2009 at 5:05 PM, Haojian Zhuang
<haojian.zhuang@gmail.com> wrote:
> On Wed, Dec 30, 2009 at 3:50 AM, Eric Miao <eric.y.miao@gmail.com> wrote:
>
>>>
>>> Check whether L2 is present or not in XSC3. If it's present, enable L2
>>> immediately.
>>>
>>> Disabling L2 after L2 is enabled that would result in unpredicatable behavior
>>> of XSC3 processor.
>>>
>>
>> You may want to enclose this with #ifdef CONFIG_CACHE_XSC3L2 .. #endif
>> at least, to allow L2 to remain disabled even if L2 is present.
>>
>
> Updated this patch.

Applied.