Why MSI is limited to 32 MSI's per device

Why MSI is limited to 32 MSI's per device

[valmiki]

Hi,

Why MSI interrupts are limited to 32 per device ?
We have 16 bit data, with which we can have 2^16 combinaitons of different
data, which in turn those many MSI vectors.

Other than increase in number interrupts to 2048 in MSI-X, what advantage we
get by using MSI-X over MSI.

I read MSI-X interrupts can be targeted to different CPU's in an SMP system.
why can't MSI interrupts can be targeted to different processors ?  


Thanks & Regards,
Valmiki
 

Why MSI is limited to 32 MSI's per device

[Mark Rutland]

On Tue, Jun 14, 2016 at 02:58:36PM +0000, valmiki wrote:
> Hi,
> 
> Why MSI interrupts are limited to 32 per device ?
> We have 16 bit data, with which we can have 2^16 combinaitons of different
> data, which in turn those many MSI vectors.

I assume you're specifically asking w.r.t. PCI.
 
Conventional PCI allowed devices to have up to 32 MSIs, no more. PCI
devices are only permitted to choose up to the low 5 bits of an MSI
payload. The remaining bits are shared by all MSIs.

> Other than increase in number interrupts to 2048 in MSI-X, what advantage we
> get by using MSI-X over MSI.

As alluded to below, MSI-X allows MSIs to be targeted at different
doorbell addresses, and provides full control of the payload of each
MSI.

There may be other gains that I am not aware of.

> I read MSI-X interrupts can be targeted to different CPU's in an SMP system.
> why can't MSI interrupts can be targeted to different processors ?  

Conventional PCI has a single doorbell address per device. I believe
that x86 had a doorbell per-cpu, and hence all MSIs for a device
targeted the same CPU. I'm not entirely certain on that, nor whether
things have changed.

Whether or not that holds elsewhere depends on your MSI controller and
IRQ controllers.

Thanks,
Mark.

Why MSI is limited to 32 MSI's per device

[valmiki]

Thanks a lot Mark.

I have one more doubt regarding MSI-X, why MSI-X table is maintained in end
points bar memory, why cant it be maintained/allocated in host memory ?

Thanks & Regards,
valmiki

Why MSI is limited to 32 MSI's per device

[Arnd Bergmann]

On Wednesday, June 15, 2016 6:39:53 AM CEST valmiki wrote:
> Thanks a lot Mark.
> 
> I have one more doubt regarding MSI-X, why MSI-X table is maintained in end
> points bar memory, why cant it be maintained/allocated in host memory ?

Making the device do a DMA read to fetch the MSI-X descriptor every time it
wants to send an interrupt message would add a serious overhead to very
time-critical operation. I don't think this is something the PCI SIG would
have considered.

	Arnd