Re: [boot-wrapper 3/3] aarch64: Enable access into RCW[S]MASK_EL1 registers from EL2 and below

[Anshuman Khandual <anshuman.khandual@arm.com>]

On 7/25/24 14:21, Mark Rutland wrote:
> On Tue, Jul 23, 2024 at 04:36:30PM +0530, Anshuman Khandual wrote:
>> FEAT_THE adds RCW[S]MASK_EL1 system registers. But access into these system
>> registers from EL2 and below trap to EL3 unless SCR_EL3.RCWMASKEn is set.
>>
>> Enable access to RCW[S]MASK_EL1 registers when they are implemented.
> 
> This looks fine.
> 
> IIUC we don't need to initialize these new registers as they only affect
> the behaviour of new instructions which we don't expect SW to use until
> privileged SW has configured these registers (as they reset to UNKNOWN
> values even at the highest implemented EL).

Right, will keep patch's position in the series unchanged as well.

> 
> Mark.
> 
>> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
>> ---
>>  arch/aarch64/include/asm/cpu.h | 2 ++
>>  arch/aarch64/init.c            | 3 +++
>>  2 files changed, 5 insertions(+)
>>
>> diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h
>> index 57d66e4..8404152 100644
>> --- a/arch/aarch64/include/asm/cpu.h
>> +++ b/arch/aarch64/include/asm/cpu.h
>> @@ -55,6 +55,7 @@
>>  #define SCR_EL3_TME			BIT(34)
>>  #define SCR_EL3_HXEn			BIT(38)
>>  #define SCR_EL3_EnTP2			BIT(41)
>> +#define SCR_EL3_RCWMASKEn		BIT(42)
>>  #define SCR_EL3_TCR2EN			BIT(43)
>>  #define SCR_EL3_SCTLR2En		BIT(44)
>>  #define SCR_EL3_PIEN			BIT(45)
>> @@ -92,6 +93,7 @@
>>  
>>  #define ID_AA64PFR1_EL1_MTE		BITS(11, 8)
>>  #define ID_AA64PFR1_EL1_SME		BITS(27, 24)
>> +#define ID_AA64PFR1_EL1_THE		BITS(51, 48)
>>  #define ID_AA64PFR0_EL1_SVE		BITS(35, 32)
>>  
>>  #define ID_AA64SMFR0_EL1		s3_0_c0_c4_5
>> diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c
>> index 5b21cb8..13a2339 100644
>> --- a/arch/aarch64/init.c
>> +++ b/arch/aarch64/init.c
>> @@ -95,6 +95,9 @@ void cpu_init_el3(void)
>>  	if (mrs_field(ID_AA64MMFR3_EL1, SCTLRX))
>>  		scr |= SCR_EL3_SCTLR2En;
>>  
>> +	if (mrs_field(ID_AA64PFR1_EL1, THE))
>> +		scr |= SCR_EL3_RCWMASKEn;
>> +
>>  	msr(SCR_EL3, scr);
>>  
>>  	msr(CPTR_EL3, cptr);
>> -- 
>> 2.25.1
>>