[PATCH 0/2] irqchip/gic-v5: Fix standalone IRSes OF driver probe and DT bindings

[PATCH 0/2] irqchip/gic-v5: Fix standalone IRSes OF driver probe and DT bindings

[Lorenzo Pieralisi]

The GICv5 architecture allows IRSes to be designed as standalone, ie with
no CPU connection, to support system topologies where the IRS is separated
from CPUs.

Current OF code fails the IRS probe if "cpus" and "arm,iaffids" properties,
that define IRS<->CPU connections, are missing (which goes against the
current schema because they are "required"), which is not correct for
the aforementioned reasons.

DT schema for GICv5 must be updated in that "cpus" and "arm,iaffids"
properties are currently defined as "required" which is not correct
(unless there is a way to keep them "required" and empty) and must
be relaxed.

I do not think it is possible to keep "cpus" and "arm,iaffids" as
"required" and allow them to be empty lists - I would need DT
maintainers feedback on that to see what is best.

I did not mark patches for stable kernels because I would like to get
feedback on the DT binding changes first before sending any change that
is potentially ABI changing back to stable kernels (strictly speaking
I do not think the DT changes can actually break anything - the only
potential issue is DT files that do declare "cpus" and "arm,iaffids" as
empty list against the schema - if they do that they are already broken
and this patchset changes nothing in that respect).

Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
---
Lorenzo Pieralisi (2):
      dt-bindings: interrupt-controller: gicv5: Relax IRS properties constraints
      irqchip/gic-v5: Fix standalone IRSes OF probe

 .../devicetree/bindings/interrupt-controller/arm,gic-v5.yaml     | 9 ++++++---
 drivers/irqchip/irq-gic-v5-irs.c                                 | 4 ++++
 2 files changed, 10 insertions(+), 3 deletions(-)
---
base-commit: cee9395acd8043be0644b25c34bfa86623f2b935
change-id: 20261014-gicv5-irs-no-cpus-8c5fba3f9940

Best regards,
--  
Lorenzo Pieralisi <lpieralisi@kernel.org>

[PATCH 1/2] dt-bindings: interrupt-controller: gicv5: Relax IRS properties constraints

[Lorenzo Pieralisi]

An IRS is architecturally allowed to be stand-alone (ie with no direct
CPU connection).

Relax "cpus" and "arm,iaffids" properties constraints allowing a standalone
IRS configuration.

Fixes: 7d7299bd07c6 ("dt-bindings: interrupt-controller: Add Arm GICv5")
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Cc: Rob Herring <robh@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
---
I have not marked the patch for stable though I think it should go
to stable kernels to fix the original schema. I am a bit nervous about
making cpus and arm,iaffids optional but I don't think there is a way
to keep them required and force them to be empty for an IRS with
no CPU connection.
---
 .../devicetree/bindings/interrupt-controller/arm,gic-v5.yaml     | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v5.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v5.yaml
index 86ca7f3ac281..b901e4288816 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v5.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v5.yaml
@@ -120,13 +120,14 @@ patternProperties:
 
       cpus:
         description:
-          CPUs managed by the IRS.
+          CPUs managed by the IRS. Omit it if the IRS has no associated CPUs.
 
       arm,iaffids:
         $ref: /schemas/types.yaml#/definitions/uint16-array
         description:
           Interrupt AFFinity ID (IAFFID) associated with the CPU whose
           CPU node phandle is at the same index in the cpus array.
+          Omit it if the IRS has no associated CPUs.
 
     patternProperties:
       "^its@[0-9a-f]+$":
@@ -210,12 +211,14 @@ patternProperties:
           - reg
           - reg-names
 
+    dependencies:
+      cpus: [ "arm,iaffids" ]
+      arm,iaffids: [ cpus ]
+
     required:
       - compatible
       - reg
       - reg-names
-      - cpus
-      - arm,iaffids
 
 additionalProperties: false
 

-- 
2.53.0

Re: [PATCH 1/2] dt-bindings: interrupt-controller: gicv5: Relax IRS properties constraints

[Lorenzo Pieralisi]

On Thu, Oct 15, 2026 at 10:20:25AM +0200, Lorenzo Pieralisi wrote:
> An IRS is architecturally allowed to be stand-alone (ie with no direct
> CPU connection).
> 
> Relax "cpus" and "arm,iaffids" properties constraints allowing a standalone
> IRS configuration.
> 
> Fixes: 7d7299bd07c6 ("dt-bindings: interrupt-controller: Add Arm GICv5")
> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
> Cc: Rob Herring <robh@kernel.org>
> Cc: Marc Zyngier <maz@kernel.org>
> ---
> I have not marked the patch for stable though I think it should go
> to stable kernels to fix the original schema. I am a bit nervous about
> making cpus and arm,iaffids optional but I don't think there is a way
> to keep them required and force them to be empty for an IRS with
> no CPU connection.

Hi Thomas, all,

I have noticed this is now queued into -tip (thanks), I would still appreciate
DT maintainers feedback though on the above and I still think that this must
go to stable kernels (I have not tagged the patches CC: stable as mentioned in
the cover letter but I believe the Fixes: tag will do ? If not I can send
them myself anyway).

Thanks,
Lorenzo

> ---
>  .../devicetree/bindings/interrupt-controller/arm,gic-v5.yaml     | 9 ++++++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v5.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v5.yaml
> index 86ca7f3ac281..b901e4288816 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v5.yaml
> +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v5.yaml
> @@ -120,13 +120,14 @@ patternProperties:
>  
>        cpus:
>          description:
> -          CPUs managed by the IRS.
> +          CPUs managed by the IRS. Omit it if the IRS has no associated CPUs.
>  
>        arm,iaffids:
>          $ref: /schemas/types.yaml#/definitions/uint16-array
>          description:
>            Interrupt AFFinity ID (IAFFID) associated with the CPU whose
>            CPU node phandle is at the same index in the cpus array.
> +          Omit it if the IRS has no associated CPUs.
>  
>      patternProperties:
>        "^its@[0-9a-f]+$":
> @@ -210,12 +211,14 @@ patternProperties:
>            - reg
>            - reg-names
>  
> +    dependencies:
> +      cpus: [ "arm,iaffids" ]
> +      arm,iaffids: [ cpus ]
> +
>      required:
>        - compatible
>        - reg
>        - reg-names
> -      - cpus
> -      - arm,iaffids
>  
>  additionalProperties: false
>  
> 
> -- 
> 2.53.0
> 

[PATCH 2/2] irqchip/gic-v5: Fix standalone IRSes OF probe

[Lorenzo Pieralisi]

An IRS is architecturally allowed to be standalone, namely, with no
direct CPUs connections. Make sure such configuration is allowed on
OF firmware by skipping "cpus" and "arm,iaffids" IRS node properties
parsing if they are not present so that the IRS configuration can
complete successfully.

Fixes: 5cb1b6dab2de ("irqchip/gic-v5: Add GICv5 IRS/SPI support")
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Cc: Sascha Bischoff <sascha.bischoff@arm.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Marc Zyngier <maz@kernel.org>
---
Please do not consider this patch before we agree on what's best
for DT bindings in patch 1, thanks.
---
 drivers/irqchip/irq-gic-v5-irs.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/irqchip/irq-gic-v5-irs.c b/drivers/irqchip/irq-gic-v5-irs.c
index b3feb6340b59..53639e6f85bd 100644
--- a/drivers/irqchip/irq-gic-v5-irs.c
+++ b/drivers/irqchip/irq-gic-v5-irs.c
@@ -609,6 +609,10 @@ static int __init gicv5_irs_of_init_affinity(struct device_node *node,
 	u16 iaffid_mask = GENMASK(iaffid_bits - 1, 0);
 	int ret, i, ncpus, niaffids;
 
+	/* An IRS is architecturally allowed to have no cpus associated with it */
+	if (!of_property_present(node, "cpus") && !of_property_present(node, "arm,iaffids"))
+		return 0;
+
 	ncpus = of_count_phandle_with_args(node, "cpus", NULL);
 	if (ncpus < 0)
 		return -EINVAL;

-- 
2.53.0

Re: [PATCH 0/2] irqchip/gic-v5: Fix standalone IRSes OF driver probe and DT bindings

[Sascha Bischoff]

On 15/10/2026 09:20, Lorenzo Pieralisi wrote:
> The GICv5 architecture allows IRSes to be designed as standalone, ie with
> no CPU connection, to support system topologies where the IRS is separated
> from CPUs.
> 
> Current OF code fails the IRS probe if "cpus" and "arm,iaffids" properties,
> that define IRS<->CPU connections, are missing (which goes against the
> current schema because they are "required"), which is not correct for
> the aforementioned reasons.
> 
> DT schema for GICv5 must be updated in that "cpus" and "arm,iaffids"
> properties are currently defined as "required" which is not correct
> (unless there is a way to keep them "required" and empty) and must
> be relaxed.
> 
> I do not think it is possible to keep "cpus" and "arm,iaffids" as
> "required" and allow them to be empty lists - I would need DT
> maintainers feedback on that to see what is best.
> 
> I did not mark patches for stable kernels because I would like to get
> feedback on the DT binding changes first before sending any change that
> is potentially ABI changing back to stable kernels (strictly speaking
> I do not think the DT changes can actually break anything - the only
> potential issue is DT files that do declare "cpus" and "arm,iaffids" as
> empty list against the schema - if they do that they are already broken
> and this patchset changes nothing in that respect).
> 
> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>

Thanks for fixing this issue, Lorenzo. It would be a shame if we 
couldn't describe all possible topologies!

These changes look good to me:

Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>

Thanks,
Sascha

> ---
> Lorenzo Pieralisi (2):
>        dt-bindings: interrupt-controller: gicv5: Relax IRS properties constraints
>        irqchip/gic-v5: Fix standalone IRSes OF probe
> 
>   .../devicetree/bindings/interrupt-controller/arm,gic-v5.yaml     | 9 ++++++---
>   drivers/irqchip/irq-gic-v5-irs.c                                 | 4 ++++
>   2 files changed, 10 insertions(+), 3 deletions(-)
> ---
> base-commit: cee9395acd8043be0644b25c34bfa86623f2b935
> change-id: 20261014-gicv5-irs-no-cpus-8c5fba3f9940
> 
> Best regards,
> --
> Lorenzo Pieralisi <lpieralisi@kernel.org>