* [PATCH] iommu/arm-smmu-qcom: Fix TTBR0 read
@ 2021-11-08 17:17 Rob Clark
2021-11-08 17:57 ` Bjorn Andersson
2021-12-14 15:18 ` Will Deacon
0 siblings, 2 replies; 3+ messages in thread
From: Rob Clark @ 2021-11-08 17:17 UTC (permalink / raw)
To: iommu
Cc: dri-devel, linux-arm-msm, freedreno, Rob Clark, Will Deacon,
Robin Murphy, Joerg Roedel, Bjorn Andersson, Jordan Crouse,
Sai Prakash Ranjan, Shawn Guo, Eric Anholt,
moderated list:ARM SMMU DRIVERS, open list
From: Rob Clark <robdclark@chromium.org>
It is a 64b register, lets not lose the upper bits.
Fixes: ab5df7b953d8 ("iommu/arm-smmu-qcom: Add an adreno-smmu-priv callback to get pagefault info")
Signed-off-by: Rob Clark <robdclark@chromium.org>
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index 55690af1b25d..c998960495b4 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -51,7 +51,7 @@ static void qcom_adreno_smmu_get_fault_info(const void *cookie,
info->fsynr1 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR1);
info->far = arm_smmu_cb_readq(smmu, cfg->cbndx, ARM_SMMU_CB_FAR);
info->cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(cfg->cbndx));
- info->ttbr0 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_TTBR0);
+ info->ttbr0 = arm_smmu_cb_readq(smmu, cfg->cbndx, ARM_SMMU_CB_TTBR0);
info->contextidr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_CONTEXTIDR);
}
--
2.31.1
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^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] iommu/arm-smmu-qcom: Fix TTBR0 read
2021-11-08 17:17 [PATCH] iommu/arm-smmu-qcom: Fix TTBR0 read Rob Clark
@ 2021-11-08 17:57 ` Bjorn Andersson
2021-12-14 15:18 ` Will Deacon
1 sibling, 0 replies; 3+ messages in thread
From: Bjorn Andersson @ 2021-11-08 17:57 UTC (permalink / raw)
To: Rob Clark
Cc: iommu, dri-devel, linux-arm-msm, freedreno, Rob Clark,
Will Deacon, Robin Murphy, Joerg Roedel, Jordan Crouse,
Sai Prakash Ranjan, Shawn Guo, Eric Anholt,
moderated list:ARM SMMU DRIVERS, open list
On Mon 08 Nov 09:17 PST 2021, Rob Clark wrote:
> From: Rob Clark <robdclark@chromium.org>
>
> It is a 64b register, lets not lose the upper bits.
>
> Fixes: ab5df7b953d8 ("iommu/arm-smmu-qcom: Add an adreno-smmu-priv callback to get pagefault info")
> Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Regards,
Bjorn
> ---
> drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> index 55690af1b25d..c998960495b4 100644
> --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> @@ -51,7 +51,7 @@ static void qcom_adreno_smmu_get_fault_info(const void *cookie,
> info->fsynr1 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR1);
> info->far = arm_smmu_cb_readq(smmu, cfg->cbndx, ARM_SMMU_CB_FAR);
> info->cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(cfg->cbndx));
> - info->ttbr0 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_TTBR0);
> + info->ttbr0 = arm_smmu_cb_readq(smmu, cfg->cbndx, ARM_SMMU_CB_TTBR0);
> info->contextidr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_CONTEXTIDR);
> }
>
> --
> 2.31.1
>
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^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] iommu/arm-smmu-qcom: Fix TTBR0 read
2021-11-08 17:17 [PATCH] iommu/arm-smmu-qcom: Fix TTBR0 read Rob Clark
2021-11-08 17:57 ` Bjorn Andersson
@ 2021-12-14 15:18 ` Will Deacon
1 sibling, 0 replies; 3+ messages in thread
From: Will Deacon @ 2021-12-14 15:18 UTC (permalink / raw)
To: Rob Clark, iommu
Cc: catalin.marinas, kernel-team, Will Deacon, Shawn Guo,
Robin Murphy, Sai Prakash Ranjan, open list, linux-arm-msm,
dri-devel, Rob Clark, Joerg Roedel, Jordan Crouse,
Bjorn Andersson, freedreno, Eric Anholt,
moderated list:ARM SMMU DRIVERS
On Mon, 8 Nov 2021 09:17:23 -0800, Rob Clark wrote:
> From: Rob Clark <robdclark@chromium.org>
>
> It is a 64b register, lets not lose the upper bits.
>
>
Applied to will (for-joerg/arm-smmu/updates), thanks!
[1/1] iommu/arm-smmu-qcom: Fix TTBR0 read
https://git.kernel.org/will/c/c31112fbd407
Cheers,
--
Will
https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev
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2021-11-08 17:17 [PATCH] iommu/arm-smmu-qcom: Fix TTBR0 read Rob Clark
2021-11-08 17:57 ` Bjorn Andersson
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