* [bootwrapper PATCH] aarch64: Recognize PAuth QARMA3
@ 2022-01-28 16:02 Vladimir Murzin
2022-02-01 12:19 ` Mark Rutland
0 siblings, 1 reply; 2+ messages in thread
From: Vladimir Murzin @ 2022-01-28 16:02 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: mark.rutland
QARMA3 is relaxed version of the QARMA5 algorithm which expected to
reduce the latency of calculation while still delivering a suitable
level of security.
Support for QARMA3 can be discovered via ID_AA64ISAR2_EL1 [1]
APA3, bits [15:12] Indicates whether the QARMA3 algorithm is
implemented in the PE for address authentication in
AArch64 state.
GPA3, bits [11:8] Indicates whether the QARMA3 algorithm is
implemented in the PE for generic code
authentication in AArch64 state.
[1] https://developer.arm.com/documentation/ddi0601/2021-12/AArch64-Registers/ID-AA64ISAR2-EL1--AArch64-Instruction-Set-Attribute-Register-2?lang=en
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
---
arch/aarch64/include/asm/cpu.h | 5 +++++
arch/aarch64/init.c | 14 +++++++++-----
2 files changed, 14 insertions(+), 5 deletions(-)
diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h
index 1be2d54..ce80b6e 100644
--- a/arch/aarch64/include/asm/cpu.h
+++ b/arch/aarch64/include/asm/cpu.h
@@ -63,6 +63,9 @@
#define ID_AA64ISAR1_EL1_GPA BITS(27, 24)
#define ID_AA64ISAR1_EL1_GPI BITS(31, 28)
+#define ID_AA64ISAR2_EL1_GPA3 BITS(11, 8)
+#define ID_AA64ISAR2_EL1_APA3 BITS(15, 12)
+
#define ID_AA64MMFR0_EL1_FGT BITS(59, 56)
#define ID_AA64MMFR0_EL1_ECV BITS(63, 60)
@@ -104,6 +107,8 @@
#define ZCR_EL3 s3_6_c1_c2_0
#define ZCR_EL3_LEN_MAX 0xf
+#define ID_AA64ISAR2_EL1 s3_0_c0_c6_2
+
#define SCTLR_EL1_CP15BEN (1 << 5)
#ifdef KERNEL_32
diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c
index 6677f2b..aa58567 100644
--- a/arch/aarch64/init.c
+++ b/arch/aarch64/init.c
@@ -30,12 +30,16 @@ static inline bool kernel_is_32bit(void)
static inline bool cpu_has_pauth(void)
{
- const unsigned long id_pauth = ID_AA64ISAR1_EL1_APA |
- ID_AA64ISAR1_EL1_API |
- ID_AA64ISAR1_EL1_GPA |
- ID_AA64ISAR1_EL1_GPI;
+ const unsigned long isar1_pauth = ID_AA64ISAR1_EL1_APA |
+ ID_AA64ISAR1_EL1_API |
+ ID_AA64ISAR1_EL1_GPA |
+ ID_AA64ISAR1_EL1_GPI;
- return mrs(ID_AA64ISAR1_EL1) & id_pauth;
+ const unsigned long isar2_pauth = ID_AA64ISAR2_EL1_APA3 |
+ ID_AA64ISAR2_EL1_GPA3;
+
+ return (mrs(ID_AA64ISAR1_EL1) & isar1_pauth) ||
+ (mrs(ID_AA64ISAR2_EL1) & isar2_pauth);
}
void cpu_init_el3(void)
--
2.7.4
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^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [bootwrapper PATCH] aarch64: Recognize PAuth QARMA3
2022-01-28 16:02 [bootwrapper PATCH] aarch64: Recognize PAuth QARMA3 Vladimir Murzin
@ 2022-02-01 12:19 ` Mark Rutland
0 siblings, 0 replies; 2+ messages in thread
From: Mark Rutland @ 2022-02-01 12:19 UTC (permalink / raw)
To: Vladimir Murzin; +Cc: linux-arm-kernel
On Fri, Jan 28, 2022 at 04:02:14PM +0000, Vladimir Murzin wrote:
> QARMA3 is relaxed version of the QARMA5 algorithm which expected to
> reduce the latency of calculation while still delivering a suitable
> level of security.
>
> Support for QARMA3 can be discovered via ID_AA64ISAR2_EL1 [1]
>
> APA3, bits [15:12] Indicates whether the QARMA3 algorithm is
> implemented in the PE for address authentication in
> AArch64 state.
>
> GPA3, bits [11:8] Indicates whether the QARMA3 algorithm is
> implemented in the PE for generic code
> authentication in AArch64 state.
>
> [1] https://developer.arm.com/documentation/ddi0601/2021-12/AArch64-Registers/ID-AA64ISAR2-EL1--AArch64-Instruction-Set-Attribute-Register-2?lang=en
>
> Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Thanks; applied.
Mark.
> ---
> arch/aarch64/include/asm/cpu.h | 5 +++++
> arch/aarch64/init.c | 14 +++++++++-----
> 2 files changed, 14 insertions(+), 5 deletions(-)
>
> diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h
> index 1be2d54..ce80b6e 100644
> --- a/arch/aarch64/include/asm/cpu.h
> +++ b/arch/aarch64/include/asm/cpu.h
> @@ -63,6 +63,9 @@
> #define ID_AA64ISAR1_EL1_GPA BITS(27, 24)
> #define ID_AA64ISAR1_EL1_GPI BITS(31, 28)
>
> +#define ID_AA64ISAR2_EL1_GPA3 BITS(11, 8)
> +#define ID_AA64ISAR2_EL1_APA3 BITS(15, 12)
> +
> #define ID_AA64MMFR0_EL1_FGT BITS(59, 56)
> #define ID_AA64MMFR0_EL1_ECV BITS(63, 60)
>
> @@ -104,6 +107,8 @@
> #define ZCR_EL3 s3_6_c1_c2_0
> #define ZCR_EL3_LEN_MAX 0xf
>
> +#define ID_AA64ISAR2_EL1 s3_0_c0_c6_2
> +
> #define SCTLR_EL1_CP15BEN (1 << 5)
>
> #ifdef KERNEL_32
> diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c
> index 6677f2b..aa58567 100644
> --- a/arch/aarch64/init.c
> +++ b/arch/aarch64/init.c
> @@ -30,12 +30,16 @@ static inline bool kernel_is_32bit(void)
>
> static inline bool cpu_has_pauth(void)
> {
> - const unsigned long id_pauth = ID_AA64ISAR1_EL1_APA |
> - ID_AA64ISAR1_EL1_API |
> - ID_AA64ISAR1_EL1_GPA |
> - ID_AA64ISAR1_EL1_GPI;
> + const unsigned long isar1_pauth = ID_AA64ISAR1_EL1_APA |
> + ID_AA64ISAR1_EL1_API |
> + ID_AA64ISAR1_EL1_GPA |
> + ID_AA64ISAR1_EL1_GPI;
>
> - return mrs(ID_AA64ISAR1_EL1) & id_pauth;
> + const unsigned long isar2_pauth = ID_AA64ISAR2_EL1_APA3 |
> + ID_AA64ISAR2_EL1_GPA3;
> +
> + return (mrs(ID_AA64ISAR1_EL1) & isar1_pauth) ||
> + (mrs(ID_AA64ISAR2_EL1) & isar2_pauth);
> }
>
> void cpu_init_el3(void)
> --
> 2.7.4
>
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