* mx93: No cache hierachy definitions for ARM cores
@ 2024-07-17 17:49 Stefan Wahren
2024-07-19 2:38 ` Fabio Estevam
0 siblings, 1 reply; 8+ messages in thread
From: Stefan Wahren @ 2024-07-17 17:49 UTC (permalink / raw)
To: Peng Fan, Fabio Estevam, Shawn Guo, Sascha Hauer
Cc: imx, Pengutronix Kernel Team, Linux ARM
Hi,
today i noticed that imx93.dtsi lacks the cache definitions for the
Cortex-A55 cores:
cacheinfo: Unable to detect cache hierarchy for CPU 0
Maybe someone with more insight can add this to the imx93.dtsi file.
Best regards
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: mx93: No cache hierachy definitions for ARM cores
2024-07-17 17:49 mx93: No cache hierachy definitions for ARM cores Stefan Wahren
@ 2024-07-19 2:38 ` Fabio Estevam
2024-07-19 4:40 ` Stefan Wahren
2024-07-19 14:52 ` Frank Li
0 siblings, 2 replies; 8+ messages in thread
From: Fabio Estevam @ 2024-07-19 2:38 UTC (permalink / raw)
To: Stefan Wahren, Frank Li
Cc: Peng Fan, Shawn Guo, Sascha Hauer, imx, Pengutronix Kernel Team,
Linux ARM
On Wed, Jul 17, 2024 at 2:49 PM Stefan Wahren <wahrenst@gmx.net> wrote:
>
> Hi,
> today i noticed that imx93.dtsi lacks the cache definitions for the
> Cortex-A55 cores:
>
> cacheinfo: Unable to detect cache hierarchy for CPU 0
>
> Maybe someone with more insight can add this to the imx93.dtsi file.
Frank, can you help?
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: mx93: No cache hierachy definitions for ARM cores
2024-07-19 2:38 ` Fabio Estevam
@ 2024-07-19 4:40 ` Stefan Wahren
2024-07-19 14:52 ` Frank Li
1 sibling, 0 replies; 8+ messages in thread
From: Stefan Wahren @ 2024-07-19 4:40 UTC (permalink / raw)
To: Fabio Estevam, Frank Li
Cc: Peng Fan, Shawn Guo, Sascha Hauer, imx, Pengutronix Kernel Team,
Linux ARM
Hi,
Am 19.07.24 um 04:38 schrieb Fabio Estevam:
> On Wed, Jul 17, 2024 at 2:49 PM Stefan Wahren <wahrenst@gmx.net> wrote:
>> Hi,
>> today i noticed that imx93.dtsi lacks the cache definitions for the
>> Cortex-A55 cores:
>>
>> cacheinfo: Unable to detect cache hierarchy for CPU 0
>>
>> Maybe someone with more insight can add this to the imx93.dtsi file.
> Frank, can you help?
>
the description for caches can be found in the device tree spezification
[1]. AFAIK there is no specific binding in the kernel documentation.
Maybe a good example for reference would be [2].
Regards
[1] - https://github.com/devicetree-org/devicetree-specification
[2] -
https://elixir.bootlin.com/linux/v6.10/source/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: mx93: No cache hierachy definitions for ARM cores
2024-07-19 2:38 ` Fabio Estevam
2024-07-19 4:40 ` Stefan Wahren
@ 2024-07-19 14:52 ` Frank Li
2024-07-24 9:48 ` Stefan Wahren
1 sibling, 1 reply; 8+ messages in thread
From: Frank Li @ 2024-07-19 14:52 UTC (permalink / raw)
To: Fabio Estevam, peng.fan, peng.fan
Cc: Stefan Wahren, Peng Fan, Shawn Guo, Sascha Hauer, imx,
Pengutronix Kernel Team, Linux ARM
On Thu, Jul 18, 2024 at 11:38:20PM -0300, Fabio Estevam wrote:
> On Wed, Jul 17, 2024 at 2:49 PM Stefan Wahren <wahrenst@gmx.net> wrote:
> >
> > Hi,
> > today i noticed that imx93.dtsi lacks the cache definitions for the
> > Cortex-A55 cores:
> >
> > cacheinfo: Unable to detect cache hierarchy for CPU 0
> >
> > Maybe someone with more insight can add this to the imx93.dtsi file.
>
> Frank, can you help?
Peng:
Some informatin missed at public RM. Can you help this? I found
it also missed in internal tree.
Frank
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: mx93: No cache hierachy definitions for ARM cores
2024-07-19 14:52 ` Frank Li
@ 2024-07-24 9:48 ` Stefan Wahren
2024-07-24 14:34 ` Sudeep Holla
0 siblings, 1 reply; 8+ messages in thread
From: Stefan Wahren @ 2024-07-24 9:48 UTC (permalink / raw)
To: Frank Li, Fabio Estevam, peng.fan, peng.fan
Cc: Shawn Guo, Sascha Hauer, imx, Pengutronix Kernel Team, Linux ARM
Hi Frank,
Am 19.07.24 um 16:52 schrieb Frank Li:
> On Thu, Jul 18, 2024 at 11:38:20PM -0300, Fabio Estevam wrote:
>> On Wed, Jul 17, 2024 at 2:49 PM Stefan Wahren <wahrenst@gmx.net> wrote:
>>> Hi,
>>> today i noticed that imx93.dtsi lacks the cache definitions for the
>>> Cortex-A55 cores:
>>>
>>> cacheinfo: Unable to detect cache hierarchy for CPU 0
>>>
>>> Maybe someone with more insight can add this to the imx93.dtsi file.
>> Frank, can you help?
> Peng:
> Some informatin missed at public RM. Can you help this? I found
> it also missed in internal tree.
does the official ARM documentation [1] provide the missing information?
[1] - https://developer.arm.com/documentation/101051/0101
>
> Frank
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: mx93: No cache hierachy definitions for ARM cores
2024-07-24 9:48 ` Stefan Wahren
@ 2024-07-24 14:34 ` Sudeep Holla
2024-07-24 15:55 ` Stefan Wahren
0 siblings, 1 reply; 8+ messages in thread
From: Sudeep Holla @ 2024-07-24 14:34 UTC (permalink / raw)
To: Stefan Wahren
Cc: Frank Li, Fabio Estevam, peng.fan, peng.fan, Sudeep Holla,
Shawn Guo, Sascha Hauer, imx, Pengutronix Kernel Team, Linux ARM
On Wed, Jul 24, 2024 at 11:48:13AM +0200, Stefan Wahren wrote:
> Hi Frank,
>
> Am 19.07.24 um 16:52 schrieb Frank Li:
> > On Thu, Jul 18, 2024 at 11:38:20PM -0300, Fabio Estevam wrote:
> > > On Wed, Jul 17, 2024 at 2:49 PM Stefan Wahren <wahrenst@gmx.net> wrote:
> > > > Hi,
> > > > today i noticed that imx93.dtsi lacks the cache definitions for the
> > > > Cortex-A55 cores:
> > > >
> > > > cacheinfo: Unable to detect cache hierarchy for CPU 0
> > > >
> > > > Maybe someone with more insight can add this to the imx93.dtsi file.
> > > Frank, can you help?
> > Peng:
> > Some informatin missed at public RM. Can you help this? I found
> > it also missed in internal tree.
> does the official ARM documentation [1] provide the missing information?
>
> [1] - https://developer.arm.com/documentation/101051/0101
I assume you meant [2] instead of [1], as Cortex A55 and M55 are different.
--
Regards,
Sudeep
[2] https://developer.arm.com/documentation/100442/0200/
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: mx93: No cache hierachy definitions for ARM cores
2024-07-24 14:34 ` Sudeep Holla
@ 2024-07-24 15:55 ` Stefan Wahren
2024-08-01 2:52 ` Peng Fan
0 siblings, 1 reply; 8+ messages in thread
From: Stefan Wahren @ 2024-07-24 15:55 UTC (permalink / raw)
To: Sudeep Holla
Cc: Frank Li, Fabio Estevam, peng.fan, peng.fan, Shawn Guo,
Sascha Hauer, imx, Pengutronix Kernel Team, Linux ARM
Am 24.07.24 um 16:34 schrieb Sudeep Holla:
> On Wed, Jul 24, 2024 at 11:48:13AM +0200, Stefan Wahren wrote:
>> Hi Frank,
>>
>> Am 19.07.24 um 16:52 schrieb Frank Li:
>>> On Thu, Jul 18, 2024 at 11:38:20PM -0300, Fabio Estevam wrote:
>>>> On Wed, Jul 17, 2024 at 2:49 PM Stefan Wahren <wahrenst@gmx.net> wrote:
>>>>> Hi,
>>>>> today i noticed that imx93.dtsi lacks the cache definitions for the
>>>>> Cortex-A55 cores:
>>>>>
>>>>> cacheinfo: Unable to detect cache hierarchy for CPU 0
>>>>>
>>>>> Maybe someone with more insight can add this to the imx93.dtsi file.
>>>> Frank, can you help?
>>> Peng:
>>> Some informatin missed at public RM. Can you help this? I found
>>> it also missed in internal tree.
>> does the official ARM documentation [1] provide the missing information?
>>
>> [1] - https://developer.arm.com/documentation/101051/0101
> I assume you meant [2] instead of [1], as Cortex A55 and M55 are different.
Sorry, you are absolutely right.
>
> --
> Regards,
> Sudeep
>
> [2] https://developer.arm.com/documentation/100442/0200/
^ permalink raw reply [flat|nested] 8+ messages in thread
* RE: mx93: No cache hierachy definitions for ARM cores
2024-07-24 15:55 ` Stefan Wahren
@ 2024-08-01 2:52 ` Peng Fan
0 siblings, 0 replies; 8+ messages in thread
From: Peng Fan @ 2024-08-01 2:52 UTC (permalink / raw)
To: Stefan Wahren, Sudeep Holla
Cc: Frank Li, Fabio Estevam, Peng Fan (OSS), Shawn Guo, Sascha Hauer,
imx@lists.linux.dev, Pengutronix Kernel Team, Linux ARM
> Subject: Re: mx93: No cache hierachy definitions for ARM cores
>
> Am 24.07.24 um 16:34 schrieb Sudeep Holla:
> > On Wed, Jul 24, 2024 at 11:48:13AM +0200, Stefan Wahren wrote:
> >> Hi Frank,
> >>
> >> Am 19.07.24 um 16:52 schrieb Frank Li:
> >>> On Thu, Jul 18, 2024 at 11:38:20PM -0300, Fabio Estevam wrote:
> >>>> On Wed, Jul 17, 2024 at 2:49 PM Stefan Wahren
> <wahrenst@gmx.net> wrote:
> >>>>> Hi,
> >>>>> today i noticed that imx93.dtsi lacks the cache definitions for
> >>>>> the
> >>>>> Cortex-A55 cores:
> >>>>>
> >>>>> cacheinfo: Unable to detect cache hierarchy for CPU 0
> >>>>>
> >>>>> Maybe someone with more insight can add this to the
> imx93.dtsi file.
> >>>> Frank, can you help?
> >>> Peng:
> >>> Some informatin missed at public RM. Can you help this? I
> found it
> >>> also missed in internal tree.
> >> does the official ARM documentation [1] provide the missing
> information?
ARM provides several cache options for vendor to choose. I will give
a look and post a patch for i.MX93 A55 cache info.
Regards,
Peng.
> >>
> >> [1] -
> >> rved=0
> > I assume you meant [2] instead of [1], as Cortex A55 and M55 are
> different.
> Sorry, you are absolutely right.
> >
> > --
> > Regards,
> > Sudeep
> >
> > [2]
> >
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2F
> deve
> >
> loper.arm.com%2Fdocumentation%2F100442%2F0200%2F&data=05%
> 7C02%7Cpeng.f
> >
> an%40nxp.com%7C4bbe72bc89434c01562208dcabf90c5f%7C686ea1
> d3bc2b4c6fa92c
> >
> d99c5c301635%7C0%7C0%7C638574333341297713%7CUnknown%7
> CTWFpbGZsb3d8eyJW
> >
> IjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%
> 3D%7C0%7C%
> >
> 7C%7C&sdata=rXF3vAX9pKXv%2FAoKmCmb5K1XPDPvu2e3aAq4jzR6F
> QE%3D&reserved=
> > 0
^ permalink raw reply [flat|nested] 8+ messages in thread
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2024-07-17 17:49 mx93: No cache hierachy definitions for ARM cores Stefan Wahren
2024-07-19 2:38 ` Fabio Estevam
2024-07-19 4:40 ` Stefan Wahren
2024-07-19 14:52 ` Frank Li
2024-07-24 9:48 ` Stefan Wahren
2024-07-24 14:34 ` Sudeep Holla
2024-07-24 15:55 ` Stefan Wahren
2024-08-01 2:52 ` Peng Fan
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