* Re: [PATCH v4 14/19] arm64: dts: mediatek: asurada: Enable PCIe and add WiFi [not found] <20220629155956.1138955-15-nfraprado@collabora.com> @ 2025-01-03 21:14 ` Bjorn Helgaas 2025-01-06 19:10 ` Nícolas F. R. A. Prado 0 siblings, 1 reply; 4+ messages in thread From: Bjorn Helgaas @ 2025-01-03 21:14 UTC (permalink / raw) To: Nícolas F. R. A. Prado Cc: Matthias Brugger, AngeloGioacchino Del Regno, kernel, Chen-Yu Tsai, Krzysztof Kozlowski, Rob Herring, devicetree, linux-arm-kernel, linux-kernel, linux-mediatek On Wed, Jun 29, 2022 at 11:59:51AM -0400, Nícolas F. R. A. Prado wrote: > Enable MT8192's PCIe controller and add support for the MT7921e WiFi > card that is present on that bus for the Asurada platform. > +&pcie { > + pinctrl-names = "default"; > + pinctrl-0 = <&pcie_pins>; > + > + pcie0: pcie@0,0 { > + device_type = "pci"; > + reg = <0x0000 0 0 0 0>; > + num-lanes = <1>; > + bus-range = <0x1 0x1>; Hi Nícolas, what's the purpose of this bus-range? IIUC this describes a Root Port, where we can read and configure the secondary/subordinate bus numbers from the RP config space, so it seems like we don't need to describe them here. > + > + #address-cells = <3>; > + #size-cells = <2>; > + ranges; > + > + wifi: wifi@0,0 { > + reg = <0x10000 0 0 0 0x100000>, > + <0x10000 0 0x100000 0 0x100000>; > + memory-region = <&wifi_restricted_dma_region>; > + }; > + }; > +}; ^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v4 14/19] arm64: dts: mediatek: asurada: Enable PCIe and add WiFi 2025-01-03 21:14 ` [PATCH v4 14/19] arm64: dts: mediatek: asurada: Enable PCIe and add WiFi Bjorn Helgaas @ 2025-01-06 19:10 ` Nícolas F. R. A. Prado 2025-01-06 20:56 ` Bjorn Helgaas 0 siblings, 1 reply; 4+ messages in thread From: Nícolas F. R. A. Prado @ 2025-01-06 19:10 UTC (permalink / raw) To: Bjorn Helgaas Cc: Matthias Brugger, AngeloGioacchino Del Regno, kernel, Chen-Yu Tsai, Krzysztof Kozlowski, Rob Herring, devicetree, linux-arm-kernel, linux-kernel, linux-mediatek On Fri, Jan 03, 2025 at 03:14:46PM -0600, Bjorn Helgaas wrote: > On Wed, Jun 29, 2022 at 11:59:51AM -0400, Nícolas F. R. A. Prado wrote: > > Enable MT8192's PCIe controller and add support for the MT7921e WiFi > > card that is present on that bus for the Asurada platform. > > > +&pcie { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pcie_pins>; > > + > > + pcie0: pcie@0,0 { > > + device_type = "pci"; > > + reg = <0x0000 0 0 0 0>; > > + num-lanes = <1>; > > + bus-range = <0x1 0x1>; > > Hi Nícolas, what's the purpose of this bus-range? IIUC this describes > a Root Port, where we can read and configure the secondary/subordinate > bus numbers from the RP config space, so it seems like we don't need > to describe them here. Hi Bjorn, that was carried over from the downstream sources. I just tried removing it and indeed I don't see any difference in the PCI log messages, or the bus number, and the wifi works just fine. I can send a follow up patch removing it. Thanks, Nícolas ^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v4 14/19] arm64: dts: mediatek: asurada: Enable PCIe and add WiFi 2025-01-06 19:10 ` Nícolas F. R. A. Prado @ 2025-01-06 20:56 ` Bjorn Helgaas 2025-01-07 12:04 ` Nícolas F. R. A. Prado 0 siblings, 1 reply; 4+ messages in thread From: Bjorn Helgaas @ 2025-01-06 20:56 UTC (permalink / raw) To: Nícolas F. R. A. Prado Cc: Matthias Brugger, AngeloGioacchino Del Regno, kernel, Chen-Yu Tsai, Krzysztof Kozlowski, Rob Herring, devicetree, linux-arm-kernel, linux-kernel, linux-mediatek, Manivannan Sadhasivam [+cc Mani] On Mon, Jan 06, 2025 at 04:10:32PM -0300, Nícolas F. R. A. Prado wrote: > On Fri, Jan 03, 2025 at 03:14:46PM -0600, Bjorn Helgaas wrote: > > On Wed, Jun 29, 2022 at 11:59:51AM -0400, Nícolas F. R. A. Prado wrote: > > > Enable MT8192's PCIe controller and add support for the MT7921e WiFi > > > card that is present on that bus for the Asurada platform. > > > > > +&pcie { > > > + pinctrl-names = "default"; > > > + pinctrl-0 = <&pcie_pins>; > > > + > > > + pcie0: pcie@0,0 { > > > + device_type = "pci"; > > > + reg = <0x0000 0 0 0 0>; > > > + num-lanes = <1>; > > > + bus-range = <0x1 0x1>; > > > > Hi Nícolas, what's the purpose of this bus-range? IIUC this describes > > a Root Port, where we can read and configure the secondary/subordinate > > bus numbers from the RP config space, so it seems like we don't need > > to describe them here. > > Hi Bjorn, > > that was carried over from the downstream sources. I just tried > removing it and indeed I don't see any difference in the PCI log > messages, or the bus number, and the wifi works just fine. I can > send a follow up patch removing it. There might be a DTC check issue if we remove the bus-range: https://lore.kernel.org/r/20250105101612.t6c4pw5uxhb5rdde@thinkpad We might need to figure out how to resolve that first. Bjorn ^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v4 14/19] arm64: dts: mediatek: asurada: Enable PCIe and add WiFi 2025-01-06 20:56 ` Bjorn Helgaas @ 2025-01-07 12:04 ` Nícolas F. R. A. Prado 0 siblings, 0 replies; 4+ messages in thread From: Nícolas F. R. A. Prado @ 2025-01-07 12:04 UTC (permalink / raw) To: Bjorn Helgaas Cc: Matthias Brugger, AngeloGioacchino Del Regno, kernel, Chen-Yu Tsai, Krzysztof Kozlowski, Rob Herring, devicetree, linux-arm-kernel, linux-kernel, linux-mediatek, Manivannan Sadhasivam On Mon, Jan 06, 2025 at 02:56:07PM -0600, Bjorn Helgaas wrote: > [+cc Mani] > > On Mon, Jan 06, 2025 at 04:10:32PM -0300, Nícolas F. R. A. Prado wrote: > > On Fri, Jan 03, 2025 at 03:14:46PM -0600, Bjorn Helgaas wrote: > > > On Wed, Jun 29, 2022 at 11:59:51AM -0400, Nícolas F. R. A. Prado wrote: > > > > Enable MT8192's PCIe controller and add support for the MT7921e WiFi > > > > card that is present on that bus for the Asurada platform. > > > > > > > +&pcie { > > > > + pinctrl-names = "default"; > > > > + pinctrl-0 = <&pcie_pins>; > > > > + > > > > + pcie0: pcie@0,0 { > > > > + device_type = "pci"; > > > > + reg = <0x0000 0 0 0 0>; > > > > + num-lanes = <1>; > > > > + bus-range = <0x1 0x1>; > > > > > > Hi Nícolas, what's the purpose of this bus-range? IIUC this describes > > > a Root Port, where we can read and configure the secondary/subordinate > > > bus numbers from the RP config space, so it seems like we don't need > > > to describe them here. > > > > Hi Bjorn, > > > > that was carried over from the downstream sources. I just tried > > removing it and indeed I don't see any difference in the PCI log > > messages, or the bus number, and the wifi works just fine. I can > > send a follow up patch removing it. > > There might be a DTC check issue if we remove the bus-range: > https://lore.kernel.org/r/20250105101612.t6c4pw5uxhb5rdde@thinkpad Ah yes, indeed there is: arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi:643.18-647.5: Warning (pci_device_bus_num): /soc/pcie@11230000/pcie@0,0/wifi@0,0: PCI bus number 1 out of range, expected (0 - 0) Thanks, Nícolas > > We might need to figure out how to resolve that first. > > Bjorn ^ permalink raw reply [flat|nested] 4+ messages in thread
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[not found] <20220629155956.1138955-15-nfraprado@collabora.com>
2025-01-03 21:14 ` [PATCH v4 14/19] arm64: dts: mediatek: asurada: Enable PCIe and add WiFi Bjorn Helgaas
2025-01-06 19:10 ` Nícolas F. R. A. Prado
2025-01-06 20:56 ` Bjorn Helgaas
2025-01-07 12:04 ` Nícolas F. R. A. Prado
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