From: Will Deacon <will@kernel.org>
To: Jason Gunthorpe <jgg@ziepe.ca>
Cc: Shyam Saini <shyamsaini@linux.microsoft.com>,
thierry.reding@gmail.com, robin.murphy@arm.com, robh@kernel.org,
joro@8bytes.org, iommu@lists.linux.dev,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
virtualization@lists.linux.dev, jacob.pan@linux.microsoft.com,
eric.auger@redhat.com, code@tyhicks.com,
eahariha@linux.microsoft.com, vijayb@linux.microsoft.com,
bboscaccy@linux.microsoft.com, saravanak@google.com,
krzk+dt@kernel.org, conor+dt@kernel.org, lizhi.hou@amd.com,
clement.leger@bootlin.com
Subject: Re: [PATCH v4 3/4] arm-smmu: select suitable MSI IOVA
Date: Fri, 19 Sep 2025 08:33:23 +0100 [thread overview]
Message-ID: <aM0HQ51DelZW_Rt8@willie-the-truck> (raw)
In-Reply-To: <20250918224322.GR1326709@ziepe.ca>
On Thu, Sep 18, 2025 at 07:43:22PM -0300, Jason Gunthorpe wrote:
> On Thu, Sep 18, 2025 at 05:49:39PM +0100, Will Deacon wrote:
> > Given that we're walking over the reserved regions to see if we have a
> > collision with MSI_IOVA_BASE, why not allocate the base address
> > dynamically if we detect a collision rather than having yet another
> > hard-coded address which we can't guarantee won't be problematic in future?
>
> I'm nervous about this. Right now the MSI_IOVA is actually UAPI and
> things like VFIO/qmeu need to accomodate it's placement in their own
> memory maps.
*shrug*
That's only the case for broken systems where the existing MSI_IOVA
can't be made to work. As far as I'm concerned, they get to keep the
pieces and will need to work on the userspace side. It's not like
MSI_IOVA2 is magically going to work (and I bet it won't be tested).
> Nicolin has some patches on the iommufd side to let userspace select
> the MSI address instead, but they are not done yet.
Maybe we should just wait for that? Carrying a temporary hack with ABI
implications to support broken hardware isn't particularly compelling
to me.
> So, randomly picking an address sounds like a bad idea to me, it would
> almost certainly unpredictably break qemu..
It's not really "random", in the sense that it would be deterministic
for a given set of reserved regions.
Will
next prev parent reply other threads:[~2025-09-19 7:33 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-09 15:45 [PATCH v4 0/4] arm-smmu: select suitable MSI IOVA Shyam Saini
2025-09-09 15:45 ` [PATCH v4 1/4] arm-smmu: move MSI_IOVA macro definitions Shyam Saini
2025-09-09 15:45 ` [PATCH v4 2/4] iommu/of: fix device tree configuration for PCI devices Shyam Saini
2025-09-24 17:44 ` Robin Murphy
2025-09-09 15:45 ` [PATCH v4 3/4] arm-smmu: select suitable MSI IOVA Shyam Saini
2025-09-18 16:49 ` Will Deacon
2025-09-18 22:43 ` Jason Gunthorpe
2025-09-19 7:33 ` Will Deacon [this message]
2025-09-19 12:08 ` Jason Gunthorpe
2025-09-23 15:56 ` Shyam Saini
2025-09-23 16:19 ` Jason Gunthorpe
2025-09-24 18:59 ` Robin Murphy
2025-09-09 15:46 ` [PATCH v4 4/4] drivers: iommu: refactor arm_smmu_get_resv_regions Shyam Saini
2025-09-09 15:58 ` Jason Gunthorpe
2025-09-15 16:28 ` Shyam Saini
2025-09-15 22:59 ` Jason Gunthorpe
2025-09-13 0:23 ` kernel test robot
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