* [PATCH v7 01/13] coresight: etm4x: fix wrong check of etm4x_sspcicrn_present()
2026-05-19 15:47 [PATCH v7 00/13] fix several inconsistencies with sysfs configuration in etmX Yeoreum Yun
@ 2026-05-19 15:48 ` Yeoreum Yun
2026-05-19 15:48 ` [PATCH v7 02/13] coresight: etm4x: fix underflow for nrseqstate Yeoreum Yun
` (11 subsequent siblings)
12 siblings, 0 replies; 39+ messages in thread
From: Yeoreum Yun @ 2026-05-19 15:48 UTC (permalink / raw)
To: coresight, linux-arm-kernel, linux-kernel
Cc: suzuki.poulose, mike.leach, james.clark, alexander.shishkin,
leo.yan, jie.gan, Yeoreum Yun
According to Embedded Trace Macrocell Architecture Specification
ETMv4.0 to ETM4.6 [0], TRCSSPCICR<n> is present only if all of
the following are true:
- TRCIDR4.NUMSSCC > n.
- TRCIDR4.NUMPC > 0b0000.
- TRCSSCSR<n>.PC == 0b1.
Comment for etm4x_sspcicrn_present() is align with the specification.
However, the check should use drvdata->nr_pe_cmp to check TRCIDR4.NUMPC
not nr_pe.
Link: https://developer.arm.com/documentation/ihi0064/latest/ [0]
Fixes: f6a18f354c58 ("coresight: etm4x: Handle access to TRCSSPCICRn")
Reviewed-by: Leo Yan <leo.yan@arm.com>
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
---
drivers/hwtracing/coresight/coresight-etm4x-core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index 14bb31bd6a0b..1e3b0344dc00 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -93,7 +93,7 @@ static int etm4_probe_cpu(unsigned int cpu);
static bool etm4x_sspcicrn_present(struct etmv4_drvdata *drvdata, int n)
{
return (n < drvdata->nr_ss_cmp) &&
- drvdata->nr_pe &&
+ drvdata->nr_pe_cmp &&
(drvdata->config.ss_status[n] & TRCSSCSRn_PC);
}
--
LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7}
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PATCH v7 02/13] coresight: etm4x: fix underflow for nrseqstate
2026-05-19 15:47 [PATCH v7 00/13] fix several inconsistencies with sysfs configuration in etmX Yeoreum Yun
2026-05-19 15:48 ` [PATCH v7 01/13] coresight: etm4x: fix wrong check of etm4x_sspcicrn_present() Yeoreum Yun
@ 2026-05-19 15:48 ` Yeoreum Yun
2026-06-01 9:40 ` Suzuki K Poulose
2026-06-01 9:52 ` Suzuki K Poulose
2026-05-19 15:48 ` [PATCH v7 03/13] coresight: etm4x: introduce ETM_MAX_SEQ_TRANSITIONS Yeoreum Yun
` (10 subsequent siblings)
12 siblings, 2 replies; 39+ messages in thread
From: Yeoreum Yun @ 2026-05-19 15:48 UTC (permalink / raw)
To: coresight, linux-arm-kernel, linux-kernel
Cc: suzuki.poulose, mike.leach, james.clark, alexander.shishkin,
leo.yan, jie.gan, Yeoreum Yun
TCRSEQEVR<n> is implemented only when TCRIDR5.NUMSEQSTATE is 0b100,
in which case n ranges from 0 to 2; otherwise, TCRIDR5.NUMSEQSTATE is 0b000.
Therefore, drvdata->nrseqstate should be checked before entering the loop.
Link: https://developer.arm.com/documentation/ihi0064/latest/ [0]
Fixes: 2e1cdfe184b5 ("coresight-etm4x: Adding CoreSight ETM4x driver")
Reviewed-by: Leo Yan <leo.yan@arm.com>
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
---
.../hwtracing/coresight/coresight-etm4x-core.c | 18 ++++++++++--------
.../coresight/coresight-etm4x-sysfs.c | 2 ++
2 files changed, 12 insertions(+), 8 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index 1e3b0344dc00..94b9385e964a 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -542,9 +542,11 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
etm4x_relaxed_write32(csa, config->vissctlr, TRCVISSCTLR);
if (drvdata->nr_pe_cmp)
etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR);
- for (i = 0; i < drvdata->nrseqstate - 1; i++)
- etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i));
+
if (drvdata->nrseqstate) {
+ for (i = 0; i < drvdata->nrseqstate - 1; i++)
+ etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i));
+
etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR);
etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR);
}
@@ -1896,10 +1898,10 @@ static int etm4_cpu_save(struct coresight_device *csdev)
if (drvdata->nr_pe_cmp)
state->trcvipcssctlr = etm4x_read32(csa, TRCVIPCSSCTLR);
- for (i = 0; i < drvdata->nrseqstate - 1; i++)
- state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i));
-
if (drvdata->nrseqstate) {
+ for (i = 0; i < drvdata->nrseqstate - 1; i++)
+ state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i));
+
state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR);
state->trcseqstr = etm4x_read32(csa, TRCSEQSTR);
}
@@ -2009,10 +2011,10 @@ static void etm4_cpu_restore(struct coresight_device *csdev)
if (drvdata->nr_pe_cmp)
etm4x_relaxed_write32(csa, state->trcvipcssctlr, TRCVIPCSSCTLR);
- for (i = 0; i < drvdata->nrseqstate - 1; i++)
- etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i));
-
if (drvdata->nrseqstate) {
+ for (i = 0; i < drvdata->nrseqstate - 1; i++)
+ etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i));
+
etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR);
etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR);
}
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
index e9eeea6240d5..0e1ad175aa1e 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
@@ -1395,6 +1395,8 @@ static ssize_t seq_idx_store(struct device *dev,
struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
struct etmv4_config *config = &drvdata->config;
+ if (!drvdata->nrseqstate)
+ return -ENOTSUPP;
if (kstrtoul(buf, 16, &val))
return -EINVAL;
if (val >= drvdata->nrseqstate - 1)
--
LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7}
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [PATCH v7 02/13] coresight: etm4x: fix underflow for nrseqstate
2026-05-19 15:48 ` [PATCH v7 02/13] coresight: etm4x: fix underflow for nrseqstate Yeoreum Yun
@ 2026-06-01 9:40 ` Suzuki K Poulose
2026-06-01 10:08 ` Yeoreum Yun
2026-06-01 9:52 ` Suzuki K Poulose
1 sibling, 1 reply; 39+ messages in thread
From: Suzuki K Poulose @ 2026-06-01 9:40 UTC (permalink / raw)
To: Yeoreum Yun, coresight, linux-arm-kernel, linux-kernel
Cc: mike.leach, james.clark, alexander.shishkin, leo.yan, jie.gan
On 19/05/2026 16:48, Yeoreum Yun wrote:
> TCRSEQEVR<n> is implemented only when TCRIDR5.NUMSEQSTATE is 0b100,
> in which case n ranges from 0 to 2; otherwise, TCRIDR5.NUMSEQSTATE is 0b000.
>
> Therefore, drvdata->nrseqstate should be checked before entering the loop.
for (i = 0; i < drvdata->nrseqstate - 1; i++)
Wouldn't that check cover the case ? (provided i is signed int ?)
Suzuki
>
> Link: https://developer.arm.com/documentation/ihi0064/latest/ [0]
> Fixes: 2e1cdfe184b5 ("coresight-etm4x: Adding CoreSight ETM4x driver")
> Reviewed-by: Leo Yan <leo.yan@arm.com>
> Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
> ---
> .../hwtracing/coresight/coresight-etm4x-core.c | 18 ++++++++++--------
> .../coresight/coresight-etm4x-sysfs.c | 2 ++
> 2 files changed, 12 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> index 1e3b0344dc00..94b9385e964a 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> @@ -542,9 +542,11 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
> etm4x_relaxed_write32(csa, config->vissctlr, TRCVISSCTLR);
> if (drvdata->nr_pe_cmp)
> etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR);
> - for (i = 0; i < drvdata->nrseqstate - 1; i++)
> - etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i));
> +
> if (drvdata->nrseqstate) {
> + for (i = 0; i < drvdata->nrseqstate - 1; i++)
> + etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i));
> +
> etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR);
> etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR);
> }
> @@ -1896,10 +1898,10 @@ static int etm4_cpu_save(struct coresight_device *csdev)
> if (drvdata->nr_pe_cmp)
> state->trcvipcssctlr = etm4x_read32(csa, TRCVIPCSSCTLR);
>
> - for (i = 0; i < drvdata->nrseqstate - 1; i++)
> - state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i));
> -
> if (drvdata->nrseqstate) {
> + for (i = 0; i < drvdata->nrseqstate - 1; i++)
> + state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i));
> +
> state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR);
> state->trcseqstr = etm4x_read32(csa, TRCSEQSTR);
> }
> @@ -2009,10 +2011,10 @@ static void etm4_cpu_restore(struct coresight_device *csdev)
> if (drvdata->nr_pe_cmp)
> etm4x_relaxed_write32(csa, state->trcvipcssctlr, TRCVIPCSSCTLR);
>
> - for (i = 0; i < drvdata->nrseqstate - 1; i++)
> - etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i));
> -
> if (drvdata->nrseqstate) {
> + for (i = 0; i < drvdata->nrseqstate - 1; i++)
> + etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i));
> +
> etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR);
> etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR);
> }
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> index e9eeea6240d5..0e1ad175aa1e 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> @@ -1395,6 +1395,8 @@ static ssize_t seq_idx_store(struct device *dev,
> struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> struct etmv4_config *config = &drvdata->config;
>
> + if (!drvdata->nrseqstate)
> + return -ENOTSUPP;
> if (kstrtoul(buf, 16, &val))
> return -EINVAL;
> if (val >= drvdata->nrseqstate - 1)
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [PATCH v7 02/13] coresight: etm4x: fix underflow for nrseqstate
2026-06-01 9:40 ` Suzuki K Poulose
@ 2026-06-01 10:08 ` Yeoreum Yun
2026-06-01 10:13 ` Suzuki K Poulose
0 siblings, 1 reply; 39+ messages in thread
From: Yeoreum Yun @ 2026-06-01 10:08 UTC (permalink / raw)
To: Suzuki K Poulose
Cc: coresight, linux-arm-kernel, linux-kernel, mike.leach,
james.clark, alexander.shishkin, leo.yan, jie.gan
> On 19/05/2026 16:48, Yeoreum Yun wrote:
> > TCRSEQEVR<n> is implemented only when TCRIDR5.NUMSEQSTATE is 0b100,
> > in which case n ranges from 0 to 2; otherwise, TCRIDR5.NUMSEQSTATE is 0b000.
> >
> > Therefore, drvdata->nrseqstate should be checked before entering the loop.
>
> for (i = 0; i < drvdata->nrseqstate - 1; i++)
>
> Wouldn't that check cover the case ? (provided i is signed int ?)
>
> Suzuki
Unfortunately, the drvdata->nrseqstate is u8 but i is signed int.
I think in this case it would iterate 255 times (0xff).
>
> >
> > Link: https://developer.arm.com/documentation/ihi0064/latest/ [0]
> > Fixes: 2e1cdfe184b5 ("coresight-etm4x: Adding CoreSight ETM4x driver")
> > Reviewed-by: Leo Yan <leo.yan@arm.com>
> > Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
> > ---
> > .../hwtracing/coresight/coresight-etm4x-core.c | 18 ++++++++++--------
> > .../coresight/coresight-etm4x-sysfs.c | 2 ++
> > 2 files changed, 12 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> > index 1e3b0344dc00..94b9385e964a 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> > @@ -542,9 +542,11 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
> > etm4x_relaxed_write32(csa, config->vissctlr, TRCVISSCTLR);
> > if (drvdata->nr_pe_cmp)
> > etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR);
> > - for (i = 0; i < drvdata->nrseqstate - 1; i++)
> > - etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i));
> > +
> > if (drvdata->nrseqstate) {
> > + for (i = 0; i < drvdata->nrseqstate - 1; i++)
> > + etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i));
> > +
> > etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR);
> > etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR);
> > }
> > @@ -1896,10 +1898,10 @@ static int etm4_cpu_save(struct coresight_device *csdev)
> > if (drvdata->nr_pe_cmp)
> > state->trcvipcssctlr = etm4x_read32(csa, TRCVIPCSSCTLR);
> > - for (i = 0; i < drvdata->nrseqstate - 1; i++)
> > - state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i));
> > -
> > if (drvdata->nrseqstate) {
> > + for (i = 0; i < drvdata->nrseqstate - 1; i++)
> > + state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i));
> > +
> > state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR);
> > state->trcseqstr = etm4x_read32(csa, TRCSEQSTR);
> > }
> > @@ -2009,10 +2011,10 @@ static void etm4_cpu_restore(struct coresight_device *csdev)
> > if (drvdata->nr_pe_cmp)
> > etm4x_relaxed_write32(csa, state->trcvipcssctlr, TRCVIPCSSCTLR);
> > - for (i = 0; i < drvdata->nrseqstate - 1; i++)
> > - etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i));
> > -
> > if (drvdata->nrseqstate) {
> > + for (i = 0; i < drvdata->nrseqstate - 1; i++)
> > + etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i));
> > +
> > etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR);
> > etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR);
> > }
> > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > index e9eeea6240d5..0e1ad175aa1e 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > @@ -1395,6 +1395,8 @@ static ssize_t seq_idx_store(struct device *dev,
> > struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > struct etmv4_config *config = &drvdata->config;
> > + if (!drvdata->nrseqstate)
> > + return -ENOTSUPP;
> > if (kstrtoul(buf, 16, &val))
> > return -EINVAL;
> > if (val >= drvdata->nrseqstate - 1)
>
--
Sincerely,
Yeoreum Yun
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [PATCH v7 02/13] coresight: etm4x: fix underflow for nrseqstate
2026-06-01 10:08 ` Yeoreum Yun
@ 2026-06-01 10:13 ` Suzuki K Poulose
2026-06-01 10:15 ` Yeoreum Yun
0 siblings, 1 reply; 39+ messages in thread
From: Suzuki K Poulose @ 2026-06-01 10:13 UTC (permalink / raw)
To: Yeoreum Yun
Cc: coresight, linux-arm-kernel, linux-kernel, mike.leach,
james.clark, alexander.shishkin, leo.yan, jie.gan
On 01/06/2026 11:08, Yeoreum Yun wrote:
>> On 19/05/2026 16:48, Yeoreum Yun wrote:
>>> TCRSEQEVR<n> is implemented only when TCRIDR5.NUMSEQSTATE is 0b100,
>>> in which case n ranges from 0 to 2; otherwise, TCRIDR5.NUMSEQSTATE is 0b000.
>>>
>>> Therefore, drvdata->nrseqstate should be checked before entering the loop.
>>
>> for (i = 0; i < drvdata->nrseqstate - 1; i++)
>>
>> Wouldn't that check cover the case ? (provided i is signed int ?)
>>
>> Suzuki
>
> Unfortunately, the drvdata->nrseqstate is u8 but i is signed int.
> I think in this case it would iterate 255 times (0xff).
Then why not fix it to signed ? Anyways, please see my other comment. We
shouldn't be relying on nrseqstate for the number of seq_ctrl registers.
Suzuki
>
>>
>>>
>>> Link: https://developer.arm.com/documentation/ihi0064/latest/ [0]
>>> Fixes: 2e1cdfe184b5 ("coresight-etm4x: Adding CoreSight ETM4x driver")
>>> Reviewed-by: Leo Yan <leo.yan@arm.com>
>>> Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
>>> ---
>>> .../hwtracing/coresight/coresight-etm4x-core.c | 18 ++++++++++--------
>>> .../coresight/coresight-etm4x-sysfs.c | 2 ++
>>> 2 files changed, 12 insertions(+), 8 deletions(-)
>>>
>>> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
>>> index 1e3b0344dc00..94b9385e964a 100644
>>> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
>>> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
>>> @@ -542,9 +542,11 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
>>> etm4x_relaxed_write32(csa, config->vissctlr, TRCVISSCTLR);
>>> if (drvdata->nr_pe_cmp)
>>> etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR);
>>> - for (i = 0; i < drvdata->nrseqstate - 1; i++)
>>> - etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i));
>>> +
>>> if (drvdata->nrseqstate) {
>>> + for (i = 0; i < drvdata->nrseqstate - 1; i++)
>>> + etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i));
>>> +
>>> etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR);
>>> etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR);
>>> }
>>> @@ -1896,10 +1898,10 @@ static int etm4_cpu_save(struct coresight_device *csdev)
>>> if (drvdata->nr_pe_cmp)
>>> state->trcvipcssctlr = etm4x_read32(csa, TRCVIPCSSCTLR);
>>> - for (i = 0; i < drvdata->nrseqstate - 1; i++)
>>> - state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i));
>>> -
>>> if (drvdata->nrseqstate) {
>>> + for (i = 0; i < drvdata->nrseqstate - 1; i++)
>>> + state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i));
>>> +
>>> state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR);
>>> state->trcseqstr = etm4x_read32(csa, TRCSEQSTR);
>>> }
>>> @@ -2009,10 +2011,10 @@ static void etm4_cpu_restore(struct coresight_device *csdev)
>>> if (drvdata->nr_pe_cmp)
>>> etm4x_relaxed_write32(csa, state->trcvipcssctlr, TRCVIPCSSCTLR);
>>> - for (i = 0; i < drvdata->nrseqstate - 1; i++)
>>> - etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i));
>>> -
>>> if (drvdata->nrseqstate) {
>>> + for (i = 0; i < drvdata->nrseqstate - 1; i++)
>>> + etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i));
>>> +
>>> etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR);
>>> etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR);
>>> }
>>> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
>>> index e9eeea6240d5..0e1ad175aa1e 100644
>>> --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
>>> +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
>>> @@ -1395,6 +1395,8 @@ static ssize_t seq_idx_store(struct device *dev,
>>> struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
>>> struct etmv4_config *config = &drvdata->config;
>>> + if (!drvdata->nrseqstate)
>>> + return -ENOTSUPP;
>>> if (kstrtoul(buf, 16, &val))
>>> return -EINVAL;
>>> if (val >= drvdata->nrseqstate - 1)
>>
>
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [PATCH v7 02/13] coresight: etm4x: fix underflow for nrseqstate
2026-06-01 10:13 ` Suzuki K Poulose
@ 2026-06-01 10:15 ` Yeoreum Yun
0 siblings, 0 replies; 39+ messages in thread
From: Yeoreum Yun @ 2026-06-01 10:15 UTC (permalink / raw)
To: Suzuki K Poulose
Cc: coresight, linux-arm-kernel, linux-kernel, mike.leach,
james.clark, alexander.shishkin, leo.yan, jie.gan
> On 01/06/2026 11:08, Yeoreum Yun wrote:
> > > On 19/05/2026 16:48, Yeoreum Yun wrote:
> > > > TCRSEQEVR<n> is implemented only when TCRIDR5.NUMSEQSTATE is 0b100,
> > > > in which case n ranges from 0 to 2; otherwise, TCRIDR5.NUMSEQSTATE is 0b000.
> > > >
> > > > Therefore, drvdata->nrseqstate should be checked before entering the loop.
> > >
> > > for (i = 0; i < drvdata->nrseqstate - 1; i++)
> > >
> > > Wouldn't that check cover the case ? (provided i is signed int ?)
> > >
> > > Suzuki
> >
> > Unfortunately, the drvdata->nrseqstate is u8 but i is signed int.
> > I think in this case it would iterate 255 times (0xff).
>
> Then why not fix it to signed ? Anyways, please see my other comment. We
> shouldn't be relying on nrseqstate for the number of seq_ctrl registers.
Yeap. I confirmed that. I think it's enough with the nr_seq_ctrl.
Thanks!
>
> >
> > >
> > > >
> > > > Link: https://developer.arm.com/documentation/ihi0064/latest/ [0]
> > > > Fixes: 2e1cdfe184b5 ("coresight-etm4x: Adding CoreSight ETM4x driver")
> > > > Reviewed-by: Leo Yan <leo.yan@arm.com>
> > > > Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
> > > > ---
> > > > .../hwtracing/coresight/coresight-etm4x-core.c | 18 ++++++++++--------
> > > > .../coresight/coresight-etm4x-sysfs.c | 2 ++
> > > > 2 files changed, 12 insertions(+), 8 deletions(-)
> > > >
> > > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> > > > index 1e3b0344dc00..94b9385e964a 100644
> > > > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> > > > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> > > > @@ -542,9 +542,11 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
> > > > etm4x_relaxed_write32(csa, config->vissctlr, TRCVISSCTLR);
> > > > if (drvdata->nr_pe_cmp)
> > > > etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR);
> > > > - for (i = 0; i < drvdata->nrseqstate - 1; i++)
> > > > - etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i));
> > > > +
> > > > if (drvdata->nrseqstate) {
> > > > + for (i = 0; i < drvdata->nrseqstate - 1; i++)
> > > > + etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i));
> > > > +
> > > > etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR);
> > > > etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR);
> > > > }
> > > > @@ -1896,10 +1898,10 @@ static int etm4_cpu_save(struct coresight_device *csdev)
> > > > if (drvdata->nr_pe_cmp)
> > > > state->trcvipcssctlr = etm4x_read32(csa, TRCVIPCSSCTLR);
> > > > - for (i = 0; i < drvdata->nrseqstate - 1; i++)
> > > > - state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i));
> > > > -
> > > > if (drvdata->nrseqstate) {
> > > > + for (i = 0; i < drvdata->nrseqstate - 1; i++)
> > > > + state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i));
> > > > +
> > > > state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR);
> > > > state->trcseqstr = etm4x_read32(csa, TRCSEQSTR);
> > > > }
> > > > @@ -2009,10 +2011,10 @@ static void etm4_cpu_restore(struct coresight_device *csdev)
> > > > if (drvdata->nr_pe_cmp)
> > > > etm4x_relaxed_write32(csa, state->trcvipcssctlr, TRCVIPCSSCTLR);
> > > > - for (i = 0; i < drvdata->nrseqstate - 1; i++)
> > > > - etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i));
> > > > -
> > > > if (drvdata->nrseqstate) {
> > > > + for (i = 0; i < drvdata->nrseqstate - 1; i++)
> > > > + etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i));
> > > > +
> > > > etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR);
> > > > etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR);
> > > > }
> > > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > > > index e9eeea6240d5..0e1ad175aa1e 100644
> > > > --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > > > +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > > > @@ -1395,6 +1395,8 @@ static ssize_t seq_idx_store(struct device *dev,
> > > > struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > > > struct etmv4_config *config = &drvdata->config;
> > > > + if (!drvdata->nrseqstate)
> > > > + return -ENOTSUPP;
> > > > if (kstrtoul(buf, 16, &val))
> > > > return -EINVAL;
> > > > if (val >= drvdata->nrseqstate - 1)
> > >
> >
>
--
Sincerely,
Yeoreum Yun
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v7 02/13] coresight: etm4x: fix underflow for nrseqstate
2026-05-19 15:48 ` [PATCH v7 02/13] coresight: etm4x: fix underflow for nrseqstate Yeoreum Yun
2026-06-01 9:40 ` Suzuki K Poulose
@ 2026-06-01 9:52 ` Suzuki K Poulose
2026-06-01 10:12 ` Yeoreum Yun
1 sibling, 1 reply; 39+ messages in thread
From: Suzuki K Poulose @ 2026-06-01 9:52 UTC (permalink / raw)
To: Yeoreum Yun, coresight, linux-arm-kernel, linux-kernel
Cc: mike.leach, james.clark, alexander.shishkin, leo.yan, jie.gan
On 19/05/2026 16:48, Yeoreum Yun wrote:
> TCRSEQEVR<n> is implemented only when TCRIDR5.NUMSEQSTATE is 0b100,
> in which case n ranges from 0 to 2; otherwise, TCRIDR5.NUMSEQSTATE is 0b000.
>
> Therefore, drvdata->nrseqstate should be checked before entering the loop.
s/TCR/TRC/g ^^^ and every other patch in the series. Seem like you have
been playing with the MMU code ;-)
>
> Link: https://developer.arm.com/documentation/ihi0064/latest/ [0]
> Fixes: 2e1cdfe184b5 ("coresight-etm4x: Adding CoreSight ETM4x driver")
> Reviewed-by: Leo Yan <leo.yan@arm.com>
> Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
> ---
> .../hwtracing/coresight/coresight-etm4x-core.c | 18 ++++++++++--------
> .../coresight/coresight-etm4x-sysfs.c | 2 ++
> 2 files changed, 12 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> index 1e3b0344dc00..94b9385e964a 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> @@ -542,9 +542,11 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
> etm4x_relaxed_write32(csa, config->vissctlr, TRCVISSCTLR);
> if (drvdata->nr_pe_cmp)
> etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR);
> - for (i = 0; i < drvdata->nrseqstate - 1; i++)
> - etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i));
> +
> if (drvdata->nrseqstate) {
> + for (i = 0; i < drvdata->nrseqstate - 1; i++)
> + etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i));
Looking at this again, I think we are contemplating two different values
from a single variable (blame the architecture). Instead, we should:
1. Disconnect number of TRCSEQEVRn from drvdata->nrseqstate, and add
nr_seq_ctrls to drvdata and initialise this at probe.
for (i = 0; i < drvdata->nr_seq_ctrls; i++)
Suzuki
> +
> etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR);
> etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR);
> }
> @@ -1896,10 +1898,10 @@ static int etm4_cpu_save(struct coresight_device *csdev)
> if (drvdata->nr_pe_cmp)
> state->trcvipcssctlr = etm4x_read32(csa, TRCVIPCSSCTLR);
>
> - for (i = 0; i < drvdata->nrseqstate - 1; i++)
> - state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i));
> -
> if (drvdata->nrseqstate) {
> + for (i = 0; i < drvdata->nrseqstate - 1; i++)
> + state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i));
> +
> state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR);
> state->trcseqstr = etm4x_read32(csa, TRCSEQSTR);
> }
> @@ -2009,10 +2011,10 @@ static void etm4_cpu_restore(struct coresight_device *csdev)
> if (drvdata->nr_pe_cmp)
> etm4x_relaxed_write32(csa, state->trcvipcssctlr, TRCVIPCSSCTLR);
>
> - for (i = 0; i < drvdata->nrseqstate - 1; i++)
> - etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i));
> -
> if (drvdata->nrseqstate) {
> + for (i = 0; i < drvdata->nrseqstate - 1; i++)
> + etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i));
> +
> etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR);
> etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR);
> }
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> index e9eeea6240d5..0e1ad175aa1e 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> @@ -1395,6 +1395,8 @@ static ssize_t seq_idx_store(struct device *dev,
> struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> struct etmv4_config *config = &drvdata->config;
>
> + if (!drvdata->nrseqstate)
> + return -ENOTSUPP;
> if (kstrtoul(buf, 16, &val))
> return -EINVAL;
> if (val >= drvdata->nrseqstate - 1)
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [PATCH v7 02/13] coresight: etm4x: fix underflow for nrseqstate
2026-06-01 9:52 ` Suzuki K Poulose
@ 2026-06-01 10:12 ` Yeoreum Yun
0 siblings, 0 replies; 39+ messages in thread
From: Yeoreum Yun @ 2026-06-01 10:12 UTC (permalink / raw)
To: Suzuki K Poulose
Cc: coresight, linux-arm-kernel, linux-kernel, mike.leach,
james.clark, alexander.shishkin, leo.yan, jie.gan
On Mon, Jun 01, 2026 at 10:52:45AM +0100, Suzuki K Poulose wrote:
> On 19/05/2026 16:48, Yeoreum Yun wrote:
> > TCRSEQEVR<n> is implemented only when TCRIDR5.NUMSEQSTATE is 0b100,
> > in which case n ranges from 0 to 2; otherwise, TCRIDR5.NUMSEQSTATE is 0b000.
> >
> > Therefore, drvdata->nrseqstate should be checked before entering the loop.
>
> s/TCR/TRC/g ^^^ and every other patch in the series. Seem like you have been
> playing with the MMU code ;-)
Sorry. I'll fix this typo and Thanks!
>
>
> >
> > Link: https://developer.arm.com/documentation/ihi0064/latest/ [0]
> > Fixes: 2e1cdfe184b5 ("coresight-etm4x: Adding CoreSight ETM4x driver")
> > Reviewed-by: Leo Yan <leo.yan@arm.com>
> > Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
> > ---
> > .../hwtracing/coresight/coresight-etm4x-core.c | 18 ++++++++++--------
> > .../coresight/coresight-etm4x-sysfs.c | 2 ++
> > 2 files changed, 12 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> > index 1e3b0344dc00..94b9385e964a 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> > @@ -542,9 +542,11 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
> > etm4x_relaxed_write32(csa, config->vissctlr, TRCVISSCTLR);
> > if (drvdata->nr_pe_cmp)
> > etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR);
> > - for (i = 0; i < drvdata->nrseqstate - 1; i++)
> > - etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i));
> > +
> > if (drvdata->nrseqstate) {
> > + for (i = 0; i < drvdata->nrseqstate - 1; i++)
> > + etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i));
>
> Looking at this again, I think we are contemplating two different values
> from a single variable (blame the architecture). Instead, we should:
>
> 1. Disconnect number of TRCSEQEVRn from drvdata->nrseqstate, and add
> nr_seq_ctrls to drvdata and initialise this at probe.
>
>
> for (i = 0; i < drvdata->nr_seq_ctrls; i++)
>
> Suzuki
Okay. THen I'll add nr_seq_ctrls instead. Thanks!
>
>
> > +
> > etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR);
> > etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR);
> > }
> > @@ -1896,10 +1898,10 @@ static int etm4_cpu_save(struct coresight_device *csdev)
> > if (drvdata->nr_pe_cmp)
> > state->trcvipcssctlr = etm4x_read32(csa, TRCVIPCSSCTLR);
> > - for (i = 0; i < drvdata->nrseqstate - 1; i++)
> > - state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i));
> > -
> > if (drvdata->nrseqstate) {
> > + for (i = 0; i < drvdata->nrseqstate - 1; i++)
> > + state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i));
> > +
> > state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR);
> > state->trcseqstr = etm4x_read32(csa, TRCSEQSTR);
> > }
> > @@ -2009,10 +2011,10 @@ static void etm4_cpu_restore(struct coresight_device *csdev)
> > if (drvdata->nr_pe_cmp)
> > etm4x_relaxed_write32(csa, state->trcvipcssctlr, TRCVIPCSSCTLR);
> > - for (i = 0; i < drvdata->nrseqstate - 1; i++)
> > - etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i));
> > -
> > if (drvdata->nrseqstate) {
> > + for (i = 0; i < drvdata->nrseqstate - 1; i++)
> > + etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i));
> > +
> > etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR);
> > etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR);
> > }
> > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > index e9eeea6240d5..0e1ad175aa1e 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > @@ -1395,6 +1395,8 @@ static ssize_t seq_idx_store(struct device *dev,
> > struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > struct etmv4_config *config = &drvdata->config;
> > + if (!drvdata->nrseqstate)
> > + return -ENOTSUPP;
> > if (kstrtoul(buf, 16, &val))
> > return -EINVAL;
> > if (val >= drvdata->nrseqstate - 1)
>
--
Sincerely,
Yeoreum Yun
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v7 03/13] coresight: etm4x: introduce ETM_MAX_SEQ_TRANSITIONS
2026-05-19 15:47 [PATCH v7 00/13] fix several inconsistencies with sysfs configuration in etmX Yeoreum Yun
2026-05-19 15:48 ` [PATCH v7 01/13] coresight: etm4x: fix wrong check of etm4x_sspcicrn_present() Yeoreum Yun
2026-05-19 15:48 ` [PATCH v7 02/13] coresight: etm4x: fix underflow for nrseqstate Yeoreum Yun
@ 2026-05-19 15:48 ` Yeoreum Yun
2026-05-28 12:58 ` Leo Yan
2026-06-01 9:53 ` Suzuki K Poulose
2026-05-19 15:48 ` [PATCH v7 04/13] coresight: etm4x: introduce struct etm4_caps Yeoreum Yun
` (9 subsequent siblings)
12 siblings, 2 replies; 39+ messages in thread
From: Yeoreum Yun @ 2026-05-19 15:48 UTC (permalink / raw)
To: coresight, linux-arm-kernel, linux-kernel
Cc: suzuki.poulose, mike.leach, james.clark, alexander.shishkin,
leo.yan, jie.gan, Yeoreum Yun
According to IHI006H Embedded Trace Macrocell Architecture
Specification [0], n could be 0-2 for TCRSEQEVR<n> when
TCRIDR5.NUMSEQSTATE is 0b100.
Therefore, introduce ETM_MAX_SEQ_TRANSITIONS macro and apply this
in TCRSEQEVR<n> relevant fields.
Link: https://developer.arm.com/documentation/ihi0064/latest/ [0]
Suggestedby: Leo Yan <leo.yan@arm.com>
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
---
drivers/hwtracing/coresight/coresight-etm4x-cfg.c | 2 +-
drivers/hwtracing/coresight/coresight-etm4x.h | 5 +++--
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
index c302072b293a..e1a59b434505 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
@@ -76,7 +76,7 @@ static int etm4_cfg_map_reg_offset(struct etmv4_drvdata *drvdata,
} else if ((offset & GENMASK(11, 4)) == TRCSEQEVRn(0)) {
/* sequencer state control registers */
idx = (offset & GENMASK(3, 0)) / 4;
- if (idx < ETM_MAX_SEQ_STATES) {
+ if (idx < ETM_MAX_SEQ_TRANSITIONS) {
reg_csdev->driver_regval = &drvcfg->seq_ctrl[idx];
err = 0;
}
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
index 89d81ce4e04e..60e08ab085c5 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.h
+++ b/drivers/hwtracing/coresight/coresight-etm4x.h
@@ -614,6 +614,7 @@ static inline u32 etm4_res_sel_pair(u8 res_sel_idx)
#define ETM_MAX_NR_PE 8
#define ETMv4_MAX_CNTR 4
#define ETM_MAX_SEQ_STATES 4
+#define ETM_MAX_SEQ_TRANSITIONS (ETM_MAX_SEQ_STATES - 1)
#define ETM_MAX_EXT_INP_SEL 4
#define ETM_MAX_EXT_INP 256
#define ETM_MAX_EXT_OUT 4
@@ -877,7 +878,7 @@ struct etmv4_config {
u32 vipcssctlr;
u8 seq_idx;
u8 syncfreq;
- u32 seq_ctrl[ETM_MAX_SEQ_STATES];
+ u32 seq_ctrl[ETM_MAX_SEQ_TRANSITIONS];
u32 seq_rst;
u32 seq_state;
u8 cntr_idx;
@@ -928,7 +929,7 @@ struct etmv4_save_state {
u32 trcvissctlr;
u32 trcvipcssctlr;
- u32 trcseqevr[ETM_MAX_SEQ_STATES];
+ u32 trcseqevr[ETM_MAX_SEQ_TRANSITIONS];
u32 trcseqrstevr;
u32 trcseqstr;
u32 trcextinselr;
--
LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7}
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [PATCH v7 03/13] coresight: etm4x: introduce ETM_MAX_SEQ_TRANSITIONS
2026-05-19 15:48 ` [PATCH v7 03/13] coresight: etm4x: introduce ETM_MAX_SEQ_TRANSITIONS Yeoreum Yun
@ 2026-05-28 12:58 ` Leo Yan
2026-05-28 13:47 ` Yeoreum Yun
2026-06-01 9:53 ` Suzuki K Poulose
1 sibling, 1 reply; 39+ messages in thread
From: Leo Yan @ 2026-05-28 12:58 UTC (permalink / raw)
To: Yeoreum Yun
Cc: coresight, linux-arm-kernel, linux-kernel, suzuki.poulose,
mike.leach, james.clark, alexander.shishkin, jie.gan
On Tue, May 19, 2026 at 04:48:02PM +0100, Yeoreum Yun wrote:
> According to IHI006H Embedded Trace Macrocell Architecture
> Specification [0], n could be 0-2 for TCRSEQEVR<n> when
> TCRIDR5.NUMSEQSTATE is 0b100.
>
> Therefore, introduce ETM_MAX_SEQ_TRANSITIONS macro and apply this
> in TCRSEQEVR<n> relevant fields.
>
> Link: https://developer.arm.com/documentation/ihi0064/latest/ [0]
> Suggestedby: Leo Yan <leo.yan@arm.com>
s/Suggestedby/Suggested-by
> Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
The change looks good to me:
Reviewed-by: Leo Yan <leo.yan@arm.com>
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v7 03/13] coresight: etm4x: introduce ETM_MAX_SEQ_TRANSITIONS
2026-05-28 12:58 ` Leo Yan
@ 2026-05-28 13:47 ` Yeoreum Yun
0 siblings, 0 replies; 39+ messages in thread
From: Yeoreum Yun @ 2026-05-28 13:47 UTC (permalink / raw)
To: Leo Yan
Cc: coresight, linux-arm-kernel, linux-kernel, suzuki.poulose,
mike.leach, james.clark, alexander.shishkin, jie.gan
On Thu, May 28, 2026 at 01:58:56PM +0100, Leo Yan wrote:
> On Tue, May 19, 2026 at 04:48:02PM +0100, Yeoreum Yun wrote:
> > According to IHI006H Embedded Trace Macrocell Architecture
> > Specification [0], n could be 0-2 for TCRSEQEVR<n> when
> > TCRIDR5.NUMSEQSTATE is 0b100.
> >
> > Therefore, introduce ETM_MAX_SEQ_TRANSITIONS macro and apply this
> > in TCRSEQEVR<n> relevant fields.
> >
> > Link: https://developer.arm.com/documentation/ihi0064/latest/ [0]
> > Suggestedby: Leo Yan <leo.yan@arm.com>
>
> s/Suggestedby/Suggested-by
Bad typo.. I'll fix.
>
> > Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
>
> The change looks good to me:
>
> Reviewed-by: Leo Yan <leo.yan@arm.com>
Thanks ;)
--
Sincerely,
Yeoreum Yun
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v7 03/13] coresight: etm4x: introduce ETM_MAX_SEQ_TRANSITIONS
2026-05-19 15:48 ` [PATCH v7 03/13] coresight: etm4x: introduce ETM_MAX_SEQ_TRANSITIONS Yeoreum Yun
2026-05-28 12:58 ` Leo Yan
@ 2026-06-01 9:53 ` Suzuki K Poulose
2026-06-01 11:14 ` Yeoreum Yun
1 sibling, 1 reply; 39+ messages in thread
From: Suzuki K Poulose @ 2026-06-01 9:53 UTC (permalink / raw)
To: Yeoreum Yun, coresight, linux-arm-kernel, linux-kernel
Cc: mike.leach, james.clark, alexander.shishkin, leo.yan, jie.gan
On 19/05/2026 16:48, Yeoreum Yun wrote:
> According to IHI006H Embedded Trace Macrocell Architecture
> Specification [0], n could be 0-2 for TCRSEQEVR<n> when
> TCRIDR5.NUMSEQSTATE is 0b100.
>
> Therefore, introduce ETM_MAX_SEQ_TRANSITIONS macro and apply this
> in TCRSEQEVR<n> relevant fields.
>
> Link: https://developer.arm.com/documentation/ihi0064/latest/ [0]
> Suggestedby: Leo Yan <leo.yan@arm.com>
> Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
> ---
> drivers/hwtracing/coresight/coresight-etm4x-cfg.c | 2 +-
> drivers/hwtracing/coresight/coresight-etm4x.h | 5 +++--
> 2 files changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
> index c302072b293a..e1a59b434505 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
> @@ -76,7 +76,7 @@ static int etm4_cfg_map_reg_offset(struct etmv4_drvdata *drvdata,
> } else if ((offset & GENMASK(11, 4)) == TRCSEQEVRn(0)) {
> /* sequencer state control registers */
> idx = (offset & GENMASK(3, 0)) / 4;
> - if (idx < ETM_MAX_SEQ_STATES) {
> + if (idx < ETM_MAX_SEQ_TRANSITIONS) {
> reg_csdev->driver_regval = &drvcfg->seq_ctrl[idx];
> err = 0;
> }
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
> index 89d81ce4e04e..60e08ab085c5 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.h
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
> @@ -614,6 +614,7 @@ static inline u32 etm4_res_sel_pair(u8 res_sel_idx)
> #define ETM_MAX_NR_PE 8
> #define ETMv4_MAX_CNTR 4
> #define ETM_MAX_SEQ_STATES 4
> +#define ETM_MAX_SEQ_TRANSITIONS (ETM_MAX_SEQ_STATES - 1)
Similar to the other comment on the patch, please don't tie this to
SEQ_STATES. Simpl define.
#define ETM_MAX_SEQ_CTRLS 3
Suzuki
> #define ETM_MAX_EXT_INP_SEL 4
> #define ETM_MAX_EXT_INP 256
> #define ETM_MAX_EXT_OUT 4
> @@ -877,7 +878,7 @@ struct etmv4_config {
> u32 vipcssctlr;
> u8 seq_idx;
> u8 syncfreq;
> - u32 seq_ctrl[ETM_MAX_SEQ_STATES];
> + u32 seq_ctrl[ETM_MAX_SEQ_TRANSITIONS];
> u32 seq_rst;
> u32 seq_state;
> u8 cntr_idx;
> @@ -928,7 +929,7 @@ struct etmv4_save_state {
> u32 trcvissctlr;
> u32 trcvipcssctlr;
>
> - u32 trcseqevr[ETM_MAX_SEQ_STATES];
> + u32 trcseqevr[ETM_MAX_SEQ_TRANSITIONS];
> u32 trcseqrstevr;
> u32 trcseqstr;
> u32 trcextinselr;
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [PATCH v7 03/13] coresight: etm4x: introduce ETM_MAX_SEQ_TRANSITIONS
2026-06-01 9:53 ` Suzuki K Poulose
@ 2026-06-01 11:14 ` Yeoreum Yun
0 siblings, 0 replies; 39+ messages in thread
From: Yeoreum Yun @ 2026-06-01 11:14 UTC (permalink / raw)
To: Suzuki K Poulose
Cc: coresight, linux-arm-kernel, linux-kernel, mike.leach,
james.clark, alexander.shishkin, leo.yan, jie.gan
On Mon, Jun 01, 2026 at 10:53:38AM +0100, Suzuki K Poulose wrote:
> On 19/05/2026 16:48, Yeoreum Yun wrote:
> > According to IHI006H Embedded Trace Macrocell Architecture
> > Specification [0], n could be 0-2 for TCRSEQEVR<n> when
> > TCRIDR5.NUMSEQSTATE is 0b100.
> >
> > Therefore, introduce ETM_MAX_SEQ_TRANSITIONS macro and apply this
> > in TCRSEQEVR<n> relevant fields.
> >
> > Link: https://developer.arm.com/documentation/ihi0064/latest/ [0]
> > Suggestedby: Leo Yan <leo.yan@arm.com>
> > Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
> > ---
> > drivers/hwtracing/coresight/coresight-etm4x-cfg.c | 2 +-
> > drivers/hwtracing/coresight/coresight-etm4x.h | 5 +++--
> > 2 files changed, 4 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
> > index c302072b293a..e1a59b434505 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
> > +++ b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
> > @@ -76,7 +76,7 @@ static int etm4_cfg_map_reg_offset(struct etmv4_drvdata *drvdata,
> > } else if ((offset & GENMASK(11, 4)) == TRCSEQEVRn(0)) {
> > /* sequencer state control registers */
> > idx = (offset & GENMASK(3, 0)) / 4;
> > - if (idx < ETM_MAX_SEQ_STATES) {
> > + if (idx < ETM_MAX_SEQ_TRANSITIONS) {
> > reg_csdev->driver_regval = &drvcfg->seq_ctrl[idx];
> > err = 0;
> > }
> > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
> > index 89d81ce4e04e..60e08ab085c5 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm4x.h
> > +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
> > @@ -614,6 +614,7 @@ static inline u32 etm4_res_sel_pair(u8 res_sel_idx)
> > #define ETM_MAX_NR_PE 8
> > #define ETMv4_MAX_CNTR 4
> > #define ETM_MAX_SEQ_STATES 4
> > +#define ETM_MAX_SEQ_TRANSITIONS (ETM_MAX_SEQ_STATES - 1)
>
> Similar to the other comment on the patch, please don't tie this to
> SEQ_STATES. Simpl define.
>
> #define ETM_MAX_SEQ_CTRLS 3
Okay. I'll untie them. Thanks!
[...]
--
Sincerely,
Yeoreum Yun
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v7 04/13] coresight: etm4x: introduce struct etm4_caps
2026-05-19 15:47 [PATCH v7 00/13] fix several inconsistencies with sysfs configuration in etmX Yeoreum Yun
` (2 preceding siblings ...)
2026-05-19 15:48 ` [PATCH v7 03/13] coresight: etm4x: introduce ETM_MAX_SEQ_TRANSITIONS Yeoreum Yun
@ 2026-05-19 15:48 ` Yeoreum Yun
2026-05-19 15:48 ` [PATCH v7 05/13] coresight: etm4x: exclude ss_status from drvdata->config Yeoreum Yun
` (8 subsequent siblings)
12 siblings, 0 replies; 39+ messages in thread
From: Yeoreum Yun @ 2026-05-19 15:48 UTC (permalink / raw)
To: coresight, linux-arm-kernel, linux-kernel
Cc: suzuki.poulose, mike.leach, james.clark, alexander.shishkin,
leo.yan, jie.gan, Yeoreum Yun
Introduce struct etm4_caps to describe ETMv4 capabilities
and move capabilities information into it.
Reviewed-by: Leo Yan <leo.yan@arm.com>
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
---
.../coresight/coresight-etm4x-core.c | 234 +++++++++---------
.../coresight/coresight-etm4x-sysfs.c | 192 ++++++++------
drivers/hwtracing/coresight/coresight-etm4x.h | 176 ++++++-------
3 files changed, 329 insertions(+), 273 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index 94b9385e964a..53fbc4826628 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -92,8 +92,9 @@ static int etm4_probe_cpu(unsigned int cpu);
*/
static bool etm4x_sspcicrn_present(struct etmv4_drvdata *drvdata, int n)
{
- return (n < drvdata->nr_ss_cmp) &&
- drvdata->nr_pe_cmp &&
+ const struct etmv4_caps *caps = &drvdata->caps;
+
+ return (n < caps->nr_ss_cmp) && caps->nr_pe_cmp &&
(drvdata->config.ss_status[n] & TRCSSCSRn_PC);
}
@@ -164,17 +165,20 @@ static void ete_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
static void etm_detect_os_lock(struct etmv4_drvdata *drvdata,
struct csdev_access *csa)
{
+ struct etmv4_caps *caps = &drvdata->caps;
u32 oslsr = etm4x_relaxed_read32(csa, TRCOSLSR);
- drvdata->os_lock_model = ETM_OSLSR_OSLM(oslsr);
+ caps->os_lock_model = ETM_OSLSR_OSLM(oslsr);
}
static void etm_write_os_lock(struct etmv4_drvdata *drvdata,
struct csdev_access *csa, u32 val)
{
+ const struct etmv4_caps *caps = &drvdata->caps;
+
val = !!val;
- switch (drvdata->os_lock_model) {
+ switch (caps->os_lock_model) {
case ETM_OSLOCK_PRESENT:
etm4x_relaxed_write32(csa, val, TRCOSLAR);
break;
@@ -183,7 +187,7 @@ static void etm_write_os_lock(struct etmv4_drvdata *drvdata,
break;
default:
pr_warn_once("CPU%d: Unsupported Trace OSLock model: %x\n",
- smp_processor_id(), drvdata->os_lock_model);
+ smp_processor_id(), caps->os_lock_model);
fallthrough;
case ETM_OSLOCK_NI:
return;
@@ -492,6 +496,7 @@ static int etm4_enable_trace_unit(struct etmv4_drvdata *drvdata)
static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
{
int i, rc;
+ const struct etmv4_caps *caps = &drvdata->caps;
struct etmv4_config *config = &drvdata->config;
struct coresight_device *csdev = drvdata->csdev;
struct device *etm_dev = &csdev->dev;
@@ -523,14 +528,14 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
if (etm4x_wait_status(csa, TRCSTATR_IDLE_BIT, 1))
dev_err(etm_dev,
"timeout while waiting for Idle Trace Status\n");
- if (drvdata->nr_pe)
+ if (caps->nr_pe)
etm4x_relaxed_write32(csa, config->pe_sel, TRCPROCSELR);
etm4x_relaxed_write32(csa, config->cfg, TRCCONFIGR);
/* nothing specific implemented */
etm4x_relaxed_write32(csa, 0x0, TRCAUXCTLR);
etm4x_relaxed_write32(csa, config->eventctrl0, TRCEVENTCTL0R);
etm4x_relaxed_write32(csa, config->eventctrl1, TRCEVENTCTL1R);
- if (drvdata->stallctl)
+ if (caps->stallctl)
etm4x_relaxed_write32(csa, config->stall_ctrl, TRCSTALLCTLR);
etm4x_relaxed_write32(csa, config->ts_ctrl, TRCTSCTLR);
etm4x_relaxed_write32(csa, config->syncfreq, TRCSYNCPR);
@@ -540,19 +545,19 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
etm4x_relaxed_write32(csa, config->vinst_ctrl, TRCVICTLR);
etm4x_relaxed_write32(csa, config->viiectlr, TRCVIIECTLR);
etm4x_relaxed_write32(csa, config->vissctlr, TRCVISSCTLR);
- if (drvdata->nr_pe_cmp)
+ if (caps->nr_pe_cmp)
etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR);
- if (drvdata->nrseqstate) {
- for (i = 0; i < drvdata->nrseqstate - 1; i++)
+ if (caps->nrseqstate) {
+ for (i = 0; i < caps->nrseqstate - 1; i++)
etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i));
etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR);
etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR);
}
- if (drvdata->numextinsel)
+ if (caps->numextinsel)
etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR);
- for (i = 0; i < drvdata->nr_cntr; i++) {
+ for (i = 0; i < caps->nr_cntr; i++) {
etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i));
etm4x_relaxed_write32(csa, config->cntr_ctrl[i], TRCCNTCTLRn(i));
etm4x_relaxed_write32(csa, config->cntr_val[i], TRCCNTVRn(i));
@@ -562,10 +567,10 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
* Resource selector pair 0 is always implemented and reserved. As
* such start at 2.
*/
- for (i = 2; i < drvdata->nr_resource * 2; i++)
+ for (i = 2; i < caps->nr_resource * 2; i++)
etm4x_relaxed_write32(csa, config->res_ctrl[i], TRCRSCTLRn(i));
- for (i = 0; i < drvdata->nr_ss_cmp; i++) {
+ for (i = 0; i < caps->nr_ss_cmp; i++) {
/* always clear status bit on restart if using single-shot */
if (config->ss_ctrl[i] || config->ss_pe_cmp[i])
config->ss_status[i] &= ~TRCSSCSRn_STATUS;
@@ -574,23 +579,23 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
if (etm4x_sspcicrn_present(drvdata, i))
etm4x_relaxed_write32(csa, config->ss_pe_cmp[i], TRCSSPCICRn(i));
}
- for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
+ for (i = 0; i < caps->nr_addr_cmp * 2; i++) {
etm4x_relaxed_write64(csa, config->addr_val[i], TRCACVRn(i));
etm4x_relaxed_write64(csa, config->addr_acc[i], TRCACATRn(i));
}
- for (i = 0; i < drvdata->numcidc; i++)
+ for (i = 0; i < caps->numcidc; i++)
etm4x_relaxed_write64(csa, config->ctxid_pid[i], TRCCIDCVRn(i));
etm4x_relaxed_write32(csa, config->ctxid_mask0, TRCCIDCCTLR0);
- if (drvdata->numcidc > 4)
+ if (caps->numcidc > 4)
etm4x_relaxed_write32(csa, config->ctxid_mask1, TRCCIDCCTLR1);
- for (i = 0; i < drvdata->numvmidc; i++)
+ for (i = 0; i < caps->numvmidc; i++)
etm4x_relaxed_write64(csa, config->vmid_val[i], TRCVMIDCVRn(i));
etm4x_relaxed_write32(csa, config->vmid_mask0, TRCVMIDCCTLR0);
- if (drvdata->numvmidc > 4)
+ if (caps->numvmidc > 4)
etm4x_relaxed_write32(csa, config->vmid_mask1, TRCVMIDCCTLR1);
- if (!drvdata->skip_power_up) {
+ if (!caps->skip_power_up) {
u32 trcpdcr = etm4x_relaxed_read32(csa, TRCPDCR);
/*
@@ -670,19 +675,20 @@ static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata,
{
int ctridx;
int rselector;
+ const struct etmv4_caps *caps = &drvdata->caps;
struct etmv4_config *config = &drvdata->config;
/* No point in trying if we don't have at least one counter */
- if (!drvdata->nr_cntr)
+ if (!caps->nr_cntr)
return -EINVAL;
/* Find a counter that hasn't been initialised */
- for (ctridx = 0; ctridx < drvdata->nr_cntr; ctridx++)
+ for (ctridx = 0; ctridx < caps->nr_cntr; ctridx++)
if (config->cntr_val[ctridx] == 0)
break;
/* All the counters have been configured already, bail out */
- if (ctridx == drvdata->nr_cntr) {
+ if (ctridx == caps->nr_cntr) {
pr_debug("%s: no available counter found\n", __func__);
return -ENOSPC;
}
@@ -698,11 +704,11 @@ static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata,
* ETMIDR4 gives the number of resource selector _pairs_, hence multiply
* by 2.
*/
- for (rselector = 2; rselector < drvdata->nr_resource * 2; rselector++)
+ for (rselector = 2; rselector < caps->nr_resource * 2; rselector++)
if (!config->res_ctrl[rselector])
break;
- if (rselector == drvdata->nr_resource * 2) {
+ if (rselector == caps->nr_resource * 2) {
pr_debug("%s: no available resource selector found\n",
__func__);
return -ENOSPC;
@@ -753,6 +759,7 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
{
int ret = 0;
struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
+ const struct etmv4_caps *caps = &drvdata->caps;
struct etmv4_config *config = &drvdata->config;
struct perf_event_attr max_timestamp = {
.ATTR_CFG_FLD_timestamp_CFG = U64_MAX,
@@ -792,8 +799,8 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
cc_threshold = ATTR_CFG_GET_FLD(attr, cc_threshold);
if (!cc_threshold)
cc_threshold = ETM_CYC_THRESHOLD_DEFAULT;
- if (cc_threshold < drvdata->ccitmin)
- cc_threshold = drvdata->ccitmin;
+ if (cc_threshold < caps->ccitmin)
+ cc_threshold = caps->ccitmin;
config->ccctlr = cc_threshold;
}
@@ -841,7 +848,7 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
}
/* return stack - enable if selected and supported */
- if (ATTR_CFG_GET_FLD(attr, retstack) && drvdata->retstack)
+ if (ATTR_CFG_GET_FLD(attr, retstack) && caps->retstack)
/* bit[12], Return stack enable bit */
config->cfg |= TRCCONFIGR_RS;
@@ -857,7 +864,7 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
/* branch broadcast - enable if selected and supported */
if (ATTR_CFG_GET_FLD(attr, branch_broadcast)) {
- if (!drvdata->trcbb) {
+ if (!caps->trcbb) {
/*
* Missing BB support could cause silent decode errors
* so fail to open if it's not supported.
@@ -1037,6 +1044,7 @@ static void etm4_disable_trace_unit(struct etmv4_drvdata *drvdata)
static void etm4_disable_hw(struct etmv4_drvdata *drvdata)
{
u32 control;
+ const struct etmv4_caps *caps = &drvdata->caps;
struct etmv4_config *config = &drvdata->config;
struct coresight_device *csdev = drvdata->csdev;
struct csdev_access *csa = &csdev->access;
@@ -1045,7 +1053,7 @@ static void etm4_disable_hw(struct etmv4_drvdata *drvdata)
etm4_cs_unlock(drvdata, csa);
etm4_disable_arch_specific(drvdata);
- if (!drvdata->skip_power_up) {
+ if (!caps->skip_power_up) {
/* power can be removed from the trace unit now */
control = etm4x_relaxed_read32(csa, TRCPDCR);
control &= ~TRCPDCR_PU;
@@ -1055,13 +1063,13 @@ static void etm4_disable_hw(struct etmv4_drvdata *drvdata)
etm4_disable_trace_unit(drvdata);
/* read the status of the single shot comparators */
- for (i = 0; i < drvdata->nr_ss_cmp; i++) {
+ for (i = 0; i < caps->nr_ss_cmp; i++) {
config->ss_status[i] =
etm4x_relaxed_read32(csa, TRCSSCSRn(i));
}
/* read back the current counter values */
- for (i = 0; i < drvdata->nr_cntr; i++) {
+ for (i = 0; i < caps->nr_cntr; i++) {
config->cntr_val[i] =
etm4x_relaxed_read32(csa, TRCCNTVRn(i));
}
@@ -1346,7 +1354,7 @@ static struct midr_range etm_wrong_ccitmin_cpus[] = {
{},
};
-static void etm4_fixup_wrong_ccitmin(struct etmv4_drvdata *drvdata)
+static void etm4_fixup_wrong_ccitmin(struct etmv4_caps *caps)
{
/*
* Erratum affected cpus will read 256 as the minimum
@@ -1356,8 +1364,8 @@ static void etm4_fixup_wrong_ccitmin(struct etmv4_drvdata *drvdata)
* this problem.
*/
if (is_midr_in_range_list(etm_wrong_ccitmin_cpus)) {
- if (drvdata->ccitmin == 256)
- drvdata->ccitmin = 4;
+ if (caps->ccitmin == 256)
+ caps->ccitmin = 4;
}
}
@@ -1370,11 +1378,13 @@ static void etm4_init_arch_data(void *info)
u32 etmidr5;
struct etm4_init_arg *init_arg = info;
struct etmv4_drvdata *drvdata;
+ struct etmv4_caps *caps;
struct csdev_access *csa;
struct device *dev = init_arg->dev;
int i;
drvdata = dev_get_drvdata(init_arg->dev);
+ caps = &drvdata->caps;
csa = init_arg->csa;
/*
@@ -1387,7 +1397,7 @@ static void etm4_init_arch_data(void *info)
if (!csa->io_mem ||
fwnode_property_present(dev_fwnode(dev), "qcom,skip-power-up"))
- drvdata->skip_power_up = true;
+ caps->skip_power_up = true;
/* Detect the support for OS Lock before we actually use it */
etm_detect_os_lock(drvdata, csa);
@@ -1402,71 +1412,71 @@ static void etm4_init_arch_data(void *info)
etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0);
/* INSTP0, bits[2:1] P0 tracing support field */
- drvdata->instrp0 = !!(FIELD_GET(TRCIDR0_INSTP0_MASK, etmidr0) == 0b11);
+ caps->instrp0 = !!(FIELD_GET(TRCIDR0_INSTP0_MASK, etmidr0) == 0b11);
/* TRCBB, bit[5] Branch broadcast tracing support bit */
- drvdata->trcbb = !!(etmidr0 & TRCIDR0_TRCBB);
+ caps->trcbb = !!(etmidr0 & TRCIDR0_TRCBB);
/* TRCCOND, bit[6] Conditional instruction tracing support bit */
- drvdata->trccond = !!(etmidr0 & TRCIDR0_TRCCOND);
+ caps->trccond = !!(etmidr0 & TRCIDR0_TRCCOND);
/* TRCCCI, bit[7] Cycle counting instruction bit */
- drvdata->trccci = !!(etmidr0 & TRCIDR0_TRCCCI);
+ caps->trccci = !!(etmidr0 & TRCIDR0_TRCCCI);
/* RETSTACK, bit[9] Return stack bit */
- drvdata->retstack = !!(etmidr0 & TRCIDR0_RETSTACK);
+ caps->retstack = !!(etmidr0 & TRCIDR0_RETSTACK);
/* NUMEVENT, bits[11:10] Number of events field */
- drvdata->nr_event = FIELD_GET(TRCIDR0_NUMEVENT_MASK, etmidr0);
+ caps->nr_event = FIELD_GET(TRCIDR0_NUMEVENT_MASK, etmidr0);
/* QSUPP, bits[16:15] Q element support field */
- drvdata->q_support = FIELD_GET(TRCIDR0_QSUPP_MASK, etmidr0);
- if (drvdata->q_support)
- drvdata->q_filt = !!(etmidr0 & TRCIDR0_QFILT);
+ caps->q_support = FIELD_GET(TRCIDR0_QSUPP_MASK, etmidr0);
+ if (caps->q_support)
+ caps->q_filt = !!(etmidr0 & TRCIDR0_QFILT);
/* TSSIZE, bits[28:24] Global timestamp size field */
- drvdata->ts_size = FIELD_GET(TRCIDR0_TSSIZE_MASK, etmidr0);
+ caps->ts_size = FIELD_GET(TRCIDR0_TSSIZE_MASK, etmidr0);
/* maximum size of resources */
etmidr2 = etm4x_relaxed_read32(csa, TRCIDR2);
/* CIDSIZE, bits[9:5] Indicates the Context ID size */
- drvdata->ctxid_size = FIELD_GET(TRCIDR2_CIDSIZE_MASK, etmidr2);
+ caps->ctxid_size = FIELD_GET(TRCIDR2_CIDSIZE_MASK, etmidr2);
/* VMIDSIZE, bits[14:10] Indicates the VMID size */
- drvdata->vmid_size = FIELD_GET(TRCIDR2_VMIDSIZE_MASK, etmidr2);
+ caps->vmid_size = FIELD_GET(TRCIDR2_VMIDSIZE_MASK, etmidr2);
/* CCSIZE, bits[28:25] size of the cycle counter in bits minus 12 */
- drvdata->ccsize = FIELD_GET(TRCIDR2_CCSIZE_MASK, etmidr2);
+ caps->ccsize = FIELD_GET(TRCIDR2_CCSIZE_MASK, etmidr2);
etmidr3 = etm4x_relaxed_read32(csa, TRCIDR3);
/* CCITMIN, bits[11:0] minimum threshold value that can be programmed */
- drvdata->ccitmin = FIELD_GET(TRCIDR3_CCITMIN_MASK, etmidr3);
- etm4_fixup_wrong_ccitmin(drvdata);
+ caps->ccitmin = FIELD_GET(TRCIDR3_CCITMIN_MASK, etmidr3);
+ etm4_fixup_wrong_ccitmin(caps);
/* EXLEVEL_S, bits[19:16] Secure state instruction tracing */
- drvdata->s_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_S_MASK, etmidr3);
- drvdata->config.s_ex_level = drvdata->s_ex_level;
+ caps->s_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_S_MASK, etmidr3);
+ drvdata->config.s_ex_level = caps->s_ex_level;
/* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */
- drvdata->ns_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_NS_MASK, etmidr3);
+ caps->ns_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_NS_MASK, etmidr3);
/*
* TRCERR, bit[24] whether a trace unit can trace a
* system error exception.
*/
- drvdata->trc_error = !!(etmidr3 & TRCIDR3_TRCERR);
+ caps->trc_error = !!(etmidr3 & TRCIDR3_TRCERR);
/* SYNCPR, bit[25] implementation has a fixed synchronization period? */
- drvdata->syncpr = !!(etmidr3 & TRCIDR3_SYNCPR);
+ caps->syncpr = !!(etmidr3 & TRCIDR3_SYNCPR);
/* STALLCTL, bit[26] is stall control implemented? */
- drvdata->stallctl = !!(etmidr3 & TRCIDR3_STALLCTL);
+ caps->stallctl = !!(etmidr3 & TRCIDR3_STALLCTL);
/* SYSSTALL, bit[27] implementation can support stall control? */
- drvdata->sysstall = !!(etmidr3 & TRCIDR3_SYSSTALL);
+ caps->sysstall = !!(etmidr3 & TRCIDR3_SYSSTALL);
/*
* NUMPROC - the number of PEs available for tracing, 5bits
* = TRCIDR3.bits[13:12]bits[30:28]
* bits[4:3] = TRCIDR3.bits[13:12] (since etm-v4.2, otherwise RES0)
* bits[3:0] = TRCIDR3.bits[30:28]
*/
- drvdata->nr_pe = (FIELD_GET(TRCIDR3_NUMPROC_HI_MASK, etmidr3) << 3) |
- FIELD_GET(TRCIDR3_NUMPROC_LO_MASK, etmidr3);
+ caps->nr_pe = (FIELD_GET(TRCIDR3_NUMPROC_HI_MASK, etmidr3) << 3) |
+ FIELD_GET(TRCIDR3_NUMPROC_LO_MASK, etmidr3);
/* NOOVERFLOW, bit[31] is trace overflow prevention supported */
- drvdata->nooverflow = !!(etmidr3 & TRCIDR3_NOOVERFLOW);
+ caps->nooverflow = !!(etmidr3 & TRCIDR3_NOOVERFLOW);
/* number of resources trace unit supports */
etmidr4 = etm4x_relaxed_read32(csa, TRCIDR4);
/* NUMACPAIRS, bits[0:3] number of addr comparator pairs for tracing */
- drvdata->nr_addr_cmp = FIELD_GET(TRCIDR4_NUMACPAIRS_MASK, etmidr4);
+ caps->nr_addr_cmp = FIELD_GET(TRCIDR4_NUMACPAIRS_MASK, etmidr4);
/* NUMPC, bits[15:12] number of PE comparator inputs for tracing */
- drvdata->nr_pe_cmp = FIELD_GET(TRCIDR4_NUMPC_MASK, etmidr4);
+ caps->nr_pe_cmp = FIELD_GET(TRCIDR4_NUMPC_MASK, etmidr4);
/*
* NUMRSPAIR, bits[19:16]
* The number of resource pairs conveyed by the HW starts at 0, i.e a
@@ -1477,41 +1487,41 @@ static void etm4_init_arch_data(void *info)
* the default TRUE and FALSE resource selectors are omitted.
* Otherwise for values 0x1 and above the number is N + 1 as per v4.2.
*/
- drvdata->nr_resource = FIELD_GET(TRCIDR4_NUMRSPAIR_MASK, etmidr4);
- if ((drvdata->arch < ETM_ARCH_V4_3) || (drvdata->nr_resource > 0))
- drvdata->nr_resource += 1;
+ caps->nr_resource = FIELD_GET(TRCIDR4_NUMRSPAIR_MASK, etmidr4);
+ if ((drvdata->arch < ETM_ARCH_V4_3) || (caps->nr_resource > 0))
+ caps->nr_resource += 1;
/*
* NUMSSCC, bits[23:20] the number of single-shot
* comparator control for tracing. Read any status regs as these
* also contain RO capability data.
*/
- drvdata->nr_ss_cmp = FIELD_GET(TRCIDR4_NUMSSCC_MASK, etmidr4);
- for (i = 0; i < drvdata->nr_ss_cmp; i++) {
+ caps->nr_ss_cmp = FIELD_GET(TRCIDR4_NUMSSCC_MASK, etmidr4);
+ for (i = 0; i < caps->nr_ss_cmp; i++) {
drvdata->config.ss_status[i] =
etm4x_relaxed_read32(csa, TRCSSCSRn(i));
}
/* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */
- drvdata->numcidc = FIELD_GET(TRCIDR4_NUMCIDC_MASK, etmidr4);
+ caps->numcidc = FIELD_GET(TRCIDR4_NUMCIDC_MASK, etmidr4);
/* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */
- drvdata->numvmidc = FIELD_GET(TRCIDR4_NUMVMIDC_MASK, etmidr4);
+ caps->numvmidc = FIELD_GET(TRCIDR4_NUMVMIDC_MASK, etmidr4);
etmidr5 = etm4x_relaxed_read32(csa, TRCIDR5);
/* NUMEXTIN, bits[8:0] number of external inputs implemented */
- drvdata->nr_ext_inp = FIELD_GET(TRCIDR5_NUMEXTIN_MASK, etmidr5);
- drvdata->numextinsel = FIELD_GET(TRCIDR5_NUMEXTINSEL_MASK, etmidr5);
+ caps->nr_ext_inp = FIELD_GET(TRCIDR5_NUMEXTIN_MASK, etmidr5);
+ caps->numextinsel = FIELD_GET(TRCIDR5_NUMEXTINSEL_MASK, etmidr5);
/* TRACEIDSIZE, bits[21:16] indicates the trace ID width */
- drvdata->trcid_size = FIELD_GET(TRCIDR5_TRACEIDSIZE_MASK, etmidr5);
+ caps->trcid_size = FIELD_GET(TRCIDR5_TRACEIDSIZE_MASK, etmidr5);
/* ATBTRIG, bit[22] implementation can support ATB triggers? */
- drvdata->atbtrig = !!(etmidr5 & TRCIDR5_ATBTRIG);
+ caps->atbtrig = !!(etmidr5 & TRCIDR5_ATBTRIG);
/*
* LPOVERRIDE, bit[23] implementation supports
* low-power state override
*/
- drvdata->lpoverride = (etmidr5 & TRCIDR5_LPOVERRIDE) && (!drvdata->skip_power_up);
+ caps->lpoverride = (etmidr5 & TRCIDR5_LPOVERRIDE) && (!caps->skip_power_up);
/* NUMSEQSTATE, bits[27:25] number of sequencer states implemented */
- drvdata->nrseqstate = FIELD_GET(TRCIDR5_NUMSEQSTATE_MASK, etmidr5);
+ caps->nrseqstate = FIELD_GET(TRCIDR5_NUMSEQSTATE_MASK, etmidr5);
/* NUMCNTR, bits[30:28] number of counters available for tracing */
- drvdata->nr_cntr = FIELD_GET(TRCIDR5_NUMCNTR_MASK, etmidr5);
+ caps->nr_cntr = FIELD_GET(TRCIDR5_NUMCNTR_MASK, etmidr5);
coresight_clear_self_claim_tag_unlocked(csa);
etm4_cs_lock(drvdata, csa);
@@ -1687,7 +1697,7 @@ static int etm4_get_next_comparator(struct etmv4_drvdata *drvdata, u32 type)
* nr_addr_cmp holds the number of comparator _pair_, so time 2
* for the total number of comparators.
*/
- nr_comparator = drvdata->nr_addr_cmp * 2;
+ nr_comparator = drvdata->caps.nr_addr_cmp * 2;
/* Go through the tally of comparators looking for a free one. */
while (index < nr_comparator) {
@@ -1844,6 +1854,7 @@ static int etm4_cpu_save(struct coresight_device *csdev)
{
int i, ret = 0;
struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
+ const struct etmv4_caps *caps = &drvdata->caps;
struct etmv4_save_state *state;
struct csdev_access *csa;
struct device *etm_dev;
@@ -1876,57 +1887,57 @@ static int etm4_cpu_save(struct coresight_device *csdev)
state = drvdata->save_state;
- if (drvdata->nr_pe)
+ if (caps->nr_pe)
state->trcprocselr = etm4x_read32(csa, TRCPROCSELR);
state->trcconfigr = etm4x_read32(csa, TRCCONFIGR);
state->trcauxctlr = etm4x_read32(csa, TRCAUXCTLR);
state->trceventctl0r = etm4x_read32(csa, TRCEVENTCTL0R);
state->trceventctl1r = etm4x_read32(csa, TRCEVENTCTL1R);
- if (drvdata->stallctl)
+ if (caps->stallctl)
state->trcstallctlr = etm4x_read32(csa, TRCSTALLCTLR);
state->trctsctlr = etm4x_read32(csa, TRCTSCTLR);
state->trcsyncpr = etm4x_read32(csa, TRCSYNCPR);
state->trcccctlr = etm4x_read32(csa, TRCCCCTLR);
state->trcbbctlr = etm4x_read32(csa, TRCBBCTLR);
state->trctraceidr = etm4x_read32(csa, TRCTRACEIDR);
- if (drvdata->q_filt)
+ if (caps->q_filt)
state->trcqctlr = etm4x_read32(csa, TRCQCTLR);
state->trcvictlr = etm4x_read32(csa, TRCVICTLR);
state->trcviiectlr = etm4x_read32(csa, TRCVIIECTLR);
state->trcvissctlr = etm4x_read32(csa, TRCVISSCTLR);
- if (drvdata->nr_pe_cmp)
+ if (caps->nr_pe_cmp)
state->trcvipcssctlr = etm4x_read32(csa, TRCVIPCSSCTLR);
- if (drvdata->nrseqstate) {
- for (i = 0; i < drvdata->nrseqstate - 1; i++)
+ if (caps->nrseqstate) {
+ for (i = 0; i < caps->nrseqstate - 1; i++)
state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i));
state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR);
state->trcseqstr = etm4x_read32(csa, TRCSEQSTR);
}
- if (drvdata->numextinsel)
+ if (caps->numextinsel)
state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR);
- for (i = 0; i < drvdata->nr_cntr; i++) {
+ for (i = 0; i < caps->nr_cntr; i++) {
state->trccntrldvr[i] = etm4x_read32(csa, TRCCNTRLDVRn(i));
state->trccntctlr[i] = etm4x_read32(csa, TRCCNTCTLRn(i));
state->trccntvr[i] = etm4x_read32(csa, TRCCNTVRn(i));
}
/* Resource selector pair 0 is reserved */
- for (i = 2; i < drvdata->nr_resource * 2; i++)
+ for (i = 2; i < caps->nr_resource * 2; i++)
state->trcrsctlr[i] = etm4x_read32(csa, TRCRSCTLRn(i));
- for (i = 0; i < drvdata->nr_ss_cmp; i++) {
+ for (i = 0; i < caps->nr_ss_cmp; i++) {
state->trcssccr[i] = etm4x_read32(csa, TRCSSCCRn(i));
state->trcsscsr[i] = etm4x_read32(csa, TRCSSCSRn(i));
if (etm4x_sspcicrn_present(drvdata, i))
state->trcsspcicr[i] = etm4x_read32(csa, TRCSSPCICRn(i));
}
- for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
+ for (i = 0; i < caps->nr_addr_cmp * 2; i++) {
state->trcacvr[i] = etm4x_read64(csa, TRCACVRn(i));
state->trcacatr[i] = etm4x_read64(csa, TRCACATRn(i));
}
@@ -1938,23 +1949,23 @@ static int etm4_cpu_save(struct coresight_device *csdev)
* unit") of ARM IHI 0064D.
*/
- for (i = 0; i < drvdata->numcidc; i++)
+ for (i = 0; i < caps->numcidc; i++)
state->trccidcvr[i] = etm4x_read64(csa, TRCCIDCVRn(i));
- for (i = 0; i < drvdata->numvmidc; i++)
+ for (i = 0; i < caps->numvmidc; i++)
state->trcvmidcvr[i] = etm4x_read64(csa, TRCVMIDCVRn(i));
state->trccidcctlr0 = etm4x_read32(csa, TRCCIDCCTLR0);
- if (drvdata->numcidc > 4)
+ if (caps->numcidc > 4)
state->trccidcctlr1 = etm4x_read32(csa, TRCCIDCCTLR1);
state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR0);
- if (drvdata->numvmidc > 4)
+ if (caps->numvmidc > 4)
state->trcvmidcctlr1 = etm4x_read32(csa, TRCVMIDCCTLR1);
state->trcclaimset = etm4x_read32(csa, TRCCLAIMCLR);
- if (!drvdata->skip_power_up)
+ if (!caps->skip_power_up)
state->trcpdcr = etm4x_read32(csa, TRCPDCR);
/* wait for TRCSTATR.IDLE to go up */
@@ -1971,7 +1982,7 @@ static int etm4_cpu_save(struct coresight_device *csdev)
* potentially save power on systems that respect the TRCPDCR_PU
* despite requesting software to save/restore state.
*/
- if (!drvdata->skip_power_up)
+ if (!caps->skip_power_up)
etm4x_relaxed_write32(csa, (state->trcpdcr & ~TRCPDCR_PU),
TRCPDCR);
out:
@@ -1983,83 +1994,84 @@ static void etm4_cpu_restore(struct coresight_device *csdev)
{
int i;
struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
+ const struct etmv4_caps *caps = &drvdata->caps;
struct etmv4_save_state *state = drvdata->save_state;
struct csdev_access *csa = &drvdata->csdev->access;
etm4_cs_unlock(drvdata, csa);
etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET);
- if (drvdata->nr_pe)
+ if (caps->nr_pe)
etm4x_relaxed_write32(csa, state->trcprocselr, TRCPROCSELR);
etm4x_relaxed_write32(csa, state->trcconfigr, TRCCONFIGR);
etm4x_relaxed_write32(csa, state->trcauxctlr, TRCAUXCTLR);
etm4x_relaxed_write32(csa, state->trceventctl0r, TRCEVENTCTL0R);
etm4x_relaxed_write32(csa, state->trceventctl1r, TRCEVENTCTL1R);
- if (drvdata->stallctl)
+ if (caps->stallctl)
etm4x_relaxed_write32(csa, state->trcstallctlr, TRCSTALLCTLR);
etm4x_relaxed_write32(csa, state->trctsctlr, TRCTSCTLR);
etm4x_relaxed_write32(csa, state->trcsyncpr, TRCSYNCPR);
etm4x_relaxed_write32(csa, state->trcccctlr, TRCCCCTLR);
etm4x_relaxed_write32(csa, state->trcbbctlr, TRCBBCTLR);
etm4x_relaxed_write32(csa, state->trctraceidr, TRCTRACEIDR);
- if (drvdata->q_filt)
+ if (caps->q_filt)
etm4x_relaxed_write32(csa, state->trcqctlr, TRCQCTLR);
etm4x_relaxed_write32(csa, state->trcvictlr, TRCVICTLR);
etm4x_relaxed_write32(csa, state->trcviiectlr, TRCVIIECTLR);
etm4x_relaxed_write32(csa, state->trcvissctlr, TRCVISSCTLR);
- if (drvdata->nr_pe_cmp)
+ if (caps->nr_pe_cmp)
etm4x_relaxed_write32(csa, state->trcvipcssctlr, TRCVIPCSSCTLR);
- if (drvdata->nrseqstate) {
- for (i = 0; i < drvdata->nrseqstate - 1; i++)
+ if (caps->nrseqstate) {
+ for (i = 0; i < caps->nrseqstate - 1; i++)
etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i));
etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR);
etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR);
}
- if (drvdata->numextinsel)
+ if (caps->numextinsel)
etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR);
- for (i = 0; i < drvdata->nr_cntr; i++) {
+ for (i = 0; i < caps->nr_cntr; i++) {
etm4x_relaxed_write32(csa, state->trccntrldvr[i], TRCCNTRLDVRn(i));
etm4x_relaxed_write32(csa, state->trccntctlr[i], TRCCNTCTLRn(i));
etm4x_relaxed_write32(csa, state->trccntvr[i], TRCCNTVRn(i));
}
/* Resource selector pair 0 is reserved */
- for (i = 2; i < drvdata->nr_resource * 2; i++)
+ for (i = 2; i < caps->nr_resource * 2; i++)
etm4x_relaxed_write32(csa, state->trcrsctlr[i], TRCRSCTLRn(i));
- for (i = 0; i < drvdata->nr_ss_cmp; i++) {
+ for (i = 0; i < caps->nr_ss_cmp; i++) {
etm4x_relaxed_write32(csa, state->trcssccr[i], TRCSSCCRn(i));
etm4x_relaxed_write32(csa, state->trcsscsr[i], TRCSSCSRn(i));
if (etm4x_sspcicrn_present(drvdata, i))
etm4x_relaxed_write32(csa, state->trcsspcicr[i], TRCSSPCICRn(i));
}
- for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
+ for (i = 0; i < caps->nr_addr_cmp * 2; i++) {
etm4x_relaxed_write64(csa, state->trcacvr[i], TRCACVRn(i));
etm4x_relaxed_write64(csa, state->trcacatr[i], TRCACATRn(i));
}
- for (i = 0; i < drvdata->numcidc; i++)
+ for (i = 0; i < caps->numcidc; i++)
etm4x_relaxed_write64(csa, state->trccidcvr[i], TRCCIDCVRn(i));
- for (i = 0; i < drvdata->numvmidc; i++)
+ for (i = 0; i < caps->numvmidc; i++)
etm4x_relaxed_write64(csa, state->trcvmidcvr[i], TRCVMIDCVRn(i));
etm4x_relaxed_write32(csa, state->trccidcctlr0, TRCCIDCCTLR0);
- if (drvdata->numcidc > 4)
+ if (caps->numcidc > 4)
etm4x_relaxed_write32(csa, state->trccidcctlr1, TRCCIDCCTLR1);
etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR0);
- if (drvdata->numvmidc > 4)
+ if (caps->numvmidc > 4)
etm4x_relaxed_write32(csa, state->trcvmidcctlr1, TRCVMIDCCTLR1);
etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET);
- if (!drvdata->skip_power_up)
+ if (!caps->skip_power_up)
etm4x_relaxed_write32(csa, state->trcpdcr, TRCPDCR);
/*
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
index 0e1ad175aa1e..7de3c58a47b4 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
@@ -62,8 +62,9 @@ static ssize_t nr_pe_cmp_show(struct device *dev,
{
unsigned long val;
struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ const struct etmv4_caps *caps = &drvdata->caps;
- val = drvdata->nr_pe_cmp;
+ val = caps->nr_pe_cmp;
return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
}
static DEVICE_ATTR_RO(nr_pe_cmp);
@@ -74,8 +75,9 @@ static ssize_t nr_addr_cmp_show(struct device *dev,
{
unsigned long val;
struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ const struct etmv4_caps *caps = &drvdata->caps;
- val = drvdata->nr_addr_cmp;
+ val = caps->nr_addr_cmp;
return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
}
static DEVICE_ATTR_RO(nr_addr_cmp);
@@ -86,8 +88,9 @@ static ssize_t nr_cntr_show(struct device *dev,
{
unsigned long val;
struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ const struct etmv4_caps *caps = &drvdata->caps;
- val = drvdata->nr_cntr;
+ val = caps->nr_cntr;
return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
}
static DEVICE_ATTR_RO(nr_cntr);
@@ -98,8 +101,9 @@ static ssize_t nr_ext_inp_show(struct device *dev,
{
unsigned long val;
struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ const struct etmv4_caps *caps = &drvdata->caps;
- val = drvdata->nr_ext_inp;
+ val = caps->nr_ext_inp;
return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
}
static DEVICE_ATTR_RO(nr_ext_inp);
@@ -110,8 +114,9 @@ static ssize_t numcidc_show(struct device *dev,
{
unsigned long val;
struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ const struct etmv4_caps *caps = &drvdata->caps;
- val = drvdata->numcidc;
+ val = caps->numcidc;
return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
}
static DEVICE_ATTR_RO(numcidc);
@@ -122,8 +127,9 @@ static ssize_t numvmidc_show(struct device *dev,
{
unsigned long val;
struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ const struct etmv4_caps *caps = &drvdata->caps;
- val = drvdata->numvmidc;
+ val = caps->numvmidc;
return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
}
static DEVICE_ATTR_RO(numvmidc);
@@ -134,8 +140,9 @@ static ssize_t nrseqstate_show(struct device *dev,
{
unsigned long val;
struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ const struct etmv4_caps *caps = &drvdata->caps;
- val = drvdata->nrseqstate;
+ val = caps->nrseqstate;
return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
}
static DEVICE_ATTR_RO(nrseqstate);
@@ -146,8 +153,9 @@ static ssize_t nr_resource_show(struct device *dev,
{
unsigned long val;
struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ const struct etmv4_caps *caps = &drvdata->caps;
- val = drvdata->nr_resource;
+ val = caps->nr_resource;
return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
}
static DEVICE_ATTR_RO(nr_resource);
@@ -158,8 +166,9 @@ static ssize_t nr_ss_cmp_show(struct device *dev,
{
unsigned long val;
struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ const struct etmv4_caps *caps = &drvdata->caps;
- val = drvdata->nr_ss_cmp;
+ val = caps->nr_ss_cmp;
return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
}
static DEVICE_ATTR_RO(nr_ss_cmp);
@@ -171,6 +180,7 @@ static ssize_t reset_store(struct device *dev,
int i;
unsigned long val;
struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ const struct etmv4_caps *caps = &drvdata->caps;
struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val))
@@ -200,7 +210,7 @@ static ssize_t reset_store(struct device *dev,
config->stall_ctrl = 0x0;
/* Reset trace synchronization period to 2^8 = 256 bytes*/
- if (drvdata->syncpr == false)
+ if (!caps->syncpr)
config->syncfreq = 0x8;
/*
@@ -209,7 +219,7 @@ static ssize_t reset_store(struct device *dev,
* each trace run.
*/
config->vinst_ctrl = FIELD_PREP(TRCVICTLR_EVENT_MASK, 0x01);
- if (drvdata->nr_addr_cmp > 0) {
+ if (caps->nr_addr_cmp > 0) {
config->mode |= ETM_MODE_VIEWINST_STARTSTOP;
/* SSSTATUS, bit[9] */
config->vinst_ctrl |= TRCVICTLR_SSSTATUS;
@@ -223,7 +233,7 @@ static ssize_t reset_store(struct device *dev,
config->vipcssctlr = 0x0;
/* Disable seq events */
- for (i = 0; i < drvdata->nrseqstate-1; i++)
+ for (i = 0; i < caps->nrseqstate - 1; i++)
config->seq_ctrl[i] = 0x0;
config->seq_rst = 0x0;
config->seq_state = 0x0;
@@ -232,38 +242,38 @@ static ssize_t reset_store(struct device *dev,
config->ext_inp = 0x0;
config->cntr_idx = 0x0;
- for (i = 0; i < drvdata->nr_cntr; i++) {
+ for (i = 0; i < caps->nr_cntr; i++) {
config->cntrldvr[i] = 0x0;
config->cntr_ctrl[i] = 0x0;
config->cntr_val[i] = 0x0;
}
config->res_idx = 0x0;
- for (i = 2; i < 2 * drvdata->nr_resource; i++)
+ for (i = 2; i < 2 * caps->nr_resource; i++)
config->res_ctrl[i] = 0x0;
config->ss_idx = 0x0;
- for (i = 0; i < drvdata->nr_ss_cmp; i++) {
+ for (i = 0; i < caps->nr_ss_cmp; i++) {
config->ss_ctrl[i] = 0x0;
config->ss_pe_cmp[i] = 0x0;
}
config->addr_idx = 0x0;
- for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
+ for (i = 0; i < caps->nr_addr_cmp * 2; i++) {
config->addr_val[i] = 0x0;
config->addr_acc[i] = 0x0;
config->addr_type[i] = ETM_ADDR_TYPE_NONE;
}
config->ctxid_idx = 0x0;
- for (i = 0; i < drvdata->numcidc; i++)
+ for (i = 0; i < caps->numcidc; i++)
config->ctxid_pid[i] = 0x0;
config->ctxid_mask0 = 0x0;
config->ctxid_mask1 = 0x0;
config->vmid_idx = 0x0;
- for (i = 0; i < drvdata->numvmidc; i++)
+ for (i = 0; i < caps->numvmidc; i++)
config->vmid_val[i] = 0x0;
config->vmid_mask0 = 0x0;
config->vmid_mask1 = 0x0;
@@ -297,6 +307,7 @@ static ssize_t mode_store(struct device *dev,
{
unsigned long val, mode;
struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ const struct etmv4_caps *caps = &drvdata->caps;
struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val))
@@ -305,7 +316,7 @@ static ssize_t mode_store(struct device *dev,
raw_spin_lock(&drvdata->spinlock);
config->mode = val & ETMv4_MODE_ALL;
- if (drvdata->instrp0 == true) {
+ if (caps->instrp0) {
/* start by clearing instruction P0 field */
config->cfg &= ~TRCCONFIGR_INSTP0_LOAD_STORE;
if (config->mode & ETM_MODE_LOAD)
@@ -323,45 +334,44 @@ static ssize_t mode_store(struct device *dev,
}
/* bit[3], Branch broadcast mode */
- if ((config->mode & ETM_MODE_BB) && (drvdata->trcbb == true))
+ if ((config->mode & ETM_MODE_BB) && (caps->trcbb))
config->cfg |= TRCCONFIGR_BB;
else
config->cfg &= ~TRCCONFIGR_BB;
/* bit[4], Cycle counting instruction trace bit */
if ((config->mode & ETMv4_MODE_CYCACC) &&
- (drvdata->trccci == true))
+ (caps->trccci == true))
config->cfg |= TRCCONFIGR_CCI;
else
config->cfg &= ~TRCCONFIGR_CCI;
/* bit[6], Context ID tracing bit */
- if ((config->mode & ETMv4_MODE_CTXID) && (drvdata->ctxid_size))
+ if ((config->mode & ETMv4_MODE_CTXID) && (caps->ctxid_size))
config->cfg |= TRCCONFIGR_CID;
else
config->cfg &= ~TRCCONFIGR_CID;
- if ((config->mode & ETM_MODE_VMID) && (drvdata->vmid_size))
+ if ((config->mode & ETM_MODE_VMID) && (caps->vmid_size))
config->cfg |= TRCCONFIGR_VMID;
else
config->cfg &= ~TRCCONFIGR_VMID;
/* bits[10:8], Conditional instruction tracing bit */
mode = ETM_MODE_COND(config->mode);
- if (drvdata->trccond == true) {
+ if (caps->trccond) {
config->cfg &= ~TRCCONFIGR_COND_MASK;
config->cfg |= mode << __bf_shf(TRCCONFIGR_COND_MASK);
}
/* bit[11], Global timestamp tracing bit */
- if ((config->mode & ETMv4_MODE_TIMESTAMP) && (drvdata->ts_size))
+ if ((config->mode & ETMv4_MODE_TIMESTAMP) && (caps->ts_size))
config->cfg |= TRCCONFIGR_TS;
else
config->cfg &= ~TRCCONFIGR_TS;
/* bit[12], Return stack enable bit */
- if ((config->mode & ETM_MODE_RETURNSTACK) &&
- (drvdata->retstack == true))
+ if ((config->mode & ETM_MODE_RETURNSTACK) && (caps->retstack))
config->cfg |= TRCCONFIGR_RS;
else
config->cfg &= ~TRCCONFIGR_RS;
@@ -375,31 +385,29 @@ static ssize_t mode_store(struct device *dev,
* Always set the low bit for any requested mode. Valid combos are
* 0b00, 0b01 and 0b11.
*/
- if (mode && drvdata->q_support)
+ if (mode && caps->q_support)
config->cfg |= TRCCONFIGR_QE_W_COUNTS;
/*
* if supported, Q elements with and without instruction
* counts are enabled
*/
- if ((mode & BIT(1)) && (drvdata->q_support & BIT(1)))
+ if ((mode & BIT(1)) && (caps->q_support & BIT(1)))
config->cfg |= TRCCONFIGR_QE_WO_COUNTS;
/* bit[11], AMBA Trace Bus (ATB) trigger enable bit */
- if ((config->mode & ETM_MODE_ATB_TRIGGER) &&
- (drvdata->atbtrig == true))
+ if ((config->mode & ETM_MODE_ATB_TRIGGER) && (caps->atbtrig))
config->eventctrl1 |= TRCEVENTCTL1R_ATB;
else
config->eventctrl1 &= ~TRCEVENTCTL1R_ATB;
/* bit[12], Low-power state behavior override bit */
- if ((config->mode & ETM_MODE_LPOVERRIDE) &&
- (drvdata->lpoverride == true))
+ if ((config->mode & ETM_MODE_LPOVERRIDE) && (caps->lpoverride))
config->eventctrl1 |= TRCEVENTCTL1R_LPOVERRIDE;
else
config->eventctrl1 &= ~TRCEVENTCTL1R_LPOVERRIDE;
/* bit[8], Instruction stall bit */
- if ((config->mode & ETM_MODE_ISTALL_EN) && (drvdata->stallctl == true))
+ if ((config->mode & ETM_MODE_ISTALL_EN) && (caps->stallctl))
config->stall_ctrl |= TRCSTALLCTLR_ISTALL;
else
config->stall_ctrl &= ~TRCSTALLCTLR_ISTALL;
@@ -411,8 +419,7 @@ static ssize_t mode_store(struct device *dev,
config->stall_ctrl &= ~TRCSTALLCTLR_INSTPRIORITY;
/* bit[13], Trace overflow prevention bit */
- if ((config->mode & ETM_MODE_NOOVERFLOW) &&
- (drvdata->nooverflow == true))
+ if ((config->mode & ETM_MODE_NOOVERFLOW) && (caps->nooverflow))
config->stall_ctrl |= TRCSTALLCTLR_NOOVERFLOW;
else
config->stall_ctrl &= ~TRCSTALLCTLR_NOOVERFLOW;
@@ -430,8 +437,7 @@ static ssize_t mode_store(struct device *dev,
config->vinst_ctrl &= ~TRCVICTLR_TRCRESET;
/* bit[11], Whether a trace unit must trace a system error exception */
- if ((config->mode & ETM_MODE_TRACE_ERR) &&
- (drvdata->trc_error == true))
+ if ((config->mode & ETM_MODE_TRACE_ERR) && (caps->trc_error))
config->vinst_ctrl |= TRCVICTLR_TRCERR;
else
config->vinst_ctrl &= ~TRCVICTLR_TRCERR;
@@ -463,13 +469,14 @@ static ssize_t pe_store(struct device *dev,
{
unsigned long val;
struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ const struct etmv4_caps *caps = &drvdata->caps;
struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val))
return -EINVAL;
raw_spin_lock(&drvdata->spinlock);
- if (val > drvdata->nr_pe) {
+ if (val > caps->nr_pe) {
raw_spin_unlock(&drvdata->spinlock);
return -EINVAL;
}
@@ -498,13 +505,14 @@ static ssize_t event_store(struct device *dev,
{
unsigned long val;
struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ const struct etmv4_caps *caps = &drvdata->caps;
struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val))
return -EINVAL;
raw_spin_lock(&drvdata->spinlock);
- switch (drvdata->nr_event) {
+ switch (caps->nr_event) {
case 0x0:
/* EVENT0, bits[7:0] */
config->eventctrl0 = val & 0xFF;
@@ -547,6 +555,7 @@ static ssize_t event_instren_store(struct device *dev,
{
unsigned long val;
struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ const struct etmv4_caps *caps = &drvdata->caps;
struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val))
@@ -555,7 +564,7 @@ static ssize_t event_instren_store(struct device *dev,
raw_spin_lock(&drvdata->spinlock);
/* start by clearing all instruction event enable bits */
config->eventctrl1 &= ~TRCEVENTCTL1R_INSTEN_MASK;
- switch (drvdata->nr_event) {
+ switch (caps->nr_event) {
case 0x0:
/* generate Event element for event 1 */
config->eventctrl1 |= val & TRCEVENTCTL1R_INSTEN_1;
@@ -603,11 +612,12 @@ static ssize_t event_ts_store(struct device *dev,
{
unsigned long val;
struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ const struct etmv4_caps *caps = &drvdata->caps;
struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val))
return -EINVAL;
- if (!drvdata->ts_size)
+ if (!caps->ts_size)
return -EINVAL;
config->ts_ctrl = val & ETMv4_EVENT_MASK;
@@ -633,11 +643,12 @@ static ssize_t syncfreq_store(struct device *dev,
{
unsigned long val;
struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ const struct etmv4_caps *caps = &drvdata->caps;
struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val))
return -EINVAL;
- if (drvdata->syncpr == true)
+ if (caps->syncpr)
return -EINVAL;
config->syncfreq = val & ETMv4_SYNC_MASK;
@@ -663,6 +674,7 @@ static ssize_t cyc_threshold_store(struct device *dev,
{
unsigned long val;
struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ const struct etmv4_caps *caps = &drvdata->caps;
struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val))
@@ -670,7 +682,7 @@ static ssize_t cyc_threshold_store(struct device *dev,
/* mask off max threshold before checking min value */
val &= ETM_CYC_THRESHOLD_MASK;
- if (val < drvdata->ccitmin)
+ if (val < caps->ccitmin)
return -EINVAL;
config->ccctlr = val;
@@ -696,13 +708,14 @@ static ssize_t bb_ctrl_store(struct device *dev,
{
unsigned long val;
struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ const struct etmv4_caps *caps = &drvdata->caps;
struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val))
return -EINVAL;
- if (drvdata->trcbb == false)
+ if (!caps->trcbb)
return -EINVAL;
- if (!drvdata->nr_addr_cmp)
+ if (!caps->nr_addr_cmp)
return -EINVAL;
/*
@@ -768,6 +781,7 @@ static ssize_t s_exlevel_vinst_store(struct device *dev,
{
unsigned long val;
struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ const struct etmv4_caps *caps = &drvdata->caps;
struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val))
@@ -777,7 +791,7 @@ static ssize_t s_exlevel_vinst_store(struct device *dev,
/* clear all EXLEVEL_S bits */
config->vinst_ctrl &= ~TRCVICTLR_EXLEVEL_S_MASK;
/* enable instruction tracing for corresponding exception level */
- val &= drvdata->s_ex_level;
+ val &= caps->s_ex_level;
config->vinst_ctrl |= val << __bf_shf(TRCVICTLR_EXLEVEL_S_MASK);
raw_spin_unlock(&drvdata->spinlock);
return size;
@@ -803,6 +817,7 @@ static ssize_t ns_exlevel_vinst_store(struct device *dev,
{
unsigned long val;
struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ const struct etmv4_caps *caps = &drvdata->caps;
struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val))
@@ -812,7 +827,7 @@ static ssize_t ns_exlevel_vinst_store(struct device *dev,
/* clear EXLEVEL_NS bits */
config->vinst_ctrl &= ~TRCVICTLR_EXLEVEL_NS_MASK;
/* enable instruction tracing for corresponding exception level */
- val &= drvdata->ns_ex_level;
+ val &= caps->ns_ex_level;
config->vinst_ctrl |= val << __bf_shf(TRCVICTLR_EXLEVEL_NS_MASK);
raw_spin_unlock(&drvdata->spinlock);
return size;
@@ -837,11 +852,12 @@ static ssize_t addr_idx_store(struct device *dev,
{
unsigned long val;
struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ const struct etmv4_caps *caps = &drvdata->caps;
struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val))
return -EINVAL;
- if (val >= drvdata->nr_addr_cmp * 2)
+ if (val >= caps->nr_addr_cmp * 2)
return -EINVAL;
/*
@@ -1060,6 +1076,7 @@ static ssize_t addr_start_store(struct device *dev,
u8 idx;
unsigned long val;
struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ const struct etmv4_caps *caps = &drvdata->caps;
struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val))
@@ -1067,7 +1084,7 @@ static ssize_t addr_start_store(struct device *dev,
raw_spin_lock(&drvdata->spinlock);
idx = config->addr_idx;
- if (!drvdata->nr_addr_cmp) {
+ if (!caps->nr_addr_cmp) {
raw_spin_unlock(&drvdata->spinlock);
return -EINVAL;
}
@@ -1115,6 +1132,7 @@ static ssize_t addr_stop_store(struct device *dev,
u8 idx;
unsigned long val;
struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ const struct etmv4_caps *caps = &drvdata->caps;
struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val))
@@ -1122,7 +1140,7 @@ static ssize_t addr_stop_store(struct device *dev,
raw_spin_lock(&drvdata->spinlock);
idx = config->addr_idx;
- if (!drvdata->nr_addr_cmp) {
+ if (!caps->nr_addr_cmp) {
raw_spin_unlock(&drvdata->spinlock);
return -EINVAL;
}
@@ -1167,6 +1185,7 @@ static ssize_t addr_ctxtype_store(struct device *dev,
u8 idx;
char str[10] = "";
struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ const struct etmv4_caps *caps = &drvdata->caps;
struct etmv4_config *config = &drvdata->config;
if (strlen(buf) >= 10)
@@ -1181,13 +1200,13 @@ static ssize_t addr_ctxtype_store(struct device *dev,
config->addr_acc[idx] &= ~TRCACATRn_CONTEXTTYPE_MASK;
else if (!strcmp(str, "ctxid")) {
/* 0b01 The trace unit performs a Context ID */
- if (drvdata->numcidc) {
+ if (caps->numcidc) {
config->addr_acc[idx] |= TRCACATRn_CONTEXTTYPE_CTXID;
config->addr_acc[idx] &= ~TRCACATRn_CONTEXTTYPE_VMID;
}
} else if (!strcmp(str, "vmid")) {
/* 0b10 The trace unit performs a VMID */
- if (drvdata->numvmidc) {
+ if (caps->numvmidc) {
config->addr_acc[idx] &= ~TRCACATRn_CONTEXTTYPE_CTXID;
config->addr_acc[idx] |= TRCACATRn_CONTEXTTYPE_VMID;
}
@@ -1196,9 +1215,9 @@ static ssize_t addr_ctxtype_store(struct device *dev,
* 0b11 The trace unit performs a Context ID
* comparison and a VMID
*/
- if (drvdata->numcidc)
+ if (caps->numcidc)
config->addr_acc[idx] |= TRCACATRn_CONTEXTTYPE_CTXID;
- if (drvdata->numvmidc)
+ if (caps->numvmidc)
config->addr_acc[idx] |= TRCACATRn_CONTEXTTYPE_VMID;
}
raw_spin_unlock(&drvdata->spinlock);
@@ -1230,14 +1249,15 @@ static ssize_t addr_context_store(struct device *dev,
u8 idx;
unsigned long val;
struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ const struct etmv4_caps *caps = &drvdata->caps;
struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val))
return -EINVAL;
- if ((drvdata->numcidc <= 1) && (drvdata->numvmidc <= 1))
+ if ((caps->numcidc <= 1) && (caps->numvmidc <= 1))
return -EINVAL;
- if (val >= (drvdata->numcidc >= drvdata->numvmidc ?
- drvdata->numcidc : drvdata->numvmidc))
+ if (val >= (caps->numcidc >= caps->numvmidc ?
+ caps->numcidc : caps->numvmidc))
return -EINVAL;
raw_spin_lock(&drvdata->spinlock);
@@ -1348,9 +1368,10 @@ static ssize_t vinst_pe_cmp_start_stop_show(struct device *dev,
{
unsigned long val;
struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ const struct etmv4_caps *caps = &drvdata->caps;
struct etmv4_config *config = &drvdata->config;
- if (!drvdata->nr_pe_cmp)
+ if (!caps->nr_pe_cmp)
return -EINVAL;
val = config->vipcssctlr;
return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
@@ -1361,11 +1382,12 @@ static ssize_t vinst_pe_cmp_start_stop_store(struct device *dev,
{
unsigned long val;
struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ const struct etmv4_caps *caps = &drvdata->caps;
struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val))
return -EINVAL;
- if (!drvdata->nr_pe_cmp)
+ if (!caps->nr_pe_cmp)
return -EINVAL;
raw_spin_lock(&drvdata->spinlock);
@@ -1393,13 +1415,14 @@ static ssize_t seq_idx_store(struct device *dev,
{
unsigned long val;
struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ const struct etmv4_caps *caps = &drvdata->caps;
struct etmv4_config *config = &drvdata->config;
- if (!drvdata->nrseqstate)
+ if (!caps->nrseqstate)
return -ENOTSUPP;
if (kstrtoul(buf, 16, &val))
return -EINVAL;
- if (val >= drvdata->nrseqstate - 1)
+ if (val >= caps->nrseqstate - 1)
return -EINVAL;
/*
@@ -1431,11 +1454,12 @@ static ssize_t seq_state_store(struct device *dev,
{
unsigned long val;
struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ const struct etmv4_caps *caps = &drvdata->caps;
struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val))
return -EINVAL;
- if (val >= drvdata->nrseqstate)
+ if (val >= caps->nrseqstate)
return -EINVAL;
config->seq_state = val;
@@ -1498,11 +1522,12 @@ static ssize_t seq_reset_event_store(struct device *dev,
{
unsigned long val;
struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ const struct etmv4_caps *caps = &drvdata->caps;
struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val))
return -EINVAL;
- if (!(drvdata->nrseqstate))
+ if (!(caps->nrseqstate))
return -EINVAL;
config->seq_rst = val & ETMv4_EVENT_MASK;
@@ -1528,11 +1553,12 @@ static ssize_t cntr_idx_store(struct device *dev,
{
unsigned long val;
struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ const struct etmv4_caps *caps = &drvdata->caps;
struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val))
return -EINVAL;
- if (val >= drvdata->nr_cntr)
+ if (val >= caps->nr_cntr)
return -EINVAL;
/*
@@ -1676,6 +1702,7 @@ static ssize_t res_idx_store(struct device *dev,
{
unsigned long val;
struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ const struct etmv4_caps *caps = &drvdata->caps;
struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val))
@@ -1684,7 +1711,7 @@ static ssize_t res_idx_store(struct device *dev,
* Resource selector pair 0 is always implemented and reserved,
* namely an idx with 0 and 1 is illegal.
*/
- if ((val < 2) || (val >= 2 * drvdata->nr_resource))
+ if ((val < 2) || (val >= 2 * caps->nr_resource))
return -EINVAL;
/*
@@ -1758,11 +1785,12 @@ static ssize_t sshot_idx_store(struct device *dev,
{
unsigned long val;
struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ const struct etmv4_caps *caps = &drvdata->caps;
struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val))
return -EINVAL;
- if (val >= drvdata->nr_ss_cmp)
+ if (val >= caps->nr_ss_cmp)
return -EINVAL;
raw_spin_lock(&drvdata->spinlock);
@@ -1876,11 +1904,12 @@ static ssize_t ctxid_idx_store(struct device *dev,
{
unsigned long val;
struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ const struct etmv4_caps *caps = &drvdata->caps;
struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val))
return -EINVAL;
- if (val >= drvdata->numcidc)
+ if (val >= caps->numcidc)
return -EINVAL;
/*
@@ -1924,6 +1953,7 @@ static ssize_t ctxid_pid_store(struct device *dev,
u8 idx;
unsigned long pid;
struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ const struct etmv4_caps *caps = &drvdata->caps;
struct etmv4_config *config = &drvdata->config;
/*
@@ -1943,7 +1973,7 @@ static ssize_t ctxid_pid_store(struct device *dev,
* ctxid comparator is implemented and ctxid is greater than 0 bits
* in length
*/
- if (!drvdata->ctxid_size || !drvdata->numcidc)
+ if (!caps->ctxid_size || !caps->numcidc)
return -EINVAL;
if (kstrtoul(buf, 16, &pid))
return -EINVAL;
@@ -1985,6 +2015,7 @@ static ssize_t ctxid_masks_store(struct device *dev,
u8 i, j, maskbyte;
unsigned long val1, val2, mask;
struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ const struct etmv4_caps *caps = &drvdata->caps;
struct etmv4_config *config = &drvdata->config;
int nr_inputs;
@@ -2000,11 +2031,11 @@ static ssize_t ctxid_masks_store(struct device *dev,
* ctxid comparator is implemented and ctxid is greater than 0 bits
* in length
*/
- if (!drvdata->ctxid_size || !drvdata->numcidc)
+ if (!caps->ctxid_size || !caps->numcidc)
return -EINVAL;
/* one mask if <= 4 comparators, two for up to 8 */
nr_inputs = sscanf(buf, "%lx %lx", &val1, &val2);
- if ((drvdata->numcidc > 4) && (nr_inputs != 2))
+ if ((caps->numcidc > 4) && (nr_inputs != 2))
return -EINVAL;
raw_spin_lock(&drvdata->spinlock);
@@ -2012,7 +2043,7 @@ static ssize_t ctxid_masks_store(struct device *dev,
* each byte[0..3] controls mask value applied to ctxid
* comparator[0..3]
*/
- switch (drvdata->numcidc) {
+ switch (caps->numcidc) {
case 0x1:
/* COMP0, bits[7:0] */
config->ctxid_mask0 = val1 & 0xFF;
@@ -2059,7 +2090,7 @@ static ssize_t ctxid_masks_store(struct device *dev,
* of ctxid comparator0 value (corresponding to byte 0) register.
*/
mask = config->ctxid_mask0;
- for (i = 0; i < drvdata->numcidc; i++) {
+ for (i = 0; i < caps->numcidc; i++) {
/* mask value of corresponding ctxid comparator */
maskbyte = mask & ETMv4_EVENT_MASK;
/*
@@ -2102,11 +2133,12 @@ static ssize_t vmid_idx_store(struct device *dev,
{
unsigned long val;
struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ const struct etmv4_caps *caps = &drvdata->caps;
struct etmv4_config *config = &drvdata->config;
if (kstrtoul(buf, 16, &val))
return -EINVAL;
- if (val >= drvdata->numvmidc)
+ if (val >= caps->numvmidc)
return -EINVAL;
/*
@@ -2147,6 +2179,7 @@ static ssize_t vmid_val_store(struct device *dev,
{
unsigned long val;
struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ const struct etmv4_caps *caps = &drvdata->caps;
struct etmv4_config *config = &drvdata->config;
/*
@@ -2160,7 +2193,7 @@ static ssize_t vmid_val_store(struct device *dev,
* only implemented when vmid tracing is enabled, i.e. at least one
* vmid comparator is implemented and at least 8 bit vmid size
*/
- if (!drvdata->vmid_size || !drvdata->numvmidc)
+ if (!caps->vmid_size || !caps->numvmidc)
return -EINVAL;
if (kstrtoul(buf, 16, &val))
return -EINVAL;
@@ -2200,6 +2233,7 @@ static ssize_t vmid_masks_store(struct device *dev,
u8 i, j, maskbyte;
unsigned long val1, val2, mask;
struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ const struct etmv4_caps *caps = &drvdata->caps;
struct etmv4_config *config = &drvdata->config;
int nr_inputs;
@@ -2214,11 +2248,11 @@ static ssize_t vmid_masks_store(struct device *dev,
* only implemented when vmid tracing is enabled, i.e. at least one
* vmid comparator is implemented and at least 8 bit vmid size
*/
- if (!drvdata->vmid_size || !drvdata->numvmidc)
+ if (!caps->vmid_size || !caps->numvmidc)
return -EINVAL;
/* one mask if <= 4 comparators, two for up to 8 */
nr_inputs = sscanf(buf, "%lx %lx", &val1, &val2);
- if ((drvdata->numvmidc > 4) && (nr_inputs != 2))
+ if ((caps->numvmidc > 4) && (nr_inputs != 2))
return -EINVAL;
raw_spin_lock(&drvdata->spinlock);
@@ -2227,7 +2261,7 @@ static ssize_t vmid_masks_store(struct device *dev,
* each byte[0..3] controls mask value applied to vmid
* comparator[0..3]
*/
- switch (drvdata->numvmidc) {
+ switch (caps->numvmidc) {
case 0x1:
/* COMP0, bits[7:0] */
config->vmid_mask0 = val1 & 0xFF;
@@ -2275,7 +2309,7 @@ static ssize_t vmid_masks_store(struct device *dev,
* of vmid comparator0 value (corresponding to byte 0) register.
*/
mask = config->vmid_mask0;
- for (i = 0; i < drvdata->numvmidc; i++) {
+ for (i = 0; i < caps->numvmidc; i++) {
/* mask value of corresponding vmid comparator */
maskbyte = mask & ETMv4_EVENT_MASK;
/*
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
index 60e08ab085c5..6d4fbae78448 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.h
+++ b/drivers/hwtracing/coresight/coresight-etm4x.h
@@ -813,6 +813,95 @@ enum etm_impdef_type {
ETM4_IMPDEF_FEATURE_MAX,
};
+/**
+ * struct etmv4_caps - specifics ETM capabilities
+ * @nr_pe: The number of processing entity available for tracing.
+ * @nr_pe_cmp: The number of processing entity comparator inputs that are
+ * available for tracing.
+ * @nr_addr_cmp:Number of pairs of address comparators available
+ * as found in ETMIDR4 0-3.
+ * @nr_cntr: Number of counters as found in ETMIDR5 bit 28-30.
+ * @nr_ext_inp: Number of external input.
+ * @numcidc: Number of contextID comparators.
+ * @numextinsel: Number of external input selector resources.
+ * @numvmidc: Number of VMID comparators.
+ * @nrseqstate: The number of sequencer states that are implemented.
+ * @nr_event: Indicates how many events the trace unit support.
+ * @nr_resource:The number of resource selection pairs available for tracing.
+ * @nr_ss_cmp: Number of single-shot comparator controls that are available.
+ * @trcid_size: Indicates the trace ID width.
+ * @ts_size: Global timestamp size field.
+ * @ctxid_size: Size of the context ID field to consider.
+ * @vmid_size: Size of the VM ID comparator to consider.
+ * @ccsize: Indicates the size of the cycle counter in bits.
+ * @ccitmin: minimum value that can be programmed in
+ * @s_ex_level: In secure state, indicates whether instruction tracing is
+ * supported for the corresponding Exception level.
+ * @ns_ex_level:In non-secure state, indicates whether instruction tracing is
+ * supported for the corresponding Exception level.
+ * @q_support: Q element support characteristics.
+ * @os_lock_model: OSLock model.
+ * @instrp0: Tracing of load and store instructions
+ * as P0 elements is supported.
+ * @q_filt: Q element filtering support, if Q elements are supported.
+ * @trcbb: Indicates if the trace unit supports branch broadcast tracing.
+ * @trccond: If the trace unit supports conditional
+ * instruction tracing.
+ * @retstack: Indicates if the implementation supports a return stack.
+ * @trccci: Indicates if the trace unit supports cycle counting
+ * for instruction.
+ * @trc_error: Whether a trace unit can trace a system
+ * error exception.
+ * @syncpr: Indicates if an implementation has a fixed
+ * synchronization period.
+ * @stallctl: If functionality that prevents trace unit buffer overflows
+ * is available.
+ * @sysstall: Does the system support stall control of the PE?
+ * @nooverflow: Indicate if overflow prevention is supported.
+ * @atbtrig: If the implementation can support ATB triggers
+ * @lpoverride: If the implementation can support low-power state over.
+ * @skip_power_up: Indicates if an implementation can skip powering up
+ * the trace unit.
+ */
+struct etmv4_caps {
+ u8 nr_pe;
+ u8 nr_pe_cmp;
+ u8 nr_addr_cmp;
+ u8 nr_cntr;
+ u8 nr_ext_inp;
+ u8 numcidc;
+ u8 numextinsel;
+ u8 numvmidc;
+ u8 nrseqstate;
+ u8 nr_event;
+ u8 nr_resource;
+ u8 nr_ss_cmp;
+ u8 trcid_size;
+ u8 ts_size;
+ u8 ctxid_size;
+ u8 vmid_size;
+ u8 ccsize;
+ u16 ccitmin;
+ u8 s_ex_level;
+ u8 ns_ex_level;
+ u8 q_support;
+ u8 os_lock_model;
+ bool instrp0 : 1;
+ bool q_filt : 1;
+ bool trcbb : 1;
+ bool trccond : 1;
+ bool retstack : 1;
+ bool trccci : 1;
+ bool trc_error : 1;
+ bool syncpr : 1;
+ bool stallctl : 1;
+ bool sysstall : 1;
+ bool nooverflow : 1;
+ bool atbtrig : 1;
+ bool lpoverride : 1;
+ bool skip_power_up : 1;
+};
+
/**
* struct etmv4_config - configuration information related to an ETMv4
* @mode: Controls various modes supported by this ETM.
@@ -820,8 +909,8 @@ enum etm_impdef_type {
* @cfg: Controls the tracing options.
* @eventctrl0: Controls the tracing of arbitrary events.
* @eventctrl1: Controls the behavior of the events that @event_ctrl0 selects.
- * @stallctl: If functionality that prevents trace unit buffer overflows
- * is available.
+ * @stall_ctrl: Enables trace unit functionality that prevents trace
+ * unit buffer overflows.
* @ts_ctrl: Controls the insertion of global timestamps in the
* trace streams.
* @syncfreq: Controls how often trace synchronization requests occur.
@@ -972,61 +1061,17 @@ struct etmv4_save_state {
* @mode: This tracer's mode, i.e sysFS, Perf or disabled.
* @cpu: The cpu this component is affined to.
* @arch: ETM architecture version.
- * @nr_pe: The number of processing entity available for tracing.
- * @nr_pe_cmp: The number of processing entity comparator inputs that are
- * available for tracing.
- * @nr_addr_cmp:Number of pairs of address comparators available
- * as found in ETMIDR4 0-3.
- * @nr_cntr: Number of counters as found in ETMIDR5 bit 28-30.
- * @nr_ext_inp: Number of external input.
- * @numcidc: Number of contextID comparators.
- * @numvmidc: Number of VMID comparators.
- * @nrseqstate: The number of sequencer states that are implemented.
- * @nr_event: Indicates how many events the trace unit support.
- * @nr_resource:The number of resource selection pairs available for tracing.
- * @nr_ss_cmp: Number of single-shot comparator controls that are available.
+ * @caps: ETM capabilities.
* @trcid: value of the current ID for this component.
- * @trcid_size: Indicates the trace ID width.
- * @ts_size: Global timestamp size field.
- * @ctxid_size: Size of the context ID field to consider.
- * @vmid_size: Size of the VM ID comparator to consider.
- * @ccsize: Indicates the size of the cycle counter in bits.
- * @ccitmin: minimum value that can be programmed in
- * @s_ex_level: In secure state, indicates whether instruction tracing is
- * supported for the corresponding Exception level.
- * @ns_ex_level:In non-secure state, indicates whether instruction tracing is
- * supported for the corresponding Exception level.
* @sticky_enable: true if ETM base configuration has been done.
* @boot_enable:True if we should start tracing at boot time.
* @os_unlock: True if access to management registers is allowed.
- * @instrp0: Tracing of load and store instructions
- * as P0 elements is supported.
- * @q_filt: Q element filtering support, if Q elements are supported.
- * @trcbb: Indicates if the trace unit supports branch broadcast tracing.
- * @trccond: If the trace unit supports conditional
- * instruction tracing.
- * @retstack: Indicates if the implementation supports a return stack.
- * @trccci: Indicates if the trace unit supports cycle counting
- * for instruction.
- * @q_support: Q element support characteristics.
- * @trc_error: Whether a trace unit can trace a system
- * error exception.
- * @syncpr: Indicates if an implementation has a fixed
- * synchronization period.
- * @stall_ctrl: Enables trace unit functionality that prevents trace
- * unit buffer overflows.
- * @sysstall: Does the system support stall control of the PE?
- * @nooverflow: Indicate if overflow prevention is supported.
- * @atbtrig: If the implementation can support ATB triggers
- * @lpoverride: If the implementation can support low-power state over.
* @trfcr: If the CPU supports FEAT_TRF, value of the TRFCR_ELx that
* allows tracing at all ELs. We don't want to compute this
* at runtime, due to the additional setting of TRFCR_CX when
* in EL2. Otherwise, 0.
* @config: structure holding configuration parameters.
* @save_state: State to be preserved across power loss
- * @skip_power_up: Indicates if an implementation can skip powering up
- * the trace unit.
* @paused: Indicates if the trace unit is paused.
* @arch_features: Bitmap of arch features of etmv4 devices.
*/
@@ -1038,46 +1083,11 @@ struct etmv4_drvdata {
raw_spinlock_t spinlock;
int cpu;
u8 arch;
- u8 nr_pe;
- u8 nr_pe_cmp;
- u8 nr_addr_cmp;
- u8 nr_cntr;
- u8 nr_ext_inp;
- u8 numcidc;
- u8 numextinsel;
- u8 numvmidc;
- u8 nrseqstate;
- u8 nr_event;
- u8 nr_resource;
- u8 nr_ss_cmp;
+ struct etmv4_caps caps;
u8 trcid;
- u8 trcid_size;
- u8 ts_size;
- u8 ctxid_size;
- u8 vmid_size;
- u8 ccsize;
- u16 ccitmin;
- u8 s_ex_level;
- u8 ns_ex_level;
- u8 q_support;
- u8 os_lock_model;
bool sticky_enable : 1;
bool boot_enable : 1;
bool os_unlock : 1;
- bool instrp0 : 1;
- bool q_filt : 1;
- bool trcbb : 1;
- bool trccond : 1;
- bool retstack : 1;
- bool trccci : 1;
- bool trc_error : 1;
- bool syncpr : 1;
- bool stallctl : 1;
- bool sysstall : 1;
- bool nooverflow : 1;
- bool atbtrig : 1;
- bool lpoverride : 1;
- bool skip_power_up : 1;
bool paused : 1;
u64 trfcr;
struct etmv4_config config;
--
LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7}
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PATCH v7 05/13] coresight: etm4x: exclude ss_status from drvdata->config
2026-05-19 15:47 [PATCH v7 00/13] fix several inconsistencies with sysfs configuration in etmX Yeoreum Yun
` (3 preceding siblings ...)
2026-05-19 15:48 ` [PATCH v7 04/13] coresight: etm4x: introduce struct etm4_caps Yeoreum Yun
@ 2026-05-19 15:48 ` Yeoreum Yun
2026-05-28 13:30 ` Leo Yan
2026-06-01 11:27 ` Suzuki K Poulose
2026-05-19 15:48 ` [PATCH v7 06/13] coresight: etm4x: remove redundant fields in etmv4_save_state Yeoreum Yun
` (7 subsequent siblings)
12 siblings, 2 replies; 39+ messages in thread
From: Yeoreum Yun @ 2026-05-19 15:48 UTC (permalink / raw)
To: coresight, linux-arm-kernel, linux-kernel
Cc: suzuki.poulose, mike.leach, james.clark, alexander.shishkin,
leo.yan, jie.gan, Yeoreum Yun
The purpose of TRCSSCSRn register is to show status of
the corresponding Single-shot Comparator Control and input supports.
That means writable field's purpose for reset or restore from idle status
not for configuration.
Therefore, exclude ss_status from drvdata->config and move it to drvdata.
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
---
.../hwtracing/coresight/coresight-etm4x-cfg.c | 1 -
.../hwtracing/coresight/coresight-etm4x-core.c | 16 +++++++++-------
.../hwtracing/coresight/coresight-etm4x-sysfs.c | 10 +++++-----
drivers/hwtracing/coresight/coresight-etm4x.h | 7 ++++++-
4 files changed, 20 insertions(+), 14 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
index e1a59b434505..9b4947d75fde 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
@@ -86,7 +86,6 @@ static int etm4_cfg_map_reg_offset(struct etmv4_drvdata *drvdata,
off_mask = (offset & GENMASK(11, 5));
do {
CHECKREGIDX(TRCSSCCRn(0), ss_ctrl, idx, off_mask);
- CHECKREGIDX(TRCSSCSRn(0), ss_status, idx, off_mask);
CHECKREGIDX(TRCSSPCICRn(0), ss_pe_cmp, idx, off_mask);
} while (0);
} else if ((offset >= TRCCIDCVRn(0)) && (offset <= TRCVMIDCVRn(7))) {
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index 53fbc4826628..7783c97b53e8 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -95,7 +95,7 @@ static bool etm4x_sspcicrn_present(struct etmv4_drvdata *drvdata, int n)
const struct etmv4_caps *caps = &drvdata->caps;
return (n < caps->nr_ss_cmp) && caps->nr_pe_cmp &&
- (drvdata->config.ss_status[n] & TRCSSCSRn_PC);
+ (drvdata->ss_status[n] & TRCSSCSRn_PC);
}
u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
@@ -571,11 +571,11 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
etm4x_relaxed_write32(csa, config->res_ctrl[i], TRCRSCTLRn(i));
for (i = 0; i < caps->nr_ss_cmp; i++) {
- /* always clear status bit on restart if using single-shot */
+ /* always clear status and pending bits on restart if using single-shot */
if (config->ss_ctrl[i] || config->ss_pe_cmp[i])
- config->ss_status[i] &= ~TRCSSCSRn_STATUS;
+ drvdata->ss_status[i] &= ~(TRCSSCSRn_STATUS | TRCSSCSRn_PENDING);
etm4x_relaxed_write32(csa, config->ss_ctrl[i], TRCSSCCRn(i));
- etm4x_relaxed_write32(csa, config->ss_status[i], TRCSSCSRn(i));
+ etm4x_relaxed_write32(csa, drvdata->ss_status[i], TRCSSCSRn(i));
if (etm4x_sspcicrn_present(drvdata, i))
etm4x_relaxed_write32(csa, config->ss_pe_cmp[i], TRCSSPCICRn(i));
}
@@ -772,6 +772,7 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
/* Clear configuration from previous run */
memset(config, 0, sizeof(struct etmv4_config));
+
if (attr->exclude_kernel)
config->mode = ETM_MODE_EXCL_KERN;
@@ -1064,7 +1065,7 @@ static void etm4_disable_hw(struct etmv4_drvdata *drvdata)
/* read the status of the single shot comparators */
for (i = 0; i < caps->nr_ss_cmp; i++) {
- config->ss_status[i] =
+ drvdata->ss_status[i] =
etm4x_relaxed_read32(csa, TRCSSCSRn(i));
}
@@ -1497,8 +1498,9 @@ static void etm4_init_arch_data(void *info)
*/
caps->nr_ss_cmp = FIELD_GET(TRCIDR4_NUMSSCC_MASK, etmidr4);
for (i = 0; i < caps->nr_ss_cmp; i++) {
- drvdata->config.ss_status[i] =
- etm4x_relaxed_read32(csa, TRCSSCSRn(i));
+ drvdata->ss_status[i] = etm4x_relaxed_read32(csa, TRCSSCSRn(i));
+ drvdata->ss_status[i] &= (TRCSSCSRn_PC | TRCSSCSRn_DV |
+ TRCSSCSRn_DA | TRCSSCSRn_INST);
}
/* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */
caps->numcidc = FIELD_GET(TRCIDR4_NUMCIDC_MASK, etmidr4);
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
index 7de3c58a47b4..71e95d152ee6 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
@@ -1829,8 +1829,8 @@ static ssize_t sshot_ctrl_store(struct device *dev,
raw_spin_lock(&drvdata->spinlock);
idx = config->ss_idx;
config->ss_ctrl[idx] = FIELD_PREP(TRCSSCCRn_SAC_ARC_RST_MASK, val);
- /* must clear bit 31 in related status register on programming */
- config->ss_status[idx] &= ~TRCSSCSRn_STATUS;
+ /* must clear bit 31 and 30 in related status register on programming */
+ drvdata->ss_status[idx] &= ~(TRCSSCSRn_STATUS | TRCSSCSRn_PENDING);
raw_spin_unlock(&drvdata->spinlock);
return size;
}
@@ -1844,7 +1844,7 @@ static ssize_t sshot_status_show(struct device *dev,
struct etmv4_config *config = &drvdata->config;
raw_spin_lock(&drvdata->spinlock);
- val = config->ss_status[config->ss_idx];
+ val = drvdata->ss_status[config->ss_idx];
raw_spin_unlock(&drvdata->spinlock);
return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
}
@@ -1879,8 +1879,8 @@ static ssize_t sshot_pe_ctrl_store(struct device *dev,
raw_spin_lock(&drvdata->spinlock);
idx = config->ss_idx;
config->ss_pe_cmp[idx] = FIELD_PREP(TRCSSPCICRn_PC_MASK, val);
- /* must clear bit 31 in related status register on programming */
- config->ss_status[idx] &= ~TRCSSCSRn_STATUS;
+ /* must clear bit 31 and 30 in related status register on programming */
+ drvdata->ss_status[idx] &= ~(TRCSSCSRn_STATUS | TRCSSCSRn_PENDING);
raw_spin_unlock(&drvdata->spinlock);
return size;
}
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
index 6d4fbae78448..43db1eb6f8cd 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.h
+++ b/drivers/hwtracing/coresight/coresight-etm4x.h
@@ -213,6 +213,7 @@
#define TRCACATRn_EXLEVEL_MASK GENMASK(14, 8)
#define TRCSSCSRn_STATUS BIT(31)
+#define TRCSSCSRn_PENDING BIT(30)
#define TRCSSCCRn_SAC_ARC_RST_MASK GENMASK(24, 0)
#define TRCSSPCICRn_PC_MASK GENMASK(7, 0)
@@ -730,6 +731,9 @@ static inline u32 etm4_res_sel_pair(u8 res_sel_idx)
#define ETM_DEFAULT_ADDR_COMP 0
#define TRCSSCSRn_PC BIT(3)
+#define TRCSSCSRn_DV BIT(2)
+#define TRCSSCSRn_DA BIT(1)
+#define TRCSSCSRn_INST BIT(0)
/* PowerDown Control Register bits */
#define TRCPDCR_PU BIT(3)
@@ -978,7 +982,6 @@ struct etmv4_config {
u32 res_ctrl[ETM_MAX_RES_SEL]; /* TRCRSCTLRn */
u8 ss_idx;
u32 ss_ctrl[ETM_MAX_SS_CMP];
- u32 ss_status[ETM_MAX_SS_CMP];
u32 ss_pe_cmp[ETM_MAX_SS_CMP];
u8 addr_idx;
u64 addr_val[ETM_MAX_SINGLE_ADDR_CMP];
@@ -1073,6 +1076,7 @@ struct etmv4_save_state {
* @config: structure holding configuration parameters.
* @save_state: State to be preserved across power loss
* @paused: Indicates if the trace unit is paused.
+ * @ss_status: The status of the corresponding single-shot comparator.
* @arch_features: Bitmap of arch features of etmv4 devices.
*/
struct etmv4_drvdata {
@@ -1092,6 +1096,7 @@ struct etmv4_drvdata {
u64 trfcr;
struct etmv4_config config;
struct etmv4_save_state *save_state;
+ u32 ss_status[ETM_MAX_SS_CMP];
DECLARE_BITMAP(arch_features, ETM4_IMPDEF_FEATURE_MAX);
};
--
LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7}
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [PATCH v7 05/13] coresight: etm4x: exclude ss_status from drvdata->config
2026-05-19 15:48 ` [PATCH v7 05/13] coresight: etm4x: exclude ss_status from drvdata->config Yeoreum Yun
@ 2026-05-28 13:30 ` Leo Yan
2026-05-28 13:46 ` Yeoreum Yun
2026-06-01 11:27 ` Suzuki K Poulose
1 sibling, 1 reply; 39+ messages in thread
From: Leo Yan @ 2026-05-28 13:30 UTC (permalink / raw)
To: Yeoreum Yun
Cc: coresight, linux-arm-kernel, linux-kernel, suzuki.poulose,
mike.leach, james.clark, alexander.shishkin, jie.gan
On Tue, May 19, 2026 at 04:48:04PM +0100, Yeoreum Yun wrote:
[...]
> @@ -571,11 +571,11 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
> etm4x_relaxed_write32(csa, config->res_ctrl[i], TRCRSCTLRn(i));
>
> for (i = 0; i < caps->nr_ss_cmp; i++) {
> - /* always clear status bit on restart if using single-shot */
> + /* always clear status and pending bits on restart if using single-shot */
> if (config->ss_ctrl[i] || config->ss_pe_cmp[i])
> - config->ss_status[i] &= ~TRCSSCSRn_STATUS;
> + drvdata->ss_status[i] &= ~(TRCSSCSRn_STATUS | TRCSSCSRn_PENDING);
> etm4x_relaxed_write32(csa, config->ss_ctrl[i], TRCSSCCRn(i));
> - etm4x_relaxed_write32(csa, config->ss_status[i], TRCSSCSRn(i));
> + etm4x_relaxed_write32(csa, drvdata->ss_status[i], TRCSSCSRn(i));
> if (etm4x_sspcicrn_present(drvdata, i))
> etm4x_relaxed_write32(csa, config->ss_pe_cmp[i], TRCSSPCICRn(i));
> }
> @@ -772,6 +772,7 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
> /* Clear configuration from previous run */
> memset(config, 0, sizeof(struct etmv4_config));
>
> +
Unexpected new line?
> @@ -1497,8 +1498,9 @@ static void etm4_init_arch_data(void *info)
> */
> caps->nr_ss_cmp = FIELD_GET(TRCIDR4_NUMSSCC_MASK, etmidr4);
> for (i = 0; i < caps->nr_ss_cmp; i++) {
> - drvdata->config.ss_status[i] =
> - etm4x_relaxed_read32(csa, TRCSSCSRn(i));
> + drvdata->ss_status[i] = etm4x_relaxed_read32(csa, TRCSSCSRn(i));
> + drvdata->ss_status[i] &= (TRCSSCSRn_PC | TRCSSCSRn_DV |
> + TRCSSCSRn_DA | TRCSSCSRn_INST);
Since etm4_enable_hw() clears the TRCSSCSRn_STATUS and
TRCSSCSRn_PENDING bits every time, here is no need to clear the
status bits during probe.
In the future, we may want to preserve the status within a session and
clear it only when starting a new session. Clearing the status bits here
still cannot handle stale status across multiple sessions, so we can
defer this improvement for later.
Thanks,
Leo
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [PATCH v7 05/13] coresight: etm4x: exclude ss_status from drvdata->config
2026-05-28 13:30 ` Leo Yan
@ 2026-05-28 13:46 ` Yeoreum Yun
0 siblings, 0 replies; 39+ messages in thread
From: Yeoreum Yun @ 2026-05-28 13:46 UTC (permalink / raw)
To: Leo Yan
Cc: coresight, linux-arm-kernel, linux-kernel, suzuki.poulose,
mike.leach, james.clark, alexander.shishkin, jie.gan
Hi Leo,
> On Tue, May 19, 2026 at 04:48:04PM +0100, Yeoreum Yun wrote:
>
> [...]
>
> > @@ -571,11 +571,11 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
> > etm4x_relaxed_write32(csa, config->res_ctrl[i], TRCRSCTLRn(i));
> >
> > for (i = 0; i < caps->nr_ss_cmp; i++) {
> > - /* always clear status bit on restart if using single-shot */
> > + /* always clear status and pending bits on restart if using single-shot */
> > if (config->ss_ctrl[i] || config->ss_pe_cmp[i])
> > - config->ss_status[i] &= ~TRCSSCSRn_STATUS;
> > + drvdata->ss_status[i] &= ~(TRCSSCSRn_STATUS | TRCSSCSRn_PENDING);
> > etm4x_relaxed_write32(csa, config->ss_ctrl[i], TRCSSCCRn(i));
> > - etm4x_relaxed_write32(csa, config->ss_status[i], TRCSSCSRn(i));
> > + etm4x_relaxed_write32(csa, drvdata->ss_status[i], TRCSSCSRn(i));
> > if (etm4x_sspcicrn_present(drvdata, i))
> > etm4x_relaxed_write32(csa, config->ss_pe_cmp[i], TRCSSPCICRn(i));
> > }
> > @@ -772,6 +772,7 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
> > /* Clear configuration from previous run */
> > memset(config, 0, sizeof(struct etmv4_config));
> >
> > +
>
> Unexpected new line?
Oops. I'll remove it.
>
> > @@ -1497,8 +1498,9 @@ static void etm4_init_arch_data(void *info)
> > */
> > caps->nr_ss_cmp = FIELD_GET(TRCIDR4_NUMSSCC_MASK, etmidr4);
> > for (i = 0; i < caps->nr_ss_cmp; i++) {
> > - drvdata->config.ss_status[i] =
> > - etm4x_relaxed_read32(csa, TRCSSCSRn(i));
> > + drvdata->ss_status[i] = etm4x_relaxed_read32(csa, TRCSSCSRn(i));
> > + drvdata->ss_status[i] &= (TRCSSCSRn_PC | TRCSSCSRn_DV |
> > + TRCSSCSRn_DA | TRCSSCSRn_INST);
>
> Since etm4_enable_hw() clears the TRCSSCSRn_STATUS and
> TRCSSCSRn_PENDING bits every time, here is no need to clear the
> status bits during probe.
>
> In the future, we may want to preserve the status within a session and
> clear it only when starting a new session. Clearing the status bits here
> still cannot handle stale status across multiple sessions, so we can
> defer this improvement for later.
Yes. That would require near future as we discussed in offline.
but the at the initialisation perspective, it should ignore those bits
since that would be random value after reset.
So, I'll remain it as it is.
--
Sincerely,
Yeoreum Yun
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v7 05/13] coresight: etm4x: exclude ss_status from drvdata->config
2026-05-19 15:48 ` [PATCH v7 05/13] coresight: etm4x: exclude ss_status from drvdata->config Yeoreum Yun
2026-05-28 13:30 ` Leo Yan
@ 2026-06-01 11:27 ` Suzuki K Poulose
2026-06-01 11:52 ` Yeoreum Yun
1 sibling, 1 reply; 39+ messages in thread
From: Suzuki K Poulose @ 2026-06-01 11:27 UTC (permalink / raw)
To: Yeoreum Yun, coresight, linux-arm-kernel, linux-kernel
Cc: mike.leach, james.clark, alexander.shishkin, leo.yan, jie.gan
Hi Levi,
On 19/05/2026 16:48, Yeoreum Yun wrote:
> The purpose of TRCSSCSRn register is to show status of
> the corresponding Single-shot Comparator Control and input supports.
> That means writable field's purpose for reset or restore from idle status
> not for configuration.
>
> Therefore, exclude ss_status from drvdata->config and move it to drvdata.
TRCSSCSRn has two different types of fields.
1. Capability
2. Status
Moving the entire register from "config" to a common dangling place
looks like shifting the problem to me.
Could we do something like :
1. Split the fields to two.
a. Store only the capability information in etmv4_caps. Bits[4:0]
b. Store the Status bit in drvdata->config , as it is really matters
to the session ? Bits[31:30]
Add a helper to write/read the TRCSSSRn which would apply/mask the bits
from drvdata->etmv4_caps->fields to the Status/Pending
Suzuki
>
> Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
> ---
> .../hwtracing/coresight/coresight-etm4x-cfg.c | 1 -
> .../hwtracing/coresight/coresight-etm4x-core.c | 16 +++++++++-------
> .../hwtracing/coresight/coresight-etm4x-sysfs.c | 10 +++++-----
> drivers/hwtracing/coresight/coresight-etm4x.h | 7 ++++++-
> 4 files changed, 20 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
> index e1a59b434505..9b4947d75fde 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
> @@ -86,7 +86,6 @@ static int etm4_cfg_map_reg_offset(struct etmv4_drvdata *drvdata,
> off_mask = (offset & GENMASK(11, 5));
> do {
> CHECKREGIDX(TRCSSCCRn(0), ss_ctrl, idx, off_mask);
> - CHECKREGIDX(TRCSSCSRn(0), ss_status, idx, off_mask);
> CHECKREGIDX(TRCSSPCICRn(0), ss_pe_cmp, idx, off_mask);
> } while (0);
> } else if ((offset >= TRCCIDCVRn(0)) && (offset <= TRCVMIDCVRn(7))) {
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> index 53fbc4826628..7783c97b53e8 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> @@ -95,7 +95,7 @@ static bool etm4x_sspcicrn_present(struct etmv4_drvdata *drvdata, int n)
> const struct etmv4_caps *caps = &drvdata->caps;
>
> return (n < caps->nr_ss_cmp) && caps->nr_pe_cmp &&
> - (drvdata->config.ss_status[n] & TRCSSCSRn_PC);
> + (drvdata->ss_status[n] & TRCSSCSRn_PC);
> }
>
> u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
> @@ -571,11 +571,11 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
> etm4x_relaxed_write32(csa, config->res_ctrl[i], TRCRSCTLRn(i));
>
> for (i = 0; i < caps->nr_ss_cmp; i++) {
> - /* always clear status bit on restart if using single-shot */
> + /* always clear status and pending bits on restart if using single-shot */
> if (config->ss_ctrl[i] || config->ss_pe_cmp[i])
> - config->ss_status[i] &= ~TRCSSCSRn_STATUS;
> + drvdata->ss_status[i] &= ~(TRCSSCSRn_STATUS | TRCSSCSRn_PENDING);
> etm4x_relaxed_write32(csa, config->ss_ctrl[i], TRCSSCCRn(i));
> - etm4x_relaxed_write32(csa, config->ss_status[i], TRCSSCSRn(i));
> + etm4x_relaxed_write32(csa, drvdata->ss_status[i], TRCSSCSRn(i));
> if (etm4x_sspcicrn_present(drvdata, i))
> etm4x_relaxed_write32(csa, config->ss_pe_cmp[i], TRCSSPCICRn(i));
> }
> @@ -772,6 +772,7 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
> /* Clear configuration from previous run */
> memset(config, 0, sizeof(struct etmv4_config));
>
> +
> if (attr->exclude_kernel)
> config->mode = ETM_MODE_EXCL_KERN;
>
> @@ -1064,7 +1065,7 @@ static void etm4_disable_hw(struct etmv4_drvdata *drvdata)
>
> /* read the status of the single shot comparators */
> for (i = 0; i < caps->nr_ss_cmp; i++) {
> - config->ss_status[i] =
> + drvdata->ss_status[i] =
> etm4x_relaxed_read32(csa, TRCSSCSRn(i));
> }
>
> @@ -1497,8 +1498,9 @@ static void etm4_init_arch_data(void *info)
> */
> caps->nr_ss_cmp = FIELD_GET(TRCIDR4_NUMSSCC_MASK, etmidr4);
> for (i = 0; i < caps->nr_ss_cmp; i++) {
> - drvdata->config.ss_status[i] =
> - etm4x_relaxed_read32(csa, TRCSSCSRn(i));
> + drvdata->ss_status[i] = etm4x_relaxed_read32(csa, TRCSSCSRn(i));
> + drvdata->ss_status[i] &= (TRCSSCSRn_PC | TRCSSCSRn_DV |
> + TRCSSCSRn_DA | TRCSSCSRn_INST);
> }
> /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */
> caps->numcidc = FIELD_GET(TRCIDR4_NUMCIDC_MASK, etmidr4);
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> index 7de3c58a47b4..71e95d152ee6 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> @@ -1829,8 +1829,8 @@ static ssize_t sshot_ctrl_store(struct device *dev,
> raw_spin_lock(&drvdata->spinlock);
> idx = config->ss_idx;
> config->ss_ctrl[idx] = FIELD_PREP(TRCSSCCRn_SAC_ARC_RST_MASK, val);
> - /* must clear bit 31 in related status register on programming */
> - config->ss_status[idx] &= ~TRCSSCSRn_STATUS;
> + /* must clear bit 31 and 30 in related status register on programming */
> + drvdata->ss_status[idx] &= ~(TRCSSCSRn_STATUS | TRCSSCSRn_PENDING);
> raw_spin_unlock(&drvdata->spinlock);
> return size;
> }
> @@ -1844,7 +1844,7 @@ static ssize_t sshot_status_show(struct device *dev,
> struct etmv4_config *config = &drvdata->config;
>
> raw_spin_lock(&drvdata->spinlock);
> - val = config->ss_status[config->ss_idx];
> + val = drvdata->ss_status[config->ss_idx];
> raw_spin_unlock(&drvdata->spinlock);
> return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> }
> @@ -1879,8 +1879,8 @@ static ssize_t sshot_pe_ctrl_store(struct device *dev,
> raw_spin_lock(&drvdata->spinlock);
> idx = config->ss_idx;
> config->ss_pe_cmp[idx] = FIELD_PREP(TRCSSPCICRn_PC_MASK, val);
> - /* must clear bit 31 in related status register on programming */
> - config->ss_status[idx] &= ~TRCSSCSRn_STATUS;
> + /* must clear bit 31 and 30 in related status register on programming */
> + drvdata->ss_status[idx] &= ~(TRCSSCSRn_STATUS | TRCSSCSRn_PENDING);
> raw_spin_unlock(&drvdata->spinlock);
> return size;
> }
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
> index 6d4fbae78448..43db1eb6f8cd 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.h
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
> @@ -213,6 +213,7 @@
> #define TRCACATRn_EXLEVEL_MASK GENMASK(14, 8)
>
> #define TRCSSCSRn_STATUS BIT(31)
> +#define TRCSSCSRn_PENDING BIT(30)
> #define TRCSSCCRn_SAC_ARC_RST_MASK GENMASK(24, 0)
>
> #define TRCSSPCICRn_PC_MASK GENMASK(7, 0)
> @@ -730,6 +731,9 @@ static inline u32 etm4_res_sel_pair(u8 res_sel_idx)
> #define ETM_DEFAULT_ADDR_COMP 0
>
> #define TRCSSCSRn_PC BIT(3)
> +#define TRCSSCSRn_DV BIT(2)
> +#define TRCSSCSRn_DA BIT(1)
> +#define TRCSSCSRn_INST BIT(0)
>
> /* PowerDown Control Register bits */
> #define TRCPDCR_PU BIT(3)
> @@ -978,7 +982,6 @@ struct etmv4_config {
> u32 res_ctrl[ETM_MAX_RES_SEL]; /* TRCRSCTLRn */
> u8 ss_idx;
> u32 ss_ctrl[ETM_MAX_SS_CMP];
> - u32 ss_status[ETM_MAX_SS_CMP];
> u32 ss_pe_cmp[ETM_MAX_SS_CMP];
> u8 addr_idx;
> u64 addr_val[ETM_MAX_SINGLE_ADDR_CMP];
> @@ -1073,6 +1076,7 @@ struct etmv4_save_state {
> * @config: structure holding configuration parameters.
> * @save_state: State to be preserved across power loss
> * @paused: Indicates if the trace unit is paused.
> + * @ss_status: The status of the corresponding single-shot comparator.
> * @arch_features: Bitmap of arch features of etmv4 devices.
> */
> struct etmv4_drvdata {
> @@ -1092,6 +1096,7 @@ struct etmv4_drvdata {
> u64 trfcr;
> struct etmv4_config config;
> struct etmv4_save_state *save_state;
> + u32 ss_status[ETM_MAX_SS_CMP];
> DECLARE_BITMAP(arch_features, ETM4_IMPDEF_FEATURE_MAX);
> };
>
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [PATCH v7 05/13] coresight: etm4x: exclude ss_status from drvdata->config
2026-06-01 11:27 ` Suzuki K Poulose
@ 2026-06-01 11:52 ` Yeoreum Yun
0 siblings, 0 replies; 39+ messages in thread
From: Yeoreum Yun @ 2026-06-01 11:52 UTC (permalink / raw)
To: Suzuki K Poulose
Cc: coresight, linux-arm-kernel, linux-kernel, mike.leach,
james.clark, alexander.shishkin, leo.yan, jie.gan
Hi Suzuki,
> On 19/05/2026 16:48, Yeoreum Yun wrote:
> > The purpose of TRCSSCSRn register is to show status of
> > the corresponding Single-shot Comparator Control and input supports.
> > That means writable field's purpose for reset or restore from idle status
> > not for configuration.
> >
> > Therefore, exclude ss_status from drvdata->config and move it to drvdata.
>
> TRCSSCSRn has two different types of fields.
>
> 1. Capability
> 2. Status
>
> Moving the entire register from "config" to a common dangling place looks
> like shifting the problem to me.
>
> Could we do something like :
>
> 1. Split the fields to two.
> a. Store only the capability information in etmv4_caps. Bits[4:0]
> b. Store the Status bit in drvdata->config , as it is really matters
> to the session ? Bits[31:30]
>
> Add a helper to write/read the TRCSSSRn which would apply/mask the bits from
> drvdata->etmv4_caps->fields to the Status/Pending
Well. I'm not sure about whether we need to this.
When I remind of discussion with Leo, The Status and Pending bits should
be preserved in the *same* session theoretically However, Unitil today
In case of *perf* it doesn't keep but always cleared at the time of
resuming session and this behavior haven't reported any issue yet.
TBH, I don't have any idea how perf could utilise those bits except
the current use case for the sysfs to show the bit via *status* file.
Futhermore, IMHO, config isn't good place for the Status/Pending bits
since those fields are not *configrable* fields so I think it would be
better to locate saving information for the status and pending bits on
drvdata or by defining other fields.
But, until we find some usage of those bits in perf, I think we can
delay this separation you suggest and it might be better to keep as-is
for the purpose of showing the status/pending bits when sysfs session is
finished.
Am I missing something?
>
> Suzuki
>
> >
> > Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
> > ---
> > .../hwtracing/coresight/coresight-etm4x-cfg.c | 1 -
> > .../hwtracing/coresight/coresight-etm4x-core.c | 16 +++++++++-------
> > .../hwtracing/coresight/coresight-etm4x-sysfs.c | 10 +++++-----
> > drivers/hwtracing/coresight/coresight-etm4x.h | 7 ++++++-
> > 4 files changed, 20 insertions(+), 14 deletions(-)
> >
> > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
> > index e1a59b434505..9b4947d75fde 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
> > +++ b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
> > @@ -86,7 +86,6 @@ static int etm4_cfg_map_reg_offset(struct etmv4_drvdata *drvdata,
> > off_mask = (offset & GENMASK(11, 5));
> > do {
> > CHECKREGIDX(TRCSSCCRn(0), ss_ctrl, idx, off_mask);
> > - CHECKREGIDX(TRCSSCSRn(0), ss_status, idx, off_mask);
> > CHECKREGIDX(TRCSSPCICRn(0), ss_pe_cmp, idx, off_mask);
> > } while (0);
> > } else if ((offset >= TRCCIDCVRn(0)) && (offset <= TRCVMIDCVRn(7))) {
> > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> > index 53fbc4826628..7783c97b53e8 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> > @@ -95,7 +95,7 @@ static bool etm4x_sspcicrn_present(struct etmv4_drvdata *drvdata, int n)
> > const struct etmv4_caps *caps = &drvdata->caps;
> > return (n < caps->nr_ss_cmp) && caps->nr_pe_cmp &&
> > - (drvdata->config.ss_status[n] & TRCSSCSRn_PC);
> > + (drvdata->ss_status[n] & TRCSSCSRn_PC);
> > }
> > u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
> > @@ -571,11 +571,11 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
> > etm4x_relaxed_write32(csa, config->res_ctrl[i], TRCRSCTLRn(i));
> > for (i = 0; i < caps->nr_ss_cmp; i++) {
> > - /* always clear status bit on restart if using single-shot */
> > + /* always clear status and pending bits on restart if using single-shot */
> > if (config->ss_ctrl[i] || config->ss_pe_cmp[i])
> > - config->ss_status[i] &= ~TRCSSCSRn_STATUS;
> > + drvdata->ss_status[i] &= ~(TRCSSCSRn_STATUS | TRCSSCSRn_PENDING);
> > etm4x_relaxed_write32(csa, config->ss_ctrl[i], TRCSSCCRn(i));
> > - etm4x_relaxed_write32(csa, config->ss_status[i], TRCSSCSRn(i));
> > + etm4x_relaxed_write32(csa, drvdata->ss_status[i], TRCSSCSRn(i));
> > if (etm4x_sspcicrn_present(drvdata, i))
> > etm4x_relaxed_write32(csa, config->ss_pe_cmp[i], TRCSSPCICRn(i));
> > }
> > @@ -772,6 +772,7 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
> > /* Clear configuration from previous run */
> > memset(config, 0, sizeof(struct etmv4_config));
> > +
> > if (attr->exclude_kernel)
> > config->mode = ETM_MODE_EXCL_KERN;
> > @@ -1064,7 +1065,7 @@ static void etm4_disable_hw(struct etmv4_drvdata *drvdata)
> > /* read the status of the single shot comparators */
> > for (i = 0; i < caps->nr_ss_cmp; i++) {
> > - config->ss_status[i] =
> > + drvdata->ss_status[i] =
> > etm4x_relaxed_read32(csa, TRCSSCSRn(i));
> > }
> > @@ -1497,8 +1498,9 @@ static void etm4_init_arch_data(void *info)
> > */
> > caps->nr_ss_cmp = FIELD_GET(TRCIDR4_NUMSSCC_MASK, etmidr4);
> > for (i = 0; i < caps->nr_ss_cmp; i++) {
> > - drvdata->config.ss_status[i] =
> > - etm4x_relaxed_read32(csa, TRCSSCSRn(i));
> > + drvdata->ss_status[i] = etm4x_relaxed_read32(csa, TRCSSCSRn(i));
> > + drvdata->ss_status[i] &= (TRCSSCSRn_PC | TRCSSCSRn_DV |
> > + TRCSSCSRn_DA | TRCSSCSRn_INST);
> > }
> > /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */
> > caps->numcidc = FIELD_GET(TRCIDR4_NUMCIDC_MASK, etmidr4);
> > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > index 7de3c58a47b4..71e95d152ee6 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > @@ -1829,8 +1829,8 @@ static ssize_t sshot_ctrl_store(struct device *dev,
> > raw_spin_lock(&drvdata->spinlock);
> > idx = config->ss_idx;
> > config->ss_ctrl[idx] = FIELD_PREP(TRCSSCCRn_SAC_ARC_RST_MASK, val);
> > - /* must clear bit 31 in related status register on programming */
> > - config->ss_status[idx] &= ~TRCSSCSRn_STATUS;
> > + /* must clear bit 31 and 30 in related status register on programming */
> > + drvdata->ss_status[idx] &= ~(TRCSSCSRn_STATUS | TRCSSCSRn_PENDING);
> > raw_spin_unlock(&drvdata->spinlock);
> > return size;
> > }
> > @@ -1844,7 +1844,7 @@ static ssize_t sshot_status_show(struct device *dev,
> > struct etmv4_config *config = &drvdata->config;
> > raw_spin_lock(&drvdata->spinlock);
> > - val = config->ss_status[config->ss_idx];
> > + val = drvdata->ss_status[config->ss_idx];
> > raw_spin_unlock(&drvdata->spinlock);
> > return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> > }
> > @@ -1879,8 +1879,8 @@ static ssize_t sshot_pe_ctrl_store(struct device *dev,
> > raw_spin_lock(&drvdata->spinlock);
> > idx = config->ss_idx;
> > config->ss_pe_cmp[idx] = FIELD_PREP(TRCSSPCICRn_PC_MASK, val);
> > - /* must clear bit 31 in related status register on programming */
> > - config->ss_status[idx] &= ~TRCSSCSRn_STATUS;
> > + /* must clear bit 31 and 30 in related status register on programming */
> > + drvdata->ss_status[idx] &= ~(TRCSSCSRn_STATUS | TRCSSCSRn_PENDING);
> > raw_spin_unlock(&drvdata->spinlock);
> > return size;
> > }
> > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
> > index 6d4fbae78448..43db1eb6f8cd 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm4x.h
> > +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
> > @@ -213,6 +213,7 @@
> > #define TRCACATRn_EXLEVEL_MASK GENMASK(14, 8)
> > #define TRCSSCSRn_STATUS BIT(31)
> > +#define TRCSSCSRn_PENDING BIT(30)
> > #define TRCSSCCRn_SAC_ARC_RST_MASK GENMASK(24, 0)
> > #define TRCSSPCICRn_PC_MASK GENMASK(7, 0)
> > @@ -730,6 +731,9 @@ static inline u32 etm4_res_sel_pair(u8 res_sel_idx)
> > #define ETM_DEFAULT_ADDR_COMP 0
> > #define TRCSSCSRn_PC BIT(3)
> > +#define TRCSSCSRn_DV BIT(2)
> > +#define TRCSSCSRn_DA BIT(1)
> > +#define TRCSSCSRn_INST BIT(0)
> > /* PowerDown Control Register bits */
> > #define TRCPDCR_PU BIT(3)
> > @@ -978,7 +982,6 @@ struct etmv4_config {
> > u32 res_ctrl[ETM_MAX_RES_SEL]; /* TRCRSCTLRn */
> > u8 ss_idx;
> > u32 ss_ctrl[ETM_MAX_SS_CMP];
> > - u32 ss_status[ETM_MAX_SS_CMP];
> > u32 ss_pe_cmp[ETM_MAX_SS_CMP];
> > u8 addr_idx;
> > u64 addr_val[ETM_MAX_SINGLE_ADDR_CMP];
> > @@ -1073,6 +1076,7 @@ struct etmv4_save_state {
> > * @config: structure holding configuration parameters.
> > * @save_state: State to be preserved across power loss
> > * @paused: Indicates if the trace unit is paused.
> > + * @ss_status: The status of the corresponding single-shot comparator.
> > * @arch_features: Bitmap of arch features of etmv4 devices.
> > */
> > struct etmv4_drvdata {
> > @@ -1092,6 +1096,7 @@ struct etmv4_drvdata {
> > u64 trfcr;
> > struct etmv4_config config;
> > struct etmv4_save_state *save_state;
> > + u32 ss_status[ETM_MAX_SS_CMP];
> > DECLARE_BITMAP(arch_features, ETM4_IMPDEF_FEATURE_MAX);
> > };
>
--
Sincerely,
Yeoreum Yun
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v7 06/13] coresight: etm4x: remove redundant fields in etmv4_save_state
2026-05-19 15:47 [PATCH v7 00/13] fix several inconsistencies with sysfs configuration in etmX Yeoreum Yun
` (4 preceding siblings ...)
2026-05-19 15:48 ` [PATCH v7 05/13] coresight: etm4x: exclude ss_status from drvdata->config Yeoreum Yun
@ 2026-05-19 15:48 ` Yeoreum Yun
2026-05-19 15:48 ` [PATCH v7 07/13] coresight: etm4x: fix leaked trace id Yeoreum Yun
` (6 subsequent siblings)
12 siblings, 0 replies; 39+ messages in thread
From: Yeoreum Yun @ 2026-05-19 15:48 UTC (permalink / raw)
To: coresight, linux-arm-kernel, linux-kernel
Cc: suzuki.poulose, mike.leach, james.clark, alexander.shishkin,
leo.yan, jie.gan, Yeoreum Yun
Some of fields are redundant in etmv4_save_state and never used:
ss_status => trcsscsr
seq_state => trcseqstr
cntr_val => trccntvr
vinst_ctrl => trcvictlr
Reviewed-by: Leo Yan <leo.yan@arm.com>
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
---
drivers/hwtracing/coresight/coresight-etm4x.h | 5 -----
1 file changed, 5 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
index 43db1eb6f8cd..cdeb2140735d 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.h
+++ b/drivers/hwtracing/coresight/coresight-etm4x.h
@@ -1046,11 +1046,6 @@ struct etmv4_save_state {
u32 trcclaimset;
- u32 cntr_val[ETMv4_MAX_CNTR];
- u32 seq_state;
- u32 vinst_ctrl;
- u32 ss_status[ETM_MAX_SS_CMP];
-
u32 trcpdcr;
};
--
LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7}
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PATCH v7 07/13] coresight: etm4x: fix leaked trace id
2026-05-19 15:47 [PATCH v7 00/13] fix several inconsistencies with sysfs configuration in etmX Yeoreum Yun
` (5 preceding siblings ...)
2026-05-19 15:48 ` [PATCH v7 06/13] coresight: etm4x: remove redundant fields in etmv4_save_state Yeoreum Yun
@ 2026-05-19 15:48 ` Yeoreum Yun
2026-05-19 15:48 ` [PATCH v7 08/13] coresight: etm4x: fix inconsistencies with sysfs configuration Yeoreum Yun
` (5 subsequent siblings)
12 siblings, 0 replies; 39+ messages in thread
From: Yeoreum Yun @ 2026-05-19 15:48 UTC (permalink / raw)
To: coresight, linux-arm-kernel, linux-kernel
Cc: suzuki.poulose, mike.leach, james.clark, alexander.shishkin,
leo.yan, jie.gan, Yeoreum Yun
If etm4_enable_sysfs() fails in cscfg_csdev_enable_active_config(),
the trace ID may be leaked because it is not released.
To address this, call etm4_release_trace_id() when etm4_enable_sysfs()
fails in cscfg_csdev_enable_active_config().
Fixes: 7ebd0ec6cf94 ("coresight: configfs: Allow configfs to activate configuration")
Reviewed-by: Jie Gan <jie.gan@oss.qualcomm.com>
Reviewed-by: Leo Yan <leo.yan@arm.com>
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
---
drivers/hwtracing/coresight/coresight-etm4x-core.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index 7783c97b53e8..9b477b36b432 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -929,8 +929,10 @@ static int etm4_enable_sysfs(struct coresight_device *csdev, struct coresight_pa
cscfg_config_sysfs_get_active_cfg(&cfg_hash, &preset);
if (cfg_hash) {
ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset);
- if (ret)
+ if (ret) {
+ etm4_release_trace_id(drvdata);
return ret;
+ }
}
raw_spin_lock(&drvdata->spinlock);
--
LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7}
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PATCH v7 08/13] coresight: etm4x: fix inconsistencies with sysfs configuration
2026-05-19 15:47 [PATCH v7 00/13] fix several inconsistencies with sysfs configuration in etmX Yeoreum Yun
` (6 preceding siblings ...)
2026-05-19 15:48 ` [PATCH v7 07/13] coresight: etm4x: fix leaked trace id Yeoreum Yun
@ 2026-05-19 15:48 ` Yeoreum Yun
2026-05-28 14:09 ` Leo Yan
2026-05-19 15:48 ` [PATCH v7 09/13] coresight: etm4x: missing cscfg_csdev_disable_active_config() in perf enable Yeoreum Yun
` (4 subsequent siblings)
12 siblings, 1 reply; 39+ messages in thread
From: Yeoreum Yun @ 2026-05-19 15:48 UTC (permalink / raw)
To: coresight, linux-arm-kernel, linux-kernel
Cc: suzuki.poulose, mike.leach, james.clark, alexander.shishkin,
leo.yan, jie.gan, Yeoreum Yun
The current ETM4x configuration via sysfs can lead to
several inconsistencies:
- If the configuration is modified via sysfs while a perf session is
active, the running configuration may differ before a sched-out and
after a subsequent sched-in.
- If a perf session and a sysfs session enable tracing concurrently,
the configuration from configfs may become corrupted.
- There is a risk of corrupting drvdata->config if a perf session enables
tracing while cscfg_csdev_disable_active_config() is being handled in
etm4_disable_sysfs().
To resolve these issues, separate the configuration into:
- active_config: the configuration applied to the current session
- config: the configuration set via sysfs
Additionally:
- Apply the configuration from configfs after taking the appropriate mode.
- Since active_config and related fields are accessed only by the local CPU
in etm4_enable/disable_sysfs_smp_call() (similar to perf enable/disable),
remove the lock/unlock from the sysfs enable/disable path and
startup/dying_cpu except when to access config fields.
Fixes: 54ff892b76c6 ("coresight: etm4x: splitting struct etmv4_drvdata")
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
---
.../hwtracing/coresight/coresight-etm4x-cfg.c | 2 +-
.../coresight/coresight-etm4x-core.c | 107 ++++++++++--------
drivers/hwtracing/coresight/coresight-etm4x.h | 2 +
3 files changed, 61 insertions(+), 50 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
index 9b4947d75fde..9d56e17e09b1 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
@@ -47,7 +47,7 @@ static int etm4_cfg_map_reg_offset(struct etmv4_drvdata *drvdata,
struct cscfg_regval_csdev *reg_csdev, u32 offset)
{
int err = -EINVAL, idx;
- struct etmv4_config *drvcfg = &drvdata->config;
+ struct etmv4_config *drvcfg = &drvdata->active_config;
u32 off_mask;
if (((offset >= TRCEVENTCTL0R) && (offset <= TRCVIPCSSCTLR)) ||
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index 9b477b36b432..f0a9f2ef4b27 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -243,6 +243,7 @@ void etm4_release_trace_id(struct etmv4_drvdata *drvdata)
struct etm4_enable_arg {
struct etmv4_drvdata *drvdata;
struct coresight_path *path;
+ struct etmv4_config config;
int rc;
};
@@ -268,10 +269,11 @@ static void etm4x_prohibit_trace(struct etmv4_drvdata *drvdata)
static u64 etm4x_get_kern_user_filter(struct etmv4_drvdata *drvdata)
{
u64 trfcr = drvdata->trfcr;
+ struct etmv4_config *config = &drvdata->active_config;
- if (drvdata->config.mode & ETM_MODE_EXCL_KERN)
+ if (config->mode & ETM_MODE_EXCL_KERN)
trfcr &= ~TRFCR_EL1_ExTRE;
- if (drvdata->config.mode & ETM_MODE_EXCL_USER)
+ if (config->mode & ETM_MODE_EXCL_USER)
trfcr &= ~TRFCR_EL1_E0TRE;
return trfcr;
@@ -279,7 +281,7 @@ static u64 etm4x_get_kern_user_filter(struct etmv4_drvdata *drvdata)
/*
* etm4x_allow_trace - Allow CPU tracing in the respective ELs,
- * as configured by the drvdata->config.mode for the current
+ * as configured by the drvdata->active_config.mode for the current
* session. Even though we have TRCVICTLR bits to filter the
* trace in the ELs, it doesn't prevent the ETM from generating
* a packet (e.g, TraceInfo) that might contain the addresses from
@@ -290,12 +292,13 @@ static u64 etm4x_get_kern_user_filter(struct etmv4_drvdata *drvdata)
static void etm4x_allow_trace(struct etmv4_drvdata *drvdata)
{
u64 trfcr, guest_trfcr;
+ struct etmv4_config *config = &drvdata->active_config;
/* If the CPU doesn't support FEAT_TRF, nothing to do */
if (!drvdata->trfcr)
return;
- if (drvdata->config.mode & ETM_MODE_EXCL_HOST)
+ if (config->mode & ETM_MODE_EXCL_HOST)
trfcr = drvdata->trfcr & ~(TRFCR_EL1_ExTRE | TRFCR_EL1_E0TRE);
else
trfcr = etm4x_get_kern_user_filter(drvdata);
@@ -303,7 +306,7 @@ static void etm4x_allow_trace(struct etmv4_drvdata *drvdata)
write_trfcr(trfcr);
/* Set filters for guests and pass to KVM */
- if (drvdata->config.mode & ETM_MODE_EXCL_GUEST)
+ if (config->mode & ETM_MODE_EXCL_GUEST)
guest_trfcr = drvdata->trfcr & ~(TRFCR_EL1_ExTRE | TRFCR_EL1_E0TRE);
else
guest_trfcr = etm4x_get_kern_user_filter(drvdata);
@@ -497,7 +500,7 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
{
int i, rc;
const struct etmv4_caps *caps = &drvdata->caps;
- struct etmv4_config *config = &drvdata->config;
+ struct etmv4_config *config = &drvdata->active_config;
struct coresight_device *csdev = drvdata->csdev;
struct device *etm_dev = &csdev->dev;
struct csdev_access *csa = &csdev->access;
@@ -618,27 +621,53 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
static void etm4_enable_sysfs_smp_call(void *info)
{
struct etm4_enable_arg *arg = info;
+ struct etmv4_drvdata *drvdata;
struct coresight_device *csdev;
+ unsigned long cfg_hash;
+ int preset;
if (WARN_ON(!arg))
return;
- csdev = arg->drvdata->csdev;
+ drvdata = arg->drvdata;
+ csdev = drvdata->csdev;
if (!coresight_take_mode(csdev, CS_MODE_SYSFS)) {
/* Someone is already using the tracer */
arg->rc = -EBUSY;
return;
}
- arg->rc = etm4_enable_hw(arg->drvdata);
+ /* enable any config activated by configfs */
+ cscfg_config_sysfs_get_active_cfg(&cfg_hash, &preset);
- /* The tracer didn't start */
+ drvdata->active_config = arg->config;
+
+ if (cfg_hash) {
+ arg->rc = cscfg_csdev_enable_active_config(csdev,
+ cfg_hash,
+ preset);
+ if (arg->rc)
+ goto err;
+ }
+
+ drvdata->trcid = arg->path->trace_id;
+
+ /* Tracer will never be paused in sysfs mode */
+ drvdata->paused = false;
+
+ arg->rc = etm4_enable_hw(drvdata);
if (arg->rc) {
- coresight_set_mode(csdev, CS_MODE_DISABLED);
- return;
+ cscfg_csdev_disable_active_config(csdev);
+ goto err;
}
+ drvdata->sticky_enable = true;
csdev->path = arg->path;
+
+ return;
+err:
+ /* The tracer didn't start */
+ coresight_set_mode(csdev, CS_MODE_DISABLED);
}
/*
@@ -676,7 +705,7 @@ static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata,
int ctridx;
int rselector;
const struct etmv4_caps *caps = &drvdata->caps;
- struct etmv4_config *config = &drvdata->config;
+ struct etmv4_config *config = &drvdata->active_config;
/* No point in trying if we don't have at least one counter */
if (!caps->nr_cntr)
@@ -760,7 +789,7 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
int ret = 0;
struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
const struct etmv4_caps *caps = &drvdata->caps;
- struct etmv4_config *config = &drvdata->config;
+ struct etmv4_config *config = &drvdata->active_config;
struct perf_event_attr max_timestamp = {
.ATTR_CFG_FLD_timestamp_CFG = U64_MAX,
};
@@ -922,25 +951,7 @@ static int etm4_enable_sysfs(struct coresight_device *csdev, struct coresight_pa
{
struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
struct etm4_enable_arg arg = { };
- unsigned long cfg_hash;
- int ret, preset;
-
- /* enable any config activated by configfs */
- cscfg_config_sysfs_get_active_cfg(&cfg_hash, &preset);
- if (cfg_hash) {
- ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset);
- if (ret) {
- etm4_release_trace_id(drvdata);
- return ret;
- }
- }
-
- raw_spin_lock(&drvdata->spinlock);
-
- drvdata->trcid = path->trace_id;
-
- /* Tracer will never be paused in sysfs mode */
- drvdata->paused = false;
+ int ret;
/*
* Executing etm4_enable_hw on the cpu whose ETM is being enabled
@@ -948,20 +959,20 @@ static int etm4_enable_sysfs(struct coresight_device *csdev, struct coresight_pa
*/
arg.drvdata = drvdata;
arg.path = path;
+
+ raw_spin_lock(&drvdata->spinlock);
+ arg.config = drvdata->config;
+ raw_spin_unlock(&drvdata->spinlock);
+
ret = smp_call_function_single(drvdata->cpu,
etm4_enable_sysfs_smp_call, &arg, 1);
if (!ret)
ret = arg.rc;
if (!ret)
- drvdata->sticky_enable = true;
-
- if (ret)
+ dev_dbg(&csdev->dev, "ETM tracing enabled\n");
+ else
etm4_release_trace_id(drvdata);
- raw_spin_unlock(&drvdata->spinlock);
-
- if (!ret)
- dev_dbg(&csdev->dev, "ETM tracing enabled\n");
return ret;
}
@@ -1048,7 +1059,7 @@ static void etm4_disable_hw(struct etmv4_drvdata *drvdata)
{
u32 control;
const struct etmv4_caps *caps = &drvdata->caps;
- struct etmv4_config *config = &drvdata->config;
+ struct etmv4_config *config = &drvdata->active_config;
struct coresight_device *csdev = drvdata->csdev;
struct csdev_access *csa = &csdev->access;
int i;
@@ -1091,6 +1102,8 @@ static void etm4_disable_sysfs_smp_call(void *info)
etm4_disable_hw(drvdata);
drvdata->csdev->path = NULL;
+ cscfg_csdev_disable_active_config(drvdata->csdev);
+
coresight_set_mode(drvdata->csdev, CS_MODE_DISABLED);
}
@@ -1135,8 +1148,6 @@ static void etm4_disable_sysfs(struct coresight_device *csdev)
{
struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
- raw_spin_lock(&drvdata->spinlock);
-
/*
* Executing etm4_disable_hw on the cpu whose ETM is being disabled
* ensures that register writes occur when cpu is powered.
@@ -1144,10 +1155,6 @@ static void etm4_disable_sysfs(struct coresight_device *csdev)
smp_call_function_single(drvdata->cpu, etm4_disable_sysfs_smp_call,
drvdata, 1);
- raw_spin_unlock(&drvdata->spinlock);
-
- cscfg_csdev_disable_active_config(csdev);
-
/*
* we only release trace IDs when resetting sysfs.
* This permits sysfs users to read the trace ID after the trace
@@ -1382,6 +1389,7 @@ static void etm4_init_arch_data(void *info)
struct etm4_init_arg *init_arg = info;
struct etmv4_drvdata *drvdata;
struct etmv4_caps *caps;
+ struct etmv4_config *config;
struct csdev_access *csa;
struct device *dev = init_arg->dev;
int i;
@@ -1389,6 +1397,7 @@ static void etm4_init_arch_data(void *info)
drvdata = dev_get_drvdata(init_arg->dev);
caps = &drvdata->caps;
csa = init_arg->csa;
+ config = &drvdata->config;
/*
* If we are unable to detect the access mechanism,
@@ -1449,7 +1458,7 @@ static void etm4_init_arch_data(void *info)
/* EXLEVEL_S, bits[19:16] Secure state instruction tracing */
caps->s_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_S_MASK, etmidr3);
- drvdata->config.s_ex_level = caps->s_ex_level;
+ config->s_ex_level = caps->s_ex_level;
/* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */
caps->ns_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_NS_MASK, etmidr3);
/*
@@ -1695,7 +1704,7 @@ static void etm4_set_default(struct etmv4_config *config)
static int etm4_get_next_comparator(struct etmv4_drvdata *drvdata, u32 type)
{
int nr_comparator, index = 0;
- struct etmv4_config *config = &drvdata->config;
+ struct etmv4_config *config = &drvdata->active_config;
/*
* nr_addr_cmp holds the number of comparator _pair_, so time 2
@@ -1736,7 +1745,7 @@ static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
{
int i, comparator, ret = 0;
u64 address;
- struct etmv4_config *config = &drvdata->config;
+ struct etmv4_config *config = &drvdata->active_config;
struct etm_filters *filters = event->hw.addr_filters;
if (!filters)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
index cdeb2140735d..485750b72635 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.h
+++ b/drivers/hwtracing/coresight/coresight-etm4x.h
@@ -1068,6 +1068,7 @@ struct etmv4_save_state {
* allows tracing at all ELs. We don't want to compute this
* at runtime, due to the additional setting of TRFCR_CX when
* in EL2. Otherwise, 0.
+ * @active_config: structure holding current applied configuration parameters.
* @config: structure holding configuration parameters.
* @save_state: State to be preserved across power loss
* @paused: Indicates if the trace unit is paused.
@@ -1089,6 +1090,7 @@ struct etmv4_drvdata {
bool os_unlock : 1;
bool paused : 1;
u64 trfcr;
+ struct etmv4_config active_config;
struct etmv4_config config;
struct etmv4_save_state *save_state;
u32 ss_status[ETM_MAX_SS_CMP];
--
LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7}
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [PATCH v7 08/13] coresight: etm4x: fix inconsistencies with sysfs configuration
2026-05-19 15:48 ` [PATCH v7 08/13] coresight: etm4x: fix inconsistencies with sysfs configuration Yeoreum Yun
@ 2026-05-28 14:09 ` Leo Yan
2026-05-28 14:26 ` Yeoreum Yun
0 siblings, 1 reply; 39+ messages in thread
From: Leo Yan @ 2026-05-28 14:09 UTC (permalink / raw)
To: Yeoreum Yun
Cc: coresight, linux-arm-kernel, linux-kernel, suzuki.poulose,
mike.leach, james.clark, alexander.shishkin, jie.gan
On Tue, May 19, 2026 at 04:48:07PM +0100, Yeoreum Yun wrote:
[...]
> --- a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
> @@ -47,7 +47,7 @@ static int etm4_cfg_map_reg_offset(struct etmv4_drvdata *drvdata,
> struct cscfg_regval_csdev *reg_csdev, u32 offset)
> {
> int err = -EINVAL, idx;
> - struct etmv4_config *drvcfg = &drvdata->config;
> + struct etmv4_config *drvcfg = &drvdata->active_config;
Wouldn't it make more sense to keep using drvdata->config for cfgfs?
This would avoid cfgfs updating the active configuration while a session
is enabled.
My understanding is after refactoring cfgfs, we will never expose
active_config or config anymore so this should not an issue. Before
that, maybe we just keep to use config so can avoid mess.
> u32 off_mask;
>
> if (((offset >= TRCEVENTCTL0R) && (offset <= TRCVIPCSSCTLR)) ||
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> index 9b477b36b432..f0a9f2ef4b27 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> @@ -243,6 +243,7 @@ void etm4_release_trace_id(struct etmv4_drvdata *drvdata)
> struct etm4_enable_arg {
> struct etmv4_drvdata *drvdata;
> struct coresight_path *path;
> + struct etmv4_config config;
> int rc;
> };
>
> @@ -268,10 +269,11 @@ static void etm4x_prohibit_trace(struct etmv4_drvdata *drvdata)
> static u64 etm4x_get_kern_user_filter(struct etmv4_drvdata *drvdata)
> {
> u64 trfcr = drvdata->trfcr;
> + struct etmv4_config *config = &drvdata->active_config;
>
> - if (drvdata->config.mode & ETM_MODE_EXCL_KERN)
> + if (config->mode & ETM_MODE_EXCL_KERN)
> trfcr &= ~TRFCR_EL1_ExTRE;
> - if (drvdata->config.mode & ETM_MODE_EXCL_USER)
> + if (config->mode & ETM_MODE_EXCL_USER)
> trfcr &= ~TRFCR_EL1_E0TRE;
>
> return trfcr;
> @@ -279,7 +281,7 @@ static u64 etm4x_get_kern_user_filter(struct etmv4_drvdata *drvdata)
>
> /*
> * etm4x_allow_trace - Allow CPU tracing in the respective ELs,
> - * as configured by the drvdata->config.mode for the current
> + * as configured by the drvdata->active_config.mode for the current
> * session. Even though we have TRCVICTLR bits to filter the
> * trace in the ELs, it doesn't prevent the ETM from generating
> * a packet (e.g, TraceInfo) that might contain the addresses from
> @@ -290,12 +292,13 @@ static u64 etm4x_get_kern_user_filter(struct etmv4_drvdata *drvdata)
> static void etm4x_allow_trace(struct etmv4_drvdata *drvdata)
> {
> u64 trfcr, guest_trfcr;
> + struct etmv4_config *config = &drvdata->active_config;
>
> /* If the CPU doesn't support FEAT_TRF, nothing to do */
> if (!drvdata->trfcr)
> return;
>
> - if (drvdata->config.mode & ETM_MODE_EXCL_HOST)
> + if (config->mode & ETM_MODE_EXCL_HOST)
> trfcr = drvdata->trfcr & ~(TRFCR_EL1_ExTRE | TRFCR_EL1_E0TRE);
> else
> trfcr = etm4x_get_kern_user_filter(drvdata);
> @@ -303,7 +306,7 @@ static void etm4x_allow_trace(struct etmv4_drvdata *drvdata)
> write_trfcr(trfcr);
>
> /* Set filters for guests and pass to KVM */
> - if (drvdata->config.mode & ETM_MODE_EXCL_GUEST)
> + if (config->mode & ETM_MODE_EXCL_GUEST)
> guest_trfcr = drvdata->trfcr & ~(TRFCR_EL1_ExTRE | TRFCR_EL1_E0TRE);
> else
> guest_trfcr = etm4x_get_kern_user_filter(drvdata);
> @@ -497,7 +500,7 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
> {
> int i, rc;
> const struct etmv4_caps *caps = &drvdata->caps;
> - struct etmv4_config *config = &drvdata->config;
> + struct etmv4_config *config = &drvdata->active_config;
> struct coresight_device *csdev = drvdata->csdev;
> struct device *etm_dev = &csdev->dev;
> struct csdev_access *csa = &csdev->access;
> @@ -618,27 +621,53 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
> static void etm4_enable_sysfs_smp_call(void *info)
> {
> struct etm4_enable_arg *arg = info;
> + struct etmv4_drvdata *drvdata;
> struct coresight_device *csdev;
> + unsigned long cfg_hash;
> + int preset;
>
> if (WARN_ON(!arg))
> return;
>
> - csdev = arg->drvdata->csdev;
> + drvdata = arg->drvdata;
> + csdev = drvdata->csdev;
> if (!coresight_take_mode(csdev, CS_MODE_SYSFS)) {
> /* Someone is already using the tracer */
> arg->rc = -EBUSY;
> return;
> }
>
> - arg->rc = etm4_enable_hw(arg->drvdata);
> + /* enable any config activated by configfs */
> + cscfg_config_sysfs_get_active_cfg(&cfg_hash, &preset);
>
> - /* The tracer didn't start */
> + drvdata->active_config = arg->config;
Can move this down to just before drvdata->trcid assignment so cscfg
operations can be put together?
> +
> + if (cfg_hash) {
> + arg->rc = cscfg_csdev_enable_active_config(csdev,
> + cfg_hash,
> + preset);
> + if (arg->rc)
> + goto err;
> + }
> +
> + drvdata->trcid = arg->path->trace_id;
> +
> + /* Tracer will never be paused in sysfs mode */
> + drvdata->paused = false;
> +
> + arg->rc = etm4_enable_hw(drvdata);
> if (arg->rc) {
> - coresight_set_mode(csdev, CS_MODE_DISABLED);
> - return;
> + cscfg_csdev_disable_active_config(csdev);
> + goto err;
Add a new goto tag (like err_enable_hw) for the disable_active_config
rollback?
> }
>
> + drvdata->sticky_enable = true;
> csdev->path = arg->path;
> +
> + return;
> +err:
> + /* The tracer didn't start */
> + coresight_set_mode(csdev, CS_MODE_DISABLED);
> }
>
> /*
> @@ -676,7 +705,7 @@ static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata,
> int ctridx;
> int rselector;
> const struct etmv4_caps *caps = &drvdata->caps;
> - struct etmv4_config *config = &drvdata->config;
> + struct etmv4_config *config = &drvdata->active_config;
>
> /* No point in trying if we don't have at least one counter */
> if (!caps->nr_cntr)
> @@ -760,7 +789,7 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
> int ret = 0;
> struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
> const struct etmv4_caps *caps = &drvdata->caps;
> - struct etmv4_config *config = &drvdata->config;
> + struct etmv4_config *config = &drvdata->active_config;
> struct perf_event_attr max_timestamp = {
> .ATTR_CFG_FLD_timestamp_CFG = U64_MAX,
> };
> @@ -922,25 +951,7 @@ static int etm4_enable_sysfs(struct coresight_device *csdev, struct coresight_pa
> {
> struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
> struct etm4_enable_arg arg = { };
> - unsigned long cfg_hash;
> - int ret, preset;
> -
> - /* enable any config activated by configfs */
> - cscfg_config_sysfs_get_active_cfg(&cfg_hash, &preset);
> - if (cfg_hash) {
> - ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset);
> - if (ret) {
> - etm4_release_trace_id(drvdata);
> - return ret;
> - }
> - }
> -
> - raw_spin_lock(&drvdata->spinlock);
> -
> - drvdata->trcid = path->trace_id;
> -
> - /* Tracer will never be paused in sysfs mode */
> - drvdata->paused = false;
> + int ret;
>
> /*
> * Executing etm4_enable_hw on the cpu whose ETM is being enabled
> @@ -948,20 +959,20 @@ static int etm4_enable_sysfs(struct coresight_device *csdev, struct coresight_pa
> */
> arg.drvdata = drvdata;
> arg.path = path;
> +
> + raw_spin_lock(&drvdata->spinlock);
> + arg.config = drvdata->config;
> + raw_spin_unlock(&drvdata->spinlock);
> +
> ret = smp_call_function_single(drvdata->cpu,
> etm4_enable_sysfs_smp_call, &arg, 1);
> if (!ret)
> ret = arg.rc;
> if (!ret)
> - drvdata->sticky_enable = true;
> -
> - if (ret)
> + dev_dbg(&csdev->dev, "ETM tracing enabled\n");
> + else
> etm4_release_trace_id(drvdata);
>
> - raw_spin_unlock(&drvdata->spinlock);
> -
> - if (!ret)
> - dev_dbg(&csdev->dev, "ETM tracing enabled\n");
> return ret;
> }
>
> @@ -1048,7 +1059,7 @@ static void etm4_disable_hw(struct etmv4_drvdata *drvdata)
> {
> u32 control;
> const struct etmv4_caps *caps = &drvdata->caps;
> - struct etmv4_config *config = &drvdata->config;
> + struct etmv4_config *config = &drvdata->active_config;
> struct coresight_device *csdev = drvdata->csdev;
> struct csdev_access *csa = &csdev->access;
> int i;
> @@ -1091,6 +1102,8 @@ static void etm4_disable_sysfs_smp_call(void *info)
> etm4_disable_hw(drvdata);
>
> drvdata->csdev->path = NULL;
> + cscfg_csdev_disable_active_config(drvdata->csdev);
Move cscfg_csdev_disable_active_config() just after etm4_disable_hw() so
the sequence is consistent with perf mode.
[...]
> @@ -1449,7 +1458,7 @@ static void etm4_init_arch_data(void *info)
>
> /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */
> caps->s_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_S_MASK, etmidr3);
> - drvdata->config.s_ex_level = caps->s_ex_level;
> + config->s_ex_level = caps->s_ex_level;
config->s_ex_level is redundant and not really a configuration item.
We should use caps->s_ex_level instead of config->s_ex_level wherever
it is used.
Thanks,
Leo
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [PATCH v7 08/13] coresight: etm4x: fix inconsistencies with sysfs configuration
2026-05-28 14:09 ` Leo Yan
@ 2026-05-28 14:26 ` Yeoreum Yun
2026-05-28 14:56 ` Leo Yan
0 siblings, 1 reply; 39+ messages in thread
From: Yeoreum Yun @ 2026-05-28 14:26 UTC (permalink / raw)
To: Leo Yan
Cc: coresight, linux-arm-kernel, linux-kernel, suzuki.poulose,
mike.leach, james.clark, alexander.shishkin, jie.gan
Hi Leo,
> On Tue, May 19, 2026 at 04:48:07PM +0100, Yeoreum Yun wrote:
>
> [...]
>
> > --- a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
> > +++ b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
> > @@ -47,7 +47,7 @@ static int etm4_cfg_map_reg_offset(struct etmv4_drvdata *drvdata,
> > struct cscfg_regval_csdev *reg_csdev, u32 offset)
> > {
> > int err = -EINVAL, idx;
> > - struct etmv4_config *drvcfg = &drvdata->config;
> > + struct etmv4_config *drvcfg = &drvdata->active_config;
>
> Wouldn't it make more sense to keep using drvdata->config for cfgfs?
> This would avoid cfgfs updating the active configuration while a session
> is enabled.
>
> My understanding is after refactoring cfgfs, we will never expose
> active_config or config anymore so this should not an issue. Before
> that, maybe we just keep to use config so can avoid mess.
I don't think so. since the cfgfs's config is updated right before
enable and in this patchset, It's applied after "take the mode".
If we do it into drvdta->config, then contention would be increased
with the access of sysfs and that nullifies almost this patch purpose
and because of we use "one config" this makes a corruption with perf
and sysfs.
Therefore, It might be right to remain this as it is.
and let's remove it at the time of refactorying.
>
> > u32 off_mask;
> >
> > if (((offset >= TRCEVENTCTL0R) && (offset <= TRCVIPCSSCTLR)) ||
> > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> > index 9b477b36b432..f0a9f2ef4b27 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> > @@ -243,6 +243,7 @@ void etm4_release_trace_id(struct etmv4_drvdata *drvdata)
> > struct etm4_enable_arg {
> > struct etmv4_drvdata *drvdata;
> > struct coresight_path *path;
> > + struct etmv4_config config;
> > int rc;
> > };
> >
> > @@ -268,10 +269,11 @@ static void etm4x_prohibit_trace(struct etmv4_drvdata *drvdata)
> > static u64 etm4x_get_kern_user_filter(struct etmv4_drvdata *drvdata)
> > {
> > u64 trfcr = drvdata->trfcr;
> > + struct etmv4_config *config = &drvdata->active_config;
> >
> > - if (drvdata->config.mode & ETM_MODE_EXCL_KERN)
> > + if (config->mode & ETM_MODE_EXCL_KERN)
> > trfcr &= ~TRFCR_EL1_ExTRE;
> > - if (drvdata->config.mode & ETM_MODE_EXCL_USER)
> > + if (config->mode & ETM_MODE_EXCL_USER)
> > trfcr &= ~TRFCR_EL1_E0TRE;
> >
> > return trfcr;
> > @@ -279,7 +281,7 @@ static u64 etm4x_get_kern_user_filter(struct etmv4_drvdata *drvdata)
> >
> > /*
> > * etm4x_allow_trace - Allow CPU tracing in the respective ELs,
> > - * as configured by the drvdata->config.mode for the current
> > + * as configured by the drvdata->active_config.mode for the current
> > * session. Even though we have TRCVICTLR bits to filter the
> > * trace in the ELs, it doesn't prevent the ETM from generating
> > * a packet (e.g, TraceInfo) that might contain the addresses from
> > @@ -290,12 +292,13 @@ static u64 etm4x_get_kern_user_filter(struct etmv4_drvdata *drvdata)
> > static void etm4x_allow_trace(struct etmv4_drvdata *drvdata)
> > {
> > u64 trfcr, guest_trfcr;
> > + struct etmv4_config *config = &drvdata->active_config;
> >
> > /* If the CPU doesn't support FEAT_TRF, nothing to do */
> > if (!drvdata->trfcr)
> > return;
> >
> > - if (drvdata->config.mode & ETM_MODE_EXCL_HOST)
> > + if (config->mode & ETM_MODE_EXCL_HOST)
> > trfcr = drvdata->trfcr & ~(TRFCR_EL1_ExTRE | TRFCR_EL1_E0TRE);
> > else
> > trfcr = etm4x_get_kern_user_filter(drvdata);
> > @@ -303,7 +306,7 @@ static void etm4x_allow_trace(struct etmv4_drvdata *drvdata)
> > write_trfcr(trfcr);
> >
> > /* Set filters for guests and pass to KVM */
> > - if (drvdata->config.mode & ETM_MODE_EXCL_GUEST)
> > + if (config->mode & ETM_MODE_EXCL_GUEST)
> > guest_trfcr = drvdata->trfcr & ~(TRFCR_EL1_ExTRE | TRFCR_EL1_E0TRE);
> > else
> > guest_trfcr = etm4x_get_kern_user_filter(drvdata);
> > @@ -497,7 +500,7 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
> > {
> > int i, rc;
> > const struct etmv4_caps *caps = &drvdata->caps;
> > - struct etmv4_config *config = &drvdata->config;
> > + struct etmv4_config *config = &drvdata->active_config;
> > struct coresight_device *csdev = drvdata->csdev;
> > struct device *etm_dev = &csdev->dev;
> > struct csdev_access *csa = &csdev->access;
> > @@ -618,27 +621,53 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
> > static void etm4_enable_sysfs_smp_call(void *info)
> > {
> > struct etm4_enable_arg *arg = info;
> > + struct etmv4_drvdata *drvdata;
> > struct coresight_device *csdev;
> > + unsigned long cfg_hash;
> > + int preset;
> >
> > if (WARN_ON(!arg))
> > return;
> >
> > - csdev = arg->drvdata->csdev;
> > + drvdata = arg->drvdata;
> > + csdev = drvdata->csdev;
> > if (!coresight_take_mode(csdev, CS_MODE_SYSFS)) {
> > /* Someone is already using the tracer */
> > arg->rc = -EBUSY;
> > return;
> > }
> >
> > - arg->rc = etm4_enable_hw(arg->drvdata);
> > + /* enable any config activated by configfs */
> > + cscfg_config_sysfs_get_active_cfg(&cfg_hash, &preset);
> >
> > - /* The tracer didn't start */
> > + drvdata->active_config = arg->config;
>
> Can move this down to just before drvdata->trcid assignment so cscfg
> operations can be put together?
No. Copy the arg->config must be before cscfg_csdev_enable_active_config().
If that's after, it overrides the "preset" and this is different from
the former behavior.
>
> > +
> > + if (cfg_hash) {
> > + arg->rc = cscfg_csdev_enable_active_config(csdev,
> > + cfg_hash,
> > + preset);
> > + if (arg->rc)
> > + goto err;
> > + }
> > +
> > + drvdata->trcid = arg->path->trace_id;
> > +
> > + /* Tracer will never be paused in sysfs mode */
> > + drvdata->paused = false;
> > +
> > + arg->rc = etm4_enable_hw(drvdata);
> > if (arg->rc) {
> > - coresight_set_mode(csdev, CS_MODE_DISABLED);
> > - return;
> > + cscfg_csdev_disable_active_config(csdev);
> > + goto err;
>
> Add a new goto tag (like err_enable_hw) for the disable_active_config
> rollback?
This is only place where cscfg_csdev_disable_active_config().
Why do we need to goto for cleanup where there is no duplication?
>
> > }
> >
> > + drvdata->sticky_enable = true;
> > csdev->path = arg->path;
> > +
> > + return;
> > +err:
> > + /* The tracer didn't start */
> > + coresight_set_mode(csdev, CS_MODE_DISABLED);
> > }
> >
> > /*
> > @@ -676,7 +705,7 @@ static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata,
> > int ctridx;
> > int rselector;
> > const struct etmv4_caps *caps = &drvdata->caps;
> > - struct etmv4_config *config = &drvdata->config;
> > + struct etmv4_config *config = &drvdata->active_config;
> >
> > /* No point in trying if we don't have at least one counter */
> > if (!caps->nr_cntr)
> > @@ -760,7 +789,7 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
> > int ret = 0;
> > struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
> > const struct etmv4_caps *caps = &drvdata->caps;
> > - struct etmv4_config *config = &drvdata->config;
> > + struct etmv4_config *config = &drvdata->active_config;
> > struct perf_event_attr max_timestamp = {
> > .ATTR_CFG_FLD_timestamp_CFG = U64_MAX,
> > };
> > @@ -922,25 +951,7 @@ static int etm4_enable_sysfs(struct coresight_device *csdev, struct coresight_pa
> > {
> > struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
> > struct etm4_enable_arg arg = { };
> > - unsigned long cfg_hash;
> > - int ret, preset;
> > -
> > - /* enable any config activated by configfs */
> > - cscfg_config_sysfs_get_active_cfg(&cfg_hash, &preset);
> > - if (cfg_hash) {
> > - ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset);
> > - if (ret) {
> > - etm4_release_trace_id(drvdata);
> > - return ret;
> > - }
> > - }
> > -
> > - raw_spin_lock(&drvdata->spinlock);
> > -
> > - drvdata->trcid = path->trace_id;
> > -
> > - /* Tracer will never be paused in sysfs mode */
> > - drvdata->paused = false;
> > + int ret;
> >
> > /*
> > * Executing etm4_enable_hw on the cpu whose ETM is being enabled
> > @@ -948,20 +959,20 @@ static int etm4_enable_sysfs(struct coresight_device *csdev, struct coresight_pa
> > */
> > arg.drvdata = drvdata;
> > arg.path = path;
> > +
> > + raw_spin_lock(&drvdata->spinlock);
> > + arg.config = drvdata->config;
> > + raw_spin_unlock(&drvdata->spinlock);
> > +
> > ret = smp_call_function_single(drvdata->cpu,
> > etm4_enable_sysfs_smp_call, &arg, 1);
> > if (!ret)
> > ret = arg.rc;
> > if (!ret)
> > - drvdata->sticky_enable = true;
> > -
> > - if (ret)
> > + dev_dbg(&csdev->dev, "ETM tracing enabled\n");
> > + else
> > etm4_release_trace_id(drvdata);
> >
> > - raw_spin_unlock(&drvdata->spinlock);
> > -
> > - if (!ret)
> > - dev_dbg(&csdev->dev, "ETM tracing enabled\n");
> > return ret;
> > }
> >
> > @@ -1048,7 +1059,7 @@ static void etm4_disable_hw(struct etmv4_drvdata *drvdata)
> > {
> > u32 control;
> > const struct etmv4_caps *caps = &drvdata->caps;
> > - struct etmv4_config *config = &drvdata->config;
> > + struct etmv4_config *config = &drvdata->active_config;
> > struct coresight_device *csdev = drvdata->csdev;
> > struct csdev_access *csa = &csdev->access;
> > int i;
> > @@ -1091,6 +1102,8 @@ static void etm4_disable_sysfs_smp_call(void *info)
> > etm4_disable_hw(drvdata);
> >
> > drvdata->csdev->path = NULL;
> > + cscfg_csdev_disable_active_config(drvdata->csdev);
>
> Move cscfg_csdev_disable_active_config() just after etm4_disable_hw() so
> the sequence is consistent with perf mode.
Fair enough. I'll do that.
>
> [...]
>
> > @@ -1449,7 +1458,7 @@ static void etm4_init_arch_data(void *info)
> >
> > /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */
> > caps->s_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_S_MASK, etmidr3);
> > - drvdata->config.s_ex_level = caps->s_ex_level;
> > + config->s_ex_level = caps->s_ex_level;
>
> config->s_ex_level is redundant and not really a configuration item.
> We should use caps->s_ex_level instead of config->s_ex_level wherever
> it is used.
Agree, but this includes it should change the omse function
declations to pass "caps" argument:
- etm4_set_comparator_filter()
- etm4_set_start_stop_filter()
If that's okay, I'll respin with it.
>
> Thanks,
> Leo
--
Sincerely,
Yeoreum Yun
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [PATCH v7 08/13] coresight: etm4x: fix inconsistencies with sysfs configuration
2026-05-28 14:26 ` Yeoreum Yun
@ 2026-05-28 14:56 ` Leo Yan
2026-05-28 15:22 ` Yeoreum Yun
0 siblings, 1 reply; 39+ messages in thread
From: Leo Yan @ 2026-05-28 14:56 UTC (permalink / raw)
To: Yeoreum Yun
Cc: coresight, linux-arm-kernel, linux-kernel, suzuki.poulose,
mike.leach, james.clark, alexander.shishkin, jie.gan
On Thu, May 28, 2026 at 03:26:57PM +0100, Yeoreum Yun wrote:
[...]
> > > @@ -47,7 +47,7 @@ static int etm4_cfg_map_reg_offset(struct etmv4_drvdata *drvdata,
> > > struct cscfg_regval_csdev *reg_csdev, u32 offset)
> > > {
> > > int err = -EINVAL, idx;
> > > - struct etmv4_config *drvcfg = &drvdata->config;
> > > + struct etmv4_config *drvcfg = &drvdata->active_config;
> >
> > Wouldn't it make more sense to keep using drvdata->config for cfgfs?
> > This would avoid cfgfs updating the active configuration while a session
> > is enabled.
> >
> > My understanding is after refactoring cfgfs, we will never expose
> > active_config or config anymore so this should not an issue. Before
> > that, maybe we just keep to use config so can avoid mess.
>
> I don't think so. since the cfgfs's config is updated right before
> enable and in this patchset, It's applied after "take the mode".
>
> If we do it into drvdta->config, then contention would be increased
> with the access of sysfs and that nullifies almost this patch purpose
> and because of we use "one config" this makes a corruption with perf
> and sysfs.
Here have two different contention: the contention between sysfs and
cfgfs, and the contention between cfgfs and a runtime config (active
config). My suggestion is to avoid the later contention, which is the
main idea in this series that avoid the runtime config is modified in
the middle of a session.
That said, I have no strong opinion.
> > > static void etm4_enable_sysfs_smp_call(void *info)
> > > {
> > > struct etm4_enable_arg *arg = info;
> > > + struct etmv4_drvdata *drvdata;
> > > struct coresight_device *csdev;
> > > + unsigned long cfg_hash;
> > > + int preset;
> > >
> > > if (WARN_ON(!arg))
> > > return;
> > >
> > > - csdev = arg->drvdata->csdev;
> > > + drvdata = arg->drvdata;
> > > + csdev = drvdata->csdev;
> > > if (!coresight_take_mode(csdev, CS_MODE_SYSFS)) {
> > > /* Someone is already using the tracer */
> > > arg->rc = -EBUSY;
> > > return;
> > > }
> > >
> > > - arg->rc = etm4_enable_hw(arg->drvdata);
> > > + /* enable any config activated by configfs */
> > > + cscfg_config_sysfs_get_active_cfg(&cfg_hash, &preset);
> > >
> > > - /* The tracer didn't start */
> > > + drvdata->active_config = arg->config;
> >
> > Can move this down to just before drvdata->trcid assignment so cscfg
> > operations can be put together?
>
> No. Copy the arg->config must be before cscfg_csdev_enable_active_config().
> If that's after, it overrides the "preset" and this is different from
> the former behavior.
Please copy config first, then do cscfg stuffs.
> > > + arg->rc = etm4_enable_hw(drvdata);
> > > if (arg->rc) {
> > > - coresight_set_mode(csdev, CS_MODE_DISABLED);
> > > - return;
> > > + cscfg_csdev_disable_active_config(csdev);
> > > + goto err;
> >
> > Add a new goto tag (like err_enable_hw) for the disable_active_config
> > rollback?
>
> This is only place where cscfg_csdev_disable_active_config().
> Why do we need to goto for cleanup where there is no duplication?
It is about to use a central place for handling errors.
> > > @@ -1449,7 +1458,7 @@ static void etm4_init_arch_data(void *info)
> > >
> > > /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */
> > > caps->s_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_S_MASK, etmidr3);
> > > - drvdata->config.s_ex_level = caps->s_ex_level;
> > > + config->s_ex_level = caps->s_ex_level;
> >
> > config->s_ex_level is redundant and not really a configuration item.
> > We should use caps->s_ex_level instead of config->s_ex_level wherever
> > it is used.
>
> Agree, but this includes it should change the omse function
> declations to pass "caps" argument:
> - etm4_set_comparator_filter()
> - etm4_set_start_stop_filter()
>
> If that's okay, I'll respin with it.
This is fine for me.
Thanks,
Leo
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [PATCH v7 08/13] coresight: etm4x: fix inconsistencies with sysfs configuration
2026-05-28 14:56 ` Leo Yan
@ 2026-05-28 15:22 ` Yeoreum Yun
2026-06-01 15:38 ` Suzuki K Poulose
0 siblings, 1 reply; 39+ messages in thread
From: Yeoreum Yun @ 2026-05-28 15:22 UTC (permalink / raw)
To: Leo Yan
Cc: coresight, linux-arm-kernel, linux-kernel, suzuki.poulose,
mike.leach, james.clark, alexander.shishkin, jie.gan
> On Thu, May 28, 2026 at 03:26:57PM +0100, Yeoreum Yun wrote:
>
> [...]
>
> > > > @@ -47,7 +47,7 @@ static int etm4_cfg_map_reg_offset(struct etmv4_drvdata *drvdata,
> > > > struct cscfg_regval_csdev *reg_csdev, u32 offset)
> > > > {
> > > > int err = -EINVAL, idx;
> > > > - struct etmv4_config *drvcfg = &drvdata->config;
> > > > + struct etmv4_config *drvcfg = &drvdata->active_config;
> > >
> > > Wouldn't it make more sense to keep using drvdata->config for cfgfs?
> > > This would avoid cfgfs updating the active configuration while a session
> > > is enabled.
> > >
> > > My understanding is after refactoring cfgfs, we will never expose
> > > active_config or config anymore so this should not an issue. Before
> > > that, maybe we just keep to use config so can avoid mess.
> >
> > I don't think so. since the cfgfs's config is updated right before
> > enable and in this patchset, It's applied after "take the mode".
> >
> > If we do it into drvdta->config, then contention would be increased
> > with the access of sysfs and that nullifies almost this patch purpose
> > and because of we use "one config" this makes a corruption with perf
> > and sysfs.
>
> Here have two different contention: the contention between sysfs and
> cfgfs, and the contention between cfgfs and a runtime config (active
> config). My suggestion is to avoid the later contention, which is the
> main idea in this series that avoid the runtime config is modified in
> the middle of a session.
What I mean the *latter* contention is also pre-existed even in the
former (Just think about the access via configfs to modify parameter
while enabling the cfgfs configuration) and this is known issue
and should be resolved with another patchset (might we can set a flag
to disable store operation via conifgfs while "activation") and
make drvdata->config for cscfg just increase the "contention" for lock.
And this patch series main idea is not for contention between
*cfgfs* and *runtime configuration* but the corruption for racebetween
*sysfs and perf configuration* when it applies for the sharing one
configuration.
That's why this is different problem what you said and that is pre-exist
one. except above case (configfs vs activate cfgfs config),
I don't believe there is no contention to be modified *runtime* while
applying the cscfg config into active config and above case might be
reolved simply by some flag to prevent current value of each feat.
What contention scenario do you mean?
> > > > static void etm4_enable_sysfs_smp_call(void *info)
> > > > {
> > > > struct etm4_enable_arg *arg = info;
> > > > + struct etmv4_drvdata *drvdata;
> > > > struct coresight_device *csdev;
> > > > + unsigned long cfg_hash;
> > > > + int preset;
> > > >
> > > > if (WARN_ON(!arg))
> > > > return;
> > > >
> > > > - csdev = arg->drvdata->csdev;
> > > > + drvdata = arg->drvdata;
> > > > + csdev = drvdata->csdev;
> > > > if (!coresight_take_mode(csdev, CS_MODE_SYSFS)) {
> > > > /* Someone is already using the tracer */
> > > > arg->rc = -EBUSY;
> > > > return;
> > > > }
> > > >
> > > > - arg->rc = etm4_enable_hw(arg->drvdata);
> > > > + /* enable any config activated by configfs */
> > > > + cscfg_config_sysfs_get_active_cfg(&cfg_hash, &preset);
> > > >
> > > > - /* The tracer didn't start */
> > > > + drvdata->active_config = arg->config;
> > >
> > > Can move this down to just before drvdata->trcid assignment so cscfg
> > > operations can be put together?
> >
> > No. Copy the arg->config must be before cscfg_csdev_enable_active_config().
> > If that's after, it overrides the "preset" and this is different from
> > the former behavior.
>
> Please copy config first, then do cscfg stuffs.
It's already did. the chuck of config is:
- cscfg_config_sysfs_get_active_cfg()
- drvdata->active_config copy
- cscfg_csdev_enable_active_config()
Why do I need to seperate the copying the config though it's a part of
"setting" configuration chunk?
>
> > > > + arg->rc = etm4_enable_hw(drvdata);
> > > > if (arg->rc) {
> > > > - coresight_set_mode(csdev, CS_MODE_DISABLED);
> > > > - return;
> > > > + cscfg_csdev_disable_active_config(csdev);
> > > > + goto err;
> > >
> > > Add a new goto tag (like err_enable_hw) for the disable_active_config
> > > rollback?
> >
> > This is only place where cscfg_csdev_disable_active_config().
> > Why do we need to goto for cleanup where there is no duplication?
>
> It is about to use a central place for handling errors.
I don't think so. cscfg_csdev_disable_active_config() should be called
when cscfg_csdev_enable_active_config() is succssed seem not to be
called freely when cscfg_csdev_enable_active_config() isn't call.
IOW, for the central place, it makes a another variable to differenciate
each case and this seems more ugly.
What the benefit for this?
>
> > > > @@ -1449,7 +1458,7 @@ static void etm4_init_arch_data(void *info)
> > > >
> > > > /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */
> > > > caps->s_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_S_MASK, etmidr3);
> > > > - drvdata->config.s_ex_level = caps->s_ex_level;
> > > > + config->s_ex_level = caps->s_ex_level;
> > >
> > > config->s_ex_level is redundant and not really a configuration item.
> > > We should use caps->s_ex_level instead of config->s_ex_level wherever
> > > it is used.
> >
> > Agree, but this includes it should change the omse function
> > declations to pass "caps" argument:
> > - etm4_set_comparator_filter()
> > - etm4_set_start_stop_filter()
> >
> > If that's okay, I'll respin with it.
>
> This is fine for me.
Okay.
>
> Thanks,
> Leo
--
Sincerely,
Yeoreum Yun
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [PATCH v7 08/13] coresight: etm4x: fix inconsistencies with sysfs configuration
2026-05-28 15:22 ` Yeoreum Yun
@ 2026-06-01 15:38 ` Suzuki K Poulose
0 siblings, 0 replies; 39+ messages in thread
From: Suzuki K Poulose @ 2026-06-01 15:38 UTC (permalink / raw)
To: Yeoreum Yun, Leo Yan
Cc: coresight, linux-arm-kernel, linux-kernel, mike.leach,
james.clark, alexander.shishkin, jie.gan
On 28/05/2026 16:22, Yeoreum Yun wrote:
>> On Thu, May 28, 2026 at 03:26:57PM +0100, Yeoreum Yun wrote:
>>
>> [...]
>>
>>>>> @@ -47,7 +47,7 @@ static int etm4_cfg_map_reg_offset(struct etmv4_drvdata *drvdata,
>>>>> struct cscfg_regval_csdev *reg_csdev, u32 offset)
>>>>> {
>>>>> int err = -EINVAL, idx;
>>>>> - struct etmv4_config *drvcfg = &drvdata->config;
>>>>> + struct etmv4_config *drvcfg = &drvdata->active_config;
>>>>
>>>> Wouldn't it make more sense to keep using drvdata->config for cfgfs?
>>>> This would avoid cfgfs updating the active configuration while a session
>>>> is enabled.
>>>>
>>>> My understanding is after refactoring cfgfs, we will never expose
>>>> active_config or config anymore so this should not an issue. Before
>>>> that, maybe we just keep to use config so can avoid mess.
>>>
>>> I don't think so. since the cfgfs's config is updated right before
>>> enable and in this patchset, It's applied after "take the mode".
>>>
>>> If we do it into drvdta->config, then contention would be increased
>>> with the access of sysfs and that nullifies almost this patch purpose
>>> and because of we use "one config" this makes a corruption with perf
>>> and sysfs.
>>
>> Here have two different contention: the contention between sysfs and
>> cfgfs, and the contention between cfgfs and a runtime config (active
>> config). My suggestion is to avoid the later contention, which is the
>> main idea in this series that avoid the runtime config is modified in
>> the middle of a session.
>
> What I mean the *latter* contention is also pre-existed even in the
> former (Just think about the access via configfs to modify parameter
> while enabling the cfgfs configuration) and this is known issue
> and should be resolved with another patchset (might we can set a flag
> to disable store operation via conifgfs while "activation") and
> make drvdata->config for cscfg just increase the "contention" for lock.
We don't need to resolve it. We consume what is available at the time of
enable. If the user changes this it doesn't matter, we don't have to
honor the request. (Similar to what we do for the size of the ETR
buffer for sysfs mode)
Suzuki
> And this patch series main idea is not for contention between
> *cfgfs* and *runtime configuration* but the corruption for racebetween
> *sysfs and perf configuration* when it applies for the sharing one
> configuration.
>
> That's why this is different problem what you said and that is pre-exist
> one. except above case (configfs vs activate cfgfs config),
> I don't believe there is no contention to be modified *runtime* while
> applying the cscfg config into active config and above case might be
> reolved simply by some flag to prevent current value of each feat.
>
> What contention scenario do you mean?
>
>>>>> static void etm4_enable_sysfs_smp_call(void *info)
>>>>> {
>>>>> struct etm4_enable_arg *arg = info;
>>>>> + struct etmv4_drvdata *drvdata;
>>>>> struct coresight_device *csdev;
>>>>> + unsigned long cfg_hash;
>>>>> + int preset;
>>>>>
>>>>> if (WARN_ON(!arg))
>>>>> return;
>>>>>
>>>>> - csdev = arg->drvdata->csdev;
>>>>> + drvdata = arg->drvdata;
>>>>> + csdev = drvdata->csdev;
>>>>> if (!coresight_take_mode(csdev, CS_MODE_SYSFS)) {
>>>>> /* Someone is already using the tracer */
>>>>> arg->rc = -EBUSY;
>>>>> return;
>>>>> }
>>>>>
>>>>> - arg->rc = etm4_enable_hw(arg->drvdata);
>>>>> + /* enable any config activated by configfs */
>>>>> + cscfg_config_sysfs_get_active_cfg(&cfg_hash, &preset);
>>>>>
>>>>> - /* The tracer didn't start */
>>>>> + drvdata->active_config = arg->config;
>>>>
>>>> Can move this down to just before drvdata->trcid assignment so cscfg
>>>> operations can be put together?
>>>
>>> No. Copy the arg->config must be before cscfg_csdev_enable_active_config().
>>> If that's after, it overrides the "preset" and this is different from
>>> the former behavior.
>>
>> Please copy config first, then do cscfg stuffs.
>
> It's already did. the chuck of config is:
> - cscfg_config_sysfs_get_active_cfg()
> - drvdata->active_config copy
> - cscfg_csdev_enable_active_config()
>
> Why do I need to seperate the copying the config though it's a part of
> "setting" configuration chunk?
>
>>
>>>>> + arg->rc = etm4_enable_hw(drvdata);
>>>>> if (arg->rc) {
>>>>> - coresight_set_mode(csdev, CS_MODE_DISABLED);
>>>>> - return;
>>>>> + cscfg_csdev_disable_active_config(csdev);
>>>>> + goto err;
>>>>
>>>> Add a new goto tag (like err_enable_hw) for the disable_active_config
>>>> rollback?
>>>
>>> This is only place where cscfg_csdev_disable_active_config().
>>> Why do we need to goto for cleanup where there is no duplication?
>>
>> It is about to use a central place for handling errors.
>
> I don't think so. cscfg_csdev_disable_active_config() should be called
> when cscfg_csdev_enable_active_config() is succssed seem not to be
> called freely when cscfg_csdev_enable_active_config() isn't call.
> IOW, for the central place, it makes a another variable to differenciate
> each case and this seems more ugly.
>
> What the benefit for this?
>
>>
>>>>> @@ -1449,7 +1458,7 @@ static void etm4_init_arch_data(void *info)
>>>>>
>>>>> /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */
>>>>> caps->s_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_S_MASK, etmidr3);
>>>>> - drvdata->config.s_ex_level = caps->s_ex_level;
>>>>> + config->s_ex_level = caps->s_ex_level;
>>>>
>>>> config->s_ex_level is redundant and not really a configuration item.
>>>> We should use caps->s_ex_level instead of config->s_ex_level wherever
>>>> it is used.
>>>
>>> Agree, but this includes it should change the omse function
>>> declations to pass "caps" argument:
>>> - etm4_set_comparator_filter()
>>> - etm4_set_start_stop_filter()
>>>
>>> If that's okay, I'll respin with it.
>>
>> This is fine for me.
>
> Okay.
>
>>
>> Thanks,
>> Leo
>
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v7 09/13] coresight: etm4x: missing cscfg_csdev_disable_active_config() in perf enable
2026-05-19 15:47 [PATCH v7 00/13] fix several inconsistencies with sysfs configuration in etmX Yeoreum Yun
` (7 preceding siblings ...)
2026-05-19 15:48 ` [PATCH v7 08/13] coresight: etm4x: fix inconsistencies with sysfs configuration Yeoreum Yun
@ 2026-05-19 15:48 ` Yeoreum Yun
2026-05-28 14:33 ` Leo Yan
2026-05-19 15:48 ` [PATCH v7 10/13] coresight: etm3x: change drvdata->spinlock type to raw_spin_lock_t Yeoreum Yun
` (3 subsequent siblings)
12 siblings, 1 reply; 39+ messages in thread
From: Yeoreum Yun @ 2026-05-19 15:48 UTC (permalink / raw)
To: coresight, linux-arm-kernel, linux-kernel
Cc: suzuki.poulose, mike.leach, james.clark, alexander.shishkin,
leo.yan, jie.gan, Yeoreum Yun
In the perf enable path, there are missing cases where
cscfg_csdev_disable_active_config() is not called:
- Branch broadcast is selected but not supported by the hardware
- etm4_enable_hw() fails
This can lead to a leak of config_desc->active_cnt.
Fix this by properly calling cscfg_csdev_disable_active_config()
in these error paths.
Fixes: 810ac401db1f ("coresight: etm4x: Add complex configuration handlers to etmv4")
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
---
.../hwtracing/coresight/coresight-etm4x-core.c | 18 ++++++++++++------
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index f0a9f2ef4b27..0889937811cb 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -899,6 +899,8 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
* Missing BB support could cause silent decode errors
* so fail to open if it's not supported.
*/
+ if (cfg_hash)
+ cscfg_csdev_disable_active_config(csdev);
ret = -EINVAL;
goto out;
} else {
@@ -915,6 +917,7 @@ static int etm4_enable_perf(struct coresight_device *csdev,
struct coresight_path *path)
{
struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
+ struct perf_event_attr *attr = &event->attr;
int ret;
if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
@@ -926,7 +929,7 @@ static int etm4_enable_perf(struct coresight_device *csdev,
/* Configure the tracer based on the session's specifics */
ret = etm4_parse_event_config(csdev, event);
if (ret)
- goto out;
+ goto err;
drvdata->trcid = path->trace_id;
@@ -935,16 +938,19 @@ static int etm4_enable_perf(struct coresight_device *csdev,
/* And enable it */
ret = etm4_enable_hw(drvdata);
-
-out:
- /* Failed to start tracer; roll back to DISABLED mode */
if (ret) {
- coresight_set_mode(csdev, CS_MODE_DISABLED);
- return ret;
+ if (ATTR_CFG_GET_FLD(attr, configid))
+ cscfg_csdev_disable_active_config(csdev);
+ goto err;
}
csdev->path = path;
return 0;
+
+err:
+ /* Failed to start tracer; roll back to DISABLED mode */
+ coresight_set_mode(csdev, CS_MODE_DISABLED);
+ return ret;
}
static int etm4_enable_sysfs(struct coresight_device *csdev, struct coresight_path *path)
--
LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7}
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [PATCH v7 09/13] coresight: etm4x: missing cscfg_csdev_disable_active_config() in perf enable
2026-05-19 15:48 ` [PATCH v7 09/13] coresight: etm4x: missing cscfg_csdev_disable_active_config() in perf enable Yeoreum Yun
@ 2026-05-28 14:33 ` Leo Yan
2026-05-28 14:43 ` Yeoreum Yun
0 siblings, 1 reply; 39+ messages in thread
From: Leo Yan @ 2026-05-28 14:33 UTC (permalink / raw)
To: Yeoreum Yun
Cc: coresight, linux-arm-kernel, linux-kernel, suzuki.poulose,
mike.leach, james.clark, alexander.shishkin, jie.gan
On Tue, May 19, 2026 at 04:48:08PM +0100, Yeoreum Yun wrote:
> In the perf enable path, there are missing cases where
> cscfg_csdev_disable_active_config() is not called:
>
> - Branch broadcast is selected but not supported by the hardware
> - etm4_enable_hw() fails
>
> This can lead to a leak of config_desc->active_cnt.
> Fix this by properly calling cscfg_csdev_disable_active_config()
> in these error paths.
>
> Fixes: 810ac401db1f ("coresight: etm4x: Add complex configuration handlers to etmv4")
> Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
> ---
> .../hwtracing/coresight/coresight-etm4x-core.c | 18 ++++++++++++------
> 1 file changed, 12 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> index f0a9f2ef4b27..0889937811cb 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> @@ -899,6 +899,8 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
> * Missing BB support could cause silent decode errors
> * so fail to open if it's not supported.
> */
> + if (cfg_hash)
> + cscfg_csdev_disable_active_config(csdev);
> ret = -EINVAL;
> goto out;
> } else {
> @@ -915,6 +917,7 @@ static int etm4_enable_perf(struct coresight_device *csdev,
> struct coresight_path *path)
> {
> struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
> + struct perf_event_attr *attr = &event->attr;
> int ret;
>
> if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
> @@ -926,7 +929,7 @@ static int etm4_enable_perf(struct coresight_device *csdev,
> /* Configure the tracer based on the session's specifics */
> ret = etm4_parse_event_config(csdev, event);
> if (ret)
> - goto out;
> + goto err;
>
> drvdata->trcid = path->trace_id;
>
> @@ -935,16 +938,19 @@ static int etm4_enable_perf(struct coresight_device *csdev,
>
> /* And enable it */
> ret = etm4_enable_hw(drvdata);
> -
> -out:
> - /* Failed to start tracer; roll back to DISABLED mode */
> if (ret) {
> - coresight_set_mode(csdev, CS_MODE_DISABLED);
> - return ret;
> + if (ATTR_CFG_GET_FLD(attr, configid))
> + cscfg_csdev_disable_active_config(csdev);
> + goto err;
> }
>
> csdev->path = path;
> return 0;
> +
> +err:
> + /* Failed to start tracer; roll back to DISABLED mode */
> + coresight_set_mode(csdev, CS_MODE_DISABLED);
> + return ret;
> }
Seems to me, it is not readable if spread error handling into both child
and parent functions. I would like we can stick to use the same function
for resource allocation and rollback for failures.
How about below change (I did not verify it yet):
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index 0889937811cb..8347efb2069b 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -794,8 +794,7 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
.ATTR_CFG_FLD_timestamp_CFG = U64_MAX,
};
struct perf_event_attr *attr = &event->attr;
- unsigned long cfg_hash;
- int preset, cc_threshold;
+ int cc_threshold;
u8 ts_level;
/* Clear configuration from previous run */
@@ -882,16 +881,6 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
/* bit[12], Return stack enable bit */
config->cfg |= TRCCONFIGR_RS;
- /*
- * Set any selected configuration and preset. A zero configid means no
- * configuration active, preset = 0 means no preset selected.
- */
- cfg_hash = ATTR_CFG_GET_FLD(attr, configid);
- if (cfg_hash) {
- preset = ATTR_CFG_GET_FLD(attr, preset);
- ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset);
- }
-
/* branch broadcast - enable if selected and supported */
if (ATTR_CFG_GET_FLD(attr, branch_broadcast)) {
if (!caps->trcbb) {
@@ -899,8 +888,6 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
* Missing BB support could cause silent decode errors
* so fail to open if it's not supported.
*/
- if (cfg_hash)
- cscfg_csdev_disable_active_config(csdev);
ret = -EINVAL;
goto out;
} else {
@@ -918,7 +905,8 @@ static int etm4_enable_perf(struct coresight_device *csdev,
{
struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
struct perf_event_attr *attr = &event->attr;
- int ret;
+ unsigned long cfg_hash;
+ int preset, ret;
if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
return -EINVAL;
@@ -931,6 +919,18 @@ static int etm4_enable_perf(struct coresight_device *csdev,
if (ret)
goto err;
+ /*
+ * Set any selected configuration and preset. A zero configid means no
+ * configuration active, preset = 0 means no preset selected.
+ */
+ cfg_hash = ATTR_CFG_GET_FLD(attr, configid);
+ if (cfg_hash) {
+ preset = ATTR_CFG_GET_FLD(attr, preset);
+ ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset);
+ if (ret)
+ goto err;
+ }
+
drvdata->trcid = path->trace_id;
/* Populate pause state */
@@ -938,15 +938,15 @@ static int etm4_enable_perf(struct coresight_device *csdev,
/* And enable it */
ret = etm4_enable_hw(drvdata);
- if (ret) {
- if (ATTR_CFG_GET_FLD(attr, configid))
- cscfg_csdev_disable_active_config(csdev);
- goto err;
- }
+ if (ret)
+ goto err_enable_hw;
csdev->path = path;
return 0;
+err_enable_hw:
+ if (cfg_hash)
+ cscfg_csdev_disable_active_config(csdev);
err:
/* Failed to start tracer; roll back to DISABLED mode */
coresight_set_mode(csdev, CS_MODE_DISABLED);
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [PATCH v7 09/13] coresight: etm4x: missing cscfg_csdev_disable_active_config() in perf enable
2026-05-28 14:33 ` Leo Yan
@ 2026-05-28 14:43 ` Yeoreum Yun
2026-05-28 15:26 ` Leo Yan
0 siblings, 1 reply; 39+ messages in thread
From: Yeoreum Yun @ 2026-05-28 14:43 UTC (permalink / raw)
To: Leo Yan
Cc: coresight, linux-arm-kernel, linux-kernel, suzuki.poulose,
mike.leach, james.clark, alexander.shishkin, jie.gan
Hi Leo,
> On Tue, May 19, 2026 at 04:48:08PM +0100, Yeoreum Yun wrote:
> > In the perf enable path, there are missing cases where
> > cscfg_csdev_disable_active_config() is not called:
> >
> > - Branch broadcast is selected but not supported by the hardware
> > - etm4_enable_hw() fails
> >
> > This can lead to a leak of config_desc->active_cnt.
> > Fix this by properly calling cscfg_csdev_disable_active_config()
> > in these error paths.
> >
> > Fixes: 810ac401db1f ("coresight: etm4x: Add complex configuration handlers to etmv4")
> > Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
> > ---
> > .../hwtracing/coresight/coresight-etm4x-core.c | 18 ++++++++++++------
> > 1 file changed, 12 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> > index f0a9f2ef4b27..0889937811cb 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> > @@ -899,6 +899,8 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
> > * Missing BB support could cause silent decode errors
> > * so fail to open if it's not supported.
> > */
> > + if (cfg_hash)
> > + cscfg_csdev_disable_active_config(csdev);
> > ret = -EINVAL;
> > goto out;
> > } else {
> > @@ -915,6 +917,7 @@ static int etm4_enable_perf(struct coresight_device *csdev,
> > struct coresight_path *path)
> > {
> > struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
> > + struct perf_event_attr *attr = &event->attr;
> > int ret;
> >
> > if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
> > @@ -926,7 +929,7 @@ static int etm4_enable_perf(struct coresight_device *csdev,
> > /* Configure the tracer based on the session's specifics */
> > ret = etm4_parse_event_config(csdev, event);
> > if (ret)
> > - goto out;
> > + goto err;
> >
> > drvdata->trcid = path->trace_id;
> >
> > @@ -935,16 +938,19 @@ static int etm4_enable_perf(struct coresight_device *csdev,
> >
> > /* And enable it */
> > ret = etm4_enable_hw(drvdata);
> > -
> > -out:
> > - /* Failed to start tracer; roll back to DISABLED mode */
> > if (ret) {
> > - coresight_set_mode(csdev, CS_MODE_DISABLED);
> > - return ret;
> > + if (ATTR_CFG_GET_FLD(attr, configid))
> > + cscfg_csdev_disable_active_config(csdev);
> > + goto err;
> > }
> >
> > csdev->path = path;
> > return 0;
> > +
> > +err:
> > + /* Failed to start tracer; roll back to DISABLED mode */
> > + coresight_set_mode(csdev, CS_MODE_DISABLED);
> > + return ret;
> > }
>
> Seems to me, it is not readable if spread error handling into both child
> and parent functions. I would like we can stick to use the same function
> for resource allocation and rollback for failures.
>
> How about below change (I did not verify it yet):
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> index 0889937811cb..8347efb2069b 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> @@ -794,8 +794,7 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
> .ATTR_CFG_FLD_timestamp_CFG = U64_MAX,
> };
> struct perf_event_attr *attr = &event->attr;
> - unsigned long cfg_hash;
> - int preset, cc_threshold;
> + int cc_threshold;
> u8 ts_level;
>
> /* Clear configuration from previous run */
> @@ -882,16 +881,6 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
> /* bit[12], Return stack enable bit */
> config->cfg |= TRCCONFIGR_RS;
>
> - /*
> - * Set any selected configuration and preset. A zero configid means no
> - * configuration active, preset = 0 means no preset selected.
> - */
> - cfg_hash = ATTR_CFG_GET_FLD(attr, configid);
> - if (cfg_hash) {
> - preset = ATTR_CFG_GET_FLD(attr, preset);
> - ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset);
> - }
> -
> /* branch broadcast - enable if selected and supported */
> if (ATTR_CFG_GET_FLD(attr, branch_broadcast)) {
> if (!caps->trcbb) {
> @@ -899,8 +888,6 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
> * Missing BB support could cause silent decode errors
> * so fail to open if it's not supported.
> */
> - if (cfg_hash)
> - cscfg_csdev_disable_active_config(csdev);
> ret = -EINVAL;
> goto out;
> } else {
> @@ -918,7 +905,8 @@ static int etm4_enable_perf(struct coresight_device *csdev,
> {
> struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
> struct perf_event_attr *attr = &event->attr;
> - int ret;
> + unsigned long cfg_hash;
> + int preset, ret;
>
> if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
> return -EINVAL;
> @@ -931,6 +919,18 @@ static int etm4_enable_perf(struct coresight_device *csdev,
> if (ret)
> goto err;
>
> + /*
> + * Set any selected configuration and preset. A zero configid means no
> + * configuration active, preset = 0 means no preset selected.
> + */
> + cfg_hash = ATTR_CFG_GET_FLD(attr, configid);
> + if (cfg_hash) {
> + preset = ATTR_CFG_GET_FLD(attr, preset);
> + ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset);
> + if (ret)
> + goto err;
> + }
> +
> drvdata->trcid = path->trace_id;
>
> /* Populate pause state */
> @@ -938,15 +938,15 @@ static int etm4_enable_perf(struct coresight_device *csdev,
>
> /* And enable it */
> ret = etm4_enable_hw(drvdata);
> - if (ret) {
> - if (ATTR_CFG_GET_FLD(attr, configid))
> - cscfg_csdev_disable_active_config(csdev);
> - goto err;
> - }
> + if (ret)
> + goto err_enable_hw;
>
> csdev->path = path;
> return 0;
>
> +err_enable_hw:
> + if (cfg_hash)
> + cscfg_csdev_disable_active_config(csdev);
> err:
> /* Failed to start tracer; roll back to DISABLED mode */
> coresight_set_mode(csdev, CS_MODE_DISABLED);
No. since preset overrides the "perf configuratoin" formerly but
this code makes it vice versa. Also, cfg_hash and prest is also part of
etm4_parse_event_config(), and it doesn't seem to good to separate
cfgfs handling from that function.
IMHO, It would be better to keep this as it is.
--
Sincerely,
Yeoreum Yun
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [PATCH v7 09/13] coresight: etm4x: missing cscfg_csdev_disable_active_config() in perf enable
2026-05-28 14:43 ` Yeoreum Yun
@ 2026-05-28 15:26 ` Leo Yan
2026-05-28 16:01 ` Yeoreum Yun
0 siblings, 1 reply; 39+ messages in thread
From: Leo Yan @ 2026-05-28 15:26 UTC (permalink / raw)
To: Yeoreum Yun
Cc: coresight, linux-arm-kernel, linux-kernel, suzuki.poulose,
mike.leach, james.clark, alexander.shishkin, jie.gan
On Thu, May 28, 2026 at 03:43:40PM +0100, Yeoreum Yun wrote:
[...]
> > @@ -931,6 +919,18 @@ static int etm4_enable_perf(struct coresight_device *csdev,
> > if (ret)
> > goto err;
> >
> > + /*
> > + * Set any selected configuration and preset. A zero configid means no
> > + * configuration active, preset = 0 means no preset selected.
> > + */
> > + cfg_hash = ATTR_CFG_GET_FLD(attr, configid);
> > + if (cfg_hash) {
> > + preset = ATTR_CFG_GET_FLD(attr, preset);
> > + ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset);
> > + if (ret)
> > + goto err;
> > + }
> > +
> No. since preset overrides the "perf configuratoin" formerly but
> this code makes it vice versa.
The above proposed change applies cfgfs after calling
etm4_parse_event_config(). This is just use preset to override the
config. Do I miss anything?
> Also, cfg_hash and prest is also part of
> etm4_parse_event_config(), and it doesn't seem to good to separate
> cfgfs handling from that function.
>
> IMHO, It would be better to keep this as it is.
I have another version to give a try. I'd leave to you and maintainers
to choose which is better.
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index 0889937811cb..471824234800 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -882,16 +882,6 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
/* bit[12], Return stack enable bit */
config->cfg |= TRCCONFIGR_RS;
- /*
- * Set any selected configuration and preset. A zero configid means no
- * configuration active, preset = 0 means no preset selected.
- */
- cfg_hash = ATTR_CFG_GET_FLD(attr, configid);
- if (cfg_hash) {
- preset = ATTR_CFG_GET_FLD(attr, preset);
- ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset);
- }
-
/* branch broadcast - enable if selected and supported */
if (ATTR_CFG_GET_FLD(attr, branch_broadcast)) {
if (!caps->trcbb) {
@@ -899,8 +889,6 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
* Missing BB support could cause silent decode errors
* so fail to open if it's not supported.
*/
- if (cfg_hash)
- cscfg_csdev_disable_active_config(csdev);
ret = -EINVAL;
goto out;
} else {
@@ -908,10 +896,31 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
}
}
+ /*
+ * Set any selected configuration and preset. A zero configid means no
+ * configuration active, preset = 0 means no preset selected.
+ */
+ cfg_hash = ATTR_CFG_GET_FLD(attr, configid);
+ if (cfg_hash) {
+ preset = ATTR_CFG_GET_FLD(attr, preset);
+ ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset);
+ }
+
out:
return ret;
}
+static void etm4_clean_event_config(struct coresight_device *csdev,
+ struct perf_event *event)
+{
+ struct perf_event_attr *attr = &event->attr;
+ unsigned long cfg_hash;
+
+ cfg_hash = ATTR_CFG_GET_FLD(attr, configid);
+ if (cfg_hash)
+ cscfg_csdev_disable_active_config(csdev);
+}
+
static int etm4_enable_perf(struct coresight_device *csdev,
struct perf_event *event,
struct coresight_path *path)
@@ -938,15 +947,14 @@ static int etm4_enable_perf(struct coresight_device *csdev,
/* And enable it */
ret = etm4_enable_hw(drvdata);
- if (ret) {
- if (ATTR_CFG_GET_FLD(attr, configid))
- cscfg_csdev_disable_active_config(csdev);
- goto err;
- }
+ if (ret)
+ goto err_hw;
csdev->path = path;
return 0;
+err_hw:
+ etm4_clean_event_config(csdev, event);
err:
/* Failed to start tracer; roll back to DISABLED mode */
coresight_set_mode(csdev, CS_MODE_DISABLED);
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [PATCH v7 09/13] coresight: etm4x: missing cscfg_csdev_disable_active_config() in perf enable
2026-05-28 15:26 ` Leo Yan
@ 2026-05-28 16:01 ` Yeoreum Yun
2026-06-01 16:11 ` Suzuki K Poulose
0 siblings, 1 reply; 39+ messages in thread
From: Yeoreum Yun @ 2026-05-28 16:01 UTC (permalink / raw)
To: Leo Yan
Cc: coresight, linux-arm-kernel, linux-kernel, suzuki.poulose,
mike.leach, james.clark, alexander.shishkin, jie.gan
> On Thu, May 28, 2026 at 03:43:40PM +0100, Yeoreum Yun wrote:
>
> [...]
>
> > > @@ -931,6 +919,18 @@ static int etm4_enable_perf(struct coresight_device *csdev,
> > > if (ret)
> > > goto err;
> > >
> > > + /*
> > > + * Set any selected configuration and preset. A zero configid means no
> > > + * configuration active, preset = 0 means no preset selected.
> > > + */
> > > + cfg_hash = ATTR_CFG_GET_FLD(attr, configid);
> > > + if (cfg_hash) {
> > > + preset = ATTR_CFG_GET_FLD(attr, preset);
> > > + ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset);
> > > + if (ret)
> > > + goto err;
> > > + }
> > > +
>
> > No. since preset overrides the "perf configuratoin" formerly but
> > this code makes it vice versa.
>
> The above proposed change applies cfgfs after calling
> etm4_parse_event_config(). This is just use preset to override the
> config. Do I miss anything?
Ah sorry. I've misread the code location that was my bad.
>
> > Also, cfg_hash and prest is also part of
> > etm4_parse_event_config(), and it doesn't seem to good to separate
> > cfgfs handling from that function.
> >
> > IMHO, It would be better to keep this as it is.
>
> I have another version to give a try. I'd leave to you and maintainers
> to choose which is better.
Funcionally, Code works. However, To be honest, the pairing between
etm4_parse_event_config() and etm4_clean_event_config() feels a bit artificial to me.
So here I have simply followed the principle that,
if etm4_parse_event_config() fails, the configuration it touched should be
cleaned up within that function; and if a failure happens after
etm4_parse_event_config() has succeeded, the caller should perform the cleanup.
Renaming etm4_parse_event_config() and splitting out the
CSCFG-related handling as suggested would be possible,
although I still feel it may not be strictly necessary.
My preference would be to keep this as-is, but Suzuki, what do you think?
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> index 0889937811cb..471824234800 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> @@ -882,16 +882,6 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
> /* bit[12], Return stack enable bit */
> config->cfg |= TRCCONFIGR_RS;
>
> - /*
> - * Set any selected configuration and preset. A zero configid means no
> - * configuration active, preset = 0 means no preset selected.
> - */
> - cfg_hash = ATTR_CFG_GET_FLD(attr, configid);
> - if (cfg_hash) {
> - preset = ATTR_CFG_GET_FLD(attr, preset);
> - ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset);
> - }
> -
> /* branch broadcast - enable if selected and supported */
> if (ATTR_CFG_GET_FLD(attr, branch_broadcast)) {
> if (!caps->trcbb) {
> @@ -899,8 +889,6 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
> * Missing BB support could cause silent decode errors
> * so fail to open if it's not supported.
> */
> - if (cfg_hash)
> - cscfg_csdev_disable_active_config(csdev);
> ret = -EINVAL;
> goto out;
> } else {
> @@ -908,10 +896,31 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
> }
> }
>
> + /*
> + * Set any selected configuration and preset. A zero configid means no
> + * configuration active, preset = 0 means no preset selected.
> + */
> + cfg_hash = ATTR_CFG_GET_FLD(attr, configid);
> + if (cfg_hash) {
> + preset = ATTR_CFG_GET_FLD(attr, preset);
> + ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset);
> + }
> +
> out:
> return ret;
> }
>
> +static void etm4_clean_event_config(struct coresight_device *csdev,
> + struct perf_event *event)
> +{
> + struct perf_event_attr *attr = &event->attr;
> + unsigned long cfg_hash;
> +
> + cfg_hash = ATTR_CFG_GET_FLD(attr, configid);
> + if (cfg_hash)
> + cscfg_csdev_disable_active_config(csdev);
> +}
> +
> static int etm4_enable_perf(struct coresight_device *csdev,
> struct perf_event *event,
> struct coresight_path *path)
> @@ -938,15 +947,14 @@ static int etm4_enable_perf(struct coresight_device *csdev,
>
> /* And enable it */
> ret = etm4_enable_hw(drvdata);
> - if (ret) {
> - if (ATTR_CFG_GET_FLD(attr, configid))
> - cscfg_csdev_disable_active_config(csdev);
> - goto err;
> - }
> + if (ret)
> + goto err_hw;
>
> csdev->path = path;
> return 0;
>
> +err_hw:
> + etm4_clean_event_config(csdev, event);
> err:
> /* Failed to start tracer; roll back to DISABLED mode */
> coresight_set_mode(csdev, CS_MODE_DISABLED);
--
Sincerely,
Yeoreum Yun
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [PATCH v7 09/13] coresight: etm4x: missing cscfg_csdev_disable_active_config() in perf enable
2026-05-28 16:01 ` Yeoreum Yun
@ 2026-06-01 16:11 ` Suzuki K Poulose
2026-06-01 16:41 ` Yeoreum Yun
0 siblings, 1 reply; 39+ messages in thread
From: Suzuki K Poulose @ 2026-06-01 16:11 UTC (permalink / raw)
To: Yeoreum Yun, Leo Yan
Cc: coresight, linux-arm-kernel, linux-kernel, mike.leach,
james.clark, alexander.shishkin, jie.gan
On 28/05/2026 17:01, Yeoreum Yun wrote:
>> On Thu, May 28, 2026 at 03:43:40PM +0100, Yeoreum Yun wrote:
>>
>> [...]
>>
>>>> @@ -931,6 +919,18 @@ static int etm4_enable_perf(struct coresight_device *csdev,
>>>> if (ret)
>>>> goto err;
>>>>
>>>> + /*
>>>> + * Set any selected configuration and preset. A zero configid means no
>>>> + * configuration active, preset = 0 means no preset selected.
>>>> + */
>>>> + cfg_hash = ATTR_CFG_GET_FLD(attr, configid);
>>>> + if (cfg_hash) {
>>>> + preset = ATTR_CFG_GET_FLD(attr, preset);
>>>> + ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset);
>>>> + if (ret)
>>>> + goto err;
>>>> + }
>>>> +
>>
>>> No. since preset overrides the "perf configuratoin" formerly but
>>> this code makes it vice versa.
>>
>> The above proposed change applies cfgfs after calling
>> etm4_parse_event_config(). This is just use preset to override the
>> config. Do I miss anything?
>
> Ah sorry. I've misread the code location that was my bad.
>
>>
>>> Also, cfg_hash and prest is also part of
>>> etm4_parse_event_config(), and it doesn't seem to good to separate
>>> cfgfs handling from that function.
>>>
>>> IMHO, It would be better to keep this as it is.
>>
>> I have another version to give a try. I'd leave to you and maintainers
>> to choose which is better.
>
> Funcionally, Code works. However, To be honest, the pairing between
> etm4_parse_event_config() and etm4_clean_event_config() feels a bit artificial to me.
>
> So here I have simply followed the principle that,
> if etm4_parse_event_config() fails, the configuration it touched should be
> cleaned up within that function; and if a failure happens after
> etm4_parse_event_config() has succeeded, the caller should perform the cleanup.
>
> Renaming etm4_parse_event_config() and splitting out the
> CSCFG-related handling as suggested would be possible,
> although I still feel it may not be strictly necessary.
>
> My preference would be to keep this as-is, but Suzuki, what do you think?
I prefer the end result with Leo's patch applied. That kind of indicates
clearly that we need to cleanup something from the event config parsing
and keeps the disabling only once, rather than spreading it.
Cheers
Suzuki
>
>>
>> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
>> index 0889937811cb..471824234800 100644
>> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
>> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
>> @@ -882,16 +882,6 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
>> /* bit[12], Return stack enable bit */
>> config->cfg |= TRCCONFIGR_RS;
>>
>> - /*
>> - * Set any selected configuration and preset. A zero configid means no
>> - * configuration active, preset = 0 means no preset selected.
>> - */
>> - cfg_hash = ATTR_CFG_GET_FLD(attr, configid);
>> - if (cfg_hash) {
>> - preset = ATTR_CFG_GET_FLD(attr, preset);
>> - ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset);
>> - }
>> -
>> /* branch broadcast - enable if selected and supported */
>> if (ATTR_CFG_GET_FLD(attr, branch_broadcast)) {
>> if (!caps->trcbb) {
>> @@ -899,8 +889,6 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
>> * Missing BB support could cause silent decode errors
>> * so fail to open if it's not supported.
>> */
>> - if (cfg_hash)
>> - cscfg_csdev_disable_active_config(csdev);
>> ret = -EINVAL;
>> goto out;
>> } else {
>> @@ -908,10 +896,31 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
>> }
>> }
>>
>> + /*
>> + * Set any selected configuration and preset. A zero configid means no
>> + * configuration active, preset = 0 means no preset selected.
>> + */
>> + cfg_hash = ATTR_CFG_GET_FLD(attr, configid);
>> + if (cfg_hash) {
>> + preset = ATTR_CFG_GET_FLD(attr, preset);
>> + ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset);
>> + }
>> +
>> out:
>> return ret;
>> }
>>
>> +static void etm4_clean_event_config(struct coresight_device *csdev,
>> + struct perf_event *event)
>> +{
>> + struct perf_event_attr *attr = &event->attr;
>> + unsigned long cfg_hash;
>> +
>> + cfg_hash = ATTR_CFG_GET_FLD(attr, configid);
>> + if (cfg_hash)
>> + cscfg_csdev_disable_active_config(csdev);
>> +}
>> +
>> static int etm4_enable_perf(struct coresight_device *csdev,
>> struct perf_event *event,
>> struct coresight_path *path)
>> @@ -938,15 +947,14 @@ static int etm4_enable_perf(struct coresight_device *csdev,
>>
>> /* And enable it */
>> ret = etm4_enable_hw(drvdata);
>> - if (ret) {
>> - if (ATTR_CFG_GET_FLD(attr, configid))
>> - cscfg_csdev_disable_active_config(csdev);
>> - goto err;
>> - }
>> + if (ret)
>> + goto err_hw;
>>
>> csdev->path = path;
>> return 0;
>>
>> +err_hw:
>> + etm4_clean_event_config(csdev, event);
>> err:
>> /* Failed to start tracer; roll back to DISABLED mode */
>> coresight_set_mode(csdev, CS_MODE_DISABLED);
>
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [PATCH v7 09/13] coresight: etm4x: missing cscfg_csdev_disable_active_config() in perf enable
2026-06-01 16:11 ` Suzuki K Poulose
@ 2026-06-01 16:41 ` Yeoreum Yun
0 siblings, 0 replies; 39+ messages in thread
From: Yeoreum Yun @ 2026-06-01 16:41 UTC (permalink / raw)
To: Suzuki K Poulose
Cc: Leo Yan, coresight, linux-arm-kernel, linux-kernel, mike.leach,
james.clark, alexander.shishkin, jie.gan
> On 28/05/2026 17:01, Yeoreum Yun wrote:
> > > On Thu, May 28, 2026 at 03:43:40PM +0100, Yeoreum Yun wrote:
> > >
> > > [...]
> > >
> > > > > @@ -931,6 +919,18 @@ static int etm4_enable_perf(struct coresight_device *csdev,
> > > > > if (ret)
> > > > > goto err;
> > > > > + /*
> > > > > + * Set any selected configuration and preset. A zero configid means no
> > > > > + * configuration active, preset = 0 means no preset selected.
> > > > > + */
> > > > > + cfg_hash = ATTR_CFG_GET_FLD(attr, configid);
> > > > > + if (cfg_hash) {
> > > > > + preset = ATTR_CFG_GET_FLD(attr, preset);
> > > > > + ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset);
> > > > > + if (ret)
> > > > > + goto err;
> > > > > + }
> > > > > +
> > >
> > > > No. since preset overrides the "perf configuratoin" formerly but
> > > > this code makes it vice versa.
> > >
> > > The above proposed change applies cfgfs after calling
> > > etm4_parse_event_config(). This is just use preset to override the
> > > config. Do I miss anything?
> >
> > Ah sorry. I've misread the code location that was my bad.
> >
> > >
> > > > Also, cfg_hash and prest is also part of
> > > > etm4_parse_event_config(), and it doesn't seem to good to separate
> > > > cfgfs handling from that function.
> > > >
> > > > IMHO, It would be better to keep this as it is.
> > >
> > > I have another version to give a try. I'd leave to you and maintainers
> > > to choose which is better.
> >
> > Funcionally, Code works. However, To be honest, the pairing between
> > etm4_parse_event_config() and etm4_clean_event_config() feels a bit artificial to me.
> >
> > So here I have simply followed the principle that,
> > if etm4_parse_event_config() fails, the configuration it touched should be
> > cleaned up within that function; and if a failure happens after
> > etm4_parse_event_config() has succeeded, the caller should perform the cleanup.
> >
> > Renaming etm4_parse_event_config() and splitting out the
> > CSCFG-related handling as suggested would be possible,
> > although I still feel it may not be strictly necessary.
> >
> > My preference would be to keep this as-is, but Suzuki, what do you think?
>
> I prefer the end result with Leo's patch applied. That kind of indicates
> clearly that we need to cleanup something from the event config parsing
> and keeps the disabling only once, rather than spreading it.
>
Okay. Then I'll apply with a little bit of modification.
Thanks
--
Sincerely,
Yeoreum Yun
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v7 10/13] coresight: etm3x: change drvdata->spinlock type to raw_spin_lock_t
2026-05-19 15:47 [PATCH v7 00/13] fix several inconsistencies with sysfs configuration in etmX Yeoreum Yun
` (8 preceding siblings ...)
2026-05-19 15:48 ` [PATCH v7 09/13] coresight: etm4x: missing cscfg_csdev_disable_active_config() in perf enable Yeoreum Yun
@ 2026-05-19 15:48 ` Yeoreum Yun
2026-05-19 15:48 ` [PATCH v7 11/13] coresight: etm3x: introduce struct etm_caps Yeoreum Yun
` (2 subsequent siblings)
12 siblings, 0 replies; 39+ messages in thread
From: Yeoreum Yun @ 2026-05-19 15:48 UTC (permalink / raw)
To: coresight, linux-arm-kernel, linux-kernel
Cc: suzuki.poulose, mike.leach, james.clark, alexander.shishkin,
leo.yan, jie.gan, Yeoreum Yun
etm_starting_cpu()/etm_dying_cpu() are called in not sleepable context.
This poses an issue in PREEMPT_RT kernel where spinlock_t is sleepable.
To address this, change etm3's drvdata->spinlock type to raw_spin_lock_t.
This will be good to align with etm4x.
Reviewed-by: Jie Gan <jie.gan@oss.qualcomm.com>
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
---
drivers/hwtracing/coresight/coresight-etm.h | 2 +-
.../coresight/coresight-etm3x-core.c | 10 +-
.../coresight/coresight-etm3x-sysfs.c | 130 +++++++++---------
3 files changed, 71 insertions(+), 71 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm.h b/drivers/hwtracing/coresight/coresight-etm.h
index 1d753cca2943..40f20daded4f 100644
--- a/drivers/hwtracing/coresight/coresight-etm.h
+++ b/drivers/hwtracing/coresight/coresight-etm.h
@@ -232,7 +232,7 @@ struct etm_drvdata {
struct csdev_access csa;
struct clk *atclk;
struct coresight_device *csdev;
- spinlock_t spinlock;
+ raw_spinlock_t spinlock;
int cpu;
int port_size;
u8 arch;
diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/hwtracing/coresight/coresight-etm3x-core.c
index 862ad0786699..60fdd87fb25d 100644
--- a/drivers/hwtracing/coresight/coresight-etm3x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c
@@ -512,7 +512,7 @@ static int etm_enable_sysfs(struct coresight_device *csdev, struct coresight_pat
struct etm_enable_arg arg = { };
int ret;
- spin_lock(&drvdata->spinlock);
+ raw_spin_lock(&drvdata->spinlock);
drvdata->traceid = path->trace_id;
@@ -536,7 +536,7 @@ static int etm_enable_sysfs(struct coresight_device *csdev, struct coresight_pat
if (ret)
etm_release_trace_id(drvdata);
- spin_unlock(&drvdata->spinlock);
+ raw_spin_unlock(&drvdata->spinlock);
if (!ret)
dev_dbg(&csdev->dev, "ETM tracing enabled\n");
@@ -631,7 +631,7 @@ static void etm_disable_sysfs(struct coresight_device *csdev)
{
struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
- spin_lock(&drvdata->spinlock);
+ raw_spin_lock(&drvdata->spinlock);
/*
* Executing etm_disable_hw on the cpu whose ETM is being disabled
@@ -640,7 +640,7 @@ static void etm_disable_sysfs(struct coresight_device *csdev)
smp_call_function_single(drvdata->cpu, etm_disable_sysfs_smp_call,
drvdata, 1);
- spin_unlock(&drvdata->spinlock);
+ raw_spin_unlock(&drvdata->spinlock);
/*
* we only release trace IDs when resetting sysfs.
@@ -811,7 +811,7 @@ static int etm_probe(struct amba_device *adev, const struct amba_id *id)
desc.access = drvdata->csa = CSDEV_ACCESS_IOMEM(base);
- spin_lock_init(&drvdata->spinlock);
+ raw_spin_lock_init(&drvdata->spinlock);
drvdata->atclk = devm_clk_get_optional_enabled(dev, "atclk");
if (IS_ERR(drvdata->atclk))
diff --git a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c
index 762109307b86..42b12c33516b 100644
--- a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c
+++ b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c
@@ -49,13 +49,13 @@ static ssize_t etmsr_show(struct device *dev,
struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
pm_runtime_get_sync(dev->parent);
- spin_lock_irqsave(&drvdata->spinlock, flags);
+ raw_spin_lock_irqsave(&drvdata->spinlock, flags);
CS_UNLOCK(drvdata->csa.base);
val = etm_readl(drvdata, ETMSR);
CS_LOCK(drvdata->csa.base);
- spin_unlock_irqrestore(&drvdata->spinlock, flags);
+ raw_spin_unlock_irqrestore(&drvdata->spinlock, flags);
pm_runtime_put(dev->parent);
return sprintf(buf, "%#lx\n", val);
@@ -76,7 +76,7 @@ static ssize_t reset_store(struct device *dev,
return ret;
if (val) {
- spin_lock(&drvdata->spinlock);
+ raw_spin_lock(&drvdata->spinlock);
memset(config, 0, sizeof(struct etm_config));
config->mode = ETM_MODE_EXCLUDE;
config->trigger_event = ETM_DEFAULT_EVENT_VAL;
@@ -86,7 +86,7 @@ static ssize_t reset_store(struct device *dev,
etm_set_default(config);
etm_release_trace_id(drvdata);
- spin_unlock(&drvdata->spinlock);
+ raw_spin_unlock(&drvdata->spinlock);
}
return size;
@@ -117,7 +117,7 @@ static ssize_t mode_store(struct device *dev,
if (ret)
return ret;
- spin_lock(&drvdata->spinlock);
+ raw_spin_lock(&drvdata->spinlock);
config->mode = val & ETM_MODE_ALL;
if (config->mode & ETM_MODE_EXCLUDE)
@@ -168,12 +168,12 @@ static ssize_t mode_store(struct device *dev,
if (config->mode & (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER))
etm_config_trace_mode(config);
- spin_unlock(&drvdata->spinlock);
+ raw_spin_unlock(&drvdata->spinlock);
return size;
err_unlock:
- spin_unlock(&drvdata->spinlock);
+ raw_spin_unlock(&drvdata->spinlock);
return ret;
}
static DEVICE_ATTR_RW(mode);
@@ -299,9 +299,9 @@ static ssize_t addr_idx_store(struct device *dev,
* Use spinlock to ensure index doesn't change while it gets
* dereferenced multiple times within a spinlock block elsewhere.
*/
- spin_lock(&drvdata->spinlock);
+ raw_spin_lock(&drvdata->spinlock);
config->addr_idx = val;
- spin_unlock(&drvdata->spinlock);
+ raw_spin_unlock(&drvdata->spinlock);
return size;
}
@@ -315,16 +315,16 @@ static ssize_t addr_single_show(struct device *dev,
struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
struct etm_config *config = &drvdata->config;
- spin_lock(&drvdata->spinlock);
+ raw_spin_lock(&drvdata->spinlock);
idx = config->addr_idx;
if (!(config->addr_type[idx] == ETM_ADDR_TYPE_NONE ||
config->addr_type[idx] == ETM_ADDR_TYPE_SINGLE)) {
- spin_unlock(&drvdata->spinlock);
+ raw_spin_unlock(&drvdata->spinlock);
return -EINVAL;
}
val = config->addr_val[idx];
- spin_unlock(&drvdata->spinlock);
+ raw_spin_unlock(&drvdata->spinlock);
return sprintf(buf, "%#lx\n", val);
}
@@ -343,17 +343,17 @@ static ssize_t addr_single_store(struct device *dev,
if (ret)
return ret;
- spin_lock(&drvdata->spinlock);
+ raw_spin_lock(&drvdata->spinlock);
idx = config->addr_idx;
if (!(config->addr_type[idx] == ETM_ADDR_TYPE_NONE ||
config->addr_type[idx] == ETM_ADDR_TYPE_SINGLE)) {
- spin_unlock(&drvdata->spinlock);
+ raw_spin_unlock(&drvdata->spinlock);
return -EINVAL;
}
config->addr_val[idx] = val;
config->addr_type[idx] = ETM_ADDR_TYPE_SINGLE;
- spin_unlock(&drvdata->spinlock);
+ raw_spin_unlock(&drvdata->spinlock);
return size;
}
@@ -367,23 +367,23 @@ static ssize_t addr_range_show(struct device *dev,
struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
struct etm_config *config = &drvdata->config;
- spin_lock(&drvdata->spinlock);
+ raw_spin_lock(&drvdata->spinlock);
idx = config->addr_idx;
if (idx % 2 != 0) {
- spin_unlock(&drvdata->spinlock);
+ raw_spin_unlock(&drvdata->spinlock);
return -EPERM;
}
if (!((config->addr_type[idx] == ETM_ADDR_TYPE_NONE &&
config->addr_type[idx + 1] == ETM_ADDR_TYPE_NONE) ||
(config->addr_type[idx] == ETM_ADDR_TYPE_RANGE &&
config->addr_type[idx + 1] == ETM_ADDR_TYPE_RANGE))) {
- spin_unlock(&drvdata->spinlock);
+ raw_spin_unlock(&drvdata->spinlock);
return -EPERM;
}
val1 = config->addr_val[idx];
val2 = config->addr_val[idx + 1];
- spin_unlock(&drvdata->spinlock);
+ raw_spin_unlock(&drvdata->spinlock);
return sprintf(buf, "%#lx %#lx\n", val1, val2);
}
@@ -403,17 +403,17 @@ static ssize_t addr_range_store(struct device *dev,
if (val1 > val2)
return -EINVAL;
- spin_lock(&drvdata->spinlock);
+ raw_spin_lock(&drvdata->spinlock);
idx = config->addr_idx;
if (idx % 2 != 0) {
- spin_unlock(&drvdata->spinlock);
+ raw_spin_unlock(&drvdata->spinlock);
return -EPERM;
}
if (!((config->addr_type[idx] == ETM_ADDR_TYPE_NONE &&
config->addr_type[idx + 1] == ETM_ADDR_TYPE_NONE) ||
(config->addr_type[idx] == ETM_ADDR_TYPE_RANGE &&
config->addr_type[idx + 1] == ETM_ADDR_TYPE_RANGE))) {
- spin_unlock(&drvdata->spinlock);
+ raw_spin_unlock(&drvdata->spinlock);
return -EPERM;
}
@@ -422,7 +422,7 @@ static ssize_t addr_range_store(struct device *dev,
config->addr_val[idx + 1] = val2;
config->addr_type[idx + 1] = ETM_ADDR_TYPE_RANGE;
config->enable_ctrl1 |= (1 << (idx/2));
- spin_unlock(&drvdata->spinlock);
+ raw_spin_unlock(&drvdata->spinlock);
return size;
}
@@ -436,16 +436,16 @@ static ssize_t addr_start_show(struct device *dev,
struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
struct etm_config *config = &drvdata->config;
- spin_lock(&drvdata->spinlock);
+ raw_spin_lock(&drvdata->spinlock);
idx = config->addr_idx;
if (!(config->addr_type[idx] == ETM_ADDR_TYPE_NONE ||
config->addr_type[idx] == ETM_ADDR_TYPE_START)) {
- spin_unlock(&drvdata->spinlock);
+ raw_spin_unlock(&drvdata->spinlock);
return -EPERM;
}
val = config->addr_val[idx];
- spin_unlock(&drvdata->spinlock);
+ raw_spin_unlock(&drvdata->spinlock);
return sprintf(buf, "%#lx\n", val);
}
@@ -464,11 +464,11 @@ static ssize_t addr_start_store(struct device *dev,
if (ret)
return ret;
- spin_lock(&drvdata->spinlock);
+ raw_spin_lock(&drvdata->spinlock);
idx = config->addr_idx;
if (!(config->addr_type[idx] == ETM_ADDR_TYPE_NONE ||
config->addr_type[idx] == ETM_ADDR_TYPE_START)) {
- spin_unlock(&drvdata->spinlock);
+ raw_spin_unlock(&drvdata->spinlock);
return -EPERM;
}
@@ -476,7 +476,7 @@ static ssize_t addr_start_store(struct device *dev,
config->addr_type[idx] = ETM_ADDR_TYPE_START;
config->startstop_ctrl |= (1 << idx);
config->enable_ctrl1 |= ETMTECR1_START_STOP;
- spin_unlock(&drvdata->spinlock);
+ raw_spin_unlock(&drvdata->spinlock);
return size;
}
@@ -490,16 +490,16 @@ static ssize_t addr_stop_show(struct device *dev,
struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
struct etm_config *config = &drvdata->config;
- spin_lock(&drvdata->spinlock);
+ raw_spin_lock(&drvdata->spinlock);
idx = config->addr_idx;
if (!(config->addr_type[idx] == ETM_ADDR_TYPE_NONE ||
config->addr_type[idx] == ETM_ADDR_TYPE_STOP)) {
- spin_unlock(&drvdata->spinlock);
+ raw_spin_unlock(&drvdata->spinlock);
return -EPERM;
}
val = config->addr_val[idx];
- spin_unlock(&drvdata->spinlock);
+ raw_spin_unlock(&drvdata->spinlock);
return sprintf(buf, "%#lx\n", val);
}
@@ -518,11 +518,11 @@ static ssize_t addr_stop_store(struct device *dev,
if (ret)
return ret;
- spin_lock(&drvdata->spinlock);
+ raw_spin_lock(&drvdata->spinlock);
idx = config->addr_idx;
if (!(config->addr_type[idx] == ETM_ADDR_TYPE_NONE ||
config->addr_type[idx] == ETM_ADDR_TYPE_STOP)) {
- spin_unlock(&drvdata->spinlock);
+ raw_spin_unlock(&drvdata->spinlock);
return -EPERM;
}
@@ -530,7 +530,7 @@ static ssize_t addr_stop_store(struct device *dev,
config->addr_type[idx] = ETM_ADDR_TYPE_STOP;
config->startstop_ctrl |= (1 << (idx + 16));
config->enable_ctrl1 |= ETMTECR1_START_STOP;
- spin_unlock(&drvdata->spinlock);
+ raw_spin_unlock(&drvdata->spinlock);
return size;
}
@@ -543,9 +543,9 @@ static ssize_t addr_acctype_show(struct device *dev,
struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
struct etm_config *config = &drvdata->config;
- spin_lock(&drvdata->spinlock);
+ raw_spin_lock(&drvdata->spinlock);
val = config->addr_acctype[config->addr_idx];
- spin_unlock(&drvdata->spinlock);
+ raw_spin_unlock(&drvdata->spinlock);
return sprintf(buf, "%#lx\n", val);
}
@@ -563,9 +563,9 @@ static ssize_t addr_acctype_store(struct device *dev,
if (ret)
return ret;
- spin_lock(&drvdata->spinlock);
+ raw_spin_lock(&drvdata->spinlock);
config->addr_acctype[config->addr_idx] = val;
- spin_unlock(&drvdata->spinlock);
+ raw_spin_unlock(&drvdata->spinlock);
return size;
}
@@ -601,9 +601,9 @@ static ssize_t cntr_idx_store(struct device *dev,
* Use spinlock to ensure index doesn't change while it gets
* dereferenced multiple times within a spinlock block elsewhere.
*/
- spin_lock(&drvdata->spinlock);
+ raw_spin_lock(&drvdata->spinlock);
config->cntr_idx = val;
- spin_unlock(&drvdata->spinlock);
+ raw_spin_unlock(&drvdata->spinlock);
return size;
}
@@ -616,9 +616,9 @@ static ssize_t cntr_rld_val_show(struct device *dev,
struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
struct etm_config *config = &drvdata->config;
- spin_lock(&drvdata->spinlock);
+ raw_spin_lock(&drvdata->spinlock);
val = config->cntr_rld_val[config->cntr_idx];
- spin_unlock(&drvdata->spinlock);
+ raw_spin_unlock(&drvdata->spinlock);
return sprintf(buf, "%#lx\n", val);
}
@@ -636,9 +636,9 @@ static ssize_t cntr_rld_val_store(struct device *dev,
if (ret)
return ret;
- spin_lock(&drvdata->spinlock);
+ raw_spin_lock(&drvdata->spinlock);
config->cntr_rld_val[config->cntr_idx] = val;
- spin_unlock(&drvdata->spinlock);
+ raw_spin_unlock(&drvdata->spinlock);
return size;
}
@@ -651,9 +651,9 @@ static ssize_t cntr_event_show(struct device *dev,
struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
struct etm_config *config = &drvdata->config;
- spin_lock(&drvdata->spinlock);
+ raw_spin_lock(&drvdata->spinlock);
val = config->cntr_event[config->cntr_idx];
- spin_unlock(&drvdata->spinlock);
+ raw_spin_unlock(&drvdata->spinlock);
return sprintf(buf, "%#lx\n", val);
}
@@ -671,9 +671,9 @@ static ssize_t cntr_event_store(struct device *dev,
if (ret)
return ret;
- spin_lock(&drvdata->spinlock);
+ raw_spin_lock(&drvdata->spinlock);
config->cntr_event[config->cntr_idx] = val & ETM_EVENT_MASK;
- spin_unlock(&drvdata->spinlock);
+ raw_spin_unlock(&drvdata->spinlock);
return size;
}
@@ -686,9 +686,9 @@ static ssize_t cntr_rld_event_show(struct device *dev,
struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
struct etm_config *config = &drvdata->config;
- spin_lock(&drvdata->spinlock);
+ raw_spin_lock(&drvdata->spinlock);
val = config->cntr_rld_event[config->cntr_idx];
- spin_unlock(&drvdata->spinlock);
+ raw_spin_unlock(&drvdata->spinlock);
return sprintf(buf, "%#lx\n", val);
}
@@ -706,9 +706,9 @@ static ssize_t cntr_rld_event_store(struct device *dev,
if (ret)
return ret;
- spin_lock(&drvdata->spinlock);
+ raw_spin_lock(&drvdata->spinlock);
config->cntr_rld_event[config->cntr_idx] = val & ETM_EVENT_MASK;
- spin_unlock(&drvdata->spinlock);
+ raw_spin_unlock(&drvdata->spinlock);
return size;
}
@@ -723,11 +723,11 @@ static ssize_t cntr_val_show(struct device *dev,
struct etm_config *config = &drvdata->config;
if (!coresight_get_mode(drvdata->csdev)) {
- spin_lock(&drvdata->spinlock);
+ raw_spin_lock(&drvdata->spinlock);
for (i = 0; i < drvdata->nr_cntr; i++)
ret += sprintf(buf, "counter %d: %x\n",
i, config->cntr_val[i]);
- spin_unlock(&drvdata->spinlock);
+ raw_spin_unlock(&drvdata->spinlock);
return ret;
}
@@ -752,9 +752,9 @@ static ssize_t cntr_val_store(struct device *dev,
if (ret)
return ret;
- spin_lock(&drvdata->spinlock);
+ raw_spin_lock(&drvdata->spinlock);
config->cntr_val[config->cntr_idx] = val;
- spin_unlock(&drvdata->spinlock);
+ raw_spin_unlock(&drvdata->spinlock);
return size;
}
@@ -947,13 +947,13 @@ static ssize_t seq_curr_state_show(struct device *dev,
}
pm_runtime_get_sync(dev->parent);
- spin_lock_irqsave(&drvdata->spinlock, flags);
+ raw_spin_lock_irqsave(&drvdata->spinlock, flags);
CS_UNLOCK(drvdata->csa.base);
val = (etm_readl(drvdata, ETMSQR) & ETM_SQR_MASK);
CS_LOCK(drvdata->csa.base);
- spin_unlock_irqrestore(&drvdata->spinlock, flags);
+ raw_spin_unlock_irqrestore(&drvdata->spinlock, flags);
pm_runtime_put(dev->parent);
out:
return sprintf(buf, "%#lx\n", val);
@@ -1012,9 +1012,9 @@ static ssize_t ctxid_idx_store(struct device *dev,
* Use spinlock to ensure index doesn't change while it gets
* dereferenced multiple times within a spinlock block elsewhere.
*/
- spin_lock(&drvdata->spinlock);
+ raw_spin_lock(&drvdata->spinlock);
config->ctxid_idx = val;
- spin_unlock(&drvdata->spinlock);
+ raw_spin_unlock(&drvdata->spinlock);
return size;
}
@@ -1034,9 +1034,9 @@ static ssize_t ctxid_pid_show(struct device *dev,
if (task_active_pid_ns(current) != &init_pid_ns)
return -EINVAL;
- spin_lock(&drvdata->spinlock);
+ raw_spin_lock(&drvdata->spinlock);
val = config->ctxid_pid[config->ctxid_idx];
- spin_unlock(&drvdata->spinlock);
+ raw_spin_unlock(&drvdata->spinlock);
return sprintf(buf, "%#lx\n", val);
}
@@ -1066,9 +1066,9 @@ static ssize_t ctxid_pid_store(struct device *dev,
if (ret)
return ret;
- spin_lock(&drvdata->spinlock);
+ raw_spin_lock(&drvdata->spinlock);
config->ctxid_pid[config->ctxid_idx] = pid;
- spin_unlock(&drvdata->spinlock);
+ raw_spin_unlock(&drvdata->spinlock);
return size;
}
--
LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7}
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PATCH v7 11/13] coresight: etm3x: introduce struct etm_caps
2026-05-19 15:47 [PATCH v7 00/13] fix several inconsistencies with sysfs configuration in etmX Yeoreum Yun
` (9 preceding siblings ...)
2026-05-19 15:48 ` [PATCH v7 10/13] coresight: etm3x: change drvdata->spinlock type to raw_spin_lock_t Yeoreum Yun
@ 2026-05-19 15:48 ` Yeoreum Yun
2026-05-19 15:48 ` [PATCH v7 12/13] coresight: etm3x: fix inconsistencies with sysfs configuration Yeoreum Yun
2026-05-19 15:48 ` [PATCH v7 13/13] coresight: etm3x: remove redundant cpu online check on etm_enable_sysfs() Yeoreum Yun
12 siblings, 0 replies; 39+ messages in thread
From: Yeoreum Yun @ 2026-05-19 15:48 UTC (permalink / raw)
To: coresight, linux-arm-kernel, linux-kernel
Cc: suzuki.poulose, mike.leach, james.clark, alexander.shishkin,
leo.yan, jie.gan, Yeoreum Yun
Introduce struct etm_caps to describe ETMv3 capabilities
and move capabilities information into it.
Since drvdata->etmccr and drvdata->etmccer are used to check
whether it supports fifofull logic and timestamping,
remove etmccr and etmccer field from drvdata and add relevant fields
in etm_caps structure.
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
---
drivers/hwtracing/coresight/coresight-etm.h | 42 ++++++++++++-------
.../coresight/coresight-etm3x-core.c | 39 ++++++++++-------
.../coresight/coresight-etm3x-sysfs.c | 29 ++++++++-----
3 files changed, 67 insertions(+), 43 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm.h b/drivers/hwtracing/coresight/coresight-etm.h
index 40f20daded4f..932bec82fb47 100644
--- a/drivers/hwtracing/coresight/coresight-etm.h
+++ b/drivers/hwtracing/coresight/coresight-etm.h
@@ -140,6 +140,30 @@
ETM_ADD_COMP_0 | \
ETM_EVENT_NOT_A)
+/**
+ * struct etm_caps - specifics ETM capabilities
+ * @port_size: port size as reported by ETMCR bit 4-6 and 21.
+ * @nr_addr_cmp:Number of pairs of address comparators as found in ETMCCR.
+ * @nr_cntr: Number of counters as found in ETMCCR bit 13-15.
+ * @nr_ext_inp: Number of external input as found in ETMCCR bit 17-19.
+ * @nr_ext_out: Number of external output as found in ETMCCR bit 20-22.
+ * @nr_ctxid_cmp: Number of contextID comparators as found in ETMCCR bit 24-25.
+ * @fifofull: FIFOFULL logic is present.
+ * @timestamp: Timestamping is implemented.
+ * @retstack: Return stack is implemented.
+ */
+struct etm_caps {
+ int port_size;
+ u8 nr_addr_cmp;
+ u8 nr_cntr;
+ u8 nr_ext_inp;
+ u8 nr_ext_out;
+ u8 nr_ctxid_cmp;
+ bool fifofull : 1;
+ bool timestamp : 1;
+ bool retstack : 1;
+};
+
/**
* struct etm_config - configuration information related to an ETM
* @mode: controls various modes supported by this ETM/PTM.
@@ -212,19 +236,12 @@ struct etm_config {
* @csdev: component vitals needed by the framework.
* @spinlock: only one at a time pls.
* @cpu: the cpu this component is affined to.
- * @port_size: port size as reported by ETMCR bit 4-6 and 21.
* @arch: ETM/PTM version number.
+ * @caps: ETM capabilities.
* @use_cpu14: true if management registers need to be accessed via CP14.
* @sticky_enable: true if ETM base configuration has been done.
* @boot_enable:true if we should start tracing at boot time.
* @os_unlock: true if access to management registers is allowed.
- * @nr_addr_cmp:Number of pairs of address comparators as found in ETMCCR.
- * @nr_cntr: Number of counters as found in ETMCCR bit 13-15.
- * @nr_ext_inp: Number of external input as found in ETMCCR bit 17-19.
- * @nr_ext_out: Number of external output as found in ETMCCR bit 20-22.
- * @nr_ctxid_cmp: Number of contextID comparators as found in ETMCCR bit 24-25.
- * @etmccr: value of register ETMCCR.
- * @etmccer: value of register ETMCCER.
* @traceid: value of the current ID for this component.
* @config: structure holding configuration parameters.
*/
@@ -234,19 +251,12 @@ struct etm_drvdata {
struct coresight_device *csdev;
raw_spinlock_t spinlock;
int cpu;
- int port_size;
u8 arch;
+ struct etm_caps caps;
bool use_cp14;
bool sticky_enable;
bool boot_enable;
bool os_unlock;
- u8 nr_addr_cmp;
- u8 nr_cntr;
- u8 nr_ext_inp;
- u8 nr_ext_out;
- u8 nr_ctxid_cmp;
- u32 etmccr;
- u32 etmccer;
u32 traceid;
struct etm_config config;
};
diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/hwtracing/coresight/coresight-etm3x-core.c
index 60fdd87fb25d..ccfde9eda537 100644
--- a/drivers/hwtracing/coresight/coresight-etm3x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c
@@ -308,6 +308,7 @@ void etm_config_trace_mode(struct etm_config *config)
static int etm_parse_event_config(struct etm_drvdata *drvdata,
struct perf_event *event)
{
+ const struct etm_caps *caps = &drvdata->caps;
struct etm_config *config = &drvdata->config;
struct perf_event_attr *attr = &event->attr;
u8 ts_level;
@@ -356,8 +357,7 @@ static int etm_parse_event_config(struct etm_drvdata *drvdata,
* has ret stack) on the same SoC. So only enable when it can be honored
* - trace will still continue normally otherwise.
*/
- if (ATTR_CFG_GET_FLD(attr, retstack) &&
- (drvdata->etmccer & ETMCCER_RETSTACK))
+ if (ATTR_CFG_GET_FLD(attr, retstack) && (caps->retstack))
config->ctrl |= ETMCR_RETURN_STACK;
return 0;
@@ -367,6 +367,7 @@ static int etm_enable_hw(struct etm_drvdata *drvdata)
{
int i, rc;
u32 etmcr;
+ const struct etm_caps *caps = &drvdata->caps;
struct etm_config *config = &drvdata->config;
struct coresight_device *csdev = drvdata->csdev;
@@ -388,7 +389,7 @@ static int etm_enable_hw(struct etm_drvdata *drvdata)
etmcr = etm_readl(drvdata, ETMCR);
/* Clear setting from a previous run if need be */
etmcr &= ~ETM3X_SUPPORTED_OPTIONS;
- etmcr |= drvdata->port_size;
+ etmcr |= caps->port_size;
etmcr |= ETMCR_ETM_EN;
etm_writel(drvdata, config->ctrl | etmcr, ETMCR);
etm_writel(drvdata, config->trigger_event, ETMTRIGGER);
@@ -396,11 +397,11 @@ static int etm_enable_hw(struct etm_drvdata *drvdata)
etm_writel(drvdata, config->enable_event, ETMTEEVR);
etm_writel(drvdata, config->enable_ctrl1, ETMTECR1);
etm_writel(drvdata, config->fifofull_level, ETMFFLR);
- for (i = 0; i < drvdata->nr_addr_cmp; i++) {
+ for (i = 0; i < caps->nr_addr_cmp; i++) {
etm_writel(drvdata, config->addr_val[i], ETMACVRn(i));
etm_writel(drvdata, config->addr_acctype[i], ETMACTRn(i));
}
- for (i = 0; i < drvdata->nr_cntr; i++) {
+ for (i = 0; i < caps->nr_cntr; i++) {
etm_writel(drvdata, config->cntr_rld_val[i], ETMCNTRLDVRn(i));
etm_writel(drvdata, config->cntr_event[i], ETMCNTENRn(i));
etm_writel(drvdata, config->cntr_rld_event[i],
@@ -414,9 +415,9 @@ static int etm_enable_hw(struct etm_drvdata *drvdata)
etm_writel(drvdata, config->seq_32_event, ETMSQ32EVR);
etm_writel(drvdata, config->seq_13_event, ETMSQ13EVR);
etm_writel(drvdata, config->seq_curr_state, ETMSQR);
- for (i = 0; i < drvdata->nr_ext_out; i++)
+ for (i = 0; i < caps->nr_ext_out; i++)
etm_writel(drvdata, ETM_DEFAULT_EVENT_VAL, ETMEXTOUTEVRn(i));
- for (i = 0; i < drvdata->nr_ctxid_cmp; i++)
+ for (i = 0; i < caps->nr_ctxid_cmp; i++)
etm_writel(drvdata, config->ctxid_pid[i], ETMCIDCVRn(i));
etm_writel(drvdata, config->ctxid_mask, ETMCIDCMR);
etm_writel(drvdata, config->sync_freq, ETMSYNCFR);
@@ -565,6 +566,7 @@ static int etm_enable(struct coresight_device *csdev, struct perf_event *event,
static void etm_disable_hw(struct etm_drvdata *drvdata)
{
int i;
+ const struct etm_caps *caps = &drvdata->caps;
struct etm_config *config = &drvdata->config;
struct coresight_device *csdev = drvdata->csdev;
@@ -574,7 +576,7 @@ static void etm_disable_hw(struct etm_drvdata *drvdata)
/* Read back sequencer and counters for post trace analysis */
config->seq_curr_state = (etm_readl(drvdata, ETMSQR) & ETM_SQR_MASK);
- for (i = 0; i < drvdata->nr_cntr; i++)
+ for (i = 0; i < caps->nr_cntr; i++)
config->cntr_val[i] = etm_readl(drvdata, ETMCNTVRn(i));
etm_set_pwrdwn(drvdata);
@@ -720,7 +722,9 @@ static void etm_init_arch_data(void *info)
{
u32 etmidr;
u32 etmccr;
+ u32 etmccer;
struct etm_drvdata *drvdata = info;
+ struct etm_caps *caps = &drvdata->caps;
/* Make sure all registers are accessible */
etm_os_unlock(drvdata);
@@ -745,16 +749,19 @@ static void etm_init_arch_data(void *info)
/* Find all capabilities */
etmidr = etm_readl(drvdata, ETMIDR);
drvdata->arch = BMVAL(etmidr, 4, 11);
- drvdata->port_size = etm_readl(drvdata, ETMCR) & PORT_SIZE_MASK;
+ caps->port_size = etm_readl(drvdata, ETMCR) & PORT_SIZE_MASK;
+
+ etmccer = etm_readl(drvdata, ETMCCER);
+ caps->timestamp = !!(etmccer & ETMCCER_TIMESTAMP);
+ caps->retstack = !!(etmccer & ETMCCER_RETSTACK);
- drvdata->etmccer = etm_readl(drvdata, ETMCCER);
etmccr = etm_readl(drvdata, ETMCCR);
- drvdata->etmccr = etmccr;
- drvdata->nr_addr_cmp = BMVAL(etmccr, 0, 3) * 2;
- drvdata->nr_cntr = BMVAL(etmccr, 13, 15);
- drvdata->nr_ext_inp = BMVAL(etmccr, 17, 19);
- drvdata->nr_ext_out = BMVAL(etmccr, 20, 22);
- drvdata->nr_ctxid_cmp = BMVAL(etmccr, 24, 25);
+ caps->fifofull = !!(etmccr & ETMCCR_FIFOFULL);
+ caps->nr_addr_cmp = BMVAL(etmccr, 0, 3) * 2;
+ caps->nr_cntr = BMVAL(etmccr, 13, 15);
+ caps->nr_ext_inp = BMVAL(etmccr, 17, 19);
+ caps->nr_ext_out = BMVAL(etmccr, 20, 22);
+ caps->nr_ctxid_cmp = BMVAL(etmccr, 24, 25);
coresight_clear_self_claim_tag_unlocked(&drvdata->csa);
etm_set_pwrdwn(drvdata);
diff --git a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c
index 42b12c33516b..f7330d830e21 100644
--- a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c
+++ b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c
@@ -15,8 +15,9 @@ static ssize_t nr_addr_cmp_show(struct device *dev,
{
unsigned long val;
struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ const struct etm_caps *caps = &drvdata->caps;
- val = drvdata->nr_addr_cmp;
+ val = caps->nr_addr_cmp;
return sprintf(buf, "%#lx\n", val);
}
static DEVICE_ATTR_RO(nr_addr_cmp);
@@ -25,8 +26,9 @@ static ssize_t nr_cntr_show(struct device *dev,
struct device_attribute *attr, char *buf)
{ unsigned long val;
struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ const struct etm_caps *caps = &drvdata->caps;
- val = drvdata->nr_cntr;
+ val = caps->nr_cntr;
return sprintf(buf, "%#lx\n", val);
}
static DEVICE_ATTR_RO(nr_cntr);
@@ -37,7 +39,7 @@ static ssize_t nr_ctxid_cmp_show(struct device *dev,
unsigned long val;
struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
- val = drvdata->nr_ctxid_cmp;
+ val = drvdata->caps.nr_ctxid_cmp;
return sprintf(buf, "%#lx\n", val);
}
static DEVICE_ATTR_RO(nr_ctxid_cmp);
@@ -80,7 +82,7 @@ static ssize_t reset_store(struct device *dev,
memset(config, 0, sizeof(struct etm_config));
config->mode = ETM_MODE_EXCLUDE;
config->trigger_event = ETM_DEFAULT_EVENT_VAL;
- for (i = 0; i < drvdata->nr_addr_cmp; i++) {
+ for (i = 0; i < drvdata->caps.nr_addr_cmp; i++) {
config->addr_type[i] = ETM_ADDR_TYPE_NONE;
}
@@ -111,6 +113,7 @@ static ssize_t mode_store(struct device *dev,
int ret;
unsigned long val;
struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ const struct etm_caps *caps = &drvdata->caps;
struct etm_config *config = &drvdata->config;
ret = kstrtoul(buf, 16, &val);
@@ -131,7 +134,7 @@ static ssize_t mode_store(struct device *dev,
config->ctrl &= ~ETMCR_CYC_ACC;
if (config->mode & ETM_MODE_STALL) {
- if (!(drvdata->etmccr & ETMCCR_FIFOFULL)) {
+ if (!caps->fifofull) {
dev_warn(dev, "stall mode not supported\n");
ret = -EINVAL;
goto err_unlock;
@@ -141,7 +144,7 @@ static ssize_t mode_store(struct device *dev,
config->ctrl &= ~ETMCR_STALL_MODE;
if (config->mode & ETM_MODE_TIMESTAMP) {
- if (!(drvdata->etmccer & ETMCCER_TIMESTAMP)) {
+ if (!caps->timestamp) {
dev_warn(dev, "timestamp not supported\n");
ret = -EINVAL;
goto err_unlock;
@@ -286,13 +289,14 @@ static ssize_t addr_idx_store(struct device *dev,
int ret;
unsigned long val;
struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ const struct etm_caps *caps = &drvdata->caps;
struct etm_config *config = &drvdata->config;
ret = kstrtoul(buf, 16, &val);
if (ret)
return ret;
- if (val >= drvdata->nr_addr_cmp)
+ if (val >= caps->nr_addr_cmp)
return -EINVAL;
/*
@@ -589,13 +593,14 @@ static ssize_t cntr_idx_store(struct device *dev,
int ret;
unsigned long val;
struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ const struct etm_caps *caps = &drvdata->caps;
struct etm_config *config = &drvdata->config;
ret = kstrtoul(buf, 16, &val);
if (ret)
return ret;
- if (val >= drvdata->nr_cntr)
+ if (val >= caps->nr_cntr)
return -EINVAL;
/*
* Use spinlock to ensure index doesn't change while it gets
@@ -720,18 +725,19 @@ static ssize_t cntr_val_show(struct device *dev,
int i, ret = 0;
u32 val;
struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ const struct etm_caps *caps = &drvdata->caps;
struct etm_config *config = &drvdata->config;
if (!coresight_get_mode(drvdata->csdev)) {
raw_spin_lock(&drvdata->spinlock);
- for (i = 0; i < drvdata->nr_cntr; i++)
+ for (i = 0; i < caps->nr_cntr; i++)
ret += sprintf(buf, "counter %d: %x\n",
i, config->cntr_val[i]);
raw_spin_unlock(&drvdata->spinlock);
return ret;
}
- for (i = 0; i < drvdata->nr_cntr; i++) {
+ for (i = 0; i < caps->nr_cntr; i++) {
val = etm_readl(drvdata, ETMCNTVRn(i));
ret += sprintf(buf, "counter %d: %x\n", i, val);
}
@@ -999,13 +1005,14 @@ static ssize_t ctxid_idx_store(struct device *dev,
int ret;
unsigned long val;
struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ const struct etm_caps *caps = &drvdata->caps;
struct etm_config *config = &drvdata->config;
ret = kstrtoul(buf, 16, &val);
if (ret)
return ret;
- if (val >= drvdata->nr_ctxid_cmp)
+ if (val >= caps->nr_ctxid_cmp)
return -EINVAL;
/*
--
LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7}
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PATCH v7 12/13] coresight: etm3x: fix inconsistencies with sysfs configuration
2026-05-19 15:47 [PATCH v7 00/13] fix several inconsistencies with sysfs configuration in etmX Yeoreum Yun
` (10 preceding siblings ...)
2026-05-19 15:48 ` [PATCH v7 11/13] coresight: etm3x: introduce struct etm_caps Yeoreum Yun
@ 2026-05-19 15:48 ` Yeoreum Yun
2026-05-19 15:48 ` [PATCH v7 13/13] coresight: etm3x: remove redundant cpu online check on etm_enable_sysfs() Yeoreum Yun
12 siblings, 0 replies; 39+ messages in thread
From: Yeoreum Yun @ 2026-05-19 15:48 UTC (permalink / raw)
To: coresight, linux-arm-kernel, linux-kernel
Cc: suzuki.poulose, mike.leach, james.clark, alexander.shishkin,
leo.yan, jie.gan, Yeoreum Yun
The current ETM3x configuration via sysfs can lead to the following
inconsistencies:
- If a configuration is modified via sysfs while a perf session is
active, the running configuration may differ between before
a sched-out and after a subsequent sched-in.
To resolve these issues, separate the configuration into:
- active_config: the configuration applied to the current session
- config: the configuration set via sysfs
Additionally:
- Since active_config and related fields are accessed only by the local CPU
in etm_enable/disable_sysfs_smp_call() (similar to perf enable/disable),
remove the lock/unlock from the sysfs enable/disable path and
starting/dying_cpu path except when to access config fields only.
Fixes: 1925a470ce69 ("coresight: etm3x: splitting struct etm_drvdata")
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
---
drivers/hwtracing/coresight/coresight-etm.h | 2 +
.../coresight/coresight-etm3x-core.c | 38 +++++++++----------
2 files changed, 21 insertions(+), 19 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm.h b/drivers/hwtracing/coresight/coresight-etm.h
index 932bec82fb47..01f1a7f2559c 100644
--- a/drivers/hwtracing/coresight/coresight-etm.h
+++ b/drivers/hwtracing/coresight/coresight-etm.h
@@ -243,6 +243,7 @@ struct etm_config {
* @boot_enable:true if we should start tracing at boot time.
* @os_unlock: true if access to management registers is allowed.
* @traceid: value of the current ID for this component.
+ * @active_config: structure holding current running configuration parameters.
* @config: structure holding configuration parameters.
*/
struct etm_drvdata {
@@ -258,6 +259,7 @@ struct etm_drvdata {
bool boot_enable;
bool os_unlock;
u32 traceid;
+ struct etm_config active_config;
struct etm_config config;
};
diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/hwtracing/coresight/coresight-etm3x-core.c
index ccfde9eda537..ed27e35b42ec 100644
--- a/drivers/hwtracing/coresight/coresight-etm3x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c
@@ -309,7 +309,7 @@ static int etm_parse_event_config(struct etm_drvdata *drvdata,
struct perf_event *event)
{
const struct etm_caps *caps = &drvdata->caps;
- struct etm_config *config = &drvdata->config;
+ struct etm_config *config = &drvdata->active_config;
struct perf_event_attr *attr = &event->attr;
u8 ts_level;
@@ -368,7 +368,7 @@ static int etm_enable_hw(struct etm_drvdata *drvdata)
int i, rc;
u32 etmcr;
const struct etm_caps *caps = &drvdata->caps;
- struct etm_config *config = &drvdata->config;
+ struct etm_config *config = &drvdata->active_config;
struct coresight_device *csdev = drvdata->csdev;
CS_UNLOCK(drvdata->csa.base);
@@ -443,24 +443,30 @@ static int etm_enable_hw(struct etm_drvdata *drvdata)
struct etm_enable_arg {
struct etm_drvdata *drvdata;
struct coresight_path *path;
+ struct etm_config config;
int rc;
};
static void etm_enable_sysfs_smp_call(void *info)
{
struct etm_enable_arg *arg = info;
+ struct etm_drvdata *drvdata;
struct coresight_device *csdev;
if (WARN_ON(!arg))
return;
- csdev = arg->drvdata->csdev;
+ drvdata = arg->drvdata;
+ csdev = drvdata->csdev;
if (!coresight_take_mode(csdev, CS_MODE_SYSFS)) {
/* Someone is already using the tracer */
arg->rc = -EBUSY;
return;
}
+ drvdata->active_config = arg->config;
+ drvdata->traceid = arg->path->trace_id;
+
arg->rc = etm_enable_hw(arg->drvdata);
/* The tracer didn't start */
@@ -469,6 +475,7 @@ static void etm_enable_sysfs_smp_call(void *info)
return;
}
+ drvdata->sticky_enable = true;
csdev->path = arg->path;
}
@@ -513,10 +520,6 @@ static int etm_enable_sysfs(struct coresight_device *csdev, struct coresight_pat
struct etm_enable_arg arg = { };
int ret;
- raw_spin_lock(&drvdata->spinlock);
-
- drvdata->traceid = path->trace_id;
-
/*
* Configure the ETM only if the CPU is online. If it isn't online
* hw configuration will take place on the local CPU during bring up.
@@ -524,23 +527,24 @@ static int etm_enable_sysfs(struct coresight_device *csdev, struct coresight_pat
if (cpu_online(drvdata->cpu)) {
arg.drvdata = drvdata;
arg.path = path;
+
+ raw_spin_lock(&drvdata->spinlock);
+ arg.config = drvdata->config;
+ raw_spin_unlock(&drvdata->spinlock);
+
ret = smp_call_function_single(drvdata->cpu,
etm_enable_sysfs_smp_call, &arg, 1);
if (!ret)
ret = arg.rc;
- if (!ret)
- drvdata->sticky_enable = true;
} else {
ret = -ENODEV;
}
- if (ret)
- etm_release_trace_id(drvdata);
-
- raw_spin_unlock(&drvdata->spinlock);
-
if (!ret)
dev_dbg(&csdev->dev, "ETM tracing enabled\n");
+ else
+ etm_release_trace_id(drvdata);
+
return ret;
}
@@ -567,7 +571,7 @@ static void etm_disable_hw(struct etm_drvdata *drvdata)
{
int i;
const struct etm_caps *caps = &drvdata->caps;
- struct etm_config *config = &drvdata->config;
+ struct etm_config *config = &drvdata->active_config;
struct coresight_device *csdev = drvdata->csdev;
CS_UNLOCK(drvdata->csa.base);
@@ -633,8 +637,6 @@ static void etm_disable_sysfs(struct coresight_device *csdev)
{
struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
- raw_spin_lock(&drvdata->spinlock);
-
/*
* Executing etm_disable_hw on the cpu whose ETM is being disabled
* ensures that register writes occur when cpu is powered.
@@ -642,8 +644,6 @@ static void etm_disable_sysfs(struct coresight_device *csdev)
smp_call_function_single(drvdata->cpu, etm_disable_sysfs_smp_call,
drvdata, 1);
- raw_spin_unlock(&drvdata->spinlock);
-
/*
* we only release trace IDs when resetting sysfs.
* This permits sysfs users to read the trace ID after the trace
--
LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7}
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PATCH v7 13/13] coresight: etm3x: remove redundant cpu online check on etm_enable_sysfs()
2026-05-19 15:47 [PATCH v7 00/13] fix several inconsistencies with sysfs configuration in etmX Yeoreum Yun
` (11 preceding siblings ...)
2026-05-19 15:48 ` [PATCH v7 12/13] coresight: etm3x: fix inconsistencies with sysfs configuration Yeoreum Yun
@ 2026-05-19 15:48 ` Yeoreum Yun
12 siblings, 0 replies; 39+ messages in thread
From: Yeoreum Yun @ 2026-05-19 15:48 UTC (permalink / raw)
To: coresight, linux-arm-kernel, linux-kernel
Cc: suzuki.poulose, mike.leach, james.clark, alexander.shishkin,
leo.yan, jie.gan, Yeoreum Yun
cpu online() check is done in coresight_validate_source_sysfs() already.
Therefore, remove redundant check in etm_enable_sysfs().
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
---
.../coresight/coresight-etm3x-core.c | 31 ++++++++-----------
1 file changed, 13 insertions(+), 18 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/hwtracing/coresight/coresight-etm3x-core.c
index ed27e35b42ec..9dbfe6a1dc4d 100644
--- a/drivers/hwtracing/coresight/coresight-etm3x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c
@@ -520,25 +520,20 @@ static int etm_enable_sysfs(struct coresight_device *csdev, struct coresight_pat
struct etm_enable_arg arg = { };
int ret;
- /*
- * Configure the ETM only if the CPU is online. If it isn't online
- * hw configuration will take place on the local CPU during bring up.
- */
- if (cpu_online(drvdata->cpu)) {
- arg.drvdata = drvdata;
- arg.path = path;
-
- raw_spin_lock(&drvdata->spinlock);
- arg.config = drvdata->config;
- raw_spin_unlock(&drvdata->spinlock);
-
- ret = smp_call_function_single(drvdata->cpu,
- etm_enable_sysfs_smp_call, &arg, 1);
- if (!ret)
- ret = arg.rc;
- } else {
+ arg.drvdata = drvdata;
+ arg.path = path;
+
+ raw_spin_lock(&drvdata->spinlock);
+ arg.config = drvdata->config;
+ raw_spin_unlock(&drvdata->spinlock);
+
+ ret = smp_call_function_single(drvdata->cpu,
+ etm_enable_sysfs_smp_call, &arg, 1);
+
+ if (!ret)
+ ret = arg.rc;
+ else
ret = -ENODEV;
- }
if (!ret)
dev_dbg(&csdev->dev, "ETM tracing enabled\n");
--
LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7}
^ permalink raw reply related [flat|nested] 39+ messages in thread