Re: [RFC PATCH 07/13] arm64: percpu: Implement preemptible read/write ops

[Mark Rutland <mark.rutland@arm.com>]

On Tue, Jul 28, 2026 at 11:05:04PM +0100, David Laight wrote:
> On Tue, 28 Jul 2026 13:38:53 +0100
> Mark Rutland <mark.rutland@arm.com> wrote:
> 
> > Generated code after this patch:
> > 
> > | <outline_this_cpu_write_u64>:
> > |        mrs     x2, sp_el0
> > |        mov     w3, #0x7c60
> > |        strh    w3, [x2, #20]
> > |        mrs     x3, tpidr_el1
> > |        str     x1, [x0, x3]
> > |        strh    wzr, [x2, #20]
> > |        ret
> 
> How is that likely to get scheduled on a typical arm64 cpu?
> In particular does the reuse of [wx]3 create a register dependency
> between the two instruction flows and stop then running in parallel.
> A typical x86 cpu (that anyone cares about) does register renaming
> so it wouldn't matter, but I don't know about arm.
> So it might be worth using different register for w3 and x3 (although
> that might cause a spill - which will be worse).

Practically speaking, any CPU which hits hazards those uses of w3 and x3
is not worth worrying about. It is not worth allocating another register
here.

Mark.