* [PATCH 1/2] serial: Add auart driver for i.MX23/28
From: Sascha Hauer @ 2011-01-11 15:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1294758545-9445-1-git-send-email-s.hauer@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/serial/Kconfig | 15 +
drivers/serial/Makefile | 1 +
drivers/serial/mxs-auart.c | 763 ++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 779 insertions(+), 0 deletions(-)
create mode 100644 drivers/serial/mxs-auart.c
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index ec3c214..de37fe5 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -1657,4 +1657,19 @@ config SERIAL_PCH_UART
This driver is for PCH(Platform controller Hub) UART of Intel EG20T
which is an IOH(Input/Output Hub) for x86 embedded processor.
Enabling PCH_DMA, this PCH UART works as DMA mode.
+
+config SERIAL_MXS_AUART
+ depends on ARCH_MXS
+ tristate "i.MXS AUART support"
+ select SERIAL_CORE
+ help
+ This driver supports the i.MX AUART port.
+
+config SERIAL_MXS_AUART_CONSOLE
+ bool "i.MXS AUART console support"
+ depends on SERIAL_MXS_AUART=y
+ select SERIAL_CORE_CONSOLE
+ help
+ Enable a i.MXS AUART port to be the system console.
+
endmenu
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 8ea92e9..c855071 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -92,3 +92,4 @@ obj-$(CONFIG_SERIAL_MRST_MAX3110) += mrst_max3110.o
obj-$(CONFIG_SERIAL_MFD_HSU) += mfd.o
obj-$(CONFIG_SERIAL_IFX6X60) += ifx6x60.o
obj-$(CONFIG_SERIAL_PCH_UART) += pch_uart.o
+obj-$(CONFIG_SERIAL_MXS_AUART) += mxs-auart.o
diff --git a/drivers/serial/mxs-auart.c b/drivers/serial/mxs-auart.c
new file mode 100644
index 0000000..dd437ea
--- /dev/null
+++ b/drivers/serial/mxs-auart.c
@@ -0,0 +1,763 @@
+/*
+ * Application UART driver for hardware found on
+ * Sigmatel STMP37XX/STMP378X and
+ * Freescale i.MX23/28
+ *
+ * Author: dmitry pervushin <dimka@embeddedalley.com>
+ *
+ * Copyright 2010 Sascha Hauer <s.hauer@pengutronix.de>
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/console.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/wait.h>
+#include <linux/tty.h>
+#include <linux/tty_driver.h>
+#include <linux/tty_flip.h>
+#include <linux/serial.h>
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+#include <linux/device.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+
+#include <asm/cacheflush.h>
+#include <mach/mx28.h>
+
+#define MXS_AUART_PORTS 5
+
+#define UARTAPP_CTRL0 0x00000000
+#define UARTAPP_CTRL0_SET 0x00000004
+#define UARTAPP_CTRL0_CLR 0x00000008
+#define UARTAPP_CTRL0_TOG 0x0000000c
+#define UARTAPP_CTRL1 0x00000010
+#define UARTAPP_CTRL1_SET 0x00000014
+#define UARTAPP_CTRL1_CLR 0x00000018
+#define UARTAPP_CTRL1_TOG 0x0000001c
+#define UARTAPP_CTRL2 0x00000020
+#define UARTAPP_CTRL2_SET 0x00000024
+#define UARTAPP_CTRL2_CLR 0x00000028
+#define UARTAPP_CTRL2_TOG 0x0000002c
+#define UARTAPP_LINECTRL 0x00000030
+#define UARTAPP_LINECTRL_SET 0x00000034
+#define UARTAPP_LINECTRL_CLR 0x00000038
+#define UARTAPP_LINECTRL_TOG 0x0000003c
+#define UARTAPP_LINECTRL2 0x00000040
+#define UARTAPP_LINECTRL2_SET 0x00000044
+#define UARTAPP_LINECTRL2_CLR 0x00000048
+#define UARTAPP_LINECTRL2_TOG 0x0000004c
+#define UARTAPP_INTR 0x00000050
+#define UARTAPP_INTR_SET 0x00000054
+#define UARTAPP_INTR_CLR 0x00000058
+#define UARTAPP_INTR_TOG 0x0000005c
+#define UARTAPP_DATA 0x00000060
+#define UARTAPP_STAT 0x00000070
+#define UARTAPP_DEBUG 0x00000080
+#define UARTAPP_VERSION 0x00000090
+#define UARTAPP_AUTOBAUD 0x000000a0
+
+#define BM_UARTAPP_CTRL0_SFTRST (1 << 31)
+#define BM_UARTAPP_CTRL0_CLKGATE (1 << 30)
+
+
+#define BM_UARTAPP_CTRL2_CTSEN (1 << 15)
+#define BM_UARTAPP_CTRL2_RTS (1 << 11)
+#define BM_UARTAPP_CTRL2_RXE (1 << 9)
+#define BM_UARTAPP_CTRL2_TXE (1 << 8)
+#define BM_UARTAPP_CTRL2_UARTEN (1 << 0)
+
+#define BP_UARTAPP_LINECTRL_BAUD_DIVINT 16
+#define BM_UARTAPP_LINECTRL_BAUD_DIVINT 0xffff0000
+#define BF_UARTAPP_LINECTRL_BAUD_DIVINT(v) (((v) & 0xffff) << 16)
+#define BP_UARTAPP_LINECTRL_BAUD_DIVFRAC 8
+#define BM_UARTAPP_LINECTRL_BAUD_DIVFRAC 0x00003f00
+#define BF_UARTAPP_LINECTRL_BAUD_DIVFRAC(v) (((v) & 0x3f) << 8)
+#define BP_UARTAPP_LINECTRL_WLEN 5
+#define BM_UARTAPP_LINECTRL_WLEN 0x00000060
+#define BF_UARTAPP_LINECTRL_WLEN(v) (((v) & 0x3) << 5)
+#define BM_UARTAPP_LINECTRL_FEN (1 << 4)
+#define BM_UARTAPP_LINECTRL_STP2 (1 << 3)
+#define BM_UARTAPP_LINECTRL_EPS (1 << 2)
+#define BM_UARTAPP_LINECTRL_PEN (1 << 1)
+#define BM_UARTAPP_LINECTRL_BRK (1 << 0)
+
+#define BM_UARTAPP_INTR_RTIEN (1 << 22)
+#define BM_UARTAPP_INTR_TXIEN (1 << 21)
+#define BM_UARTAPP_INTR_RXIEN (1 << 20)
+#define BM_UARTAPP_INTR_CTSMIEN (1 << 17)
+#define BM_UARTAPP_INTR_RTIS (1 << 6)
+#define BM_UARTAPP_INTR_TXIS (1 << 5)
+#define BM_UARTAPP_INTR_RXIS (1 << 4)
+#define BM_UARTAPP_INTR_CTSMIS (1 << 1)
+
+#define BM_UARTAPP_STAT_BUSY (1 << 29)
+#define BM_UARTAPP_STAT_CTS (1 << 28)
+#define BM_UARTAPP_STAT_TXFE (1 << 27)
+#define BM_UARTAPP_STAT_TXFF (1 << 25)
+#define BM_UARTAPP_STAT_RXFE (1 << 24)
+#define BM_UARTAPP_STAT_OERR (1 << 19)
+#define BM_UARTAPP_STAT_BERR (1 << 18)
+#define BM_UARTAPP_STAT_PERR (1 << 17)
+#define BM_UARTAPP_STAT_FERR (1 << 16)
+
+#define MXS_AUART_MAJOR 242
+#define MXS_AUART_RX_THRESHOLD 16
+
+static struct uart_driver auart_driver;
+
+struct mxs_auart_port {
+ struct uart_port port;
+
+ unsigned int flags;
+ unsigned int ctrl;
+
+ unsigned int irq;
+
+ struct clk *clk;
+ struct device *dev;
+};
+
+static void mxs_auart_stop_tx(struct uart_port *u);
+
+#define to_auart_port(u) container_of(u, struct mxs_auart_port, port)
+
+static inline void mxs_auart_tx_chars(struct mxs_auart_port *s)
+{
+ struct circ_buf *xmit = &s->port.state->xmit;
+
+ while (!(readl(s->port.membase + UARTAPP_STAT) &
+ BM_UARTAPP_STAT_TXFF)) {
+ if (s->port.x_char) {
+ writel(s->port.x_char,
+ s->port.membase + UARTAPP_DATA);
+ s->port.x_char = 0;
+ continue;
+ }
+ if (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) {
+ writel(xmit->buf[xmit->tail],
+ s->port.membase + UARTAPP_DATA);
+ xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
+ if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+ uart_write_wakeup(&s->port);
+ } else
+ break;
+ }
+ if (uart_circ_empty(&(s->port.state->xmit)))
+ writel(BM_UARTAPP_INTR_TXIEN,
+ s->port.membase + UARTAPP_INTR_CLR);
+ else
+ writel(BM_UARTAPP_INTR_TXIEN,
+ s->port.membase + UARTAPP_INTR_SET);
+
+ if (uart_tx_stopped(&s->port))
+ mxs_auart_stop_tx(&s->port);
+}
+
+static inline unsigned int
+mxs_auart_rx_char(struct mxs_auart_port *s, unsigned int stat, u8 c)
+{
+ int flag;
+
+ flag = TTY_NORMAL;
+ if (stat & BM_UARTAPP_STAT_BERR) {
+ stat &= ~BM_UARTAPP_STAT_BERR;
+ s->port.icount.brk++;
+ if (uart_handle_break(&s->port))
+ return stat;
+ flag = TTY_BREAK;
+ } else if (stat & BM_UARTAPP_STAT_PERR) {
+ stat &= ~BM_UARTAPP_STAT_PERR;
+ s->port.icount.parity++;
+ flag = TTY_PARITY;
+ } else if (stat & BM_UARTAPP_STAT_FERR) {
+ stat &= ~BM_UARTAPP_STAT_FERR;
+ s->port.icount.frame++;
+ flag = TTY_FRAME;
+ }
+
+ if (stat & BM_UARTAPP_STAT_OERR)
+ s->port.icount.overrun++;
+
+ if (uart_handle_sysrq_char(&s->port, c))
+ return stat;
+
+ uart_insert_char(&s->port, stat, BM_UARTAPP_STAT_OERR, c, flag);
+
+ return stat;
+}
+
+static void mxs_auart_rx_chars(struct mxs_auart_port *s)
+{
+ u8 c;
+ struct tty_struct *tty = s->port.state->port.tty;
+ u32 stat = 0;
+
+ for (;;) {
+ stat = readl(s->port.membase + UARTAPP_STAT);
+ if (stat & BM_UARTAPP_STAT_RXFE)
+ break;
+ c = readl(s->port.membase + UARTAPP_DATA);
+ stat = mxs_auart_rx_char(s, stat, c);
+ writel(stat, s->port.membase + UARTAPP_STAT);
+ }
+
+ writel(stat, s->port.membase + UARTAPP_STAT);
+ tty_flip_buffer_push(tty);
+}
+
+static int mxs_auart_request_port(struct uart_port *u)
+{
+ return 0;
+}
+
+static int mxs_auart_verify_port(struct uart_port *u,
+ struct serial_struct *ser)
+{
+ if (u->type != PORT_UNKNOWN && u->type != PORT_IMX)
+ return -EINVAL;
+ return 0;
+}
+
+static void mxs_auart_config_port(struct uart_port *u, int flags)
+{
+}
+
+static const char *mxs_auart_type(struct uart_port *u)
+{
+ struct mxs_auart_port *s = to_auart_port(u);
+
+ return dev_name(s->dev);
+}
+
+static void mxs_auart_release_port(struct uart_port *u)
+{
+}
+
+static void mxs_auart_set_mctrl(struct uart_port *u, unsigned mctrl)
+{
+ struct mxs_auart_port *s = to_auart_port(u);
+
+ u32 ctrl = readl(u->membase + UARTAPP_CTRL2);
+
+ ctrl &= ~BM_UARTAPP_CTRL2_RTS;
+ if (mctrl & TIOCM_RTS)
+ ctrl |= BM_UARTAPP_CTRL2_RTS;
+ s->ctrl = mctrl;
+ writel(ctrl, u->membase + UARTAPP_CTRL2);
+}
+
+static u32 mxs_auart_get_mctrl(struct uart_port *u)
+{
+ struct mxs_auart_port *s = to_auart_port(u);
+ u32 stat = readl(u->membase + UARTAPP_STAT);
+ int ctrl2 = readl(u->membase + UARTAPP_CTRL2);
+ u32 mctrl = s->ctrl;
+
+ mctrl &= ~TIOCM_CTS;
+ if (stat & BM_UARTAPP_STAT_CTS)
+ mctrl |= TIOCM_CTS;
+
+ if (ctrl2 & BM_UARTAPP_CTRL2_RTS)
+ mctrl |= TIOCM_RTS;
+
+ return mctrl;
+}
+
+static void mxs_auart_settermios(struct uart_port *u,
+ struct ktermios *termios,
+ struct ktermios *old)
+{
+ u32 bm, ctrl, ctrl2, div;
+ unsigned int cflag, baud;
+
+ cflag = termios->c_cflag;
+
+ ctrl = BM_UARTAPP_LINECTRL_FEN;
+ ctrl2 = readl(u->membase + UARTAPP_CTRL2);
+
+ /* byte size */
+ switch (cflag & CSIZE) {
+ case CS5:
+ bm = 0;
+ break;
+ case CS6:
+ bm = 1;
+ break;
+ case CS7:
+ bm = 2;
+ break;
+ case CS8:
+ bm = 3;
+ break;
+ default:
+ return;
+ }
+
+ ctrl |= BF_UARTAPP_LINECTRL_WLEN(bm);
+
+ /* parity */
+ if (cflag & PARENB) {
+ ctrl |= BM_UARTAPP_LINECTRL_PEN;
+ if ((cflag & PARODD) == 0)
+ ctrl |= BM_UARTAPP_LINECTRL_EPS;
+ }
+
+ /* figure out the stop bits requested */
+ if (cflag & CSTOPB)
+ ctrl |= BM_UARTAPP_LINECTRL_STP2;
+
+ /* figure out the hardware flow control settings */
+ if (cflag & CRTSCTS)
+ ctrl2 |= BM_UARTAPP_CTRL2_CTSEN;
+ else
+ ctrl2 &= ~BM_UARTAPP_CTRL2_CTSEN;
+
+ /* set baud rate */
+ baud = uart_get_baud_rate(u, termios, old, 0, u->uartclk);
+ div = u->uartclk * 32 / baud;
+ ctrl |= BF_UARTAPP_LINECTRL_BAUD_DIVFRAC(div & 0x3F);
+ ctrl |= BF_UARTAPP_LINECTRL_BAUD_DIVINT(div >> 6);
+
+ if ((cflag & CREAD) != 0)
+ ctrl2 |= BM_UARTAPP_CTRL2_RXE;
+
+ writel(ctrl, u->membase + UARTAPP_LINECTRL);
+ writel(ctrl2, u->membase + UARTAPP_CTRL2);
+}
+
+static irqreturn_t mxs_auart_irq_handle(int irq, void *context)
+{
+ u32 istatus, istat;
+ struct mxs_auart_port *s = context;
+ u32 stat = readl(s->port.membase + UARTAPP_STAT);
+
+ istatus = istat = readl(s->port.membase + UARTAPP_INTR);
+
+ if (istat & BM_UARTAPP_INTR_CTSMIS) {
+ uart_handle_cts_change(&s->port, stat & BM_UARTAPP_STAT_CTS);
+ writel(BM_UARTAPP_INTR_CTSMIS,
+ s->port.membase + UARTAPP_INTR_CLR);
+ istat &= ~BM_UARTAPP_INTR_CTSMIS;
+ }
+
+ if (istat & (BM_UARTAPP_INTR_RTIS | BM_UARTAPP_INTR_RXIS)) {
+ mxs_auart_rx_chars(s);
+ istat &= ~(BM_UARTAPP_INTR_RTIS | BM_UARTAPP_INTR_RXIS);
+ }
+
+ if (istat & BM_UARTAPP_INTR_TXIS) {
+ mxs_auart_tx_chars(s);
+ istat &= ~BM_UARTAPP_INTR_TXIS;
+ }
+
+ writel(istatus & (BM_UARTAPP_INTR_RTIS
+ | BM_UARTAPP_INTR_TXIS
+ | BM_UARTAPP_INTR_RXIS
+ | BM_UARTAPP_INTR_CTSMIS),
+ s->port.membase + UARTAPP_INTR_CLR);
+
+ return IRQ_HANDLED;
+}
+
+static void mxs_auart_reset(struct uart_port *u)
+{
+ int i;
+ unsigned int reg;
+
+ writel(BM_UARTAPP_CTRL0_SFTRST,
+ u->membase + UARTAPP_CTRL0_CLR);
+
+ for (i = 0; i < 10000; i++) {
+ reg = readl(u->membase + UARTAPP_CTRL0);
+ if (!(reg & BM_UARTAPP_CTRL0_SFTRST))
+ break;
+ udelay(3);
+ }
+
+ writel(BM_UARTAPP_CTRL0_CLKGATE,
+ u->membase + UARTAPP_CTRL0_CLR);
+}
+
+static int mxs_auart_startup(struct uart_port *u)
+{
+ struct mxs_auart_port *s = to_auart_port(u);
+
+ clk_enable(s->clk);
+
+ writel(BM_UARTAPP_CTRL2_UARTEN,
+ s->port.membase + UARTAPP_CTRL2_SET);
+
+ writel(BM_UARTAPP_INTR_RXIEN | BM_UARTAPP_INTR_RTIEN,
+ s->port.membase + UARTAPP_INTR);
+
+ writel(BM_UARTAPP_INTR_CTSMIEN,
+ s->port.membase + UARTAPP_INTR_SET);
+
+ /*
+ * Enable fifo so all four bytes of a DMA word are written to
+ * output (otherwise, only the LSB is written, ie. 1 in 4 bytes)
+ */
+ writel(BM_UARTAPP_LINECTRL_FEN,
+ s->port.membase + UARTAPP_LINECTRL_SET);
+
+ return 0;
+}
+
+static void mxs_auart_shutdown(struct uart_port *u)
+{
+ struct mxs_auart_port *s = to_auart_port(u);
+
+ writel(BM_UARTAPP_CTRL0_SFTRST,
+ s->port.membase + UARTAPP_CTRL0_SET);
+
+ writel(BM_UARTAPP_INTR_RXIEN | BM_UARTAPP_INTR_RTIEN |
+ BM_UARTAPP_INTR_CTSMIEN,
+ s->port.membase + UARTAPP_INTR_CLR);
+
+ clk_disable(s->clk);
+}
+
+static unsigned int mxs_auart_tx_empty(struct uart_port *u)
+{
+ if (readl(u->membase + UARTAPP_STAT) & BM_UARTAPP_STAT_TXFE)
+ return TIOCSER_TEMT;
+ else
+ return 0;
+}
+
+static void mxs_auart_start_tx(struct uart_port *u)
+{
+ struct mxs_auart_port *s = to_auart_port(u);
+
+ /* enable transmitter */
+ writel(BM_UARTAPP_CTRL2_TXE, u->membase + UARTAPP_CTRL2_SET);
+
+ mxs_auart_tx_chars(s);
+}
+
+static void mxs_auart_stop_tx(struct uart_port *u)
+{
+ writel(BM_UARTAPP_CTRL2_TXE, u->membase + UARTAPP_CTRL2_CLR);
+}
+
+static void mxs_auart_stop_rx(struct uart_port *u)
+{
+ writel(BM_UARTAPP_CTRL2_RXE, u->membase + UARTAPP_CTRL2_CLR);
+}
+
+static void mxs_auart_break_ctl(struct uart_port *u, int ctl)
+{
+ if (ctl)
+ writel(BM_UARTAPP_LINECTRL_BRK,
+ u->membase + UARTAPP_LINECTRL_SET);
+ else
+ writel(BM_UARTAPP_LINECTRL_BRK,
+ u->membase + UARTAPP_LINECTRL_CLR);
+}
+
+static void mxs_auart_enable_ms(struct uart_port *port)
+{
+ /* just empty */
+}
+
+static struct uart_ops mxs_auart_ops = {
+ .tx_empty = mxs_auart_tx_empty,
+ .start_tx = mxs_auart_start_tx,
+ .stop_tx = mxs_auart_stop_tx,
+ .stop_rx = mxs_auart_stop_rx,
+ .enable_ms = mxs_auart_enable_ms,
+ .break_ctl = mxs_auart_break_ctl,
+ .set_mctrl = mxs_auart_set_mctrl,
+ .get_mctrl = mxs_auart_get_mctrl,
+ .startup = mxs_auart_startup,
+ .shutdown = mxs_auart_shutdown,
+ .set_termios = mxs_auart_settermios,
+ .type = mxs_auart_type,
+ .release_port = mxs_auart_release_port,
+ .request_port = mxs_auart_request_port,
+ .config_port = mxs_auart_config_port,
+ .verify_port = mxs_auart_verify_port,
+};
+
+static struct mxs_auart_port *auart_port[MXS_AUART_PORTS];
+
+#ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
+static void mxs_auart_console_putchar(struct uart_port *port, int ch)
+{
+ unsigned int status;
+
+ do {
+ status = readl(port->membase + UARTAPP_STAT);
+ } while (status & BM_UARTAPP_STAT_TXFF);
+ writel(ch, port->membase + UARTAPP_DATA);
+}
+
+static void
+auart_console_write(struct console *co, const char *str, unsigned int count)
+{
+ struct mxs_auart_port *s;
+ struct uart_port *port;
+ unsigned int status, old_cr;
+
+ if (co->index > MXS_AUART_PORTS || co->index < 0)
+ return;
+
+ s = auart_port[co->index];
+ port = &s->port;
+
+ clk_enable(s->clk);
+
+ /* First save the CR then disable the interrupts */
+ old_cr = readl(port->membase + UARTAPP_CTRL2);
+ writel(BM_UARTAPP_CTRL2_UARTEN | BM_UARTAPP_CTRL2_TXE,
+ port->membase + UARTAPP_CTRL2_SET);
+
+ uart_console_write(port, str, count, mxs_auart_console_putchar);
+
+ /*
+ * Finally, wait for transmitter to become empty
+ * and restore the TCR
+ */
+ do {
+ status = readl(port->membase + UARTAPP_STAT);
+ } while (status & BM_UARTAPP_STAT_BUSY);
+
+ writel(old_cr, port->membase + UARTAPP_CTRL2);
+
+ clk_disable(s->clk);
+}
+
+static void __init
+auart_console_get_options(struct uart_port *port, int *baud,
+ int *parity, int *bits)
+{
+ if (readl(port->membase + UARTAPP_CTRL2)
+ & BM_UARTAPP_CTRL2_UARTEN) {
+ unsigned int lcr_h, quot;
+ lcr_h = readl(port->membase + UARTAPP_LINECTRL);
+
+ *parity = 'n';
+ if (lcr_h & BM_UARTAPP_LINECTRL_PEN) {
+ if (lcr_h & BM_UARTAPP_LINECTRL_EPS)
+ *parity = 'e';
+ else
+ *parity = 'o';
+ }
+
+ if ((lcr_h & BM_UARTAPP_LINECTRL_WLEN)
+ == BF_UARTAPP_LINECTRL_WLEN(2))
+ *bits = 7;
+ else
+ *bits = 8;
+
+ quot = (((readl(port->membase + UARTAPP_LINECTRL)
+ & BM_UARTAPP_LINECTRL_BAUD_DIVINT))
+ >> (BP_UARTAPP_LINECTRL_BAUD_DIVINT - 6))
+ | (((readl(port->membase + UARTAPP_LINECTRL)
+ & BM_UARTAPP_LINECTRL_BAUD_DIVFRAC))
+ >> BP_UARTAPP_LINECTRL_BAUD_DIVFRAC);
+ if (quot == 0)
+ quot = 1;
+ *baud = (port->uartclk << 2) / quot;
+ }
+}
+
+static int __init
+auart_console_setup(struct console *co, char *options)
+{
+ struct mxs_auart_port *s;
+ int baud = 9600;
+ int bits = 8;
+ int parity = 'n';
+ int flow = 'n';
+ int ret;
+
+ /*
+ * Check whether an invalid uart number has been specified, and
+ * if so, search for the first available port that does have
+ * console support.
+ */
+ if (co->index == -1 || co->index >= ARRAY_SIZE(auart_port))
+ co->index = 0;
+ s = auart_port[co->index];
+ if (!s)
+ return -ENODEV;
+
+ clk_enable(s->clk);
+
+ if (options)
+ uart_parse_options(options, &baud, &parity, &bits, &flow);
+ else
+ auart_console_get_options(&s->port, &baud, &parity, &bits);
+
+ ret = uart_set_options(&s->port, co, baud, parity, bits, flow);
+
+ clk_disable(s->clk);
+
+ return ret;
+}
+
+static struct console auart_console = {
+ .name = "ttyAPP",
+ .write = auart_console_write,
+ .device = uart_console_device,
+ .setup = auart_console_setup,
+ .flags = CON_PRINTBUFFER,
+ .index = -1,
+ .data = &auart_driver,
+};
+#endif
+
+static struct uart_driver auart_driver = {
+ .owner = THIS_MODULE,
+ .driver_name = "ttyAPP",
+ .dev_name = "ttyAPP",
+ .major = 0,
+ .minor = 0,
+ .nr = MXS_AUART_PORTS,
+#ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
+ .cons = &auart_console,
+#endif
+};
+
+static int __devinit mxs_auart_probe(struct platform_device *pdev)
+{
+ struct mxs_auart_port *s;
+ u32 version;
+ int ret = 0;
+ struct resource *r;
+
+ s = kzalloc(sizeof(struct mxs_auart_port), GFP_KERNEL);
+ if (!s) {
+ ret = -ENOMEM;
+ goto out;
+ }
+
+ s->clk = clk_get(&pdev->dev, NULL);
+ if (IS_ERR(s->clk)) {
+ ret = PTR_ERR(s->clk);
+ goto out_free;
+ }
+
+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!r) {
+ ret = -ENXIO;
+ goto out_free_clk;
+ }
+
+ s->port.mapbase = r->start;
+ s->port.membase = ioremap(r->start, resource_size(r));
+ s->port.ops = &mxs_auart_ops;
+ s->port.iotype = UPIO_MEM;
+ s->port.line = pdev->id < 0 ? 0 : pdev->id;
+ s->port.fifosize = 16;
+ s->port.uartclk = clk_get_rate(s->clk);
+ s->port.type = PORT_IMX;
+ s->port.dev = s->dev = get_device(&pdev->dev);
+
+ s->flags = 0;
+ s->ctrl = 0;
+
+ s->irq = platform_get_irq(pdev, 0);
+ s->port.irq = s->irq;
+ ret = request_irq(s->irq, mxs_auart_irq_handle, 0, dev_name(&pdev->dev), s);
+ if (ret)
+ goto out_free_clk;
+
+ platform_set_drvdata(pdev, s);
+
+ auart_port[pdev->id] = s;
+
+ mxs_auart_reset(&s->port);
+
+ ret = uart_add_one_port(&auart_driver, &s->port);
+ if (ret)
+ goto out_free_irq;
+
+ version = readl(s->port.membase + UARTAPP_VERSION);
+ dev_info(&pdev->dev, "Found APPUART %d.%d.%d\n",
+ (version >> 24) & 0xff,
+ (version >> 16) & 0xff, version & 0xffff);
+
+ return 0;
+
+out_free_irq:
+ auart_port[pdev->id] = NULL;
+ free_irq(s->irq, s);
+out_free_clk:
+ clk_put(s->clk);
+out_free:
+ kfree(s);
+out:
+ return ret;
+}
+
+static int __devexit mxs_auart_remove(struct platform_device *pdev)
+{
+ struct mxs_auart_port *s = platform_get_drvdata(pdev);
+
+ uart_remove_one_port(&auart_driver, &s->port);
+
+ auart_port[pdev->id] = NULL;
+
+ clk_put(s->clk);
+ free_irq(s->irq, s);
+ kfree(s);
+
+ return 0;
+}
+
+static struct platform_driver mxs_auart_driver = {
+ .probe = mxs_auart_probe,
+ .remove = __devexit_p(mxs_auart_remove),
+ .driver = {
+ .name = "mxs-auart",
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init mxs_auart_init(void)
+{
+ int r;
+
+ r = uart_register_driver(&auart_driver);
+ if (r)
+ goto out;
+
+ r = platform_driver_register(&mxs_auart_driver);
+ if (r)
+ goto out_err;
+
+ return 0;
+out_err:
+ uart_unregister_driver(&auart_driver);
+out:
+ return r;
+}
+
+static void __exit mxs_auart_exit(void)
+{
+ platform_driver_unregister(&mxs_auart_driver);
+ uart_unregister_driver(&auart_driver);
+}
+
+module_init(mxs_auart_init);
+module_exit(mxs_auart_exit);
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Freescale MXS application uart driver");
+MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
--
1.7.2.3
^ permalink raw reply related
* Add i.MX23/28 auart support
From: Sascha Hauer @ 2011-01-11 15:09 UTC (permalink / raw)
To: linux-arm-kernel
The following series adds support for the auart found on i.MX23/28
Sascha Hauer (2):
serial: Add auart driver for i.MX23/28
ARM i.MXS: Add auart platform support for i.MX28
arch/arm/mach-mxs/clock-mx28.c | 5 +
arch/arm/mach-mxs/devices-mx28.h | 8 +
arch/arm/mach-mxs/devices/Kconfig | 3 +
arch/arm/mach-mxs/devices/Makefile | 1 +
arch/arm/mach-mxs/devices/platform-auart.c | 54 ++
arch/arm/mach-mxs/include/mach/devices-common.h | 10 +
drivers/serial/Kconfig | 15 +
drivers/serial/Makefile | 1 +
drivers/serial/mxs-auart.c | 763 +++++++++++++++++++++++
9 files changed, 860 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-mxs/devices/platform-auart.c
create mode 100644 drivers/serial/mxs-auart.c
^ permalink raw reply
* [PATCH 2/2] ARM i.MX53 enable LOCO board bootup
From: Fabio Estevam @ 2011-01-11 14:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1294726998-20830-3-git-send-email-yong.shen@freescale.com>
Hi Yong,
On Tue, Jan 11, 2011 at 4:23 AM, <yong.shen@freescale.com> wrote:
> From: Yong Shen <yong.shen@freescale.com>
>
> 1. Add Kconfig and Makefile entries
> 2. Add board definition
> 3. enable uart and fec for LOCO board
>
> Signed-off-by: Yong Shen <yong.shen@freescale.com>
> ---
....
> + ? ? ? }
> + ? ? ? gpio_direction_output(LOCO_FEC_PHY_RST, 0);
> + ? ? ? gpio_set_value(LOCO_FEC_PHY_RST, 0);
As Baruch pointed out on a previous post, you can remove the
gpio_set_value line here.
Regards,
Fabio Estevam
^ permalink raw reply
* Locking in the clk API
From: Jeremy Kerr @ 2011-01-11 14:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110111121816.GB774@linux-sh.org>
Hi Paul,
> Again, you are approaching it from the angle that an atomic clock is a
> special requirement rather than the default behaviour.
I'm not considering it a special requirement, but it's still a requirement
(that the called function does not sleep).
The problem with the inverse logic (clk_enable/clk_enable_sleepable) is that
now you've made the caller need to know what kind of clock it has, or might
have one day.
* For clk_enable/clk_enable_atomic, the decision is: is this call in an
atomic context?
* For clk_enable/clk_enable_sleepable, the decision is: might the clock code
have given us a sleeping clock?
Note that it's much easier to guarantee correctness for the first than it is
for the second.
Cheers,
Jeremy
^ permalink raw reply
* Locking in the clk API
From: Pavel Machek @ 2011-01-11 14:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110111092842.GJ12552@n2100.arm.linux.org.uk>
Hi!
> Another solution occurs to me: clk_enable() which returns -EAGAIN if
> it's called in an atomic context but needs to sleep, and let the driver
> deal with the clock not being enabled when it wants it. The down side
> is it requires the driver to have additional code to sort out such a
> problem.
I do not think that "atomic context" is possible to reliably detect
inside a function like that.
Pavel
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
^ permalink raw reply
* [PATCH 7/7 v2] OMAP: runtime: McSPI driver runtime conversion
From: Govindraj @ 2011-01-11 14:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <877hegl47q.fsf@ti.com>
On Sat, Jan 8, 2011 at 4:19 AM, Kevin Hilman <khilman@ti.com> wrote:
> Grant Likely <grant.likely@secretlab.ca> writes:
>
>> On Wed, Dec 01, 2010 at 07:32:11PM +0530, Govindraj.R wrote:
>>> McSPI runtime conversion.
>>> Changes involves:
>>> 1) remove clock framework apis to use runtime framework apis.
>>> 2) context restore from runtime resume which is a callback for get_sync.
>>> 3) Remove SYSCONFIG(sysc) register handling
>>> ? ? ? ? (a) Remove context save and restore of sysc reg and remove soft reset
>>> ? ? ? ? ? ? done from sysc reg as this will be done with hwmod framework.
>>> ? ? ? ? (b) Also cleanup sysc reg bit macros.
>>> 4) Rename the omap2_mcspi_reset function to omap2_mcspi_master_setup
>>> ? ?function as with hwmod changes soft reset will be done in
>>> ? ?hwmod framework itself and use the return value from clock
>>> ? ?enable function to return for failure scenarios.
>>>
>>> Signed-off-by: Charulatha V <charu@ti.com>
>>> Signed-off-by: Govindraj.R <govindraj.raja@ti.com>
>>> Reviewed-by: Partha Basak <p-basak2@ti.com>
>>
>> One comment below, but otherwise looks good to me. ?Since the majority
>> of the changes are in arch/arm, feel free to add my Acked-by for the
>> whole series and merge via the omap tree.
>
> Thanks, we'll merge this through the OMAP tree.
>
>> None of my comments are showstoppers, so I'm even fine with merging
>> them as-is as long as followup patches are posted to address the
>> comments.
>
> Govindraj, since we've missed 2.6.38 for this series, I'd like to see the last few
> minor issues cleaned up before merge, especially the various casting and
> CodingStyle issues that Grant found.
Yes sure will post out v3 in a weeks time. Fixing comments and
adding ack from Grant.
--
Thanks,
Govindraj.R
>
> Kevin
>
>> In particular, I'd really like to see the data duplication issue from
>> the first 4 patches addressed.
>>
>> Acked-by: Grant Likely <grant.likely@secretlab.ca>
>>
>>
>>> ---
>>> ?drivers/spi/omap2_mcspi.c | ?120 +++++++++++++++++---------------------------
>>> ?1 files changed, 46 insertions(+), 74 deletions(-)
>>>
>>> diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c
>>> index ad3811e..a1b157f 100644
>>> --- a/drivers/spi/omap2_mcspi.c
>>> +++ b/drivers/spi/omap2_mcspi.c
>>> @@ -33,6 +33,7 @@
>>> ?#include <linux/clk.h>
>>> ?#include <linux/io.h>
>>> ?#include <linux/slab.h>
>>> +#include <linux/pm_runtime.h>
>>>
>>> ?#include <linux/spi/spi.h>
>>>
>>> @@ -46,7 +47,6 @@
>>> ?#define OMAP2_MCSPI_MAX_CTRL ? ? ? ? ? ? ? ?4
>>>
>>> ?#define OMAP2_MCSPI_REVISION ? ? ? ? ? ? ? ?0x00
>>> -#define OMAP2_MCSPI_SYSCONFIG ? ? ? ? ? ? ? 0x10
>>> ?#define OMAP2_MCSPI_SYSSTATUS ? ? ? ? ? ? ? 0x14
>>> ?#define OMAP2_MCSPI_IRQSTATUS ? ? ? ? ? ? ? 0x18
>>> ?#define OMAP2_MCSPI_IRQENABLE ? ? ? ? ? ? ? 0x1c
>>> @@ -63,13 +63,6 @@
>>>
>>> ?/* per-register bitmasks: */
>>>
>>> -#define OMAP2_MCSPI_SYSCONFIG_SMARTIDLE ? ? BIT(4)
>>> -#define OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP ? ? BIT(2)
>>> -#define OMAP2_MCSPI_SYSCONFIG_AUTOIDLE ? ? ?BIT(0)
>>> -#define OMAP2_MCSPI_SYSCONFIG_SOFTRESET ? ? BIT(1)
>>> -
>>> -#define OMAP2_MCSPI_SYSSTATUS_RESETDONE ? ? BIT(0)
>>> -
>>> ?#define OMAP2_MCSPI_MODULCTRL_SINGLE ? ? ? ?BIT(0)
>>> ?#define OMAP2_MCSPI_MODULCTRL_MS ? ?BIT(2)
>>> ?#define OMAP2_MCSPI_MODULCTRL_STEST BIT(3)
>>> @@ -122,13 +115,12 @@ struct omap2_mcspi {
>>> ? ? ?spinlock_t ? ? ? ? ? ? ?lock;
>>> ? ? ?struct list_head ? ? ? ?msg_queue;
>>> ? ? ?struct spi_master ? ? ? *master;
>>> - ? ?struct clk ? ? ? ? ? ? ?*ick;
>>> - ? ?struct clk ? ? ? ? ? ? ?*fck;
>>> ? ? ?/* Virtual base address of the controller */
>>> ? ? ?void __iomem ? ? ? ? ? ?*base;
>>> ? ? ?unsigned long ? ? ? ? ? phys;
>>> ? ? ?/* SPI1 has 4 channels, while SPI2 has 2 */
>>> ? ? ?struct omap2_mcspi_dma ?*dma_channels;
>>> + ? ?struct ?device ? ? ? ? ?*dev;
>>
>> Inconsistent indentation with the rest of the structure (tabs vs. spaces).
>>
>>> ?};
>>>
>>> ?struct omap2_mcspi_cs {
>>> @@ -144,7 +136,6 @@ struct omap2_mcspi_cs {
>>> ? * corresponding registers are modified.
>>> ? */
>>> ?struct omap2_mcspi_regs {
>>> - ? ?u32 sysconfig;
>>> ? ? ?u32 modulctrl;
>>> ? ? ?u32 wakeupenable;
>>> ? ? ?struct list_head cs;
>>> @@ -268,9 +259,6 @@ static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
>>> ? ? ?mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL,
>>> ? ? ? ? ? ? ? ? ? ? ?omap2_mcspi_ctx[spi_cntrl->bus_num - 1].modulctrl);
>>>
>>> - ? ?mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_SYSCONFIG,
>>> - ? ? ? ? ? ? ? ? ? ?omap2_mcspi_ctx[spi_cntrl->bus_num - 1].sysconfig);
>>> -
>>> ? ? ?mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE,
>>> ? ? ? ? ? ? ? ? ? ? ?omap2_mcspi_ctx[spi_cntrl->bus_num - 1].wakeupenable);
>>>
>>> @@ -280,20 +268,12 @@ static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
>>> ?}
>>> ?static void omap2_mcspi_disable_clocks(struct omap2_mcspi *mcspi)
>>> ?{
>>> - ? ?clk_disable(mcspi->ick);
>>> - ? ?clk_disable(mcspi->fck);
>>> + ? ?pm_runtime_put_sync(mcspi->dev);
>>> ?}
>>>
>>> ?static int omap2_mcspi_enable_clocks(struct omap2_mcspi *mcspi)
>>> ?{
>>> - ? ?if (clk_enable(mcspi->ick))
>>> - ? ? ? ? ? ?return -ENODEV;
>>> - ? ?if (clk_enable(mcspi->fck))
>>> - ? ? ? ? ? ?return -ENODEV;
>>> -
>>> - ? ?omap2_mcspi_restore_ctx(mcspi);
>>> -
>>> - ? ?return 0;
>>> + ? ?return pm_runtime_get_sync(mcspi->dev);
>>> ?}
>>>
>>> ?static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
>>> @@ -819,8 +799,9 @@ static int omap2_mcspi_setup(struct spi_device *spi)
>>> ? ? ? ? ? ? ? ? ? ? ?return ret;
>>> ? ? ?}
>>>
>>> - ? ?if (omap2_mcspi_enable_clocks(mcspi))
>>> - ? ? ? ? ? ?return -ENODEV;
>>> + ? ?ret = omap2_mcspi_enable_clocks(mcspi);
>>> + ? ?if (ret < 0)
>>> + ? ? ? ? ? ?return ret;
>>>
>>> ? ? ?ret = omap2_mcspi_setup_transfer(spi, NULL);
>>> ? ? ?omap2_mcspi_disable_clocks(mcspi);
>>> @@ -863,10 +844,11 @@ static void omap2_mcspi_work(struct work_struct *work)
>>> ? ? ?struct omap2_mcspi ? ? ?*mcspi;
>>>
>>> ? ? ?mcspi = container_of(work, struct omap2_mcspi, work);
>>> - ? ?spin_lock_irq(&mcspi->lock);
>>>
>>> - ? ?if (omap2_mcspi_enable_clocks(mcspi))
>>> - ? ? ? ? ? ?goto out;
>>> + ? ?if (omap2_mcspi_enable_clocks(mcspi) < 0)
>>> + ? ? ? ? ? ?return;
>>> +
>>> + ? ?spin_lock_irq(&mcspi->lock);
>>>
>>> ? ? ?/* We only enable one channel at a time -- the one whose message is
>>> ? ? ? * at the head of the queue -- although this controller would gladly
>>> @@ -979,10 +961,9 @@ static void omap2_mcspi_work(struct work_struct *work)
>>> ? ? ? ? ? ? ?spin_lock_irq(&mcspi->lock);
>>> ? ? ?}
>>>
>>> - ? ?omap2_mcspi_disable_clocks(mcspi);
>>> -
>>> -out:
>>> ? ? ?spin_unlock_irq(&mcspi->lock);
>>> +
>>> + ? ?omap2_mcspi_disable_clocks(mcspi);
>>> ?}
>>>
>>> ?static int omap2_mcspi_transfer(struct spi_device *spi, struct spi_message *m)
>>> @@ -1063,25 +1044,15 @@ static int omap2_mcspi_transfer(struct spi_device *spi, struct spi_message
>>> *m)
>>> ? ? ?return 0;
>>> ?}
>>>
>>> -static int __init omap2_mcspi_reset(struct omap2_mcspi *mcspi)
>>> +static int __init omap2_mcspi_master_setup(struct omap2_mcspi *mcspi)
>>> ?{
>>> ? ? ?struct spi_master ? ? ? *master = mcspi->master;
>>> ? ? ?u32 ? ? ? ? ? ? ? ? ? ? tmp;
>>> + ? ?int ret = 0;
>>>
>>> - ? ?if (omap2_mcspi_enable_clocks(mcspi))
>>> - ? ? ? ? ? ?return -1;
>>> -
>>> - ? ?mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG,
>>> - ? ? ? ? ? ? ? ? ? ?OMAP2_MCSPI_SYSCONFIG_SOFTRESET);
>>> - ? ?do {
>>> - ? ? ? ? ? ?tmp = mcspi_read_reg(master, OMAP2_MCSPI_SYSSTATUS);
>>> - ? ?} while (!(tmp & OMAP2_MCSPI_SYSSTATUS_RESETDONE));
>>> -
>>> - ? ?tmp = OMAP2_MCSPI_SYSCONFIG_AUTOIDLE |
>>> - ? ? ? ? ? ?OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP |
>>> - ? ? ? ? ? ?OMAP2_MCSPI_SYSCONFIG_SMARTIDLE;
>>> - ? ?mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG, tmp);
>>> - ? ?omap2_mcspi_ctx[master->bus_num - 1].sysconfig = tmp;
>>> + ? ?ret = omap2_mcspi_enable_clocks(mcspi);
>>> + ? ?if (ret < 0)
>>> + ? ? ? ? ? ?return ret;
>>>
>>> ? ? ?tmp = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
>>> ? ? ?mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, tmp);
>>> @@ -1092,6 +1063,18 @@ static int __init omap2_mcspi_reset(struct omap2_mcspi *mcspi)
>>> ? ? ?return 0;
>>> ?}
>>>
>>> +static int omap_mcspi_runtime_resume(struct device *dev)
>>> +{
>>> + ? ?struct omap2_mcspi ? ? ?*mcspi;
>>> + ? ?struct spi_master ? ? ? *master;
>>> +
>>> + ? ?master = dev_get_drvdata(dev);
>>> + ? ?mcspi = spi_master_get_devdata(master);
>>> + ? ?omap2_mcspi_restore_ctx(mcspi);
>>> +
>>> + ? ?return 0;
>>> +}
>>> +
>>>
>>> ?static int __init omap2_mcspi_probe(struct platform_device *pdev)
>>> ?{
>>> @@ -1142,34 +1125,22 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev)
>>> ? ? ?if (!mcspi->base) {
>>> ? ? ? ? ? ? ?dev_dbg(&pdev->dev, "can't ioremap MCSPI\n");
>>> ? ? ? ? ? ? ?status = -ENOMEM;
>>> - ? ? ? ? ? ?goto err1aa;
>>> + ? ? ? ? ? ?goto err2;
>>> ? ? ?}
>>>
>>> + ? ?mcspi->dev = &pdev->dev;
>>> ? ? ?INIT_WORK(&mcspi->work, omap2_mcspi_work);
>>>
>>> ? ? ?spin_lock_init(&mcspi->lock);
>>> ? ? ?INIT_LIST_HEAD(&mcspi->msg_queue);
>>> ? ? ?INIT_LIST_HEAD(&omap2_mcspi_ctx[master->bus_num - 1].cs);
>>>
>>> - ? ?mcspi->ick = clk_get(&pdev->dev, "ick");
>>> - ? ?if (IS_ERR(mcspi->ick)) {
>>> - ? ? ? ? ? ?dev_dbg(&pdev->dev, "can't get mcspi_ick\n");
>>> - ? ? ? ? ? ?status = PTR_ERR(mcspi->ick);
>>> - ? ? ? ? ? ?goto err1a;
>>> - ? ?}
>>> - ? ?mcspi->fck = clk_get(&pdev->dev, "fck");
>>> - ? ?if (IS_ERR(mcspi->fck)) {
>>> - ? ? ? ? ? ?dev_dbg(&pdev->dev, "can't get mcspi_fck\n");
>>> - ? ? ? ? ? ?status = PTR_ERR(mcspi->fck);
>>> - ? ? ? ? ? ?goto err2;
>>> - ? ?}
>>> -
>>> ? ? ?mcspi->dma_channels = kcalloc(master->num_chipselect,
>>> ? ? ? ? ? ? ? ? ? ? ?sizeof(struct omap2_mcspi_dma),
>>> ? ? ? ? ? ? ? ? ? ? ?GFP_KERNEL);
>>>
>>> ? ? ?if (mcspi->dma_channels == NULL)
>>> - ? ? ? ? ? ?goto err3;
>>> + ? ? ? ? ? ?goto err2;
>>>
>>> ? ? ?for (i = 0; i < master->num_chipselect; i++) {
>>> ? ? ? ? ? ? ?char dma_ch_name[14];
>>> @@ -1199,8 +1170,10 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev)
>>> ? ? ? ? ? ? ?mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start;
>>> ? ? ?}
>>>
>>> - ? ?if (omap2_mcspi_reset(mcspi) < 0)
>>> - ? ? ? ? ? ?goto err4;
>>> + ? ?pm_runtime_enable(&pdev->dev);
>>> +
>>> + ? ?if (status || omap2_mcspi_master_setup(mcspi) < 0)
>>> + ? ? ? ? ? ?goto err3;
>>>
>>> ? ? ?status = spi_register_master(master);
>>> ? ? ?if (status < 0)
>>> @@ -1209,17 +1182,13 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev)
>>> ? ? ?return status;
>>>
>>> ?err4:
>>> - ? ?kfree(mcspi->dma_channels);
>>> + ? ?spi_master_put(master);
>>> ?err3:
>>> - ? ?clk_put(mcspi->fck);
>>> + ? ?kfree(mcspi->dma_channels);
>>> ?err2:
>>> - ? ?clk_put(mcspi->ick);
>>> -err1a:
>>> - ? ?iounmap(mcspi->base);
>>> -err1aa:
>>> ? ? ?release_mem_region(r->start, (r->end - r->start) + 1);
>>> + ? ?iounmap(mcspi->base);
>>> ?err1:
>>> - ? ?spi_master_put(master);
>>> ? ? ?return status;
>>> ?}
>>>
>>> @@ -1235,9 +1204,7 @@ static int __exit omap2_mcspi_remove(struct platform_device *pdev)
>>> ? ? ?mcspi = spi_master_get_devdata(master);
>>> ? ? ?dma_channels = mcspi->dma_channels;
>>>
>>> - ? ?clk_put(mcspi->fck);
>>> - ? ?clk_put(mcspi->ick);
>>> -
>>> + ? ?omap2_mcspi_disable_clocks(mcspi);
>>> ? ? ?r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>>> ? ? ?release_mem_region(r->start, (r->end - r->start) + 1);
>>>
>>> @@ -1252,10 +1219,15 @@ static int __exit omap2_mcspi_remove(struct platform_device *pdev)
>>> ?/* work with hotplug and coldplug */
>>> ?MODULE_ALIAS("platform:omap2_mcspi");
>>>
>>> +static const struct dev_pm_ops omap_mcspi_dev_pm_ops = {
>>> + ? ?.runtime_resume = omap_mcspi_runtime_resume,
>>> +};
>>> +
>>> ?static struct platform_driver omap2_mcspi_driver = {
>>> ? ? ?.driver = {
>>> ? ? ? ? ? ? ?.name = ? ? ? ? "omap2_mcspi",
>>> ? ? ? ? ? ? ?.owner = ? ? ? ?THIS_MODULE,
>>> + ? ? ? ? ? ?.pm = &omap_mcspi_dev_pm_ops,
>>> ? ? ?},
>>> ? ? ?.remove = ? ? ? __exit_p(omap2_mcspi_remove),
>>> ?};
>>> --
>>> 1.7.1
>>>
>>>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at ?http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply
* about arm_add_memory
From: wangjun @ 2011-01-11 14:19 UTC (permalink / raw)
To: linux-arm-kernel
in /arch/arm/kernel/setup.c
static int __init arm_add_memory(unsigned long start, unsigned long size)
...
size -= start & ~PAGE_MASK;
bank->start = PAGE_ALIGN(start);
bank->size = size & PAGE_MASK;
bank->node = PHYS_TO_NID(start);
.....
what size -= start & ~PAGE_MASK to do ?
thanks!
-------------- next part --------------
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^ permalink raw reply
* [PATCH v4 08/10] ARM: mxs: add ocotp read function
From: Uwe Kleine-König @ 2011-01-11 14:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110111133137.GS12078@pengutronix.de>
Hello Sascha,
On Tue, Jan 11, 2011 at 02:31:37PM +0100, Sascha Hauer wrote:
> On Thu, Jan 06, 2011 at 03:13:16PM +0800, Shawn Guo wrote:
> > diff --git a/arch/arm/mach-mxs/ocotp.c b/arch/arm/mach-mxs/ocotp.c
> > new file mode 100644
> > index 0000000..e2d39aa
> > --- /dev/null
> > +++ b/arch/arm/mach-mxs/ocotp.c
> > @@ -0,0 +1,79 @@
> > +/*
> > + * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation; either version 2 of the License, or
> > + * (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#include <linux/delay.h>
> > +#include <linux/err.h>
> > +#include <linux/mutex.h>
> > +
> > +#include <mach/mxs.h>
> > +
> > +#define BM_OCOTP_CTRL_BUSY (1 << 8)
> > +#define BM_OCOTP_CTRL_ERROR (1 << 9)
> > +#define BM_OCOTP_CTRL_RD_BANK_OPEN (1 << 12)
> > +
> > +static DEFINE_MUTEX(ocotp_mutex);
> > +
> > +int mxs_read_ocotp(unsigned offset, size_t count, u32 *values)
> > +{
> > + void __iomem *ocotp_base = MXS_IO_ADDRESS(MXS_OCOTP_BASE_ADDR);
> > + int timeout = 0x400;
> > + size_t i;
> > +
> > + mutex_lock(&ocotp_mutex);
> > +
> > + /*
> > + * clk_enable(hbus_clk) for ocotp can be skipped
> > + * as it must be on when system is running.
> > + */
> > +
> > + /* try to clear ERROR bit */
> > + __mxs_clrl(BM_OCOTP_CTRL_ERROR, ocotp_base);
>
> This operation does not try to clear the error bit but actually clears
> it...
>
> > +
> > + /* check both BUSY and ERROR cleared */
> > + while ((__raw_readl(ocotp_base) &
> > + (BM_OCOTP_CTRL_BUSY | BM_OCOTP_CTRL_ERROR)) && --timeout)
> > + cpu_relax();
>
> ...which means you do not have to poll the error bit here...
well, I don't know how the hardware works here, but in general the
argument is broken. Registers are not memory, so just because you set a
bit in register space it doesn't mean it is really set when you read
from the same address.
If there is something wrong with the ocotp I'd even expect that clearing
the error bit doesn't work because it doesn't change the general
condition.
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-K?nig |
Industrial Linux Solutions | http://www.pengutronix.de/ |
^ permalink raw reply
* Locking in the clk API
From: Uwe Kleine-König @ 2011-01-11 13:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110111121816.GB774@linux-sh.org>
On Tue, Jan 11, 2011 at 09:18:16PM +0900, Paul Mundt wrote:
> On Tue, Jan 11, 2011 at 06:30:18PM +0800, Jeremy Kerr wrote:
> > Hi Paul,
> >
> > > No, the sleeping clock case is and always will be a corner case, and I
> > > have no interest in pretending otherwise. On SH we have hundreds of
> > > clocks that are all usable in the atomic context and perhaps less than a
> > > dozen that aren't (and even in those cases much of the PLL negotiation is
> > > handled in hardware so there's never any visibility for the lock-down
> > > from the software side, other architectures also have similar behaviour).
> >
> > I'm not too worried about the corner-cases on the *implementation* side, more
> > the corner-cases on the API side: are we seeing more users of the API that
> > require an atomic clock, or more that don't care?
> >
> Again, you are approaching it from the angle that an atomic clock is a
> special requirement rather than the default behaviour. Sleeping for
particularly if atomic behaviour is the common behaviour it's important
to get it right, because the less common sleeping clocks don't get much
test covering.
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-K?nig |
Industrial Linux Solutions | http://www.pengutronix.de/ |
^ permalink raw reply
* Change SUEN3 MACH to KM_KIRKWOOD
From: Valentin Longchamp @ 2011-01-11 13:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110111134525.GE11039@n2100.arm.linux.org.uk>
Russell King - ARM Linux wrote:
> On Tue, Jan 11, 2011 at 09:38:57AM +0100, Valentin Longchamp wrote:
>> Sorry I made a typo in the subject of the previous mail.
>>
>> To avoid any confusion, the desired name definitely is KM_KIRKWOOD (and
>> not KMKIRKWOOD as written in the subject of the previous mail).
>
> Please confirm that that the update I've just done is correct. Thanks.
Yes the current name in the database is correct. Thank you for the change.
--
Valentin Longchamp
Embedded Software Engineer
Hardware and Chip Integration
______________________________________
KEYMILE AG
Schwarzenburgstr. 73
CH-3097 Liebefeld
Phone +41 31 377 1318
Fax +41 31 377 1212
valentin.longchamp at keymile.com
www.keymile.com
______________________________________
>>Be the FIRST on the LAST MILE<<
^ permalink raw reply
* Change SUEN3 MACH to KM_KIRKWOOD
From: Russell King - ARM Linux @ 2011-01-11 13:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4D2C1721.3040000@keymile.com>
On Tue, Jan 11, 2011 at 09:38:57AM +0100, Valentin Longchamp wrote:
> Sorry I made a typo in the subject of the previous mail.
>
> To avoid any confusion, the desired name definitely is KM_KIRKWOOD (and
> not KMKIRKWOOD as written in the subject of the previous mail).
Please confirm that that the update I've just done is correct. Thanks.
^ permalink raw reply
* [PATCH] arm: mm: Poison freed init memory
From: Pavel Machek @ 2011-01-11 13:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110111090615.GH12552@n2100.arm.linux.org.uk>
Hi!
> > Ok it seems that 0xcc was chosen by Pavel since it's a breakpoint
> > instruction (sorry for not noticing that earlier [1]).
>
> It may be on x86, but on ARM:
>
> 0: cccccccc stclgt 12, cr12, [ip], {204}
>
> That's a co-processor #12 instruction which will only be executed of
> the processor condition codes satisfy 'gt'.
>
> > There was some discussion about handling initdata with Pavel's patch
> > but it seems that nothing came of it?
>
> I'm not sure who this Pavel is who you keep referring to - the message
> you link to is a discussion between William Irvin and hpa.
I was surprised, too, but it looks like I was the one who ported patch
from x86-64.
I'm not really sure if initdata poisoning happened... it is too long
ago.
Pavel
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
^ permalink raw reply
* [PATCH v4 08/10] ARM: mxs: add ocotp read function
From: Sascha Hauer @ 2011-01-11 13:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1294297998-26930-9-git-send-email-shawn.guo@freescale.com>
On Thu, Jan 06, 2011 at 03:13:16PM +0800, Shawn Guo wrote:
> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
> ---
> Changes for v4:
> - Call cpu_relax() during polling
>
> Changes for v2:
> - Add mutex locking for mxs_read_ocotp()
> - Use type size_t for count and i
> - Add comment for clk_enable/disable skipping
> - Add ERROR bit clearing and polling step
>
> arch/arm/mach-mxs/Makefile | 2 +-
> arch/arm/mach-mxs/include/mach/common.h | 1 +
> arch/arm/mach-mxs/ocotp.c | 79 +++++++++++++++++++++++++++++++
> 3 files changed, 81 insertions(+), 1 deletions(-)
> create mode 100644 arch/arm/mach-mxs/ocotp.c
>
> diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile
> index 39d3f9c..f23ebbd 100644
> --- a/arch/arm/mach-mxs/Makefile
> +++ b/arch/arm/mach-mxs/Makefile
> @@ -1,5 +1,5 @@
> # Common support
> -obj-y := clock.o devices.o gpio.o icoll.o iomux.o system.o timer.o
> +obj-y := clock.o devices.o gpio.o icoll.o iomux.o ocotp.o system.o timer.o
>
> obj-$(CONFIG_SOC_IMX23) += clock-mx23.o mm-mx23.o
> obj-$(CONFIG_SOC_IMX28) += clock-mx28.o mm-mx28.o
> diff --git a/arch/arm/mach-mxs/include/mach/common.h b/arch/arm/mach-mxs/include/mach/common.h
> index 59133eb..cf02552 100644
> --- a/arch/arm/mach-mxs/include/mach/common.h
> +++ b/arch/arm/mach-mxs/include/mach/common.h
> @@ -13,6 +13,7 @@
>
> struct clk;
>
> +extern int mxs_read_ocotp(int offset, int count, u32 *values);
> extern int mxs_reset_block(void __iomem *);
> extern void mxs_timer_init(struct clk *, int);
>
> diff --git a/arch/arm/mach-mxs/ocotp.c b/arch/arm/mach-mxs/ocotp.c
> new file mode 100644
> index 0000000..e2d39aa
> --- /dev/null
> +++ b/arch/arm/mach-mxs/ocotp.c
> @@ -0,0 +1,79 @@
> +/*
> + * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/delay.h>
> +#include <linux/err.h>
> +#include <linux/mutex.h>
> +
> +#include <mach/mxs.h>
> +
> +#define BM_OCOTP_CTRL_BUSY (1 << 8)
> +#define BM_OCOTP_CTRL_ERROR (1 << 9)
> +#define BM_OCOTP_CTRL_RD_BANK_OPEN (1 << 12)
> +
> +static DEFINE_MUTEX(ocotp_mutex);
> +
> +int mxs_read_ocotp(unsigned offset, size_t count, u32 *values)
> +{
> + void __iomem *ocotp_base = MXS_IO_ADDRESS(MXS_OCOTP_BASE_ADDR);
> + int timeout = 0x400;
> + size_t i;
> +
> + mutex_lock(&ocotp_mutex);
> +
> + /*
> + * clk_enable(hbus_clk) for ocotp can be skipped
> + * as it must be on when system is running.
> + */
> +
> + /* try to clear ERROR bit */
> + __mxs_clrl(BM_OCOTP_CTRL_ERROR, ocotp_base);
This operation does not try to clear the error bit but actually clears
it...
> +
> + /* check both BUSY and ERROR cleared */
> + while ((__raw_readl(ocotp_base) &
> + (BM_OCOTP_CTRL_BUSY | BM_OCOTP_CTRL_ERROR)) && --timeout)
> + cpu_relax();
...which means you do not have to poll the error bit here...
> +
> + if (unlikely(!timeout))
> + goto error_unlock;
> +
> + /* open OCOTP banks for read */
> + __mxs_setl(BM_OCOTP_CTRL_RD_BANK_OPEN, ocotp_base);
> +
> + /* approximately wait 32 hclk cycles */
> + udelay(1);
> +
> + /* poll BUSY bit becoming cleared */
> + timeout = 0x400;
> + while ((__raw_readl(ocotp_base) & BM_OCOTP_CTRL_BUSY) && --timeout)
> + cpu_relax();
...which means you can factor out a ocotp_wait_busy function and let the
code speak instead of the comments.
> +
> + if (unlikely(!timeout))
> + goto error_unlock;
> +
> + for (i = 0; i < count; i++, offset += 4)
> + *values++ = __raw_readl(ocotp_base + offset);
The registers in the ocotp are 16 byte aligned. Does it really make
sense to provide a function allowing to read the gaps between the
registers?
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply
* [PATCH v4 05/10] net/fec: add dual fec support for mx28
From: Greg Ungerer @ 2011-01-11 13:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110111130749.GQ24920@pengutronix.de>
Hi Uwe,
On 11/01/11 23:07, Uwe Kleine-K?nig wrote:
> Hi Greg,
>
> On Tue, Jan 11, 2011 at 10:24:12PM +1000, Greg Ungerer wrote:
>> On 11/01/11 20:27, Sascha Hauer wrote:
>>> On Thu, Jan 06, 2011 at 03:13:13PM +0800, Shawn Guo wrote:
>>> This option is used nowhere and should be removed. Certainly it does not
>>> have the effect of enabling the second ethernet controller.
>>
>> It does for a ColdFire platform...
>>
>> grep -r CONFIG_FEC2 *
>>
>> arch/m68knommu/configs/m5275evb_defconfig:CONFIG_FEC2=y
>> arch/m68knommu/platform/527x/config.c:#ifdef CONFIG_FEC2
>> arch/m68knommu/platform/527x/config.c:#ifdef CONFIG_FEC2
> IMHO Sascha's comment[1] applies here, too.
I am not arguing that it doesn't :-)
Simply that removing that config option and doing nothing
else would not be the right thing to do.
Regards
Greg
> And someone might want to do what he suggested soon or the patch
> removing CONFIG_FEC2[2] needs to be commented accordingly.
>
> Best regards
> Uwe
>
> [1] http://thread.gmane.org/gmane.linux.network/182929/focus=183378
> [2] http://mid.gmane.org/1294747672-4433-1-git-send-email-shawn.guo at freescale.com
>
--
------------------------------------------------------------------------
Greg Ungerer -- Principal Engineer EMAIL: gerg at snapgear.com
SnapGear Group, McAfee PHONE: +61 7 3435 2888
8 Gardner Close, FAX: +61 7 3891 3630
Milton, QLD, 4064, Australia WEB: http://www.SnapGear.com
^ permalink raw reply
* [PATCH] ux500: Add Rohm BH1780GLI Light Sensor to i2c_board_info
From: Lee Jones @ 2011-01-11 13:10 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/mach-ux500/board-mop500.c | 11 +++++++++++
1 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 2635bb7..ff67408 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -134,6 +134,15 @@ static struct i2c_board_info mop500_i2c0_devices[] = {
},
};
+static struct i2c_board_info mop500_i2c2_devices[] = {
+#if defined(CONFIG_SENSORS_BH1780)
+ {
+ /* Light sensor Rohm BH1780GLI */
+ I2C_BOARD_INFO("bh1780", 0x29),
+ },
+#endif
+};
+
#define U8500_I2C_CONTROLLER(id, _slsu, _tft, _rft, clk, _sm) \
static struct nmk_i2c_controller u8500_i2c##id##_data = { \
/* \
@@ -322,6 +331,8 @@ static void __init u8500_init_machine(void)
i2c_register_board_info(0, mop500_i2c0_devices,
ARRAY_SIZE(mop500_i2c0_devices));
+ i2c_register_board_info(2, mop500_i2c2_devices,
+ ARRAY_SIZE(mop500_i2c0_devices));
}
MACHINE_START(U8500, "ST-Ericsson MOP500 platform")
--
1.7.1
^ permalink raw reply related
* [PATCH v4 05/10] net/fec: add dual fec support for mx28
From: Uwe Kleine-König @ 2011-01-11 13:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4D2C4BEC.1030003@snapgear.com>
Hi Greg,
On Tue, Jan 11, 2011 at 10:24:12PM +1000, Greg Ungerer wrote:
> On 11/01/11 20:27, Sascha Hauer wrote:
> >On Thu, Jan 06, 2011 at 03:13:13PM +0800, Shawn Guo wrote:
> >This option is used nowhere and should be removed. Certainly it does not
> >have the effect of enabling the second ethernet controller.
>
> It does for a ColdFire platform...
>
> grep -r CONFIG_FEC2 *
>
> arch/m68knommu/configs/m5275evb_defconfig:CONFIG_FEC2=y
> arch/m68knommu/platform/527x/config.c:#ifdef CONFIG_FEC2
> arch/m68knommu/platform/527x/config.c:#ifdef CONFIG_FEC2
IMHO Sascha's comment[1] applies here, too.
And someone might want to do what he suggested soon or the patch
removing CONFIG_FEC2[2] needs to be commented accordingly.
Best regards
Uwe
[1] http://thread.gmane.org/gmane.linux.network/182929/focus=183378
[2] http://mid.gmane.org/1294747672-4433-1-git-send-email-shawn.guo at freescale.com
--
Pengutronix e.K. | Uwe Kleine-K?nig |
Industrial Linux Solutions | http://www.pengutronix.de/ |
^ permalink raw reply
* [PATCH] ARM: nommu: avoid mapping vectors page when !CONFIG_MMU
From: Will Deacon @ 2011-01-11 13:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4D2C4E05.7050608@snapgear.com>
Hi Greg,
> > When running without an MMU, we do not need to install a mapping for the
> > vectors page. Attempting to do so causes a compile-time error because
> > install_special_mapping is not defined.
> >
> > This patch adds compile-time guards to the vector mapping functions
> > so that we can build nommu configurations once more.
> >
> > Cc: Greg Ungerer<gerg@uclinux.org>
> > Signed-off-by: Will Deacon<will.deacon@arm.com>
>
> I hit this a couple of days ago too, looks good.
>
> Acked-by: Greg Ungerer <gerg@uclinux.org>
Thanks. Submitted to Russell as 6619/1.
Will
^ permalink raw reply
* [PATCH 2/4] ARM: i.MX53 EVK: add spi device
From: Uwe Kleine-König @ 2011-01-11 13:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1294749950-8571-2-git-send-email-yong.shen@freescale.com>
Hi Yong,
On Tue, Jan 11, 2011 at 08:45:48PM +0800, yong.shen at freescale.com wrote:
> From: Yong Shen <yong.shen@freescale.com>
>
> 1. add platform data for spi device
> 2. Kconfig change
>
> Signed-off-by: Yong Shen <yong.shen@freescale.com>
> ---
> arch/arm/mach-mx5/Kconfig | 1 +
> arch/arm/mach-mx5/board-mx53_evk.c | 21 +++++++++++++++++++++
> 2 files changed, 22 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
> index 23b0e3f..777740b 100644
> --- a/arch/arm/mach-mx5/Kconfig
> +++ b/arch/arm/mach-mx5/Kconfig
> @@ -126,6 +126,7 @@ config MACH_MX53_EVK
> select IMX_HAVE_PLATFORM_IMX_UART
> select IMX_HAVE_PLATFORM_IMX_I2C
> select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
> + select IMX_HAVE_PLATFORM_SPI_IMX
> help
> Include support for MX53 EVK platform. This includes specific
> configurations for the board and its peripherals.
> diff --git a/arch/arm/mach-mx5/board-mx53_evk.c b/arch/arm/mach-mx5/board-mx53_evk.c
> index 4043451..739bc62 100644
> --- a/arch/arm/mach-mx5/board-mx53_evk.c
> +++ b/arch/arm/mach-mx5/board-mx53_evk.c
> @@ -33,6 +33,8 @@
> #include <mach/iomux-mx53.h>
>
> #define SMD_FEC_PHY_RST IMX_GPIO_NR(7, 6)
> +#define EVK_ECSPI1_CS0 IMX_GPIO_NR(2, 30)
> +#define EVK_ECSPI1_CS1 IMX_GPIO_NR(3, 19)
>
> #include "crm_regs.h"
> #include "devices-imx53.h"
> @@ -52,6 +54,13 @@ static iomux_v3_cfg_t mx53_evk_pads[] = {
> MX53_PAD_ATA_CS_1__UART3_RXD,
> MX53_PAD_ATA_DA_1__UART3_CTS,
> MX53_PAD_ATA_DA_2__UART3_RTS,
> +
> + MX53_PAD_EIM_D16__GPIO_3_16,
> + MX53_PAD_EIM_D17__GPIO_3_17,
> + MX53_PAD_EIM_D18__GPIO_3_18,
> +
> + MX53_PAD_EIM_EB2__GPIO_2_30,
> + MX53_PAD_EIM_D19__GPIO_3_19,
It would be nice to document what the pins are used for. For e.g.
MX53_PAD_ATA_DA_1__UART3_CTS it's quite obvious, but just from looking
at your patch I don't see what MX53_PAD_EIM_D1[678]__GPIO_3_1[678] are
used for.
Best regards
Uwe
> };
>
> static const struct imxuart_platform_data mx53_evk_uart_pdata __initconst = {
> @@ -89,6 +98,16 @@ static struct fec_platform_data mx53_evk_fec_pdata = {
> .phy = PHY_INTERFACE_MODE_RMII,
> };
>
> +static int mx53_evk_spi_cs[] = {
> + EVK_ECSPI1_CS0,
> + EVK_ECSPI1_CS1,
> +};
> +
> +static const struct spi_imx_master mx53_evk_spi_data __initconst = {
> + .chipselect = mx53_evk_spi_cs,
> + .num_chipselect = ARRAY_SIZE(mx53_evk_spi_cs),
> +};
> +
> static void __init mx53_evk_board_init(void)
> {
> mxc_iomux_v3_setup_multiple_pads(mx53_evk_pads,
> @@ -102,6 +121,8 @@ static void __init mx53_evk_board_init(void)
>
> imx53_add_sdhci_esdhc_imx(0, NULL);
> imx53_add_sdhci_esdhc_imx(1, NULL);
> +
> + imx53_add_ecspi(0, &mx53_evk_spi_data);
> }
>
> static void __init mx53_evk_timer_init(void)
> --
> 1.7.1
>
>
>
--
Pengutronix e.K. | Uwe Kleine-K?nig |
Industrial Linux Solutions | http://www.pengutronix.de/ |
^ permalink raw reply
* [PATCH v2 4/4] ARM: i.MX5: uart clock bug fix
From: yong.shen at freescale.com @ 2011-01-11 12:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1294750464-8660-1-git-send-email-yong.shen@freescale.com>
From: Yong Shen <yong.shen@freescale.com>
uart clk is from pll3 on mx53 instead of mx51
Signed-off-by: Yong Shen <yong.shen@freescale.com>
---
arch/arm/mach-mx5/clock-mx51-mx53.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c
index a20d0c0..3fb7ff8 100644
--- a/arch/arm/mach-mx5/clock-mx51-mx53.c
+++ b/arch/arm/mach-mx5/clock-mx51-mx53.c
@@ -1370,7 +1370,6 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
clk_tree_init();
- clk_set_parent(&uart_root_clk, &pll3_sw_clk);
clk_enable(&cpu_clk);
clk_enable(&main_bus_clk);
@@ -1413,6 +1412,7 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc,
clk_tree_init();
+ clk_set_parent(&uart_root_clk, &pll3_sw_clk);
clk_enable(&cpu_clk);
clk_enable(&main_bus_clk);
--
1.7.1
^ permalink raw reply related
* [PATCH v2 3/4] ARM: i.MX53 EVK: add spi nor device
From: yong.shen at freescale.com @ 2011-01-11 12:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1294750464-8660-1-git-send-email-yong.shen@freescale.com>
From: Yong Shen <yong.shen@freescale.com>
add spi board information for spi nor device
Signed-off-by: Yong Shen <yong.shen@freescale.com>
---
arch/arm/mach-mx5/board-mx53_evk.c | 15 +++++++++++++++
1 files changed, 15 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-mx5/board-mx53_evk.c b/arch/arm/mach-mx5/board-mx53_evk.c
index 739bc62..3b0d5ee 100644
--- a/arch/arm/mach-mx5/board-mx53_evk.c
+++ b/arch/arm/mach-mx5/board-mx53_evk.c
@@ -24,6 +24,8 @@
#include <linux/fec.h>
#include <linux/delay.h>
#include <linux/gpio.h>
+#include <linux/spi/flash.h>
+#include <linux/spi/spi.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
@@ -98,6 +100,17 @@ static struct fec_platform_data mx53_evk_fec_pdata = {
.phy = PHY_INTERFACE_MODE_RMII,
};
+static struct spi_board_info mx53_evk_spi_board_info[] __initdata = {
+ {
+ .modalias = "mtd_dataflash",
+ .max_speed_hz = 25000000,
+ .bus_num = 0,
+ .chip_select = 1,
+ .mode = SPI_MODE_0,
+ .platform_data = NULL,
+ },
+};
+
static int mx53_evk_spi_cs[] = {
EVK_ECSPI1_CS0,
EVK_ECSPI1_CS1,
@@ -122,6 +135,8 @@ static void __init mx53_evk_board_init(void)
imx53_add_sdhci_esdhc_imx(0, NULL);
imx53_add_sdhci_esdhc_imx(1, NULL);
+ spi_register_board_info(mx53_evk_spi_board_info,
+ ARRAY_SIZE(mx53_evk_spi_board_info));
imx53_add_ecspi(0, &mx53_evk_spi_data);
}
--
1.7.1
^ permalink raw reply related
* [PATCH v2 2/4] ARM: i.MX53 EVK: add spi device
From: yong.shen at freescale.com @ 2011-01-11 12:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1294750464-8660-1-git-send-email-yong.shen@freescale.com>
From: Yong Shen <yong.shen@freescale.com>
1. add platform data for spi device
2. Kconfig change
Signed-off-by: Yong Shen <yong.shen@freescale.com>
---
arch/arm/mach-mx5/Kconfig | 1 +
arch/arm/mach-mx5/board-mx53_evk.c | 21 +++++++++++++++++++++
2 files changed, 22 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
index 23b0e3f..777740b 100644
--- a/arch/arm/mach-mx5/Kconfig
+++ b/arch/arm/mach-mx5/Kconfig
@@ -126,6 +126,7 @@ config MACH_MX53_EVK
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+ select IMX_HAVE_PLATFORM_SPI_IMX
help
Include support for MX53 EVK platform. This includes specific
configurations for the board and its peripherals.
diff --git a/arch/arm/mach-mx5/board-mx53_evk.c b/arch/arm/mach-mx5/board-mx53_evk.c
index 4043451..739bc62 100644
--- a/arch/arm/mach-mx5/board-mx53_evk.c
+++ b/arch/arm/mach-mx5/board-mx53_evk.c
@@ -33,6 +33,8 @@
#include <mach/iomux-mx53.h>
#define SMD_FEC_PHY_RST IMX_GPIO_NR(7, 6)
+#define EVK_ECSPI1_CS0 IMX_GPIO_NR(2, 30)
+#define EVK_ECSPI1_CS1 IMX_GPIO_NR(3, 19)
#include "crm_regs.h"
#include "devices-imx53.h"
@@ -52,6 +54,13 @@ static iomux_v3_cfg_t mx53_evk_pads[] = {
MX53_PAD_ATA_CS_1__UART3_RXD,
MX53_PAD_ATA_DA_1__UART3_CTS,
MX53_PAD_ATA_DA_2__UART3_RTS,
+
+ MX53_PAD_EIM_D16__GPIO_3_16,
+ MX53_PAD_EIM_D17__GPIO_3_17,
+ MX53_PAD_EIM_D18__GPIO_3_18,
+
+ MX53_PAD_EIM_EB2__GPIO_2_30,
+ MX53_PAD_EIM_D19__GPIO_3_19,
};
static const struct imxuart_platform_data mx53_evk_uart_pdata __initconst = {
@@ -89,6 +98,16 @@ static struct fec_platform_data mx53_evk_fec_pdata = {
.phy = PHY_INTERFACE_MODE_RMII,
};
+static int mx53_evk_spi_cs[] = {
+ EVK_ECSPI1_CS0,
+ EVK_ECSPI1_CS1,
+};
+
+static const struct spi_imx_master mx53_evk_spi_data __initconst = {
+ .chipselect = mx53_evk_spi_cs,
+ .num_chipselect = ARRAY_SIZE(mx53_evk_spi_cs),
+};
+
static void __init mx53_evk_board_init(void)
{
mxc_iomux_v3_setup_multiple_pads(mx53_evk_pads,
@@ -102,6 +121,8 @@ static void __init mx53_evk_board_init(void)
imx53_add_sdhci_esdhc_imx(0, NULL);
imx53_add_sdhci_esdhc_imx(1, NULL);
+
+ imx53_add_ecspi(0, &mx53_evk_spi_data);
}
static void __init mx53_evk_timer_init(void)
--
1.7.1
^ permalink raw reply related
* [PATCH v2 1/4] ARM: i.MX53: enable spi support
From: yong.shen at freescale.com @ 2011-01-11 12:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1294750464-8660-1-git-send-email-yong.shen@freescale.com>
From: Yong Shen <yong.shen@freescale.com>
1. register spi clock
2. add macro definitions for spi platform data
3. fix some bugs of register and iomux definition
Signed-off-by: Yong Shen <yong.shen@freescale.com>
---
arch/arm/mach-mx5/clock-mx51-mx53.c | 3 +++
arch/arm/mach-mx5/devices-imx53.h | 4 ++++
arch/arm/plat-mxc/devices/platform-spi_imx.c | 12 ++++++++++++
arch/arm/plat-mxc/include/mach/iomux-mx53.h | 6 +++---
arch/arm/plat-mxc/include/mach/mx53.h | 10 +++++-----
5 files changed, 27 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c
index d0f58a3..a20d0c0 100644
--- a/arch/arm/mach-mx5/clock-mx51-mx53.c
+++ b/arch/arm/mach-mx5/clock-mx51-mx53.c
@@ -1330,6 +1330,9 @@ static struct clk_lookup mx53_lookups[] = {
_REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
_REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)
_REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk)
+ _REGISTER_CLOCK("imx53-ecspi.0", NULL, ecspi1_clk)
+ _REGISTER_CLOCK("imx53-ecspi.1", NULL, ecspi2_clk)
+ _REGISTER_CLOCK("imx53-cspi.0", NULL, cspi_clk)
};
static void clk_tree_init(void)
diff --git a/arch/arm/mach-mx5/devices-imx53.h b/arch/arm/mach-mx5/devices-imx53.h
index f7c89ef..8639735 100644
--- a/arch/arm/mach-mx5/devices-imx53.h
+++ b/arch/arm/mach-mx5/devices-imx53.h
@@ -25,3 +25,7 @@ extern const struct imx_sdhci_esdhc_imx_data
imx53_sdhci_esdhc_imx_data[] __initconst;
#define imx53_add_sdhci_esdhc_imx(id, pdata) \
imx_add_sdhci_esdhc_imx(&imx53_sdhci_esdhc_imx_data[id], pdata)
+
+extern const struct imx_spi_imx_data imx53_ecspi_data[] __initconst;
+#define imx53_add_ecspi(id, pdata) \
+ imx_add_spi_imx(&imx53_ecspi_data[id], pdata)
diff --git a/arch/arm/plat-mxc/devices/platform-spi_imx.c b/arch/arm/plat-mxc/devices/platform-spi_imx.c
index 8ea49ad..013c85f 100644
--- a/arch/arm/plat-mxc/devices/platform-spi_imx.c
+++ b/arch/arm/plat-mxc/devices/platform-spi_imx.c
@@ -81,6 +81,18 @@ const struct imx_spi_imx_data imx51_ecspi_data[] __initconst = {
};
#endif /* ifdef CONFIG_SOC_IMX51 */
+#ifdef CONFIG_SOC_IMX53
+const struct imx_spi_imx_data imx53_cspi_data __initconst =
+ imx_spi_imx_data_entry_single(MX53, CSPI, "imx53-cspi", 0, , SZ_4K);
+
+const struct imx_spi_imx_data imx53_ecspi_data[] __initconst = {
+#define imx53_ecspi_data_entry(_id, _hwid) \
+ imx_spi_imx_data_entry(MX53, ECSPI, "imx53-ecspi", _id, _hwid, SZ_4K)
+ imx53_ecspi_data_entry(0, 1),
+ imx53_ecspi_data_entry(1, 2),
+};
+#endif /* ifdef CONFIG_SOC_IMX53 */
+
struct platform_device *__init imx_add_spi_imx(
const struct imx_spi_imx_data *data,
const struct spi_imx_master *pdata)
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx53.h b/arch/arm/plat-mxc/include/mach/iomux-mx53.h
index 2673007..02f1ff3 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx53.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx53.h
@@ -131,9 +131,9 @@ typedef enum iomux_config {
#define MX53_PAD_JTAG_TDO__JTAG_TDO IOMUX_PAD(0x454, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
#define MX53_PAD_EIM_A25__GPIO_5_2 IOMUX_PAD(0x458, 0x110,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
#define MX53_PAD_EIM_EB2__GPIO_2_30 IOMUX_PAD(0x45C, 0x114,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D16__GPIO_3_16 IOMUX_PAD(0x460, 0x118,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D17__GPIO_3_17 IOMUX_PAD(0x464, 0x11C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D18__GPIO_3_18 IOMUX_PAD(0x468, 0x120,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D16__GPIO_3_16 IOMUX_PAD(0x460, 0x118,IOMUX_CONFIG_ALT4, 0x79c, 3, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D17__GPIO_3_17 IOMUX_PAD(0x464, 0x11C,IOMUX_CONFIG_ALT4, 0x7a0, 3, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D18__GPIO_3_18 IOMUX_PAD(0x468, 0x120,IOMUX_CONFIG_ALT4, 0x7a4, 3, NO_PAD_CTRL)
#define MX53_PAD_EIM_D19__GPIO_3_19 IOMUX_PAD(0x46C, 0x124,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
#define MX53_PAD_EIM_D20__GPIO_3_20 IOMUX_PAD(0x470, 0x128,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
#define MX53_PAD_EIM_D21__GPIO_3_21 IOMUX_PAD(0x474, 0x12C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
diff --git a/arch/arm/plat-mxc/include/mach/mx53.h b/arch/arm/plat-mxc/include/mach/mx53.h
index 340937f..d7a8e52 100644
--- a/arch/arm/plat-mxc/include/mach/mx53.h
+++ b/arch/arm/plat-mxc/include/mach/mx53.h
@@ -56,7 +56,7 @@
#define MX53_ESDHC1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00004000)
#define MX53_ESDHC2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00008000)
#define MX53_UART3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0000C000)
-#define MX53_CSPI1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00010000)
+#define MX53_ECSPI1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00010000)
#define MX53_SSI2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00014000)
#define MX53_ESDHC3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00020000)
#define MX53_ESDHC4_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00024000)
@@ -117,12 +117,12 @@
#define MX53_ARM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A0000)
#define MX53_OWIRE_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A4000)
#define MX53_FIRI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A8000)
-#define MX53_CSPI2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000AC000)
+#define MX53_ECSPI2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000AC000)
#define MX53_SDMA_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B0000)
#define MX53_SCC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B4000)
#define MX53_ROMCP_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B8000)
#define MX53_RTIC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000BC000)
-#define MX53_CSPI3_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C0000)
+#define MX53_CSPI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C0000)
#define MX53_I2C2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C4000)
#define MX53_I2C1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C8000)
#define MX53_SSI1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000CC000)
@@ -264,8 +264,8 @@
#define MX53_INT_UART3 33
#define MX53_INT_RESV34 34
#define MX53_INT_RESV35 35
-#define MX53_INT_CSPI1 36
-#define MX53_INT_CSPI2 37
+#define MX53_INT_ECSPI1 36
+#define MX53_INT_ECSPI2 37
#define MX53_INT_CSPI 38
#define MX53_INT_GPT 39
#define MX53_INT_EPIT1 40
--
1.7.1
^ permalink raw reply related
* ARM: i.MX53: spi related patches
From: yong.shen at freescale.com @ 2011-01-11 12:54 UTC (permalink / raw)
To: linux-arm-kernel
Change log:
1. the spi_imx driver changes are seperated from this patch set and sent to spi dev list
2. addressed comments from Uwe and Sascha
3. Add spi nor device by the way
Yong
^ permalink raw reply
* [PATCH 2/4] ARM: i.MX53 EVK: add spi device
From: Yong Shen @ 2011-01-11 12:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1294749950-8571-2-git-send-email-yong.shen@freescale.com>
Please ignore this one.
Yong
On Tue, Jan 11, 2011 at 8:45 PM, <yong.shen@freescale.com> wrote:
> From: Yong Shen <yong.shen@freescale.com>
>
> 1. add platform data for spi device
> 2. Kconfig change
>
> Signed-off-by: Yong Shen <yong.shen@freescale.com>
> ---
> ?arch/arm/mach-mx5/Kconfig ? ? ? ? ?| ? ?1 +
> ?arch/arm/mach-mx5/board-mx53_evk.c | ? 21 +++++++++++++++++++++
> ?2 files changed, 22 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
> index 23b0e3f..777740b 100644
> --- a/arch/arm/mach-mx5/Kconfig
> +++ b/arch/arm/mach-mx5/Kconfig
> @@ -126,6 +126,7 @@ config MACH_MX53_EVK
> ? ? ? ?select IMX_HAVE_PLATFORM_IMX_UART
> ? ? ? ?select IMX_HAVE_PLATFORM_IMX_I2C
> ? ? ? ?select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
> + ? ? ? select IMX_HAVE_PLATFORM_SPI_IMX
> ? ? ? ?help
> ? ? ? ? ?Include support for MX53 EVK platform. This includes specific
> ? ? ? ? ?configurations for the board and its peripherals.
> diff --git a/arch/arm/mach-mx5/board-mx53_evk.c b/arch/arm/mach-mx5/board-mx53_evk.c
> index 4043451..739bc62 100644
> --- a/arch/arm/mach-mx5/board-mx53_evk.c
> +++ b/arch/arm/mach-mx5/board-mx53_evk.c
> @@ -33,6 +33,8 @@
> ?#include <mach/iomux-mx53.h>
>
> ?#define SMD_FEC_PHY_RST ? ? ? ? ? ? ? ?IMX_GPIO_NR(7, 6)
> +#define EVK_ECSPI1_CS0 ? ? ? ? IMX_GPIO_NR(2, 30)
> +#define EVK_ECSPI1_CS1 ? ? ? ? IMX_GPIO_NR(3, 19)
>
> ?#include "crm_regs.h"
> ?#include "devices-imx53.h"
> @@ -52,6 +54,13 @@ static iomux_v3_cfg_t mx53_evk_pads[] = {
> ? ? ? ?MX53_PAD_ATA_CS_1__UART3_RXD,
> ? ? ? ?MX53_PAD_ATA_DA_1__UART3_CTS,
> ? ? ? ?MX53_PAD_ATA_DA_2__UART3_RTS,
> +
> + ? ? ? MX53_PAD_EIM_D16__GPIO_3_16,
> + ? ? ? MX53_PAD_EIM_D17__GPIO_3_17,
> + ? ? ? MX53_PAD_EIM_D18__GPIO_3_18,
> +
> + ? ? ? MX53_PAD_EIM_EB2__GPIO_2_30,
> + ? ? ? MX53_PAD_EIM_D19__GPIO_3_19,
> ?};
>
> ?static const struct imxuart_platform_data mx53_evk_uart_pdata __initconst = {
> @@ -89,6 +98,16 @@ static struct fec_platform_data mx53_evk_fec_pdata = {
> ? ? ? ?.phy = PHY_INTERFACE_MODE_RMII,
> ?};
>
> +static int mx53_evk_spi_cs[] = {
> + ? ? ? EVK_ECSPI1_CS0,
> + ? ? ? EVK_ECSPI1_CS1,
> +};
> +
> +static const struct spi_imx_master mx53_evk_spi_data __initconst = {
> + ? ? ? .chipselect ? ? = mx53_evk_spi_cs,
> + ? ? ? .num_chipselect = ARRAY_SIZE(mx53_evk_spi_cs),
> +};
> +
> ?static void __init mx53_evk_board_init(void)
> ?{
> ? ? ? ?mxc_iomux_v3_setup_multiple_pads(mx53_evk_pads,
> @@ -102,6 +121,8 @@ static void __init mx53_evk_board_init(void)
>
> ? ? ? ?imx53_add_sdhci_esdhc_imx(0, NULL);
> ? ? ? ?imx53_add_sdhci_esdhc_imx(1, NULL);
> +
> + ? ? ? imx53_add_ecspi(0, &mx53_evk_spi_data);
> ?}
>
> ?static void __init mx53_evk_timer_init(void)
> --
> 1.7.1
>
>
>
^ permalink raw reply
* [PATCH 2/4] ARM: i.MX53 EVK: add spi device
From: yong.shen at freescale.com @ 2011-01-11 12:45 UTC (permalink / raw)
To: linux-arm-kernel
From: Yong Shen <yong.shen@freescale.com>
1. add platform data for spi device
2. Kconfig change
Signed-off-by: Yong Shen <yong.shen@freescale.com>
---
arch/arm/mach-mx5/Kconfig | 1 +
arch/arm/mach-mx5/board-mx53_evk.c | 21 +++++++++++++++++++++
2 files changed, 22 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
index 23b0e3f..777740b 100644
--- a/arch/arm/mach-mx5/Kconfig
+++ b/arch/arm/mach-mx5/Kconfig
@@ -126,6 +126,7 @@ config MACH_MX53_EVK
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+ select IMX_HAVE_PLATFORM_SPI_IMX
help
Include support for MX53 EVK platform. This includes specific
configurations for the board and its peripherals.
diff --git a/arch/arm/mach-mx5/board-mx53_evk.c b/arch/arm/mach-mx5/board-mx53_evk.c
index 4043451..739bc62 100644
--- a/arch/arm/mach-mx5/board-mx53_evk.c
+++ b/arch/arm/mach-mx5/board-mx53_evk.c
@@ -33,6 +33,8 @@
#include <mach/iomux-mx53.h>
#define SMD_FEC_PHY_RST IMX_GPIO_NR(7, 6)
+#define EVK_ECSPI1_CS0 IMX_GPIO_NR(2, 30)
+#define EVK_ECSPI1_CS1 IMX_GPIO_NR(3, 19)
#include "crm_regs.h"
#include "devices-imx53.h"
@@ -52,6 +54,13 @@ static iomux_v3_cfg_t mx53_evk_pads[] = {
MX53_PAD_ATA_CS_1__UART3_RXD,
MX53_PAD_ATA_DA_1__UART3_CTS,
MX53_PAD_ATA_DA_2__UART3_RTS,
+
+ MX53_PAD_EIM_D16__GPIO_3_16,
+ MX53_PAD_EIM_D17__GPIO_3_17,
+ MX53_PAD_EIM_D18__GPIO_3_18,
+
+ MX53_PAD_EIM_EB2__GPIO_2_30,
+ MX53_PAD_EIM_D19__GPIO_3_19,
};
static const struct imxuart_platform_data mx53_evk_uart_pdata __initconst = {
@@ -89,6 +98,16 @@ static struct fec_platform_data mx53_evk_fec_pdata = {
.phy = PHY_INTERFACE_MODE_RMII,
};
+static int mx53_evk_spi_cs[] = {
+ EVK_ECSPI1_CS0,
+ EVK_ECSPI1_CS1,
+};
+
+static const struct spi_imx_master mx53_evk_spi_data __initconst = {
+ .chipselect = mx53_evk_spi_cs,
+ .num_chipselect = ARRAY_SIZE(mx53_evk_spi_cs),
+};
+
static void __init mx53_evk_board_init(void)
{
mxc_iomux_v3_setup_multiple_pads(mx53_evk_pads,
@@ -102,6 +121,8 @@ static void __init mx53_evk_board_init(void)
imx53_add_sdhci_esdhc_imx(0, NULL);
imx53_add_sdhci_esdhc_imx(1, NULL);
+
+ imx53_add_ecspi(0, &mx53_evk_spi_data);
}
static void __init mx53_evk_timer_init(void)
--
1.7.1
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