* [PATCH 2/2] ARM i.MX23/28: Add framebuffer device support
From: Li Frank-B20596 @ 2011-02-10 3:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297257651-8002-3-git-send-email-s.hauer@pengutronix.de>
> diff --git a/arch/arm/mach-mxs/clock-mx23.c b/arch/arm/mach-mxs/clock-
> mx23.c
> index ca72a05..bfc7f27 100644
> --- a/arch/arm/mach-mxs/clock-mx23.c
> +++ b/arch/arm/mach-mxs/clock-mx23.c
> @@ -446,7 +446,7 @@ static struct clk_lookup lookups[] = {
> _REGISTER_CLOCK(NULL, "hclk", hbus_clk)
> _REGISTER_CLOCK(NULL, "usb", usb_clk)
> _REGISTER_CLOCK(NULL, "audio", audio_clk)
> - _REGISTER_CLOCK(NULL, "pwm", pwm_clk)
> + _REGISTER_CLOCK("imx23-fb", NULL, lcdif_clk)
> };
Why remove mx23 pwm clk here?
^ permalink raw reply
* [PATCH 1/2] video: Add i.MX23/28 framebuffer driver
From: Li Frank-B20596 @ 2011-02-10 3:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297257651-8002-2-git-send-email-s.hauer@pengutronix.de>
> +#define CTRL 0x00
> +#define CTRL1 0x10
> +#define MX28_CTRL2 0x20
> +#define MX23_TRANSFER_COUNT 0x20
> +#define MX28_TRANSFER_COUNT 0x30
> +#define MX28_CUR_BUF 0x40
> +#define MX28_NEXT_BUF 0x50
> +#define MX23_CUR_BUF 0x30
> +#define MX23_NEXT_BUF 0x40
> +#define TIMING 0x60
> +#define VDCTRL0 0x70
> +#define VDCTRL1 0x80
> +#define VDCTRL2 0x90
> +#define VDCTRL3 0xa0
> +#define VDCTRL4 0xb0
Why you give up mx23/mx28 register define role, which generate from SOC xml.
There is a set header files for each mx23/mx28 module, which generate from xml.
I know original header files affect run time one Image.
But I think we can copy common part of such register definition because
That keep consistent with mx23/mx28 data sheet. Data sheet and header file generate
from one source xml.
HW_<Module name>_<Register name>.
BM_<Module name>_<Register name>_Bit name.
^ permalink raw reply
* [PATCH v3 2/5] ARM: pm: add generic CPU suspend/resume support
From: Colin Cross @ 2011-02-10 3:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110207141734.GG31929@n2100.arm.linux.org.uk>
On Mon, Feb 7, 2011 at 6:17 AM, Russell King - ARM Linux
<linux@arm.linux.org.uk> wrote:
> diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
> index 0c1172b..a5187dd 100644
> --- a/arch/arm/mm/proc-v7.S
> +++ b/arch/arm/mm/proc-v7.S
> +ENTRY(cpu_v7_do_suspend)
> + ? ? ? stmfd ? sp!, {r4 - r11, lr}
> + ? ? ? mrc ? ? p15, 0, r4, c13, c0, 0 ?@ FCSE/PID
> + ? ? ? mrc ? ? p15, 0, r5, c13, c0, 1 ?@ Context ID
> + ? ? ? mrc ? ? p15, 0, r6, c3, c0, 0 ? @ Domain ID
> + ? ? ? mrc ? ? p15, 0, r7, c2, c0, 0 ? @ TTB 0
> + ? ? ? mrc ? ? p15, 0, r8, c2, c0, 1 ? @ TTB 1
> + ? ? ? mrc ? ? p15, 0, r9, c1, c0, 0 ? @ Control register
> + ? ? ? mrc ? ? p15, 0, r10, c1, c0, 1 ?@ Auxiliary control register
> + ? ? ? mrc ? ? p15, 0, r11, c1, c0, 2 ?@ Co-processor access control
The diagnostic register also needs to be saved to keep the errata bits
set in __v7_setup.
> + ? ? ? stmia ? r0, {r4 - r11}
> + ? ? ? ldmfd ? sp!, {r4 - r11, pc}
> +ENDPROC(cpu_v7_do_suspend)
> +
> +ENTRY(cpu_v7_do_resume)
> + ? ? ? mov ? ? ip, #0
> + ? ? ? mcr ? ? p15, 0, ip, c8, c7, 0 ? @ invalidate TLBs
> + ? ? ? mcr ? ? p15, 0, ip, c7, c5, 0 ? @ invalidate I cache
Does this need the same ALT_SMP/ALT_UP combo as v7_flush_icache_all?
<snip>
Tegra2 suspend and cpuidle works on top of this patch and the patch
that adds SMP support to sleep_save_sp. Tegra seems to need to
invalidate the entire l1 data cache before enabling it, so I'm using a
custom reset vector that branches to cpu_resume, and I'm handling the
TLB invalidate in the function cpu_resume returns to.
Tested-by: Colin Cross <ccross@android.com>
Are you targeting 2.6.39 with these patches? They replace a few
hundred lines of code in the Tegra2 suspend, hotplug, and idle
patches, so I'd like to wait until this is in before pushing mine.
^ permalink raw reply
* [PATCH]ARM: mmp: add Trizeps6 board support
From: Eric Miao @ 2011-02-10 2:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <AANLkTikHbJ+x0nEvdXQpzADwT3XfJNqR6O_WzaEtFWnh@mail.gmail.com>
Corrected the linux-arm-kernel ML address.
On Thu, Feb 10, 2011 at 10:24 AM, Eric Miao <eric.y.miao@gmail.com> wrote:
> On Thu, Feb 10, 2011 at 7:53 AM, Yupeng Schneider
> <yupeng.schneider@ipms.fraunhofer.de> wrote:
>> Hi all,
>>
>> the following patch add the BSP for the Trizeps6 board with pxa168 Processor.
>>
>> Signed-off-by: Yupeng Schneider <yupeng.schneider@googlemail.com>
>
> Hi Yupeng,
>
> This is really a nice patch. I would be better if this can be separated into
> some smaller patches further:
>
> 1. some of the MFP macros in trizeps6.h, they are generic and can be
> placed into mfp-pxa168.h, or is there any reason that the macros in
> mfp-pxa168.h do not work on your board?
>
> 2. individual patches for adding uart3, audio, and cpld
>
> 3. then the patch for the board
>
> Sounds OK? Let me know your ideas.
>
> Thanks
> - eric
>
>> ---
>> ?arch/arm/mach-mmp/Kconfig ? ? ? ? ? ? ? ? ? ? ?| ? 29 ++
>> ?arch/arm/mach-mmp/Makefile ? ? ? ? ? ? ? ? ? ? | ? ?1 +
>> ?arch/arm/mach-mmp/include/mach/audio.h ? ? ? ? | ? 29 ++
>> ?arch/arm/mach-mmp/include/mach/pxa168.h ? ? ? ?| ? 21 +
>> ?arch/arm/mach-mmp/include/mach/regs-apmu.h ? ? | ? ?1 +
>> ?arch/arm/mach-mmp/include/mach/trizeps6.h ? ? ?| ?122 ++++++
>> ?arch/arm/mach-mmp/include/mach/trizeps6_cpld.h | ? 87 +++++
>> ?arch/arm/mach-mmp/pxa168.c ? ? ? ? ? ? ? ? ? ? | ? 10 +
>> ?arch/arm/mach-mmp/trizeps6.c ? ? ? ? ? ? ? ? ? | ?469
>> ++++++++++++++++++++++++
>> ?arch/arm/mach-mmp/trizeps6_cpld.c ? ? ? ? ? ? ?| ?145 ++++++++
>> ?10 files changed, 914 insertions(+), 0 deletions(-)
>> ?create mode 100755 arch/arm/mach-mmp/include/mach/audio.h
>> ?create mode 100755 arch/arm/mach-mmp/include/mach/trizeps6.h
>> ?create mode 100755 arch/arm/mach-mmp/include/mach/trizeps6_cpld.h create
>> mode 100755 arch/arm/mach-mmp/trizeps6.c
>> ?create mode 100755 arch/arm/mach-mmp/trizeps6_cpld.c
>>
>> diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig index
>> 0711d3b..8c6be81 100644
>> --- a/arch/arm/mach-mmp/Kconfig
>> +++ b/arch/arm/mach-mmp/Kconfig
>> @@ -64,6 +64,35 @@ config MACH_TETON_BGA
>> ? ? ? ? ?Say 'Y' here if you want to support the Marvell PXA168-based
>> ? ? ? ? ?Teton BGA Development Board.
>>
>> +comment "Third Party Dev Platforms (sorted by vendor name)"
>> +
>> +config MACH_TRIZEPS6
>> + ? ? ? bool "Keith und Koep Trizeps6 DIMM-Module"
>> + ? ? ? select TRIZEPS6_PCMCIA
>> + ? ? ? select CPU_PXA168
>> + ? ? ? help
>> + ? ? ? ? Say 'Y' here if you want to support TRIZEPS VI board Development Board.
>> +
>> +choice
>> + ? ? ? prompt "Select base board for Trizeps module"
>> + ? ? ? depends on MACH_TRIZEPS6
>> +
>> +config MACH_TRIZEPS6_CONXS
>> + ? ? ? bool "ConXS Eval Board"
>> +
>> +config MACH_TRIZEPS6_UCONXS
>> + ? ? ? bool "uConXS Eval Board"
>> +
>> +config MACH_TRIZEPS6_ANY
>> + ? ? ? bool "another Board"
>> +
>> +endchoice
>> +
>> +config TRIZEPS6_PCMCIA
>> + ? ? ? bool
>> + ? ? ? help
>> + ? ? ? ? Enable PCMCIA support for Trizeps modules
>> +
>> ?endmenu
>>
>> ?config CPU_PXA168
>> diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile index
>> 751cdbf..1b8744f 100644
>> --- a/arch/arm/mach-mmp/Makefile
>> +++ b/arch/arm/mach-mmp/Makefile
>> @@ -18,3 +18,4 @@ obj-$(CONFIG_MACH_TTC_DKB) ? ?+= ttc_dkb.o
>> ?obj-$(CONFIG_MACH_FLINT) ? ? ? += flint.o
>> ?obj-$(CONFIG_MACH_MARVELL_JASPER) += jasper.o
>> ?obj-$(CONFIG_MACH_TETON_BGA) ? += teton_bga.o
>> +obj-$(CONFIG_MACH_TRIZEPS6) ? ?+= trizeps6.o trizeps6_cpld.o
>> diff --git a/arch/arm/mach-mmp/include/mach/audio.h
>> b/arch/arm/mach-mmp/include/mach/audio.h
>> index 0000000..6ef474f
>> --- /dev/null
>> +++ b/arch/arm/mach-mmp/include/mach/audio.h
>> @@ -0,0 +1,29 @@
>> +#ifndef __ASM_ARCH_AUDIO_H__
>> +#define __ASM_ARCH_AUDIO_H__
>> +
>> +#include <sound/core.h>
>> +#include <sound/pcm.h>
>> +#include <sound/ac97_codec.h>
>> +
>> +/*
>> + * @reset_gpio: AC97 reset gpio (normally gpio113 or gpio95)
>> + * ? ? ? ? ? ? ?a -1 value means no gpio will be used for reset
>> + * @codec_pdata: AC97 codec platform_data
>> +
>> + * reset_gpio should only be specified for pxa27x CPUs where a silicon +
>> * bug prevents correct operation of the reset line. If not specified, + *
>> the default behaviour on these CPUs is to consider gpio 113 as the + *
>> AC97 reset line, which is the default on most boards.
>> + */
>> +struct pxa2xx_audio_ops_t {
>> + ? ? ? int (*startup)(struct snd_pcm_substream *, void *);
>> + ? ? ? void (*shutdown)(struct snd_pcm_substream *, void *);
>> + ? ? ? void (*suspend)(void *);
>> + ? ? ? void (*resume)(void *);
>> + ? ? ? void *priv;
>> + ? ? ? int reset_gpio;
>> + ? ? ? void *codec_pdata[AC97_BUS_MAX_DEVICES];
>> +};
>> +
>> +
>> +#endif
>> diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h
>> b/arch/arm/mach-mmp/include/mach/pxa168.h
>> index 1801e42..c4a9977 100644
>> --- a/arch/arm/mach-mmp/include/mach/pxa168.h
>> +++ b/arch/arm/mach-mmp/include/mach/pxa168.h
>> @@ -14,9 +14,12 @@ extern void pxa168_clear_keypad_wakeup(void);
>> ?#include <video/pxa168fb.h>
>> ?#include <plat/pxa27x_keypad.h>
>> ?#include <mach/cputype.h>
>> +#include <linux/pxa168_eth.h>
>> +#include <mach/audio.h>
>>
>> ?extern struct pxa_device_desc pxa168_device_uart1;
>> ?extern struct pxa_device_desc pxa168_device_uart2;
>> +extern struct pxa_device_desc pxa168_device_uart3;
>> ?extern struct pxa_device_desc pxa168_device_twsi0;
>> ?extern struct pxa_device_desc pxa168_device_twsi1;
>> ?extern struct pxa_device_desc pxa168_device_pwm1;
>> @@ -31,6 +34,9 @@ extern struct pxa_device_desc pxa168_device_ssp5;
>> ?extern struct pxa_device_desc pxa168_device_nand;
>> ?extern struct pxa_device_desc pxa168_device_fb;
>> ?extern struct pxa_device_desc pxa168_device_keypad;
>> +extern struct pxa_device_desc pxa168_device_mfu;
>> +extern struct pxa_device_desc pxa168_device_ac97;
>> +
>>
>> ?static inline int pxa168_add_uart(int id)
>> ?{
>> @@ -39,6 +45,7 @@ static inline int pxa168_add_uart(int id)
>> ? ? ? ?switch (id) {
>> ? ? ? ?case 1: d = &pxa168_device_uart1; break;
>> ? ? ? ?case 2: d = &pxa168_device_uart2; break;
>> + ? ? ? case 3: d = &pxa168_device_uart3; break;
>> ? ? ? ?}
>>
>> ? ? ? ?if (d == NULL)
>> @@ -117,4 +124,18 @@ static inline int pxa168_add_keypad(struct
>> pxa27x_keypad_platform_data *data)
>> ? ? ? ?return pxa_register_device(&pxa168_device_keypad, data, sizeof(*data));
>> ?}
>>
>> +static inline int pxa168_add_mfu(struct pxa168_eth_platform_data *data) +{
>> +#if defined(CONFIG_PXA168_ETH)
>> + ? ? ? return pxa_register_device(&pxa168_device_mfu, data, sizeof(*data)); +#else
>> + ? ? ? return 0;
>> +#endif
>> +}
>> +
>> +static inline int pxa168_add_ac97(struct pxa2xx_audio_ops_t *ops) +{
>> + ? ? ? return pxa_register_device(&pxa168_device_ac97, ops , sizeof(*ops)); +}
>> +
>> ?#endif /* __ASM_MACH_PXA168_H */
>> diff --git a/arch/arm/mach-mmp/include/mach/regs-apmu.h
>> b/arch/arm/mach-mmp/include/mach/regs-apmu.h
>> index ac47023..68d39bc 100644
>> --- a/arch/arm/mach-mmp/include/mach/regs-apmu.h
>> +++ b/arch/arm/mach-mmp/include/mach/regs-apmu.h
>> @@ -27,6 +27,7 @@
>> ?#define APMU_DMA ? ? ? APMU_REG(0x064)
>> ?#define APMU_GEU ? ? ? APMU_REG(0x068)
>> ?#define APMU_BUS ? ? ? APMU_REG(0x06c)
>> +#define APMU_MFU ? ? ? APMU_REG(0x0fc)
>>
>> ?#define APMU_FNCLK_EN ?(1 << 4)
>> ?#define APMU_AXICLK_EN (1 << 3)
>> diff --git a/arch/arm/mach-mmp/include/mach/trizeps6.h
>> b/arch/arm/mach-mmp/include/mach/trizeps6.h
>> index 0000000..40b526a
>> --- /dev/null
>> +++ b/arch/arm/mach-mmp/include/mach/trizeps6.h
>> @@ -0,0 +1,122 @@
>> +/************************************************************************
>> + * Include file for TRIZEPS6 SoM and ConXS eval-board
>> + * Copyright (c) Yupeng Schneider
>> + * 2010
>> +
>> ************************************************************************/ +
>> +/*
>> + * Includes/Defines
>> + */
>> +#ifndef _TRIPEPS6_H_
>> +#define _TRIPEPS6_H_
>> +
>> +#define STUART_SODIMM ?1
>> +
>> +/* UART */
>> +#define GPIO104_UART1_DSR ? ? ?MFP_CFG(GPIO104, AF2)
>> +#define GPIO105_UART1_DCD ? ? ?MFP_CFG(GPIO105, AF2)
>> +#define GPIO107_UART2_TXD ? ? ?MFP_CFG_DRV(GPIO126, AF2, FAST)
>> +#define GPIO107_UART2_RXD ? ? ?MFP_CFG_DRV(GPIO36, AF2, FAST)
>> +#define GPIO109_UART2_CTS ? ? ?MFP_CFG(GPIO123, AF2)
>> +#define GPIO109_UART2_RTS ? ? ?MFP_CFG(GPIO124, AF2)
>> +#define GPIO30_UART3_TXD ? ? ? MFP_CFG_DRV(GPIO30, AF2, FAST)
>> +#define GPIO31_UART3_RXD ? ? ? MFP_CFG_DRV(GPIO31, AF2, FAST)
>> +#define GPIO32_UART3_CTS ? ? ? MFP_CFG(GPIO32, AF2)
>> +#define GPIO33_UART3_RTS ? ? ? MFP_CFG(GPIO33, AF2)
>> +
>> +/* MMC2 */
>> +#define ? ? ? ?GPIO122_MMC2_DAT3 ? ? ? MFP_CFG_DRV(GPIO122, AF4, FAST)
>> +#define ? ? ? ?GPIO121_MMC2_DAT2 ? ? ? MFP_CFG_DRV(GPIO121, AF4, FAST)
>> +#define ? ? ? ?GPIO120_MMC2_DAT1 ? ? ? MFP_CFG_DRV(GPIO120, AF4, FAST)
>> +#define ? ? ? ?GPIO119_MMC2_DAT0 ? ? ? MFP_CFG_DRV(GPIO119, AF4, FAST)
>> +#define ? ? ? ?GPIO28_MMC2_CMD ? ? ? ? MFP_CFG_DRV(GPIO28, AF6, FAST)
>> +#define ? ? ? ?GPIO29_MMC2_CLK ? ? ? ? MFP_CFG_DRV(GPIO29, AF6, FAST)
>> +#define GPIO53_MMC2_CD ? ? ? ? MFP_CFG(GPIO53, AF0)
>> +
>> +/*MMC4*/
>> +#define ? ? ? ?GPIO78_MMC4_DAT3 ? ? ? ?MFP_CFG_DRV(GPIO78, AF5, FAST)
>> +#define ? ? ? ?GPIO79_MMC4_DAT2 ? ? ? ?MFP_CFG_DRV(GPIO79, AF5, FAST)
>> +#define ? ? ? ?GPIO80_MMC4_DAT1 ? ? ? ?MFP_CFG_DRV(GPIO80, AF5, FAST)
>> +#define ? ? ? ?GPIO81_MMC4_DAT0 ? ? ? ?MFP_CFG_DRV(GPIO81, AF5, FAST)
>> +#define ? ? ? ?GPIO82_MMC4_CMD ? ? ? ? MFP_CFG_DRV(GPIO82, AF5, FAST)
>> +#define ? ? ? ?GPIO83_MMC4_CLK ? ? ? ? MFP_CFG_DRV(GPIO83, AF5, FAST)
>> +
>> +/* I2C */
>> +#define GPIO102_CI2C_SDA ? ? ? MFP_CFG(GPIO102, AF1)
>> +
>> +/* MFU */
>> +#define GPIO86_TX_CLK ? MFP_CFG(GPIO86, AF5)
>> +#define GPIO87_TX_EN ? ?MFP_CFG(GPIO87, AF5)
>> +#define GPIO88_TX_DQ3 ? MFP_CFG(GPIO88, AF5)
>> +#define GPIO89_TX_DQ2 ? MFP_CFG(GPIO89, AF5)
>> +#define GPIO90_TX_DQ1 ? MFP_CFG(GPIO90, AF5)
>> +#define GPIO91_TX_DQ0 ? MFP_CFG(GPIO91, AF5)
>> +#define GPIO92_MII_CRS ? MFP_CFG(GPIO92, AF5)
>> +#define GPIO93_MII_COL ? MFP_CFG(GPIO93, AF5)
>> +#define GPIO94_RX_CLK ? MFP_CFG(GPIO94, AF5)
>> +#define GPIO95_RX_ER ? MFP_CFG(GPIO95, AF5)
>> +#define GPIO96_RX_DQ3 ? MFP_CFG(GPIO96, AF5)
>> +#define GPIO97_RX_DQ2 ? MFP_CFG(GPIO97, AF5)
>> +#define GPIO98_RX_DQ1 ? MFP_CFG(GPIO98, AF5)
>> +#define GPIO99_RX_DQ0 ? MFP_CFG(GPIO99, AF5)
>> +#define GPIO100_MII_MDC ? MFP_CFG(GPIO100, AF5)
>> +#define GPIO101_MII_MDIO ? MFP_CFG(GPIO101, AF5)
>> +#define GPIO103_RX_DV ? MFP_CFG(GPIO103, AF5)
>> +
>> +/* AC97 */
>> +#define GPIO115_AC97_BITCLK ? ?MFP_CFG(GPIO115, AF6)
>> +#define GPIO114_AC97_SDATA_IN_0 ? ? ? ?MFP_CFG(GPIO114, AF6)
>> +#define GPIO116_AC97_SDATA_IN_1 ? ? ? ?MFP_CFG(GPIO116, AF6)
>> +#define GPIO117_AC97_SDATA_OUT MFP_CFG(GPIO117, AF6)
>> +#define GPIO118_AC97_SYNC ? ? ?MFP_CFG(GPIO118, AF6)
>> +
>> +
>> +
>> +#define TRIZEPS6_PHYS_BASE ? ? ? ? ? ? 0xd4000000
>> +
>> +
>> +#define TRIZEPS6_PIC_PHYS ? ? ?(0x88000000) ? ?/* CS0-3 Logic chip on ConXS */
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? /* Logic on ConXS-board CSFR register*/
>> +#define TRIZEPS6_CFSR_PHYS ? ? (TRIZEPS6_PIC_PHYS)
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? /* Logic on ConXS-board BOCR register*/
>> +#define TRIZEPS6_BOCR_PHYS ? ? (TRIZEPS6_PIC_PHYS+0x00200000)
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? /* Logic on ConXS-board IRCR register*/
>> +#define TRIZEPS6_IRCR_PHYS ? ? (TRIZEPS6_PIC_PHYS+0x00300000)
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? /* Logic on ConXS-board UPSR register*/
>> +#define TRIZEPS6_UPSR_PHYS ? ? (TRIZEPS6_PIC_PHYS+0x00280000)
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? /* Logic on ConXS-board DICR register*/
>> +#define TRIZEPS6_DICR_PHYS ? ? (TRIZEPS6_PIC_PHYS+0x00380000)
>> +
>> +
>> +#define TRIZEPS6_CPLD_PHYS ?(0x8e000000) /* CPLD on Trizeps6 module */ +
>> +#define TRIZEPS6_CPLD_CTRL_PHYS (TRIZEPS6_CPLD_PHYS)
>> +#define TRIZEPS6_CPLD_FTUR_PHYS (TRIZEPS6_CPLD_PHYS+0x4)
>> +#define TRIZEPS6_CPLD_HIBE_PHYS (TRIZEPS6_CPLD_PHYS+0x8)
>> +#define TRIZEPS6_CPLD_PWM_PHYS (TRIZEPS6_CPLD_PHYS+0xc)
>> +#define TRIZEPS6_CPLD_PLDR_PHYS (TRIZEPS6_CPLD_PHYS+0x10)
>> +#define TRIZEPS6_CPLD_PSET_PHYS (TRIZEPS6_CPLD_PHYS+0x14)
>> +#define TRIZEPS6_CPLD_TTLO_PHYS (TRIZEPS6_CPLD_PHYS+0x18)
>> +
>> +
>> +/* MMC socket */
>> +#define GPIO_MMC2_DET ? ? ? ? ?53
>> +#define TRIZEPS6_MMC2_IRQ ? ? ?IRQ_GPIO(mfp_to_gpio(MFP_PIN_GPIO53))
>> +#define GPIO_MMC4_DET ? ? ? ? ?41
>> +#define TRIZEPS6_MMC4_IRQ ? ? ?IRQ_GPIO(mfp_to_gpio(MFP_PIN_GPIO41)
>> +
>> +/* Off-module PIC on ConXS board */
>> +#define GPIO_PIC ? ? ? ? ? ? ? 51
>> +#define TRIZEPS6_PIC_IRQ ? ? ? IRQ_GPIO(mfp_to_gpio(MFP_PIN_GPIO51)
>> +
>> +/* PCMCIA socket Compact Flash */
>> +#define GPIO_PCD ? ? ? ? ? ? ? 43 ? ? ? ? ? ? ?/* PCMCIA Card Detect */
>> +#define TRIZEPS6_CD_IRQ ? ? ? ? ? ? ? ?IRQ_GPIO(mfp_to_gpio(MFP_PIN_GPIO43)
>> +#define GPIO_PRDY ? ? ? ? ? ? ?113 ? ? ? ? ? ? /* READY / nINT */
>> +#define TRIZEPS6_READY_NINT ? ?IRQ_GPIO(mfp_to_gpio(MFP_PIN_GPIO113) +
>> +#define trizeps6_GPIO_CODEC_IRQ ? ? ? ? ? ? ? ?116
>> +
>> +extern void trizeps6_ac97_acreset(int i);
>> +
>> +#endif /* _TRIPEPS6_H_ */
>> diff --git a/arch/arm/mach-mmp/include/mach/trizeps6_cpld.h
>> b/arch/arm/mach-mmp/include/mach/trizeps6_cpld.h
>> index 0000000..8538a6b
>> --- /dev/null
>> +++ b/arch/arm/mach-mmp/include/mach/trizeps6_cpld.h
>> @@ -0,0 +1,87 @@
>> +#ifndef _TRIPEPS6_CPLD_H_
>> +#define _TRIPEPS6_CPLD_H_
>> +
>> +/* index of resource */
>> +#define CTRL_S ? ? ? ? 0
>> +#define CTRL_R ? ? ? ? 1
>> +#define FTUR_S ? ? ? ? 2
>> +#define FTUR_R ? ? ? ? 3
>> +#define HIBE_S ? ? ? ? 4
>> +#define HIBE_R ? ? ? ? 5
>> +#define PWM ? ? ? ? ? ?6
>> +#define PLDR_S ? ? ? ? 7
>> +#define PLDR_R ? ? ? ? 8
>> +#define PSET_S ? ? ? ? 9
>> +#define PSET_R ? ? ? ? 10
>> +#define TTLO_S ? ? ? ? 11
>> +#define TTLO_R ? ? ? ? 12
>> +
>> +#define CPLD_CTRL_S cpld.addr[CTRL_S].val
>> +#define CPLD_CTRL_R cpld.addr[CTRL_R].val
>> +#define CPLD_CONTROL_GR ? ? ? ? ? ? ? ? ? ? ? ?(1 << 0)
>> +#define CPLD_CONTROL_CODEC ? ? ? ? ? ? (1 << 2)
>> +#define CPLD_CONTROL_ETHPHY ? ? ? ? ? ?(1 << 3)
>> +#define CPLD_CONTROL_RWL ? ? ? ? ? ? ? (1 << 4)
>> +#define CPLD_CONTROL_RBT ? ? ? ? ? ? ? (1 << 5)
>> +
>> +#define CPLD_FTUR_S cpld.addr[FTUR_S].val
>> +#define CPLD_FTUR_R cpld.addr[FTUR_R].val
>> +#define CPLD_FEATURE_UART3_SODIMM ? ? ?(1 << 0)
>> +#define CPLD_FEATURE_UART3_BT ? ? ? ? ?(1 << 1)
>> +#define CPLD_FEATURE_CF_MODE ? ? ? ? ? (1 << 2)
>> +#define CPLD_FEATURE_TTLIO ? ? ? ? ? ? (1 << 3)
>> +#define CPLD_PWM_SODIMM_P69 ? ? ? ? ? ?(1 << 4)
>> +#define CPLD_PWM_SODIMM_P77 ? ? ? ? ? ?(1 << 5)
>> +#define CPLD_PWM_SODIMM_P106 ? (1 << 6)
>> +#define CPLD_BT_PWM_SODIMM ? ? ? ? ? ? (1 << 7)
>> +
>> +#define CPLD_HIBE_S cpld.addr[HIBE_S].val
>> +#define CPLD_HIBE_R cpld.addr[HIBE_R].val
>> +#define CPLD_HIBERNATE_MODE ? ? ? ? ? ? ? ? ? ? ? ? ? ?(1 << 0)
>> +#define CPLD_HIBERNATE_WAKE_TOUCH ? ? ? ? ? ? ?(1 << 1)
>> +#define CPLD_HIBERNATE_WAKE_PMIC ? ? ? ? ? ? ? (1 << 2)
>> +#define CPLD_HIBERNATE_WAKE_IRQ_P43 ? ? ? ? ? ?(1 << 3)
>> +
>> +#define CPLD_PWM cpld.addr[PWM].val
>> +
>> +#define CPLD_PINLDR ? ?cpld.addr[PINLDR].val
>> +#define CPLD_PINLDR_P69 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?(1 << 0)
>> +#define CPLD_PINLDR_P100_PSKTSEL ? ? ? ? ? ? ? (1 << 1)
>> +#define CPLD_PINLDR_P98_CFNREG ? ? ? ? ? ? ? ? (1 << 2)
>> +#define CPLD_PINLDR_P104_CFNIOIS16 ? ? ? ? ? ? (1 << 3)
>> +#define CPLD_PINLDR_P93_RDNWR ? ? ? ? ? ? ? ? ?(1 << 4)
>> +#define CPLD_PINLDR_P104_IRQ_P43 ? ? ? ? ? ? ? (1 << 5)
>> +
>> +#define CPLD_PSET_S cpld.addr[PSET_S].val
>> +#define CPLD_PSET_R cpld.addr[PSET_R].val
>> +#define CPLD_PINSET_P69 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?(1 << 0)
>> +#define CPLD_PINSET_P100_PSKTSEL ? ? ? ? ? ? ? (1 << 1)
>> +#define CPLD_PINSET_P98_CFNREG ? ? ? ? ? ? ? ? (1 << 2)
>> +#define CPLD_PINSET_P104_CFNIOIS16 ? ? ? ? ? ? (1 << 3)
>> +#define CPLD_PINSET_P93_RDnWR ? ? ? ? ? ? ? ? ?(1 << 4)
>> +
>> +#define CPLD_TTLO_S cpld.addr[TTLO_S].val
>> +#define CPLD_TTLO_R cpld.addr[TTLO_R].val
>> +#define CPLD_TTLIO_W_A8 ? ? ? ? ? ? ? ? ? ? ? ?(1 << 0)
>> +#define CPLD_TTLIO_W_A9 ? ? ? ? ? ? ? ? ? ? ? ?(1 << 1)
>> +#define CPLD_TTLIO_W_A10 ? ? ? ? ? ? ? (1 << 2)
>> +#define CPLD_TTLIO_W_A11 ? ? ? ? ? ? ? (1 << 3)
>> +#define CPLD_TTLIO_W_A12 ? ? ? ? ? ? ? (1 << 4)
>> +#define CPLD_TTLIO_W_A13 ? ? ? ? ? ? ? (1 << 5)
>> +#define CPLD_TTLIO_W_A14 ? ? ? ? ? ? ? (1 << 6)
>> +#define CPLD_TTLIO_W_A15 ? ? ? ? ? ? ? (1 << 7)
>> +#define CPLD_TTLIO_r_A0 ? ? ? ? ? ? ? ? ? ? ? ?(1 << 0)
>> +#define CPLD_TTLIO_r_A1 ? ? ? ? ? ? ? ? ? ? ? ?(1 << 1)
>> +#define CPLD_TTLIO_r_A2 ? ? ? ? ? ? ? ? ? ? ? ?(1 << 2)
>> +#define CPLD_TTLIO_r_A3 ? ? ? ? ? ? ? ? ? ? ? ?(1 << 3)
>> +#define CPLD_TTLIO_r_A4 ? ? ? ? ? ? ? ? ? ? ? ?(1 << 4)
>> +#define CPLD_TTLIO_r_A5 ? ? ? ? ? ? ? ? ? ? ? ?(1 << 5)
>> +#define CPLD_TTLIO_r_A6 ? ? ? ? ? ? ? ? ? ? ? ?(1 << 6)
>> +#define CPLD_TTLIO_r_A7 ? ? ? ? ? ? ? ? ? ? ? ?(1 << 7)
>> +
>> +
>> +
>> +extern unsigned short trizeps6_cpld_readw(unsigned int reg);
>> +extern inline void trizeps6_cpld_writew(unsigned int reg, unsigned short
>> value);
>> +
>> +#endif /* _TRIPEPS6_CPLD_H_ */
>> diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c index
>> 72b4e76..9c2396e 100644
>> --- a/arch/arm/mach-mmp/pxa168.c
>> +++ b/arch/arm/mach-mmp/pxa168.c
>> @@ -66,6 +66,7 @@ void __init pxa168_init_irq(void)
>> ?/* APB peripheral clocks */
>> ?static APBC_CLK(uart1, PXA168_UART1, 1, 14745600);
>> ?static APBC_CLK(uart2, PXA168_UART2, 1, 14745600);
>> +static APBC_CLK(uart3, PXA168_UART3, 1, 14745600);
>> ?static APBC_CLK(twsi0, PXA168_TWSI0, 1, 33000000);
>> ?static APBC_CLK(twsi1, PXA168_TWSI1, 1, 33000000);
>> ?static APBC_CLK(pwm1, PXA168_PWM1, 1, 13000000);
>> @@ -78,14 +79,18 @@ static APBC_CLK(ssp3, PXA168_SSP3, 4, 0);
>> ?static APBC_CLK(ssp4, PXA168_SSP4, 4, 0);
>> ?static APBC_CLK(ssp5, PXA168_SSP5, 4, 0);
>> ?static APBC_CLK(keypad, PXA168_KPC, 0, 32000);
>> +static APBC_CLK(ac97, PXA168_AC97, 0, 24576000);
>> +
>>
>> ?static APMU_CLK(nand, NAND, 0x01db, 208000000);
>> ?static APMU_CLK(lcd, LCD, 0x7f, 312000000);
>> +static APMU_CLK(mfu, MFU, 0x9, 0);
>>
>> ?/* device and clock bindings */
>> ?static struct clk_lookup pxa168_clkregs[] = {
>> ? ? ? ?INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
>> ? ? ? ?INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
>> + ? ? ? INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL),
>> ? ? ? ?INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL),
>> ? ? ? ?INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL),
>> ? ? ? ?INIT_CLKREG(&clk_pwm1, "pxa168-pwm.0", NULL),
>> @@ -100,6 +105,8 @@ static struct clk_lookup pxa168_clkregs[] = {
>> ? ? ? ?INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
>> ? ? ? ?INIT_CLKREG(&clk_lcd, "pxa168-fb", NULL),
>> ? ? ? ?INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL),
>> + ? ? ? INIT_CLKREG(&clk_mfu, "pxa168-eth", "MFUCLK"),
>> + ? ? ? INIT_CLKREG(&clk_ac97, "pxa2xx-ac97", "AC97CLK"),
>> ?};
>>
>> ?static int __init pxa168_init(void)
>> @@ -149,6 +156,7 @@ void pxa168_clear_keypad_wakeup(void)
>> ?/* on-chip devices */
>> ?PXA168_DEVICE(uart1, "pxa2xx-uart", 0, UART1, 0xd4017000, 0x30, 21, 22);
>> PXA168_DEVICE(uart2, "pxa2xx-uart", 1, UART2, 0xd4018000, 0x30, 23, 24);
>> +PXA168_DEVICE(uart3, "pxa2xx-uart", 2, UART3, 0xd4026000, 0x30, 23, 24);
>> ?PXA168_DEVICE(twsi0, "pxa2xx-i2c", 0, TWSI0, 0xd4011000, 0x28);
>> ?PXA168_DEVICE(twsi1, "pxa2xx-i2c", 1, TWSI1, 0xd4025000, 0x28);
>> ?PXA168_DEVICE(pwm1, "pxa168-pwm", 0, NONE, 0xd401a000, 0x10);
>> @@ -163,3 +171,5 @@ PXA168_DEVICE(ssp4, "pxa168-ssp", 3, SSP4, 0xd4020000,
>> 0x40, 58, 59);
>> ?PXA168_DEVICE(ssp5, "pxa168-ssp", 4, SSP5, 0xd4021000, 0x40, 60, 61);
>> PXA168_DEVICE(fb, "pxa168-fb", -1, LCD, 0xd420b000, 0x1c8);
>> ?PXA168_DEVICE(keypad, "pxa27x-keypad", -1, KEYPAD, 0xd4012000, 0x4c);
>> +PXA168_DEVICE(mfu, "pxa168-eth", -1, MFU, 0xc0800000, 0x0FFF);
>> +PXA168_DEVICE(ac97, "pxa2xx-ac97", -1, AC97, 0xd402B000, 0x0fff); diff
>> --git a/arch/arm/mach-mmp/trizeps6.c b/arch/arm/mach-mmp/trizeps6.c index
>> 0000000..a935f14
>> --- /dev/null
>> +++ b/arch/arm/mach-mmp/trizeps6.c
>> @@ -0,0 +1,469 @@
>> +/*
>> + * ?linux/arch/arm/mach-mmp/trizeps6.c
>> + *
>> + * ?Support for the Keith und Koep Trizeps6 Modul Platform
>> + * ?based on Marvell PXA168-CPU
>> + *
>> + * ?Author: ? ?Yupeng Schneider
>> + *
>> + * ?This program is free software; you can redistribute it and/or modify
>> + * ?it under the terms of the GNU General Public License version 2 as + *
>> ?publishhed by the Free Software Foundation.
>> + */
>> +
>> +#include <linux/init.h>
>> +#include <linux/kernel.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/mtd/mtd.h>
>> +#include <linux/mtd/partitions.h>
>> +#include <linux/mtd/nand.h>
>> +#include <linux/delay.h>
>> +#include <asm/mach-types.h>
>> +#include <asm/mach/arch.h>
>> +#include <mach/addr-map.h>
>> +#include <mach/mfp-pxa168.h>
>> +#include <mach/pxa168.h>
>> +#include <mach/gpio.h>
>> +#include <linux/pxa168_eth.h>
>> +#include <mach/irqs.h>
>> +#include <mach/trizeps6.h>
>> +#include <mach/trizeps6_cpld.h>
>> +#include "common.h"
>> +#include <linux/mmc/sdhci.h>
>> +#include <linux/ucb1400.h>
>> +#include <mach/audio.h>
>> +
>> +
>> +static unsigned long trizeps6_pin_config[] __initdata = {
>> + ? ? ? /* Data Flash Interface */
>> + ? ? ? GPIO0_DFI_D15,
>> + ? ? ? GPIO1_DFI_D14,
>> + ? ? ? GPIO2_DFI_D13,
>> + ? ? ? GPIO3_DFI_D12,
>> + ? ? ? GPIO4_DFI_D11,
>> + ? ? ? GPIO5_DFI_D10,
>> + ? ? ? GPIO6_DFI_D9,
>> + ? ? ? GPIO7_DFI_D8,
>> + ? ? ? GPIO8_DFI_D7,
>> + ? ? ? GPIO9_DFI_D6,
>> + ? ? ? GPIO10_DFI_D5,
>> + ? ? ? GPIO11_DFI_D4,
>> + ? ? ? GPIO12_DFI_D3,
>> + ? ? ? GPIO13_DFI_D2,
>> + ? ? ? GPIO14_DFI_D1,
>> + ? ? ? GPIO15_DFI_D0,
>> +
>> + ? ? ? /* Static Memory Controller */
>> + ? ? ? GPIO18_SMC_nCS0,
>> + ? ? ? GPIO34_SMC_nCS1,
>> + ? ? ? GPIO23_SMC_nLUA,
>> + ? ? ? GPIO25_SMC_nLLA,
>> + ? ? ? GPIO28_SMC_RDY,
>> + ? ? ? GPIO29_SMC_SCLK,
>> + ? ? ? GPIO35_SMC_BE1,
>> + ? ? ? GPIO36_SMC_BE2,
>> +
>> +
>> + ? ? ? /* UART1 */
>> + ? ? ? GPIO107_UART1_RXD,
>> + ? ? ? GPIO108_UART1_TXD,
>> + ? ? ? GPIO107_UART1_RXD,
>> + ? ? ? GPIO108_UART1_TXD,
>> + ? ? ? GPIO109_UART1_RTS,
>> + ? ? ? GPIO110_UART1_CTS,
>> + ? ? ? GPIO111_UART1_RI,
>> + ? ? ? GPIO104_UART1_DSR,
>> + ? ? ? GPIO112_UART1_DTR,
>> + ? ? ? GPIO105_UART1_DCD,
>> +
>> + ? ? ? /* UART2 */
>> + ? ? ? GPIO107_UART2_TXD,
>> + ? ? ? GPIO107_UART2_RXD,
>> + ? ? ? GPIO109_UART2_CTS,
>> + ? ? ? GPIO109_UART2_RTS,
>> +
>> + ? ? ? /* UART3 */
>> + ? ? ? GPIO30_UART3_TXD,
>> + ? ? ? GPIO31_UART3_RXD,
>> + ? ? ? GPIO32_UART3_CTS,
>> + ? ? ? GPIO33_UART3_RTS,
>> +
>> +
>> + ? ? ? /* MFU */
>> + ? ? ? GPIO86_TX_CLK,
>> + ? ? ? GPIO87_TX_EN,
>> + ? ? ? GPIO88_TX_DQ3,
>> + ? ? ? GPIO89_TX_DQ2,
>> + ? ? ? GPIO90_TX_DQ1,
>> + ? ? ? GPIO91_TX_DQ0,
>> + ? ? ? GPIO92_MII_CRS,
>> + ? ? ? GPIO93_MII_COL,
>> + ? ? ? GPIO94_RX_CLK,
>> + ? ? ? GPIO95_RX_ER,
>> + ? ? ? GPIO96_RX_DQ3,
>> + ? ? ? GPIO97_RX_DQ2,
>> + ? ? ? GPIO98_RX_DQ1,
>> + ? ? ? GPIO99_RX_DQ0,
>> + ? ? ? GPIO100_MII_MDC,
>> + ? ? ? GPIO101_MII_MDIO,
>> + ? ? ? GPIO103_RX_DV,
>> +
>> + ? ? ? /* USB OTG */
>> + ? ? ? GPIO85_GPIO,
>> + ? ? ? GPIO47_GPIO,
>> +
>> + ? ? ? /* i2c bus */
>> + ? ? ? GPIO102_CI2C_SDA,
>> + ? ? ? GPIO106_CI2C_SCL,
>> +
>> +
>> + ? ? ? /* MMC2 */
>> + ? ? ? GPIO122_MMC2_DAT3 | MFP_PULL_HIGH,
>> + ? ? ? GPIO121_MMC2_DAT2 | MFP_PULL_HIGH,
>> + ? ? ? GPIO120_MMC2_DAT1 | MFP_PULL_HIGH,
>> + ? ? ? GPIO119_MMC2_DAT0 | MFP_PULL_HIGH,
>> + ? ? ? GPIO28_MMC2_CMD | MFP_PULL_HIGH,
>> + ? ? ? GPIO29_MMC2_CLK,
>> + ? ? ? GPIO53_MMC2_CD | MFP_PULL_LOW, ? ? ? ? ? ? ? ? ?/* TRIZEPS6_MMC2_IRQ */
>> +
>> + ? ? ? /* MMC4 */
>> + ? ? ? GPIO78_MMC4_DAT3 | MFP_PULL_HIGH,
>> + ? ? ? GPIO79_MMC4_DAT2 | MFP_PULL_HIGH,
>> + ? ? ? GPIO80_MMC4_DAT1 | MFP_PULL_HIGH,
>> + ? ? ? GPIO81_MMC4_DAT0 | MFP_PULL_HIGH,
>> + ? ? ? GPIO82_MMC4_CMD | MFP_PULL_HIGH,
>> + ? ? ? GPIO83_MMC4_CLK,
>> +
>> + ? ? ? /* LCD */
>> + ? ? ? GPIO56_LCD_FCLK_RD,
>> + ? ? ? GPIO57_LCD_LCLK_A0,
>> + ? ? ? GPIO58_LCD_PCLK_WR,
>> + ? ? ? GPIO59_LCD_DENA_BIAS,
>> + ? ? ? GPIO60_LCD_DD0,
>> + ? ? ? GPIO61_LCD_DD1,
>> + ? ? ? GPIO62_LCD_DD2,
>> + ? ? ? GPIO63_LCD_DD3,
>> + ? ? ? GPIO64_LCD_DD4,
>> + ? ? ? GPIO65_LCD_DD5,
>> + ? ? ? GPIO66_LCD_DD6,
>> + ? ? ? GPIO67_LCD_DD7,
>> + ? ? ? GPIO68_LCD_DD8,
>> + ? ? ? GPIO69_LCD_DD9,
>> + ? ? ? GPIO70_LCD_DD10,
>> + ? ? ? GPIO71_LCD_DD11,
>> + ? ? ? GPIO72_LCD_DD12,
>> + ? ? ? GPIO73_LCD_DD13,
>> + ? ? ? GPIO74_LCD_DD14,
>> + ? ? ? GPIO75_LCD_DD15,
>> +
>> +
>> + ? ? ? /* AC97 */
>> + ? ? ? GPIO115_AC97_BITCLK,
>> + ? ? ? GPIO114_AC97_SDATA_IN_0,
>> + ? ? ? GPIO117_AC97_SDATA_OUT,
>> + ? ? ? GPIO118_AC97_SYNC,
>> + ? ? ? GPIO116_GPIO,
>> +
>> +
>> + ? ? ? GPIO51_GPIO, ? ? ? ? ? ? ? ? ? ?/* TRIZEPS6_PIC_IRQ */
>> + ? ? ? GPIO27_GPIO, ? ? ? ? ? ? ? ? ? ?/* Ethernet IRQ */
>> +};
>> +
>> +
>> +
>> +/****************************************************************************
>> + * CPLD
>> +
>> ****************************************************************************/
>> +
>> +static struct resource tri6_cpld_resources[] = {
>> + ? ? ? [CTRL_S] = {
>> + ? ? ? ? ? ? ? .start ?= TRIZEPS6_CPLD_CTRL_PHYS,
>> + ? ? ? ? ? ? ? .end ? ?= TRIZEPS6_CPLD_CTRL_PHYS+1,
>> + ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
>> + ? ? ? },
>> + ? ? ? [CTRL_R] = {
>> + ? ? ? ? ? ? ? .start ?= TRIZEPS6_CPLD_CTRL_PHYS+2,
>> + ? ? ? ? ? ? ? .end ? ?= TRIZEPS6_CPLD_CTRL_PHYS+3,
>> + ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
>> + ? ? ? },
>> + ? ? ? [FTUR_S] = {
>> + ? ? ? ? ? ? ? .start ?= TRIZEPS6_CPLD_FTUR_PHYS,
>> + ? ? ? ? ? ? ? .end ? ?= TRIZEPS6_CPLD_FTUR_PHYS+1,
>> + ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
>> + ? ? ? },
>> + ? ? ? [FTUR_R] = {
>> + ? ? ? ? ? ? ? .start ?= TRIZEPS6_CPLD_FTUR_PHYS+2,
>> + ? ? ? ? ? ? ? .end ? ?= TRIZEPS6_CPLD_FTUR_PHYS+3,
>> + ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
>> + ? ? ? },
>> + ? ? ? [HIBE_S] = {
>> + ? ? ? ? ? ? ? .start ?= TRIZEPS6_CPLD_HIBE_PHYS,
>> + ? ? ? ? ? ? ? .end ? ?= TRIZEPS6_CPLD_HIBE_PHYS+1,
>> + ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
>> + ? ? ? },
>> + ? ? ? [HIBE_R] = {
>> + ? ? ? ? ? ? ? .start ?= TRIZEPS6_CPLD_HIBE_PHYS+2,
>> + ? ? ? ? ? ? ? .end ? ?= TRIZEPS6_CPLD_HIBE_PHYS+3,
>> + ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
>> + ? ? ? },
>> + ? ? ? [PWM] = {
>> + ? ? ? ? ? ? ? .start ?= TRIZEPS6_CPLD_PWM_PHYS,
>> + ? ? ? ? ? ? ? .end ? ?= TRIZEPS6_CPLD_PWM_PHYS+1,
>> + ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
>> + ? ? ? },
>> + ? ? ? [PLDR_S] = {
>> + ? ? ? ? ? ? ? .start ?= TRIZEPS6_CPLD_PLDR_PHYS,
>> + ? ? ? ? ? ? ? .end ? ?= TRIZEPS6_CPLD_PLDR_PHYS+1,
>> + ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
>> + ? ? ? },
>> + ? ? ? [PLDR_R] = {
>> + ? ? ? ? ? ? ? .start ?= TRIZEPS6_CPLD_PLDR_PHYS+2,
>> + ? ? ? ? ? ? ? .end ? ?= TRIZEPS6_CPLD_PLDR_PHYS+3,
>> + ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
>> + ? ? ? },
>> + ? ? ? [PSET_S] = {
>> + ? ? ? ? ? ? ? .start ?= TRIZEPS6_CPLD_PSET_PHYS,
>> + ? ? ? ? ? ? ? .end ? ?= TRIZEPS6_CPLD_PSET_PHYS+1,
>> + ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
>> + ? ? ? },
>> + ? ? ? [PSET_R] = {
>> + ? ? ? ? ? ? ? .start ?= TRIZEPS6_CPLD_PSET_PHYS+2,
>> + ? ? ? ? ? ? ? .end ? ?= TRIZEPS6_CPLD_PSET_PHYS+3,
>> + ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
>> + ? ? ? },
>> + ? ? ? [TTLO_S] = {
>> + ? ? ? ? ? ? ? .start ?= TRIZEPS6_CPLD_TTLO_PHYS,
>> + ? ? ? ? ? ? ? .end ? ?= TRIZEPS6_CPLD_TTLO_PHYS+1,
>> + ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
>> + ? ? ? },
>> + ? ? ? [TTLO_R] = {
>> + ? ? ? ? ? ? ? .start ?= TRIZEPS6_CPLD_TTLO_PHYS+2,
>> + ? ? ? ? ? ? ? .end ? ?= TRIZEPS6_CPLD_TTLO_PHYS+3,
>> + ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
>> + ? ? ? },
>> +};
>> +
>> +static int tri6_cpld_platdata = 1;
>> +
>> +static struct platform_device cpld_device = {
>> + ? ? ? .name ? ? ? ? ? = "trizeps6-cpld",
>> + ? ? ? .id ? ? ? ? ? ? = -1,
>> + ? ? ? .num_resources ?= ARRAY_SIZE(tri6_cpld_resources),
>> + ? ? ? .resource ? ? ? = tri6_cpld_resources,
>> + ? ? ? .dev ? ? ? ? ? ?= {
>> + ? ? ? ? ? ? ? .platform_data = &tri6_cpld_platdata,
>> + ? ? ? }
>> +};
>> +
>> +
>> +/******************************************************************************
>> + * Audio and Touchscreen
>> +
>> ******************************************************************************/
>> +
>> +static struct ucb1400_pdata trizeps6_ucb1400_pdata = {
>> + ? ? ? .irq ? ? ? ? ? ?= ?gpio_to_irq(trizeps6_GPIO_CODEC_IRQ),
>> +};
>> +
>> +static struct pxa2xx_audio_ops_t trizeps6_ac97_pdata = {
>> + ? ? ? .codec_pdata ? ?= { &trizeps6_ucb1400_pdata, },
>> +};
>> +
>> +static struct platform_device trizeps6_ucb1400_device = {
>> + ? ? ? .name ? ? ? ? ? = "ucb1400_core",
>> + ? ? ? .id ? ? ? ? ? ? = -1,
>> + ? ? ? .dev ? ? ? ? ? ?= {
>> + ? ? ? ? ? ? ? .platform_data = &trizeps6_ucb1400_pdata,
>> + ? ? ? },
>> +};
>> +
>> +static void __init trizeps6_ts_init(void)
>> +{
>> + ? ? ? pxa168_add_ac97(&trizeps6_ac97_pdata);
>> + ? ? ? platform_device_register(&trizeps6_ucb1400_device);
>> +}
>> +
>> +void trizeps6_ac97_acreset(int i)
>> +{ ? ? ?unsigned short value;
>> +
>> + ? ? ? if (i == 1) {
>> +
>> + ? ? ? ? ? ? ? value = trizeps6_cpld_readw(CTRL_S);
>> + ? ? ? ? ? ? ? trizeps6_cpld_writew(CTRL_S, value | CPLD_CONTROL_CODEC);
>> + ? ? ? }
>> + ? ? ? if (!i) {
>> + ? ? ? ? ? ? ? value = trizeps6_cpld_readw(CTRL_R);
>> + ? ? ? ? ? ? ? trizeps6_cpld_writew(CTRL_R, value | CPLD_CONTROL_CODEC);
>> + ? ? ? }
>> +}
>> +
>> +/******************************************************************************
>> + * Ethernet
>> +
>> ******************************************************************************/
>> +static int trizeps6_eth_init(void)
>> +{
>> + ? ? ? unsigned short value;
>> +
>> + ? ? ? value = trizeps6_cpld_readw(CTRL_R);
>> + ? ? ? trizeps6_cpld_writew(CTRL_R, value | CPLD_CONTROL_ETHPHY);
>> + ? ? ? return 0;
>> +
>> +}
>> +
>> +static struct pxa168_eth_platform_data trizeps6_eth_data = {
>> + ? ? ? .phy_addr ? ? ? = 0x1f,
>> + ? ? ? .port_number = 0,
>> + ? ? ? .init ? ? ? ? ? = trizeps6_eth_init,
>> +};
>> +
>> +/******************************************************************************
>> + * NAND
>> +
>> ******************************************************************************/
>> +static struct pxa3xx_nand_timing stnand02gw3b2d_timing = {
>> + ? ? ? .tCH ? ?= 10,
>> + ? ? ? .tCS ? ?= 40,
>> + ? ? ? .tWH ? ?= 20,
>> + ? ? ? .tWP ? ?= 24,
>> + ? ? ? .tRH ? ?= 20,
>> + ? ? ? .tRP ? ?= 24,
>> + ? ? ? .tR ? ? ? ? = 50000,
>> + ? ? ? .tWHR ? = 120,
>> + ? ? ? .tAR ? ?= 20,
>> +
>> +};
>> +
>> +static struct pxa3xx_nand_cmdset largepage_cmdset = {
>> + ? ? ? .read1 ? ? ? ? ?= 0x3000,
>> + ? ? ? .read2 ? ? ? ? ?= 0x0050,
>> + ? ? ? .program ? ? ? ?= 0x1080,
>> + ? ? ? .read_status ? ?= 0x0070,
>> + ? ? ? .read_id ? ? ? ?= 0x0090,
>> + ? ? ? .erase ? ? ? ? ?= 0xD060,
>> + ? ? ? .reset ? ? ? ? ?= 0x00FF,
>> + ? ? ? .lock ? ? ? ? ? = 0x002A,
>> + ? ? ? .unlock ? ? ? ? = 0x2423,
>> + ? ? ? .lock_status ? ?= 0x007A,
>> +};
>> +
>> +static struct pxa3xx_nand_flash trizeps6_flashes[] = {
>> + ? ? ? {
>> + ? ? ? ? ? ? ? .timing = &stnand02gw3b2d_timing,
>> + ? ? ? ? ? ? ? .cmdset = &largepage_cmdset,
>> + ? ? ? ? ? ? ? .page_per_block = 64,
>> + ? ? ? ? ? ? ? .page_size ? ? ?= 2048,
>> + ? ? ? ? ? ? ? .flash_width ? ?= 8,
>> + ? ? ? ? ? ? ? .dfc_width ? ? ?= 8,
>> + ? ? ? ? ? ? ? .num_blocks ? ? = 2048,
>> + ? ? ? ? ? ? ? .chip_id ? ? ? ?= 0xda20,
>> + ? ? ? },
>> +};
>> +
>> +
>> +static struct mtd_partition trizeps6_nand_partitions[] = {
>> + ? ? ? {
>> + ? ? ? ? ? ? ? .name ? ? ? ? ? = "bootloader",
>> + ? ? ? ? ? ? ? .offset ? ? ? ? = 0,
>> + ? ? ? ? ? ? ? .size ? ? ? ? ? = SZ_16M,
>> + ? ? ? ? ? ? ? .mask_flags ? ? = MTD_WRITEABLE,
>> + ? ? ? }, {
>> + ? ? ? ? ? ? ? .name ? ? ? ? ? = "reserved",
>> + ? ? ? ? ? ? ? .offset ? ? ? ? = MTDPART_OFS_APPEND,
>> + ? ? ? ? ? ? ? .size ? ? ? ? ? = SZ_128K,
>> + ? ? ? ? ? ? ? .mask_flags ? ? = MTD_WRITEABLE,
>> + ? ? ? }, {
>> + ? ? ? ? ? ? ? .name ? ? ? ? ? = "kernel",
>> + ? ? ? ? ? ? ? .offset ? ? ? ? = MTDPART_OFS_APPEND,
>> + ? ? ? ? ? ? ? .size ? ? ? ? ? = (2*SZ_2M + SZ_1M),
>> + ? ? ? ? ? ? ? .mask_flags ? ? = 0,
>> + ? ? ? }, {
>> + ? ? ? ? ? ? ? .name ? ? ? ? ? = "filesystem",
>> + ? ? ? ? ? ? ? .offset ? ? ? ? = MTDPART_OFS_APPEND,
>> + ? ? ? ? ? ? ? .size = (SZ_256M - 3*SZ_8M),
>> + ? ? ? ? ? ? ? .mask_flags ? ? = 0,
>> + ? ? ? }
>> +};
>> +
>> +static struct pxa3xx_nand_platform_data trizeps6_nand_info = {
>> + ? ? ? .enable_arbiter = 1,
>> + ? ? ? .parts ? ? ? ? ?= trizeps6_nand_partitions,
>> + ? ? ? .nr_parts ? ? ? = ARRAY_SIZE(trizeps6_nand_partitions),
>> + ? ? ? .flash ? ? ?= trizeps6_flashes,
>> + ? ? ? .num_flash ?= ARRAY_SIZE(trizeps6_flashes),
>> + ? ? ? .keep_config = 0
>> +};
>> +
>> +
>> +
>> +static struct i2c_board_info trizeps6_i2c_devices[] ?= {
>> + ? ? ? { I2C_BOARD_INFO("pcf8593", 0x51), },
>> +};
>> +
>> +
>> +/******************************************************************************
>> + * LCD
>> +
>> ******************************************************************************/
>> +static struct fb_videomode trizeps6_video_modes[] = {
>> + ? ? ? [0] = {
>> + ? ? ? ? ? ? ? .pixclock ? ? ? = 39720,
>> + ? ? ? ? ? ? ? .refresh ? ? ? ?= 60,
>> + ? ? ? ? ? ? ? .xres ? ? ? ? ? = 640,
>> + ? ? ? ? ? ? ? .yres ? ? ? ? ? = 480,
>> + ? ? ? ? ? ? ? .hsync_len ? ? ?= 63,
>> + ? ? ? ? ? ? ? .left_margin ? ?= 12,
>> + ? ? ? ? ? ? ? .right_margin ? = 12,
>> + ? ? ? ? ? ? ? .vsync_len ? ? ?= 4,
>> + ? ? ? ? ? ? ? .upper_margin ? = 32,
>> + ? ? ? ? ? ? ? .lower_margin ? = 10,
>> + ? ? ? ? ? ? ? .sync ? ? ? ? ? = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT,
>> + ? ? ? },
>> +};
>> +
>> +static struct pxa168fb_mach_info trizeps6_lcd_info = {
>> + ? ? ? .id ? ? ? ? ? ? ? ? ? ? = "Base-trizeps6",
>> + ? ? ? .modes ? ? ? ? ? ? ? ? ?= trizeps6_video_modes,
>> + ? ? ? .num_modes ? ? ? ? ? ? ?= ARRAY_SIZE(trizeps6_video_modes),
>> + ? ? ? .pix_fmt ? ? ? ? ? ? ? ?= PIX_FMT_RGB565,
>> + ? ? ? .io_pin_allocation_mode = PIN_MODE_DUMB_16_GPIO,
>> + ? ? ? .dumb_mode ? ? ? ? ? ? ?= DUMB_MODE_RGB565,
>> + ? ? ? .active ? ? ? ? ? ? ? ? = 1,
>> + ? ? ? .panel_rbswap ? ? ? ? ? = 1,
>> + ? ? ? .invert_pixclock ? ? ? ?= 0,
>> +};
>> +
>> +
>> +static struct platform_device *trizeps6_devices[] __initdata = {
>> + ? ? ? &cpld_device,
>> +};
>> +
>> +static void __init trizeps6_init(void)
>> +{
>> + ? ? ? mfp_config(ARRAY_AND_SIZE(trizeps6_pin_config));
>> +
>> + ? ? ? pxa168_add_uart(1);
>> + ? ? ? pxa168_add_uart(2);
>> +#ifdef STUART_SODIMM
>> + ? ? ? pxa168_add_uart(3);
>> +#endif
>> + ? ? ? pxa168_add_nand(&trizeps6_nand_info);
>> + ? ? ? platform_add_devices(trizeps6_devices,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ARRAY_SIZE(trizeps6_devices));
>> +
>> + ? ? ? pxa168_add_fb(&trizeps6_lcd_info);
>> + ? ? ? pxa168_add_mfu(&trizeps6_eth_data);
>> + ? ? ? pxa168_add_twsi(0, NULL, ARRAY_AND_SIZE(trizeps6_i2c_devices));
>> + ? ? ? trizeps6_ts_init();
>> +}
>> +
>> +static void __init trizeps6_map_io(void)
>> +{
>> + ? ? ? mmp_map_io();
>> +}
>> +
>> +MACHINE_START(TRIZEPS6, "PXA168-based Keith & Koep Trizeps VI Development
>> Module")
>> + ? ? ? /* MAINTAINER("Yupeng Schneider" <yupeng.schneider@googlemail.com>) */
>> + ? ? ? .map_io ? ? ? ? = trizeps6_map_io,
>> + ? ? ? .init_irq ? ? ? = pxa168_init_irq,
>> + ? ? ? .timer ? ? ? ? ?= &pxa168_timer,
>> + ? ? ? .init_machine ? = trizeps6_init,
>> +MACHINE_END
>> +
>> +
>> diff --git a/arch/arm/mach-mmp/trizeps6_cpld.c
>> b/arch/arm/mach-mmp/trizeps6_cpld.c
>> index 0000000..2577b0f
>> --- /dev/null
>> +++ b/arch/arm/mach-mmp/trizeps6_cpld.c
>> @@ -0,0 +1,145 @@
>> +/*
>> + * ?linux/arch/arm/mach-mmp/trizeps6_cpld.c
>> + *
>> + *
>> + * ?Author: ? ?Yupeng Schneider
>> + * ?Created: ? 27 10, 2010
>> + * ?Copyright: Yupeng Schneider
>> + *
>> + * ?This program is free software; you can redistribute it and/or modify
>> + * ?it under the terms of the GNU General Public License version 2 as + *
>> ?published by the Free Software Foundation.*/
>> +
>> +#include <linux/kernel.h>
>> +#include <linux/ioport.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/device.h>
>> +#include <linux/module.h>
>> +
>> +#include <asm/io.h>
>> +#include <asm/delay.h>
>> +#include <mach/trizeps6.h>
>> +#include <mach/trizeps6_cpld.h>
>> +
>> +struct cpld_info {
>> + ? ? ? struct region {
>> + ? ? ? ? ? ? ? struct resource *res;
>> + ? ? ? ? ? ? ? struct resource *req;
>> + ? ? ? ? ? ? ? void __iomem ? ?*iom;
>> + ? ? ? ? ? ? ? unsigned short ? val;
>> + ? ? ? } addr[7];
>> +} cpld_info;
>> +
>> +static struct cpld_info cpld = { { { 0 } } };
>> +
>> +inline void trizeps6_cpld_writew(unsigned int reg, unsigned short value) +{
>> + ? ? ? if ((cpld.addr[reg].iom != NULL))
>> + ? ? ? ? ? ? ? writew(value, cpld.addr[reg].iom);
>> +
>> +}
>> +
>> +unsigned short trizeps6_cpld_readw(unsigned int reg)
>> +{
>> + ? ? ? short value = 0;
>> + ? ? ? if (reg != HIBE_S || reg != HIBE_R || reg != PWM || reg != PSET_S || reg
>> != PSET_R) {
>> +
>> + ? ? ? ? ? ? ? if ((cpld.addr[reg].iom != NULL))
>> + ? ? ? ? ? ? ? ? ? ? ? value = readw(cpld.addr[reg].iom);
>> + ? ? ? }
>> + ? ? ? return value;
>> +}
>> +EXPORT_SYMBOL(trizeps6_cpld_readw);
>> +
>> +static int trizeps6_cpld_probe(struct platform_device *pdev)
>> +{
>> + ? ? ? int i;
>> +
>> + ? ? ? CPLD_CTRL_R = CPLD_CONTROL_ETHPHY | CPLD_CONTROL_GR;
>> +#ifdef STUART_SODIMM
>> + ? ? ? CPLD_FTUR_S = CPLD_FEATURE_UART3_SODIMM;
>> +#endif
>> + ? ? ? for (i = CTRL_S; i <= TTLO_R; i++) {
>> + ? ? ? ? ? ? ? cpld.addr[i].res = platform_get_resource(pdev, IORESOURCE_MEM, i);
>> + ? ? ? ? ? ? ? if (cpld.addr[i].res == NULL) {
>> + ? ? ? ? ? ? ? ? ? ? ? dev_err(&pdev->dev, "cannot get resource %d area\n", i);
>> + ? ? ? ? ? ? ? ? ? ? ? return -EIO;
>> + ? ? ? ? ? ? ? }
>> + ? ? ? ? ? ? ? cpld.addr[i].req = request_mem_region(cpld.addr[i].res->start,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2, pdev->name);
>> + ? ? ? ? ? ? ? if (cpld.addr[i].req == NULL) {
>> + ? ? ? ? ? ? ? ? ? ? ? dev_err(&pdev->dev, "cannot claim addr area %d\n", i);
>> + ? ? ? ? ? ? ? ? ? ? ? return -EIO;
>> + ? ? ? ? ? ? ? }
>> + ? ? ? ? ? ? ? cpld.addr[i].iom = ioremap(cpld.addr[i].res->start, 2);
>> + ? ? ? ? ? ? ? if (cpld.addr[i].iom == NULL) {
>> + ? ? ? ? ? ? ? ? ? ? ? dev_err(&pdev->dev, "cannot remap addr area %d\n", i);
>> + ? ? ? ? ? ? ? ? ? ? ? return -EIO;
>> + ? ? ? ? ? ? ? }
>> + ? ? ? ? ? ? ? switch (i) {
>> + ? ? ? ? ? ? ? case CTRL_R:
>> + ? ? ? ? ? ? ? ? ? ? ? trizeps6_cpld_writew(CTRL_R, CPLD_CTRL_R);
>> + ? ? ? ? ? ? ? ? ? ? ? break;
>> + ? ? ? ? ? ? ? case FTUR_S:
>> + ? ? ? ? ? ? ? ? ? ? ? trizeps6_cpld_writew(FTUR_S, CPLD_FTUR_S);
>> + ? ? ? ? ? ? ? ? ? ? ? break;
>> + ? ? ? ? ? ? ? default:
>> + ? ? ? ? ? ? ? ? ? ? ? ;
>> +
>> + ? ? ? ? ? ? ? }
>> + ? ? ? ? ? ? ? dev_dbg(&pdev->dev, "mapped region ?[%d] %08x -> %p\n", i,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (int)cpld.addr[i].req->start, cpld.addr[i].iom);
>> + ? ? ? }
>> +
>> +
>> + ? ? ? return 0;
>> +}
>> +
>> +static int trizeps6_cpld_remove(struct platform_device *pdev)
>> +{
>> + ? ? ? dev_dbg(&pdev->dev, "trizeps6_cpld_remove()\n");
>> + ? ? ? return 0;
>> +}
>> +
>> +#ifdef CONFIG_PM
>> +static int trizeps6_cpld_suspend(struct platform_device *pdev,
>> pm_message_t state)
>> +{
>> + ? ? ? return 0;
>> +}
>> +
>> +static int trizeps6_cpld_resume(struct platform_device *pdev)
>> +{
>> + ? ? ? return 0;
>> +}
>> +#endif
>> +
>> +static struct platform_driver trizeps6_cpld_driver = {
>> + ? ? ? .probe ? ? ? ? ?= trizeps6_cpld_probe,
>> + ? ? ? .remove ? ? ? ? = trizeps6_cpld_remove,
>> +#ifdef CONFIG_PM
>> + ? ? ? .suspend ? ? ? ?= trizeps6_cpld_suspend,
>> + ? ? ? .resume ? ? ? ? = trizeps6_cpld_resume,
>> +#endif
>> + ? ? ? .driver ? ? ? ? = {
>> + ? ? ? ? ? ? ? .name ? ? ? ? ? = "trizeps6-cpld",
>> + ? ? ? },
>> +};
>> +
>> +
>> +static int __devinit trizeps6_cpld_init(void)
>> +{
>> +
>> + ? ? ? return platform_driver_register(&trizeps6_cpld_driver);
>> +}
>> +
>> +static void trizeps6_cpld_exit(void)
>> +{
>> + ? ? ? platform_driver_unregister(&trizeps6_cpld_driver);
>> +}
>> +
>> +arch_initcall(trizeps6_cpld_init);
>> +module_exit(trizeps6_cpld_exit);
>> +
>> +MODULE_AUTHOR("Yupeng Schneider <yupeng.schneider@googlemail.com>");
>> +MODULE_DESCRIPTION("Trizeps VI CPLD");
>> +MODULE_LICENSE("GPL");
>> --
>> 1.6.3.3
>>
>>
>>
>>
>
^ permalink raw reply
* ARM: mmp: add Trizeps6 board support
From: Eric Miao @ 2011-02-10 2:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <42563.88.65.119.194.1297298342.squirrel@88.65.119.194>
On Thu, Feb 10, 2011 at 8:39 AM, Yupeng Schneider
<yupeng.schneider@ipms.fraunhofer.de> wrote:
> Hello Eric,
>
> i have made a BSP for the Trizeps6 Modul based on pxa168 Processor. Here
> is just a part of it, which now could be published, the other part could
> not because of NDA. Now i have a question:
>
> The Trizeps6 uses the same baseboard (ConXS) as the Trizeps4. Where would
> u to place the file conxs.c to make it accessible for mach-pxa und
> mach-mmp?
>
I would recommend arch/arm/plat-pxa/ or arch/arm/common/ at this moment.
> yours,
> Y.
>
>
>
>
>
>
>
^ permalink raw reply
* [PATCH] OMAP4: PandaBoard: Adding DVI support
From: Robert Nelson @ 2011-02-10 1:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <AANLkTi=h8oyJGcBAXercT9OeKae9PiDhu_ta+7EAC++J@mail.gmail.com>
On Wed, Feb 9, 2011 at 1:07 PM, Robert Nelson <robertcnelson@gmail.com> wrote:
> On Wed, Feb 9, 2011 at 8:08 AM, Gadiyar, Anand <gadiyar@ti.com> wrote:
>> On Wed, Feb 9, 2011 at 7:25 PM, Raghuveer Murthy
>> <raghuveer.murthy@ti.com> wrote:
>>> Adding DVI support to OMAP4 PandaBoard.
>>>
>>> PandaBoard uses TFP410 DVI Framer chip
>>> http://focus.ti.com/lit/ds/symlink/tfp410.pdf
>>>
>>> The TFP410 gets its power enable and display data over GPIO lines muxed
>>> in from OMAP4430. PandaBoard supports other LCD displays through expansion
>>> connectors, following board rework. This will disable the DVI interface.
>>> However, the existing mux settings remain the same
>>>
>>> PandaBoard additionally supports display over HDMI interface. It is
>>> mutually exclusive to display over DVI. Hence the mux settings need to be
>>> configured seperately, as and when HDMI is enabled
>>>
>>> Also, I2C3 bus used for reading EDID data from DVI Monitors is
>>> registered here. Since the design is similar to BeagleBoard, the code
>>> for the same is taken from the kernel.org commit e3333f48dd5cb21
>>> (omap: Adding beagle i2c eeprom driver to read EDID)
>>>
>>> Reviewed-by: Manjunath G Kondaiah <manjugk@ti.com>
>>> Reviewed-by: Anand Gadiyar <gadiyar@ti.com>
>>
>> I've also tested it on the Panda, and gone through this and most
>> of the other patches in the series. So if you like, you could
>> consider this an:
>>
>> Acked-by: Anand Gadiyar <gadiyar@ti.com>
>>
>>> Reviewed-by: Nishanth Menon <nm@ti.com>
>>> Reviewed-by: Sumit Semwal <sumit.semwal@ti.com>
>>> Signed-off-by: Raghuveer Murthy <raghuveer.murthy@ti.com>
>>> ---
>>>
>>> Base
>>> ====
>>> url =
>>> git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
>>> branch "master"
>>> commit 100b33c8bd8a3235fd0b7948338d6cbb3db3c63d
>>> tag 2.6.38-rc4
>>>
>>
>> To make it easier for someone to test, I've extracted this
>> and the 6 dependent series from patchwork, and hosted
>> them in a branch on my devel tree. They are available
>> against v2.6.38-rc4 here:
>>
>> git://dev.omapzoom.org/pub/scm/anand/linux-omap-usb.git
>>
>> in the display-patches-for-v2.6.38-rc4 branch if someone
>> wants to take a look.
>
> These work great on my Panda A1, (mainline 2.6.38-rc4 base) haven't
> seen any regressions on my Beagle C4 with the same patchset/image..
for the panda patches:
Tested-by: Robert Nelson <robertcnelson@gmail.com>
--
Robert Nelson
http://www.rcn-ee.com/
^ permalink raw reply
* [PATCH] ARM: omap1/nokia770: mark some functions __init
From: Tony Lindgren @ 2011-02-10 0:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110209192727.GC20795@atomide.com>
* Tony Lindgren <tony@atomide.com> [110209 11:26]:
> * Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de> [110208 01:58]:
>
> > > There are two more patches in this thread that are not yet
> > > applied/commented. Should I resend?
Thanks Uwe, I've applied them into devel-cleanup branch for the
next merge window.
Regards,
Tony
^ permalink raw reply
* ARM: mmp: add Trizeps6 board support
From: Yupeng Schneider @ 2011-02-10 0:39 UTC (permalink / raw)
To: linux-arm-kernel
Hello Eric,
i have made a BSP for the Trizeps6 Modul based on pxa168 Processor. Here
is just a part of it, which now could be published, the other part could
not because of NDA. Now i have a question:
The Trizeps6 uses the same baseboard (ConXS) as the Trizeps4. Where would
u to place the file conxs.c to make it accessible for mach-pxa und
mach-mmp?
yours,
Y.
^ permalink raw reply
* [PATCH]ARM: mmp: add Trizeps6 board support
From: Yupeng Schneider @ 2011-02-10 0:06 UTC (permalink / raw)
To: linux-arm-kernel
Hi all,
the following patch add the BSP for the Trizeps6 board with pxa168 Processor.
Signed-off-by: Yupeng Schneider <yupeng.schneider@googlemail.com>
---
arch/arm/mach-mmp/Kconfig | 29 ++
arch/arm/mach-mmp/Makefile | 1 +
arch/arm/mach-mmp/include/mach/audio.h | 29 ++
arch/arm/mach-mmp/include/mach/pxa168.h | 21 +
arch/arm/mach-mmp/include/mach/regs-apmu.h | 1 +
arch/arm/mach-mmp/include/mach/trizeps6.h | 122 ++++++
arch/arm/mach-mmp/include/mach/trizeps6_cpld.h | 87 +++++
arch/arm/mach-mmp/pxa168.c | 10 +
arch/arm/mach-mmp/trizeps6.c | 469
++++++++++++++++++++++++
arch/arm/mach-mmp/trizeps6_cpld.c | 145 ++++++++
10 files changed, 914 insertions(+), 0 deletions(-)
create mode 100755 arch/arm/mach-mmp/include/mach/audio.h
create mode 100755 arch/arm/mach-mmp/include/mach/trizeps6.h
create mode 100755 arch/arm/mach-mmp/include/mach/trizeps6_cpld.h create
mode 100755 arch/arm/mach-mmp/trizeps6.c
create mode 100755 arch/arm/mach-mmp/trizeps6_cpld.c
diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig index
0711d3b..8c6be81 100644
--- a/arch/arm/mach-mmp/Kconfig
+++ b/arch/arm/mach-mmp/Kconfig
@@ -64,6 +64,35 @@ config MACH_TETON_BGA
Say 'Y' here if you want to support the Marvell PXA168-based
Teton BGA Development Board.
+comment "Third Party Dev Platforms (sorted by vendor name)"
+
+config MACH_TRIZEPS6
+ bool "Keith und Koep Trizeps6 DIMM-Module"
+ select TRIZEPS6_PCMCIA
+ select CPU_PXA168
+ help
+ Say 'Y' here if you want to support TRIZEPS VI board Development Board.
+
+choice
+ prompt "Select base board for Trizeps module"
+ depends on MACH_TRIZEPS6
+
+config MACH_TRIZEPS6_CONXS
+ bool "ConXS Eval Board"
+
+config MACH_TRIZEPS6_UCONXS
+ bool "uConXS Eval Board"
+
+config MACH_TRIZEPS6_ANY
+ bool "another Board"
+
+endchoice
+
+config TRIZEPS6_PCMCIA
+ bool
+ help
+ Enable PCMCIA support for Trizeps modules
+
endmenu
config CPU_PXA168
diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile index
751cdbf..1b8744f 100644
--- a/arch/arm/mach-mmp/Makefile
+++ b/arch/arm/mach-mmp/Makefile
@@ -18,3 +18,4 @@ obj-$(CONFIG_MACH_TTC_DKB) += ttc_dkb.o
obj-$(CONFIG_MACH_FLINT) += flint.o
obj-$(CONFIG_MACH_MARVELL_JASPER) += jasper.o
obj-$(CONFIG_MACH_TETON_BGA) += teton_bga.o
+obj-$(CONFIG_MACH_TRIZEPS6) += trizeps6.o trizeps6_cpld.o
diff --git a/arch/arm/mach-mmp/include/mach/audio.h
b/arch/arm/mach-mmp/include/mach/audio.h
index 0000000..6ef474f
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/audio.h
@@ -0,0 +1,29 @@
+#ifndef __ASM_ARCH_AUDIO_H__
+#define __ASM_ARCH_AUDIO_H__
+
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/ac97_codec.h>
+
+/*
+ * @reset_gpio: AC97 reset gpio (normally gpio113 or gpio95)
+ * a -1 value means no gpio will be used for reset
+ * @codec_pdata: AC97 codec platform_data
+
+ * reset_gpio should only be specified for pxa27x CPUs where a silicon +
* bug prevents correct operation of the reset line. If not specified, + *
the default behaviour on these CPUs is to consider gpio 113 as the + *
AC97 reset line, which is the default on most boards.
+ */
+struct pxa2xx_audio_ops_t {
+ int (*startup)(struct snd_pcm_substream *, void *);
+ void (*shutdown)(struct snd_pcm_substream *, void *);
+ void (*suspend)(void *);
+ void (*resume)(void *);
+ void *priv;
+ int reset_gpio;
+ void *codec_pdata[AC97_BUS_MAX_DEVICES];
+};
+
+
+#endif
diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h
b/arch/arm/mach-mmp/include/mach/pxa168.h
index 1801e42..c4a9977 100644
--- a/arch/arm/mach-mmp/include/mach/pxa168.h
+++ b/arch/arm/mach-mmp/include/mach/pxa168.h
@@ -14,9 +14,12 @@ extern void pxa168_clear_keypad_wakeup(void);
#include <video/pxa168fb.h>
#include <plat/pxa27x_keypad.h>
#include <mach/cputype.h>
+#include <linux/pxa168_eth.h>
+#include <mach/audio.h>
extern struct pxa_device_desc pxa168_device_uart1;
extern struct pxa_device_desc pxa168_device_uart2;
+extern struct pxa_device_desc pxa168_device_uart3;
extern struct pxa_device_desc pxa168_device_twsi0;
extern struct pxa_device_desc pxa168_device_twsi1;
extern struct pxa_device_desc pxa168_device_pwm1;
@@ -31,6 +34,9 @@ extern struct pxa_device_desc pxa168_device_ssp5;
extern struct pxa_device_desc pxa168_device_nand;
extern struct pxa_device_desc pxa168_device_fb;
extern struct pxa_device_desc pxa168_device_keypad;
+extern struct pxa_device_desc pxa168_device_mfu;
+extern struct pxa_device_desc pxa168_device_ac97;
+
static inline int pxa168_add_uart(int id)
{
@@ -39,6 +45,7 @@ static inline int pxa168_add_uart(int id)
switch (id) {
case 1: d = &pxa168_device_uart1; break;
case 2: d = &pxa168_device_uart2; break;
+ case 3: d = &pxa168_device_uart3; break;
}
if (d == NULL)
@@ -117,4 +124,18 @@ static inline int pxa168_add_keypad(struct
pxa27x_keypad_platform_data *data)
return pxa_register_device(&pxa168_device_keypad, data, sizeof(*data));
}
+static inline int pxa168_add_mfu(struct pxa168_eth_platform_data *data) +{
+#if defined(CONFIG_PXA168_ETH)
+ return pxa_register_device(&pxa168_device_mfu, data, sizeof(*data)); +#else
+ return 0;
+#endif
+}
+
+static inline int pxa168_add_ac97(struct pxa2xx_audio_ops_t *ops) +{
+ return pxa_register_device(&pxa168_device_ac97, ops , sizeof(*ops)); +}
+
#endif /* __ASM_MACH_PXA168_H */
diff --git a/arch/arm/mach-mmp/include/mach/regs-apmu.h
b/arch/arm/mach-mmp/include/mach/regs-apmu.h
index ac47023..68d39bc 100644
--- a/arch/arm/mach-mmp/include/mach/regs-apmu.h
+++ b/arch/arm/mach-mmp/include/mach/regs-apmu.h
@@ -27,6 +27,7 @@
#define APMU_DMA APMU_REG(0x064)
#define APMU_GEU APMU_REG(0x068)
#define APMU_BUS APMU_REG(0x06c)
+#define APMU_MFU APMU_REG(0x0fc)
#define APMU_FNCLK_EN (1 << 4)
#define APMU_AXICLK_EN (1 << 3)
diff --git a/arch/arm/mach-mmp/include/mach/trizeps6.h
b/arch/arm/mach-mmp/include/mach/trizeps6.h
index 0000000..40b526a
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/trizeps6.h
@@ -0,0 +1,122 @@
+/************************************************************************
+ * Include file for TRIZEPS6 SoM and ConXS eval-board
+ * Copyright (c) Yupeng Schneider
+ * 2010
+
************************************************************************/ +
+/*
+ * Includes/Defines
+ */
+#ifndef _TRIPEPS6_H_
+#define _TRIPEPS6_H_
+
+#define STUART_SODIMM 1
+
+/* UART */
+#define GPIO104_UART1_DSR MFP_CFG(GPIO104, AF2)
+#define GPIO105_UART1_DCD MFP_CFG(GPIO105, AF2)
+#define GPIO107_UART2_TXD MFP_CFG_DRV(GPIO126, AF2, FAST)
+#define GPIO107_UART2_RXD MFP_CFG_DRV(GPIO36, AF2, FAST)
+#define GPIO109_UART2_CTS MFP_CFG(GPIO123, AF2)
+#define GPIO109_UART2_RTS MFP_CFG(GPIO124, AF2)
+#define GPIO30_UART3_TXD MFP_CFG_DRV(GPIO30, AF2, FAST)
+#define GPIO31_UART3_RXD MFP_CFG_DRV(GPIO31, AF2, FAST)
+#define GPIO32_UART3_CTS MFP_CFG(GPIO32, AF2)
+#define GPIO33_UART3_RTS MFP_CFG(GPIO33, AF2)
+
+/* MMC2 */
+#define GPIO122_MMC2_DAT3 MFP_CFG_DRV(GPIO122, AF4, FAST)
+#define GPIO121_MMC2_DAT2 MFP_CFG_DRV(GPIO121, AF4, FAST)
+#define GPIO120_MMC2_DAT1 MFP_CFG_DRV(GPIO120, AF4, FAST)
+#define GPIO119_MMC2_DAT0 MFP_CFG_DRV(GPIO119, AF4, FAST)
+#define GPIO28_MMC2_CMD MFP_CFG_DRV(GPIO28, AF6, FAST)
+#define GPIO29_MMC2_CLK MFP_CFG_DRV(GPIO29, AF6, FAST)
+#define GPIO53_MMC2_CD MFP_CFG(GPIO53, AF0)
+
+/*MMC4*/
+#define GPIO78_MMC4_DAT3 MFP_CFG_DRV(GPIO78, AF5, FAST)
+#define GPIO79_MMC4_DAT2 MFP_CFG_DRV(GPIO79, AF5, FAST)
+#define GPIO80_MMC4_DAT1 MFP_CFG_DRV(GPIO80, AF5, FAST)
+#define GPIO81_MMC4_DAT0 MFP_CFG_DRV(GPIO81, AF5, FAST)
+#define GPIO82_MMC4_CMD MFP_CFG_DRV(GPIO82, AF5, FAST)
+#define GPIO83_MMC4_CLK MFP_CFG_DRV(GPIO83, AF5, FAST)
+
+/* I2C */
+#define GPIO102_CI2C_SDA MFP_CFG(GPIO102, AF1)
+
+/* MFU */
+#define GPIO86_TX_CLK MFP_CFG(GPIO86, AF5)
+#define GPIO87_TX_EN MFP_CFG(GPIO87, AF5)
+#define GPIO88_TX_DQ3 MFP_CFG(GPIO88, AF5)
+#define GPIO89_TX_DQ2 MFP_CFG(GPIO89, AF5)
+#define GPIO90_TX_DQ1 MFP_CFG(GPIO90, AF5)
+#define GPIO91_TX_DQ0 MFP_CFG(GPIO91, AF5)
+#define GPIO92_MII_CRS MFP_CFG(GPIO92, AF5)
+#define GPIO93_MII_COL MFP_CFG(GPIO93, AF5)
+#define GPIO94_RX_CLK MFP_CFG(GPIO94, AF5)
+#define GPIO95_RX_ER MFP_CFG(GPIO95, AF5)
+#define GPIO96_RX_DQ3 MFP_CFG(GPIO96, AF5)
+#define GPIO97_RX_DQ2 MFP_CFG(GPIO97, AF5)
+#define GPIO98_RX_DQ1 MFP_CFG(GPIO98, AF5)
+#define GPIO99_RX_DQ0 MFP_CFG(GPIO99, AF5)
+#define GPIO100_MII_MDC MFP_CFG(GPIO100, AF5)
+#define GPIO101_MII_MDIO MFP_CFG(GPIO101, AF5)
+#define GPIO103_RX_DV MFP_CFG(GPIO103, AF5)
+
+/* AC97 */
+#define GPIO115_AC97_BITCLK MFP_CFG(GPIO115, AF6)
+#define GPIO114_AC97_SDATA_IN_0 MFP_CFG(GPIO114, AF6)
+#define GPIO116_AC97_SDATA_IN_1 MFP_CFG(GPIO116, AF6)
+#define GPIO117_AC97_SDATA_OUT MFP_CFG(GPIO117, AF6)
+#define GPIO118_AC97_SYNC MFP_CFG(GPIO118, AF6)
+
+
+
+#define TRIZEPS6_PHYS_BASE 0xd4000000
+
+
+#define TRIZEPS6_PIC_PHYS (0x88000000) /* CS0-3 Logic chip on ConXS */
+ /* Logic on ConXS-board CSFR register*/
+#define TRIZEPS6_CFSR_PHYS (TRIZEPS6_PIC_PHYS)
+ /* Logic on ConXS-board BOCR register*/
+#define TRIZEPS6_BOCR_PHYS (TRIZEPS6_PIC_PHYS+0x00200000)
+ /* Logic on ConXS-board IRCR register*/
+#define TRIZEPS6_IRCR_PHYS (TRIZEPS6_PIC_PHYS+0x00300000)
+ /* Logic on ConXS-board UPSR register*/
+#define TRIZEPS6_UPSR_PHYS (TRIZEPS6_PIC_PHYS+0x00280000)
+ /* Logic on ConXS-board DICR register*/
+#define TRIZEPS6_DICR_PHYS (TRIZEPS6_PIC_PHYS+0x00380000)
+
+
+#define TRIZEPS6_CPLD_PHYS (0x8e000000) /* CPLD on Trizeps6 module */ +
+#define TRIZEPS6_CPLD_CTRL_PHYS (TRIZEPS6_CPLD_PHYS)
+#define TRIZEPS6_CPLD_FTUR_PHYS (TRIZEPS6_CPLD_PHYS+0x4)
+#define TRIZEPS6_CPLD_HIBE_PHYS (TRIZEPS6_CPLD_PHYS+0x8)
+#define TRIZEPS6_CPLD_PWM_PHYS (TRIZEPS6_CPLD_PHYS+0xc)
+#define TRIZEPS6_CPLD_PLDR_PHYS (TRIZEPS6_CPLD_PHYS+0x10)
+#define TRIZEPS6_CPLD_PSET_PHYS (TRIZEPS6_CPLD_PHYS+0x14)
+#define TRIZEPS6_CPLD_TTLO_PHYS (TRIZEPS6_CPLD_PHYS+0x18)
+
+
+/* MMC socket */
+#define GPIO_MMC2_DET 53
+#define TRIZEPS6_MMC2_IRQ IRQ_GPIO(mfp_to_gpio(MFP_PIN_GPIO53))
+#define GPIO_MMC4_DET 41
+#define TRIZEPS6_MMC4_IRQ IRQ_GPIO(mfp_to_gpio(MFP_PIN_GPIO41)
+
+/* Off-module PIC on ConXS board */
+#define GPIO_PIC 51
+#define TRIZEPS6_PIC_IRQ IRQ_GPIO(mfp_to_gpio(MFP_PIN_GPIO51)
+
+/* PCMCIA socket Compact Flash */
+#define GPIO_PCD 43 /* PCMCIA Card Detect */
+#define TRIZEPS6_CD_IRQ IRQ_GPIO(mfp_to_gpio(MFP_PIN_GPIO43)
+#define GPIO_PRDY 113 /* READY / nINT */
+#define TRIZEPS6_READY_NINT IRQ_GPIO(mfp_to_gpio(MFP_PIN_GPIO113) +
+#define trizeps6_GPIO_CODEC_IRQ 116
+
+extern void trizeps6_ac97_acreset(int i);
+
+#endif /* _TRIPEPS6_H_ */
diff --git a/arch/arm/mach-mmp/include/mach/trizeps6_cpld.h
b/arch/arm/mach-mmp/include/mach/trizeps6_cpld.h
index 0000000..8538a6b
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/trizeps6_cpld.h
@@ -0,0 +1,87 @@
+#ifndef _TRIPEPS6_CPLD_H_
+#define _TRIPEPS6_CPLD_H_
+
+/* index of resource */
+#define CTRL_S 0
+#define CTRL_R 1
+#define FTUR_S 2
+#define FTUR_R 3
+#define HIBE_S 4
+#define HIBE_R 5
+#define PWM 6
+#define PLDR_S 7
+#define PLDR_R 8
+#define PSET_S 9
+#define PSET_R 10
+#define TTLO_S 11
+#define TTLO_R 12
+
+#define CPLD_CTRL_S cpld.addr[CTRL_S].val
+#define CPLD_CTRL_R cpld.addr[CTRL_R].val
+#define CPLD_CONTROL_GR (1 << 0)
+#define CPLD_CONTROL_CODEC (1 << 2)
+#define CPLD_CONTROL_ETHPHY (1 << 3)
+#define CPLD_CONTROL_RWL (1 << 4)
+#define CPLD_CONTROL_RBT (1 << 5)
+
+#define CPLD_FTUR_S cpld.addr[FTUR_S].val
+#define CPLD_FTUR_R cpld.addr[FTUR_R].val
+#define CPLD_FEATURE_UART3_SODIMM (1 << 0)
+#define CPLD_FEATURE_UART3_BT (1 << 1)
+#define CPLD_FEATURE_CF_MODE (1 << 2)
+#define CPLD_FEATURE_TTLIO (1 << 3)
+#define CPLD_PWM_SODIMM_P69 (1 << 4)
+#define CPLD_PWM_SODIMM_P77 (1 << 5)
+#define CPLD_PWM_SODIMM_P106 (1 << 6)
+#define CPLD_BT_PWM_SODIMM (1 << 7)
+
+#define CPLD_HIBE_S cpld.addr[HIBE_S].val
+#define CPLD_HIBE_R cpld.addr[HIBE_R].val
+#define CPLD_HIBERNATE_MODE (1 << 0)
+#define CPLD_HIBERNATE_WAKE_TOUCH (1 << 1)
+#define CPLD_HIBERNATE_WAKE_PMIC (1 << 2)
+#define CPLD_HIBERNATE_WAKE_IRQ_P43 (1 << 3)
+
+#define CPLD_PWM cpld.addr[PWM].val
+
+#define CPLD_PINLDR cpld.addr[PINLDR].val
+#define CPLD_PINLDR_P69 (1 << 0)
+#define CPLD_PINLDR_P100_PSKTSEL (1 << 1)
+#define CPLD_PINLDR_P98_CFNREG (1 << 2)
+#define CPLD_PINLDR_P104_CFNIOIS16 (1 << 3)
+#define CPLD_PINLDR_P93_RDNWR (1 << 4)
+#define CPLD_PINLDR_P104_IRQ_P43 (1 << 5)
+
+#define CPLD_PSET_S cpld.addr[PSET_S].val
+#define CPLD_PSET_R cpld.addr[PSET_R].val
+#define CPLD_PINSET_P69 (1 << 0)
+#define CPLD_PINSET_P100_PSKTSEL (1 << 1)
+#define CPLD_PINSET_P98_CFNREG (1 << 2)
+#define CPLD_PINSET_P104_CFNIOIS16 (1 << 3)
+#define CPLD_PINSET_P93_RDnWR (1 << 4)
+
+#define CPLD_TTLO_S cpld.addr[TTLO_S].val
+#define CPLD_TTLO_R cpld.addr[TTLO_R].val
+#define CPLD_TTLIO_W_A8 (1 << 0)
+#define CPLD_TTLIO_W_A9 (1 << 1)
+#define CPLD_TTLIO_W_A10 (1 << 2)
+#define CPLD_TTLIO_W_A11 (1 << 3)
+#define CPLD_TTLIO_W_A12 (1 << 4)
+#define CPLD_TTLIO_W_A13 (1 << 5)
+#define CPLD_TTLIO_W_A14 (1 << 6)
+#define CPLD_TTLIO_W_A15 (1 << 7)
+#define CPLD_TTLIO_r_A0 (1 << 0)
+#define CPLD_TTLIO_r_A1 (1 << 1)
+#define CPLD_TTLIO_r_A2 (1 << 2)
+#define CPLD_TTLIO_r_A3 (1 << 3)
+#define CPLD_TTLIO_r_A4 (1 << 4)
+#define CPLD_TTLIO_r_A5 (1 << 5)
+#define CPLD_TTLIO_r_A6 (1 << 6)
+#define CPLD_TTLIO_r_A7 (1 << 7)
+
+
+
+extern unsigned short trizeps6_cpld_readw(unsigned int reg);
+extern inline void trizeps6_cpld_writew(unsigned int reg, unsigned short
value);
+
+#endif /* _TRIPEPS6_CPLD_H_ */
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c index
72b4e76..9c2396e 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -66,6 +66,7 @@ void __init pxa168_init_irq(void)
/* APB peripheral clocks */
static APBC_CLK(uart1, PXA168_UART1, 1, 14745600);
static APBC_CLK(uart2, PXA168_UART2, 1, 14745600);
+static APBC_CLK(uart3, PXA168_UART3, 1, 14745600);
static APBC_CLK(twsi0, PXA168_TWSI0, 1, 33000000);
static APBC_CLK(twsi1, PXA168_TWSI1, 1, 33000000);
static APBC_CLK(pwm1, PXA168_PWM1, 1, 13000000);
@@ -78,14 +79,18 @@ static APBC_CLK(ssp3, PXA168_SSP3, 4, 0);
static APBC_CLK(ssp4, PXA168_SSP4, 4, 0);
static APBC_CLK(ssp5, PXA168_SSP5, 4, 0);
static APBC_CLK(keypad, PXA168_KPC, 0, 32000);
+static APBC_CLK(ac97, PXA168_AC97, 0, 24576000);
+
static APMU_CLK(nand, NAND, 0x01db, 208000000);
static APMU_CLK(lcd, LCD, 0x7f, 312000000);
+static APMU_CLK(mfu, MFU, 0x9, 0);
/* device and clock bindings */
static struct clk_lookup pxa168_clkregs[] = {
INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
+ INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL),
INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL),
INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL),
INIT_CLKREG(&clk_pwm1, "pxa168-pwm.0", NULL),
@@ -100,6 +105,8 @@ static struct clk_lookup pxa168_clkregs[] = {
INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
INIT_CLKREG(&clk_lcd, "pxa168-fb", NULL),
INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL),
+ INIT_CLKREG(&clk_mfu, "pxa168-eth", "MFUCLK"),
+ INIT_CLKREG(&clk_ac97, "pxa2xx-ac97", "AC97CLK"),
};
static int __init pxa168_init(void)
@@ -149,6 +156,7 @@ void pxa168_clear_keypad_wakeup(void)
/* on-chip devices */
PXA168_DEVICE(uart1, "pxa2xx-uart", 0, UART1, 0xd4017000, 0x30, 21, 22);
PXA168_DEVICE(uart2, "pxa2xx-uart", 1, UART2, 0xd4018000, 0x30, 23, 24);
+PXA168_DEVICE(uart3, "pxa2xx-uart", 2, UART3, 0xd4026000, 0x30, 23, 24);
PXA168_DEVICE(twsi0, "pxa2xx-i2c", 0, TWSI0, 0xd4011000, 0x28);
PXA168_DEVICE(twsi1, "pxa2xx-i2c", 1, TWSI1, 0xd4025000, 0x28);
PXA168_DEVICE(pwm1, "pxa168-pwm", 0, NONE, 0xd401a000, 0x10);
@@ -163,3 +171,5 @@ PXA168_DEVICE(ssp4, "pxa168-ssp", 3, SSP4, 0xd4020000,
0x40, 58, 59);
PXA168_DEVICE(ssp5, "pxa168-ssp", 4, SSP5, 0xd4021000, 0x40, 60, 61);
PXA168_DEVICE(fb, "pxa168-fb", -1, LCD, 0xd420b000, 0x1c8);
PXA168_DEVICE(keypad, "pxa27x-keypad", -1, KEYPAD, 0xd4012000, 0x4c);
+PXA168_DEVICE(mfu, "pxa168-eth", -1, MFU, 0xc0800000, 0x0FFF);
+PXA168_DEVICE(ac97, "pxa2xx-ac97", -1, AC97, 0xd402B000, 0x0fff); diff
--git a/arch/arm/mach-mmp/trizeps6.c b/arch/arm/mach-mmp/trizeps6.c index
0000000..a935f14
--- /dev/null
+++ b/arch/arm/mach-mmp/trizeps6.c
@@ -0,0 +1,469 @@
+/*
+ * linux/arch/arm/mach-mmp/trizeps6.c
+ *
+ * Support for the Keith und Koep Trizeps6 Modul Platform
+ * based on Marvell PXA168-CPU
+ *
+ * Author: Yupeng Schneider
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as + *
publishhed by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/nand.h>
+#include <linux/delay.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/addr-map.h>
+#include <mach/mfp-pxa168.h>
+#include <mach/pxa168.h>
+#include <mach/gpio.h>
+#include <linux/pxa168_eth.h>
+#include <mach/irqs.h>
+#include <mach/trizeps6.h>
+#include <mach/trizeps6_cpld.h>
+#include "common.h"
+#include <linux/mmc/sdhci.h>
+#include <linux/ucb1400.h>
+#include <mach/audio.h>
+
+
+static unsigned long trizeps6_pin_config[] __initdata = {
+ /* Data Flash Interface */
+ GPIO0_DFI_D15,
+ GPIO1_DFI_D14,
+ GPIO2_DFI_D13,
+ GPIO3_DFI_D12,
+ GPIO4_DFI_D11,
+ GPIO5_DFI_D10,
+ GPIO6_DFI_D9,
+ GPIO7_DFI_D8,
+ GPIO8_DFI_D7,
+ GPIO9_DFI_D6,
+ GPIO10_DFI_D5,
+ GPIO11_DFI_D4,
+ GPIO12_DFI_D3,
+ GPIO13_DFI_D2,
+ GPIO14_DFI_D1,
+ GPIO15_DFI_D0,
+
+ /* Static Memory Controller */
+ GPIO18_SMC_nCS0,
+ GPIO34_SMC_nCS1,
+ GPIO23_SMC_nLUA,
+ GPIO25_SMC_nLLA,
+ GPIO28_SMC_RDY,
+ GPIO29_SMC_SCLK,
+ GPIO35_SMC_BE1,
+ GPIO36_SMC_BE2,
+
+
+ /* UART1 */
+ GPIO107_UART1_RXD,
+ GPIO108_UART1_TXD,
+ GPIO107_UART1_RXD,
+ GPIO108_UART1_TXD,
+ GPIO109_UART1_RTS,
+ GPIO110_UART1_CTS,
+ GPIO111_UART1_RI,
+ GPIO104_UART1_DSR,
+ GPIO112_UART1_DTR,
+ GPIO105_UART1_DCD,
+
+ /* UART2 */
+ GPIO107_UART2_TXD,
+ GPIO107_UART2_RXD,
+ GPIO109_UART2_CTS,
+ GPIO109_UART2_RTS,
+
+ /* UART3 */
+ GPIO30_UART3_TXD,
+ GPIO31_UART3_RXD,
+ GPIO32_UART3_CTS,
+ GPIO33_UART3_RTS,
+
+
+ /* MFU */
+ GPIO86_TX_CLK,
+ GPIO87_TX_EN,
+ GPIO88_TX_DQ3,
+ GPIO89_TX_DQ2,
+ GPIO90_TX_DQ1,
+ GPIO91_TX_DQ0,
+ GPIO92_MII_CRS,
+ GPIO93_MII_COL,
+ GPIO94_RX_CLK,
+ GPIO95_RX_ER,
+ GPIO96_RX_DQ3,
+ GPIO97_RX_DQ2,
+ GPIO98_RX_DQ1,
+ GPIO99_RX_DQ0,
+ GPIO100_MII_MDC,
+ GPIO101_MII_MDIO,
+ GPIO103_RX_DV,
+
+ /* USB OTG */
+ GPIO85_GPIO,
+ GPIO47_GPIO,
+
+ /* i2c bus */
+ GPIO102_CI2C_SDA,
+ GPIO106_CI2C_SCL,
+
+
+ /* MMC2 */
+ GPIO122_MMC2_DAT3 | MFP_PULL_HIGH,
+ GPIO121_MMC2_DAT2 | MFP_PULL_HIGH,
+ GPIO120_MMC2_DAT1 | MFP_PULL_HIGH,
+ GPIO119_MMC2_DAT0 | MFP_PULL_HIGH,
+ GPIO28_MMC2_CMD | MFP_PULL_HIGH,
+ GPIO29_MMC2_CLK,
+ GPIO53_MMC2_CD | MFP_PULL_LOW, /* TRIZEPS6_MMC2_IRQ */
+
+ /* MMC4 */
+ GPIO78_MMC4_DAT3 | MFP_PULL_HIGH,
+ GPIO79_MMC4_DAT2 | MFP_PULL_HIGH,
+ GPIO80_MMC4_DAT1 | MFP_PULL_HIGH,
+ GPIO81_MMC4_DAT0 | MFP_PULL_HIGH,
+ GPIO82_MMC4_CMD | MFP_PULL_HIGH,
+ GPIO83_MMC4_CLK,
+
+ /* LCD */
+ GPIO56_LCD_FCLK_RD,
+ GPIO57_LCD_LCLK_A0,
+ GPIO58_LCD_PCLK_WR,
+ GPIO59_LCD_DENA_BIAS,
+ GPIO60_LCD_DD0,
+ GPIO61_LCD_DD1,
+ GPIO62_LCD_DD2,
+ GPIO63_LCD_DD3,
+ GPIO64_LCD_DD4,
+ GPIO65_LCD_DD5,
+ GPIO66_LCD_DD6,
+ GPIO67_LCD_DD7,
+ GPIO68_LCD_DD8,
+ GPIO69_LCD_DD9,
+ GPIO70_LCD_DD10,
+ GPIO71_LCD_DD11,
+ GPIO72_LCD_DD12,
+ GPIO73_LCD_DD13,
+ GPIO74_LCD_DD14,
+ GPIO75_LCD_DD15,
+
+
+ /* AC97 */
+ GPIO115_AC97_BITCLK,
+ GPIO114_AC97_SDATA_IN_0,
+ GPIO117_AC97_SDATA_OUT,
+ GPIO118_AC97_SYNC,
+ GPIO116_GPIO,
+
+
+ GPIO51_GPIO, /* TRIZEPS6_PIC_IRQ */
+ GPIO27_GPIO, /* Ethernet IRQ */
+};
+
+
+
+/****************************************************************************
+ * CPLD
+
****************************************************************************/
+
+static struct resource tri6_cpld_resources[] = {
+ [CTRL_S] = {
+ .start = TRIZEPS6_CPLD_CTRL_PHYS,
+ .end = TRIZEPS6_CPLD_CTRL_PHYS+1,
+ .flags = IORESOURCE_MEM,
+ },
+ [CTRL_R] = {
+ .start = TRIZEPS6_CPLD_CTRL_PHYS+2,
+ .end = TRIZEPS6_CPLD_CTRL_PHYS+3,
+ .flags = IORESOURCE_MEM,
+ },
+ [FTUR_S] = {
+ .start = TRIZEPS6_CPLD_FTUR_PHYS,
+ .end = TRIZEPS6_CPLD_FTUR_PHYS+1,
+ .flags = IORESOURCE_MEM,
+ },
+ [FTUR_R] = {
+ .start = TRIZEPS6_CPLD_FTUR_PHYS+2,
+ .end = TRIZEPS6_CPLD_FTUR_PHYS+3,
+ .flags = IORESOURCE_MEM,
+ },
+ [HIBE_S] = {
+ .start = TRIZEPS6_CPLD_HIBE_PHYS,
+ .end = TRIZEPS6_CPLD_HIBE_PHYS+1,
+ .flags = IORESOURCE_MEM,
+ },
+ [HIBE_R] = {
+ .start = TRIZEPS6_CPLD_HIBE_PHYS+2,
+ .end = TRIZEPS6_CPLD_HIBE_PHYS+3,
+ .flags = IORESOURCE_MEM,
+ },
+ [PWM] = {
+ .start = TRIZEPS6_CPLD_PWM_PHYS,
+ .end = TRIZEPS6_CPLD_PWM_PHYS+1,
+ .flags = IORESOURCE_MEM,
+ },
+ [PLDR_S] = {
+ .start = TRIZEPS6_CPLD_PLDR_PHYS,
+ .end = TRIZEPS6_CPLD_PLDR_PHYS+1,
+ .flags = IORESOURCE_MEM,
+ },
+ [PLDR_R] = {
+ .start = TRIZEPS6_CPLD_PLDR_PHYS+2,
+ .end = TRIZEPS6_CPLD_PLDR_PHYS+3,
+ .flags = IORESOURCE_MEM,
+ },
+ [PSET_S] = {
+ .start = TRIZEPS6_CPLD_PSET_PHYS,
+ .end = TRIZEPS6_CPLD_PSET_PHYS+1,
+ .flags = IORESOURCE_MEM,
+ },
+ [PSET_R] = {
+ .start = TRIZEPS6_CPLD_PSET_PHYS+2,
+ .end = TRIZEPS6_CPLD_PSET_PHYS+3,
+ .flags = IORESOURCE_MEM,
+ },
+ [TTLO_S] = {
+ .start = TRIZEPS6_CPLD_TTLO_PHYS,
+ .end = TRIZEPS6_CPLD_TTLO_PHYS+1,
+ .flags = IORESOURCE_MEM,
+ },
+ [TTLO_R] = {
+ .start = TRIZEPS6_CPLD_TTLO_PHYS+2,
+ .end = TRIZEPS6_CPLD_TTLO_PHYS+3,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static int tri6_cpld_platdata = 1;
+
+static struct platform_device cpld_device = {
+ .name = "trizeps6-cpld",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(tri6_cpld_resources),
+ .resource = tri6_cpld_resources,
+ .dev = {
+ .platform_data = &tri6_cpld_platdata,
+ }
+};
+
+
+/******************************************************************************
+ * Audio and Touchscreen
+
******************************************************************************/
+
+static struct ucb1400_pdata trizeps6_ucb1400_pdata = {
+ .irq = gpio_to_irq(trizeps6_GPIO_CODEC_IRQ),
+};
+
+static struct pxa2xx_audio_ops_t trizeps6_ac97_pdata = {
+ .codec_pdata = { &trizeps6_ucb1400_pdata, },
+};
+
+static struct platform_device trizeps6_ucb1400_device = {
+ .name = "ucb1400_core",
+ .id = -1,
+ .dev = {
+ .platform_data = &trizeps6_ucb1400_pdata,
+ },
+};
+
+static void __init trizeps6_ts_init(void)
+{
+ pxa168_add_ac97(&trizeps6_ac97_pdata);
+ platform_device_register(&trizeps6_ucb1400_device);
+}
+
+void trizeps6_ac97_acreset(int i)
+{ unsigned short value;
+
+ if (i == 1) {
+
+ value = trizeps6_cpld_readw(CTRL_S);
+ trizeps6_cpld_writew(CTRL_S, value | CPLD_CONTROL_CODEC);
+ }
+ if (!i) {
+ value = trizeps6_cpld_readw(CTRL_R);
+ trizeps6_cpld_writew(CTRL_R, value | CPLD_CONTROL_CODEC);
+ }
+}
+
+/******************************************************************************
+ * Ethernet
+
******************************************************************************/
+static int trizeps6_eth_init(void)
+{
+ unsigned short value;
+
+ value = trizeps6_cpld_readw(CTRL_R);
+ trizeps6_cpld_writew(CTRL_R, value | CPLD_CONTROL_ETHPHY);
+ return 0;
+
+}
+
+static struct pxa168_eth_platform_data trizeps6_eth_data = {
+ .phy_addr = 0x1f,
+ .port_number = 0,
+ .init = trizeps6_eth_init,
+};
+
+/******************************************************************************
+ * NAND
+
******************************************************************************/
+static struct pxa3xx_nand_timing stnand02gw3b2d_timing = {
+ .tCH = 10,
+ .tCS = 40,
+ .tWH = 20,
+ .tWP = 24,
+ .tRH = 20,
+ .tRP = 24,
+ .tR = 50000,
+ .tWHR = 120,
+ .tAR = 20,
+
+};
+
+static struct pxa3xx_nand_cmdset largepage_cmdset = {
+ .read1 = 0x3000,
+ .read2 = 0x0050,
+ .program = 0x1080,
+ .read_status = 0x0070,
+ .read_id = 0x0090,
+ .erase = 0xD060,
+ .reset = 0x00FF,
+ .lock = 0x002A,
+ .unlock = 0x2423,
+ .lock_status = 0x007A,
+};
+
+static struct pxa3xx_nand_flash trizeps6_flashes[] = {
+ {
+ .timing = &stnand02gw3b2d_timing,
+ .cmdset = &largepage_cmdset,
+ .page_per_block = 64,
+ .page_size = 2048,
+ .flash_width = 8,
+ .dfc_width = 8,
+ .num_blocks = 2048,
+ .chip_id = 0xda20,
+ },
+};
+
+
+static struct mtd_partition trizeps6_nand_partitions[] = {
+ {
+ .name = "bootloader",
+ .offset = 0,
+ .size = SZ_16M,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "reserved",
+ .offset = MTDPART_OFS_APPEND,
+ .size = SZ_128K,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "kernel",
+ .offset = MTDPART_OFS_APPEND,
+ .size = (2*SZ_2M + SZ_1M),
+ .mask_flags = 0,
+ }, {
+ .name = "filesystem",
+ .offset = MTDPART_OFS_APPEND,
+ .size = (SZ_256M - 3*SZ_8M),
+ .mask_flags = 0,
+ }
+};
+
+static struct pxa3xx_nand_platform_data trizeps6_nand_info = {
+ .enable_arbiter = 1,
+ .parts = trizeps6_nand_partitions,
+ .nr_parts = ARRAY_SIZE(trizeps6_nand_partitions),
+ .flash = trizeps6_flashes,
+ .num_flash = ARRAY_SIZE(trizeps6_flashes),
+ .keep_config = 0
+};
+
+
+
+static struct i2c_board_info trizeps6_i2c_devices[] = {
+ { I2C_BOARD_INFO("pcf8593", 0x51), },
+};
+
+
+/******************************************************************************
+ * LCD
+
******************************************************************************/
+static struct fb_videomode trizeps6_video_modes[] = {
+ [0] = {
+ .pixclock = 39720,
+ .refresh = 60,
+ .xres = 640,
+ .yres = 480,
+ .hsync_len = 63,
+ .left_margin = 12,
+ .right_margin = 12,
+ .vsync_len = 4,
+ .upper_margin = 32,
+ .lower_margin = 10,
+ .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT,
+ },
+};
+
+static struct pxa168fb_mach_info trizeps6_lcd_info = {
+ .id = "Base-trizeps6",
+ .modes = trizeps6_video_modes,
+ .num_modes = ARRAY_SIZE(trizeps6_video_modes),
+ .pix_fmt = PIX_FMT_RGB565,
+ .io_pin_allocation_mode = PIN_MODE_DUMB_16_GPIO,
+ .dumb_mode = DUMB_MODE_RGB565,
+ .active = 1,
+ .panel_rbswap = 1,
+ .invert_pixclock = 0,
+};
+
+
+static struct platform_device *trizeps6_devices[] __initdata = {
+ &cpld_device,
+};
+
+static void __init trizeps6_init(void)
+{
+ mfp_config(ARRAY_AND_SIZE(trizeps6_pin_config));
+
+ pxa168_add_uart(1);
+ pxa168_add_uart(2);
+#ifdef STUART_SODIMM
+ pxa168_add_uart(3);
+#endif
+ pxa168_add_nand(&trizeps6_nand_info);
+ platform_add_devices(trizeps6_devices,
+ ARRAY_SIZE(trizeps6_devices));
+
+ pxa168_add_fb(&trizeps6_lcd_info);
+ pxa168_add_mfu(&trizeps6_eth_data);
+ pxa168_add_twsi(0, NULL, ARRAY_AND_SIZE(trizeps6_i2c_devices));
+ trizeps6_ts_init();
+}
+
+static void __init trizeps6_map_io(void)
+{
+ mmp_map_io();
+}
+
+MACHINE_START(TRIZEPS6, "PXA168-based Keith & Koep Trizeps VI Development
Module")
+ /* MAINTAINER("Yupeng Schneider" <yupeng.schneider@googlemail.com>) */
+ .map_io = trizeps6_map_io,
+ .init_irq = pxa168_init_irq,
+ .timer = &pxa168_timer,
+ .init_machine = trizeps6_init,
+MACHINE_END
+
+
diff --git a/arch/arm/mach-mmp/trizeps6_cpld.c
b/arch/arm/mach-mmp/trizeps6_cpld.c
index 0000000..2577b0f
--- /dev/null
+++ b/arch/arm/mach-mmp/trizeps6_cpld.c
@@ -0,0 +1,145 @@
+/*
+ * linux/arch/arm/mach-mmp/trizeps6_cpld.c
+ *
+ *
+ * Author: Yupeng Schneider
+ * Created: 27 10, 2010
+ * Copyright: Yupeng Schneider
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as + *
published by the Free Software Foundation.*/
+
+#include <linux/kernel.h>
+#include <linux/ioport.h>
+#include <linux/platform_device.h>
+#include <linux/device.h>
+#include <linux/module.h>
+
+#include <asm/io.h>
+#include <asm/delay.h>
+#include <mach/trizeps6.h>
+#include <mach/trizeps6_cpld.h>
+
+struct cpld_info {
+ struct region {
+ struct resource *res;
+ struct resource *req;
+ void __iomem *iom;
+ unsigned short val;
+ } addr[7];
+} cpld_info;
+
+static struct cpld_info cpld = { { { 0 } } };
+
+inline void trizeps6_cpld_writew(unsigned int reg, unsigned short value) +{
+ if ((cpld.addr[reg].iom != NULL))
+ writew(value, cpld.addr[reg].iom);
+
+}
+
+unsigned short trizeps6_cpld_readw(unsigned int reg)
+{
+ short value = 0;
+ if (reg != HIBE_S || reg != HIBE_R || reg != PWM || reg != PSET_S || reg
!= PSET_R) {
+
+ if ((cpld.addr[reg].iom != NULL))
+ value = readw(cpld.addr[reg].iom);
+ }
+ return value;
+}
+EXPORT_SYMBOL(trizeps6_cpld_readw);
+
+static int trizeps6_cpld_probe(struct platform_device *pdev)
+{
+ int i;
+
+ CPLD_CTRL_R = CPLD_CONTROL_ETHPHY | CPLD_CONTROL_GR;
+#ifdef STUART_SODIMM
+ CPLD_FTUR_S = CPLD_FEATURE_UART3_SODIMM;
+#endif
+ for (i = CTRL_S; i <= TTLO_R; i++) {
+ cpld.addr[i].res = platform_get_resource(pdev, IORESOURCE_MEM, i);
+ if (cpld.addr[i].res == NULL) {
+ dev_err(&pdev->dev, "cannot get resource %d area\n", i);
+ return -EIO;
+ }
+ cpld.addr[i].req = request_mem_region(cpld.addr[i].res->start,
+ 2, pdev->name);
+ if (cpld.addr[i].req == NULL) {
+ dev_err(&pdev->dev, "cannot claim addr area %d\n", i);
+ return -EIO;
+ }
+ cpld.addr[i].iom = ioremap(cpld.addr[i].res->start, 2);
+ if (cpld.addr[i].iom == NULL) {
+ dev_err(&pdev->dev, "cannot remap addr area %d\n", i);
+ return -EIO;
+ }
+ switch (i) {
+ case CTRL_R:
+ trizeps6_cpld_writew(CTRL_R, CPLD_CTRL_R);
+ break;
+ case FTUR_S:
+ trizeps6_cpld_writew(FTUR_S, CPLD_FTUR_S);
+ break;
+ default:
+ ;
+
+ }
+ dev_dbg(&pdev->dev, "mapped region [%d] %08x -> %p\n", i,
+ (int)cpld.addr[i].req->start, cpld.addr[i].iom);
+ }
+
+
+ return 0;
+}
+
+static int trizeps6_cpld_remove(struct platform_device *pdev)
+{
+ dev_dbg(&pdev->dev, "trizeps6_cpld_remove()\n");
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int trizeps6_cpld_suspend(struct platform_device *pdev,
pm_message_t state)
+{
+ return 0;
+}
+
+static int trizeps6_cpld_resume(struct platform_device *pdev)
+{
+ return 0;
+}
+#endif
+
+static struct platform_driver trizeps6_cpld_driver = {
+ .probe = trizeps6_cpld_probe,
+ .remove = trizeps6_cpld_remove,
+#ifdef CONFIG_PM
+ .suspend = trizeps6_cpld_suspend,
+ .resume = trizeps6_cpld_resume,
+#endif
+ .driver = {
+ .name = "trizeps6-cpld",
+ },
+};
+
+
+static int __devinit trizeps6_cpld_init(void)
+{
+
+ return platform_driver_register(&trizeps6_cpld_driver);
+}
+
+static void trizeps6_cpld_exit(void)
+{
+ platform_driver_unregister(&trizeps6_cpld_driver);
+}
+
+arch_initcall(trizeps6_cpld_init);
+module_exit(trizeps6_cpld_exit);
+
+MODULE_AUTHOR("Yupeng Schneider <yupeng.schneider@googlemail.com>");
+MODULE_DESCRIPTION("Trizeps VI CPLD");
+MODULE_LICENSE("GPL");
--
1.6.3.3
^ permalink raw reply related
* [PATCH V3 1/1] ST SPEAr: PCIE gadget suppport
From: Andrew Morton @ 2011-02-09 23:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1296742149-18102-1-git-send-email-pratyush.anand@st.com>
On Thu, 3 Feb 2011 19:39:09 +0530
Pratyush Anand <pratyush.anand@st.com> wrote:
> This is a configurable gadget. can be configured by configfs interface. Any
> IP available at PCIE bus can be programmed to be used by host
> controller.It supoorts both INTX and MSI.
> By default, gadget is configured for INTX and SYSRAM1 is mapped to BAR0
> with size 0x1000
>
>
> ...
>
> --- /dev/null
> +++ b/Documentation/ABI/testing/configfs-spear-pcie-gadget
> @@ -0,0 +1,30 @@
> +What: /config/pcie-gadget
> +Date: Feb 2011
> +KernelVersion: 2.6.37
> +Contact: Pratyush Anand <pratyush.anand@st.com>
> +Description:
> +
> + Interface is used to configure selected dual mode pcie controller
> + as device and then program its various registers to configure it
> + as a particular device type.
> + This interfaces can be used to show spear's pcie device capability.
> +
> + Nodes are only visible when configfs is mounted. To mount configfs
> + in /config directory use:
> + # mount -t configfs none /config/
> +
> + /config/pcie-gadget/
> + link ... used to enable ltssm and read its status.
> + int_type ...used to configure and read type of supported
> + interrupt
> + no_of_msi ... used to configure number of MSI vector needed and
> + to read no of MSI granted.
> + inta ... write 1 to assert INTA and 0 to de-assert.
> + send_msi ... write MSI vector to be sent.
> + vendor_id ... used to write and read vendor id (hex)
> + device_id ... used to write and read device id (hex)
> + bar0_size ... used to write and read bar0_size
> + bar0_address ... used to write and read bar0 mapped area in hex.
> + bar0_rw_offset ... used to write and read offset of bar0 where
> + bar0_data will be written or read.
> + bar0_data ... used to write and read data at bar0_rw_offset.
This interface implies that there will only ever be one device in the
machine, yes? Seems a bit short-sighted?
>
> ...
>
> +Node programming example
> +===========================
> +Program all PCIE registers in such a way that when this device is connected
> +to the pcie host, then host sees this device as 1MB RAM.
> +#mount -t configfs none /Config
> +# cd /config/pcie_gadget/
> +Now you have all the nodes in this directory.
> +program vendor id as 0x104a
> +# echo 104A >> vendor_id
> +
> +program device id as 0xCD80
> +# echo CD80 >> device_id
> +
> +program BAR0 size as 1MB
> +# echo 100000 >> bar0_size
I'd be more comfortable if all the hex inputs and outputs had a leading
0x.
>
> ...
>
> +static void spear_dbi_read_reg(struct spear_pcie_gadget_config *config,
> + int where, int size, u32 *val)
> +{
> + struct pcie_app_reg __iomem *app_reg
> + = (struct pcie_app_reg __iomem *) config->va_app_base;
> + u32 va_address;
> +
> + /* Enable DBI access */
> + enable_dbi_access(app_reg);
> +
> + va_address = (u32)config->va_dbi_base + (where & ~0x3);
This will be buggy on 64-bit machines.
> + *val = readl(va_address);
I guess the code won't be running on 64-bit machines ;)
Still, it would be good to minimise the obvious portability problems.
> + if (size == 1)
> + *val = (*val >> (8 * (where & 3))) & 0xff;
> + else if (size == 2)
> + *val = (*val >> (8 * (where & 3))) & 0xffff;
> +
> + /* Disable DBI access */
> + disable_dbi_access(app_reg);
> +}
> +
> +static void spear_dbi_write_reg(struct spear_pcie_gadget_config *config,
> + int where, int size, u32 val)
> +{
> + struct pcie_app_reg __iomem *app_reg
> + = (struct pcie_app_reg __iomem *) config->va_app_base;
Is the typecast needed? We shouldn't *need* to cast a void **iomem *
in this manner. If we do need the cast then something is broken.
> + u32 va_address;
> +
> + /* Enable DBI access */
> + enable_dbi_access(app_reg);
> +
> + va_address = (u32)config->va_dbi_base + (where & ~0x3);
> +
> + if (size == 4)
> + writel(val, va_address);
> + else if (size == 2)
> + writew(val, va_address + (where & 2));
> + else if (size == 1)
> + writeb(val, va_address + (where & 3));
> +
> + /* Disable DBI access */
> + disable_dbi_access(app_reg);
> +}
> +
>
> ...
>
> +static ssize_t pcie_gadget_store_link(
> + struct spear_pcie_gadget_config *config,
> + const char *buf, size_t count)
> +{
> + struct pcie_app_reg __iomem *app_reg =
> + (struct pcie_app_reg __iomem *) config->va_app_base;
> + char link[10];
> +
> + if (strlen(buf) >= 10)
> + return -EINVAL;
> +
> + if (sscanf(buf, "%s", link) != 1)
> + return -EINVAL;
> +
> + if (!strcmp(link, "UP"))
> + writel(readl(&app_reg->app_ctrl_0) | (1 << APP_LTSSM_ENABLE_ID),
> + &app_reg->app_ctrl_0);
> + else
> + writel(readl(&app_reg->app_ctrl_0)
> + & ~(1 << APP_LTSSM_ENABLE_ID),
> + &app_reg->app_ctrl_0);
> + return count;
> +}
This function looks unnecessarily complex. Why not do something like
if (sysfs_streq(buf, "UP"))
...
else if (sysfs_streq(buf, "UP"))
...
else
fail;
And note that the code at present is sloppily treating all input other
than "UP" as "DOWN". Don't do that.
> +static ssize_t pcie_gadget_show_int_type(
> + struct spear_pcie_gadget_config *config,
> + char *buf)
> +{
> + return sprintf(buf, "%s", config->int_type);
> +}
> +
> +static ssize_t pcie_gadget_store_int_type(
> + struct spear_pcie_gadget_config *config,
> + const char *buf, size_t count)
> +{
> + char int_type[10];
> + u32 cap, vec, flags;
> + unsigned long vector;
> +
> + if (strlen(buf) >= 10)
> + return -EINVAL;
> +
> + if (sscanf(buf, "%s", int_type) != 1)
> + return -EINVAL;
Similarly, the local copy of the string isn't needed.
> + if (!strcmp(int_type, "INTA"))
> + spear_dbi_write_reg(config, PCI_INTERRUPT_LINE, 1, 1);
> +
> + else if (!strcmp(int_type, "MSI")) {
> + vector = config->requested_msi;
> + vec = 0;
> + while (vector > 1) {
> + vector /= 2;
> + vec++;
> + }
> + spear_dbi_write_reg(config, PCI_INTERRUPT_LINE, 1, 0);
> + cap = pci_find_own_capability(config, PCI_CAP_ID_MSI);
> + spear_dbi_read_reg(config, cap + PCI_MSI_FLAGS, 1, &flags);
> + flags &= ~PCI_MSI_FLAGS_QMASK;
> + flags |= vec << 1;
> + spear_dbi_write_reg(config, cap + PCI_MSI_FLAGS, 1, flags);
> + } else
> + return -EINVAL;
> +
> + strcpy(config->int_type, int_type);
> +
> + return count;
> +}
> +
> +static ssize_t pcie_gadget_show_no_of_msi(
> + struct spear_pcie_gadget_config *config,
> + char *buf)
> +{
> + struct pcie_app_reg __iomem *app_reg =
> + (struct pcie_app_reg __iomem *)config->va_app_base;
> + u32 cap, vector, vec, flags;
> +
> + if ((readl(&app_reg->msg_status) & (1 << CFG_MSI_EN_ID))
> + != (1 << CFG_MSI_EN_ID))
> + vector = 0;
> + else {
> + cap = pci_find_own_capability(config, PCI_CAP_ID_MSI);
> + spear_dbi_read_reg(config, cap + PCI_MSI_FLAGS, 1, &flags);
> + flags &= ~PCI_MSI_FLAGS_QSIZE;
> + vec = flags >> 4;
> + vector = 1;
> + while (vec--)
> + vector *= 2;
> + }
> + config->configured_msi = vector;
Wait. A "show" function is modifying kernel state?!?!?
> +
> + return sprintf(buf, "%u", vector);
> +}
> +
>
> ...
>
> +static ssize_t pcie_gadget_store_send_msi(
> + struct spear_pcie_gadget_config *config,
> + const char *buf, size_t count)
> +{
> + struct pcie_app_reg __iomem *app_reg =
> + (struct pcie_app_reg __iomem *)config->va_app_base;
> + unsigned long vector;
> + u32 ven_msi;
> +
> + if (strict_strtoul(buf, 0, &vector))
> + return -EINVAL;
> +
> + if (!config->configured_msi)
> + return -EINVAL;
This is racy, isn't it? Some other thread could be concurrently
modifying ->configured_msi? (It's a minor issue IMO).
> + if (vector >= config->configured_msi)
> + return -EINVAL;
> +
> + ven_msi = readl(&app_reg->ven_msi_1);
> + ven_msi &= ~VEN_MSI_FUN_NUM_MASK;
> + ven_msi |= 0 << VEN_MSI_FUN_NUM_ID;
> + ven_msi &= ~VEN_MSI_TC_MASK;
> + ven_msi |= 0 << VEN_MSI_TC_ID;
> + ven_msi &= ~VEN_MSI_VECTOR_MASK;
> + ven_msi |= vector << VEN_MSI_VECTOR_ID;
> +
> + /*generating interrupt for msi vector*/
> + ven_msi |= VEN_MSI_REQ_EN;
> + writel(ven_msi, &app_reg->ven_msi_1);
> + /*need to wait till this bit is cleared, it is not cleared
> + * autometically[Bug RTL] TBD*/
> + udelay(1);
> + ven_msi &= ~VEN_MSI_REQ_EN;
> + writel(ven_msi, &app_reg->ven_msi_1);
> +
> + return count;
> +}
> +
>
> ...
>
> +static ssize_t pcie_gadget_store_bar0_address(
> + struct spear_pcie_gadget_config *config,
> + const char *buf, size_t count)
> +{
> + struct pcie_app_reg __iomem *app_reg =
> + (struct pcie_app_reg __iomem *)config->va_app_base;
> + unsigned long address;
> +
> + if (strict_strtoul(buf, 0, &address))
> + return -EINVAL;
> +
> + address &= ~(config->bar0_size - 1);
> + if (config->va_bar0_address)
> + iounmap((void *)config->va_bar0_address);
`void __iomem *' would be a more accurate cast and might avoid sparse
warnings.
Even better would be to avoid the cast all together. Does
va_bar0_address have the correct type?
> + config->va_bar0_address = (u32)ioremap(address, config->bar0_size);
> + if (!config->va_bar0_address)
> + return -ENOMEM;
> +
> + writel(address, &app_reg->pim0_mem_addr_start);
> +
> + return count;
> +}
> +
>
> ...
>
^ permalink raw reply
* [RFC PATCH] ARM: pmu: add OF match support
From: Rob Herring @ 2011-02-09 23:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <AANLkTikrBx1Y7MFGCJe=Gx-9fUxhwuYq-BZ4stGBGav6@mail.gmail.com>
On 02/09/2011 01:03 PM, Grant Likely wrote:
> On Wed, Feb 9, 2011 at 11:53 AM, Will Deacon<will.deacon@arm.com> wrote:
>> Grant,
>>
>>>> Following on from Rob's update, it would be nice if you could specify that
>>>> the PMU is a CPU PMU (as opposed to L2-cache, bus, gpu etc) in the string.
>>>> That way adding different PMUs in the future seems more natural and it accounts
>>>> for your concerns above. Is that ok, or does the compatible string have to
>>>> match that used by the platform bus?
>>>
>>> It does make sense to encode the specific implementation into the
>>> compatible string. A single device driver can bind against multiple
>>> compatible strings. ie. the match table could include {.compatible =
>>> "arm,cortex-a9-pmu"},{.compatible = "arm,cortex-a9-l2cache-pmu"}...
>>
>> Ok - that's great! Specifying the CPU is probably a little verbose, but
>> something like "arm,armv7pmu" would be really helpful when it comes to
>> multiple devices.
>>
>>>> As for versioning, the PMU detection is done dynamically at runtime,
>>>> so knowing that we're poking a CPU is enough.
>>>
>>> Fair enough. It is still good practice in the compatible list to
>>> encode the specific PMU implementation (maybe arm,cortex-a9-pmu?)
>>> instead of trying to define a 'generic' or wildcard compatible value.
>>> Newer implementations can always claim compatibility with an older
>>> implementation so that the kernel doesn't have to be modified to find
>>> the new devices. "arm,pmu" is probably too generic.
>>
>> "arm,pmu" is definitely too generic. If it's good practice to specify
>> as much as possible, then go for it - I just feel a little uneasy having
>> to add lots of redundant kernel code but it sounds like you'll hopefully
>> prove me wrong on that :)
>
> Shouldn't be any redundant kernel code. It's just a list of match
> values, and the driver code already knows how to handle it. The
> advantage of being specific is that if the driver ever does need
> information about the specific implementation (say, because the
> hardware reported value is buggy), then the data is available.
By that argument, we should use "<vendor>,cortex-a9-rXpX-pmu." As a
particular rev of the A9 PMU or vendor's SOC could be buggy. That would
quickly grow into a long list. Just with cpu models, we would have:
cortex-a9
cortex-a8
cortex-a15
cortex-a5
arm1136
arm1176
l210
l220
pl310
various xscale flavors
Qualcomm SMP
Keep in mind that the whole point of this platform device is just to
specify the interrupt connection which is the only part that varies by
SOC (and is not probe-able).
Rob
^ permalink raw reply
* [PATCH] ARM: mm: don't free memmap entries in the middle of a MAX_ORDER_NR_PAGES block
From: Dima Zavin @ 2011-02-09 22:36 UTC (permalink / raw)
To: linux-arm-kernel
On some machines, nodes do not always start on MAX_ORDER_NR_PAGES
boundaries. The rest of the VM assumes that pages within a
MAX_ORDER_NR_PAGES range always have valid memmap entries. So,
we round down the bank_start in free_unused_memmap to ensure that
there are valid page structs for all pages within a MAX_ORDER_NR_PAGES
block of pages.
Signed-off-by: Dima Zavin <dima@android.com>
---
arch/arm/mm/init.c | 3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index cddd684..1290fbe 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -424,7 +424,8 @@ static void __init free_unused_memmap(struct meminfo *mi)
for_each_bank(i, mi) {
struct membank *bank = &mi->bank[i];
- bank_start = bank_pfn_start(bank);
+ bank_start = round_down(bank_pfn_start(bank),
+ MAX_ORDER_NR_PAGES);
/*
* If we had a previous bank, and there is a space
--
1.7.3.1
^ permalink raw reply related
* [PATCH 0/6] Switch pxa25x_udc devices to use gpio-vbus tranceiver
From: Dmitry Eremin-Solenikov @ 2011-02-09 22:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1296666003-31647-1-git-send-email-dbaryshkov@gmail.com>
Hello,
On 2/2/11, Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> wrote:
> pxa25x_udc driver contains functionality duplicating gpio-vbus tranceiver
> functions. Switch all devices, that depend on it, to use gpio-vbus
> and (in the last patches) drop related code from pxa25x_udc.
Any comments on this patchset?
--
With best wishes
Dmitry
^ permalink raw reply
* [PATCH] msm: Remove arch-specific gpiomux tables
From: Rohit Vaswani @ 2011-02-09 21:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <AANLkTimOAOirgH7haDJjf265zdbvoei=f=GGxQEh+5dh@mail.gmail.com>
Hi Dima,
Thanks for your feedback. What you mention is absolutely right, and
accommodating that requires an architectural change which we have ready
and I will be pushing that out anytime.
This patch addresses your comments for removing the separate gpiomux
config file. My next patch series should provide you a complete picture.
Thanks,
Rohit
On 2/9/2011 12:59 PM, Dima Zavin wrote:
> I don't like this solution of putting the magicly named array into the
> board file. What if I want multiple boards to be built into the same
> kernel? What if I want multiple tables in case I have different
> revisions of the board?
>
> The more correct way would be to add a function to gpiomux.c to be
> able to apply a list of gpiomux configs, something like:
>
> int msm_gpiomux_config_table(struct msm_gpiomux_cfg *table, int num);
>
> --Dima
>
> On Fri, Feb 4, 2011 at 5:44 PM, Rohit Vaswani<rvaswani@codeaurora.org> wrote:
>> The gpiomux configs are board-specific and thus should be
>> a part of the board file.
>>
>> Signed-off-by: Rohit Vaswani<rvaswani@codeaurora.org>
>> ---
>> arch/arm/mach-msm/Makefile | 4 +-
>> arch/arm/mach-msm/board-msm8x60.c | 3 ++
>> arch/arm/mach-msm/board-qsd8x50.c | 12 ++++++++
>> arch/arm/mach-msm/gpiomux-8x50.c | 51
>> -------------------------------------
>> arch/arm/mach-msm/gpiomux-8x60.c | 19 -------------
>> 5 files changed, 17 insertions(+), 72 deletions(-)
>> delete mode 100644 arch/arm/mach-msm/gpiomux-8x50.c
>> delete mode 100644 arch/arm/mach-msm/gpiomux-8x60.c
>>
>> diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
>> index ea8c74f..b6c6ec8 100644
>> --- a/arch/arm/mach-msm/Makefile
>> +++ b/arch/arm/mach-msm/Makefile
>> @@ -30,8 +30,8 @@ obj-$(CONFIG_ARCH_MSM8X60) += board-msm8x60.o
>> obj-$(CONFIG_ARCH_MSM8960) += board-msm8960.o devices-msm8960.o
>>
>> obj-$(CONFIG_ARCH_MSM7X30) += gpiomux-v1.o gpiomux.o
>> -obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o gpiomux-v1.o gpiomux.o
>> -obj-$(CONFIG_ARCH_MSM8X60) += gpiomux-8x60.o gpiomux-v2.o gpiomux.o
>> +obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-v1.o gpiomux.o
>> +obj-$(CONFIG_ARCH_MSM8X60) += gpiomux-v2.o gpiomux.o
>> ifdef CONFIG_MSM_V2_TLMM
>> ifndef CONFIG_ARCH_MSM8960
>> # TODO: TLMM Mapping issues need to be resolved
>> diff --git a/arch/arm/mach-msm/board-msm8x60.c
>> b/arch/arm/mach-msm/board-msm8x60.c
>> index b3c55f1..6c0b868 100644
>> --- a/arch/arm/mach-msm/board-msm8x60.c
>> +++ b/arch/arm/mach-msm/board-msm8x60.c
>> @@ -27,6 +27,9 @@
>>
>> #include<mach/board.h>
>> #include<mach/msm_iomap.h>
>> +#include "gpiomux.h"
>> +
>> +struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {};
>>
>>
>> static void __init msm8x60_map_io(void)
>> diff --git a/arch/arm/mach-msm/board-qsd8x50.c
>> b/arch/arm/mach-msm/board-qsd8x50.c
>> index b464d48..b63b7c4 100644
>> --- a/arch/arm/mach-msm/board-qsd8x50.c
>> +++ b/arch/arm/mach-msm/board-qsd8x50.c
>> @@ -36,9 +36,21 @@
>> #include<mach/mmc.h>
>>
>> #include "devices.h"
>> +#include "gpiomux.h"
>>
>> extern struct sys_timer msm_timer;
>>
>> +struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {
>> + [86] = { /* UART3 RX */
>> + .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
>> + GPIOMUX_FUNC_1 | GPIOMUX_VALID,
>> + },
>> + [87] = { /* UART3 TX */
>> + .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
>> + GPIOMUX_FUNC_1 | GPIOMUX_VALID,
>> + },
>> +};
>> +
>> static const resource_size_t qsd8x50_surf_smc91x_base __initdata =
>> 0x70000300;
>> static const unsigned qsd8x50_surf_smc91x_gpio __initdata = 156;
>>
>> diff --git a/arch/arm/mach-msm/gpiomux-8x50.c
>> b/arch/arm/mach-msm/gpiomux-8x50.c
>> deleted file mode 100644
>> index f7a4ea5..0000000
>> --- a/arch/arm/mach-msm/gpiomux-8x50.c
>> +++ /dev/null
>> @@ -1,51 +0,0 @@
>> -/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
>> - *
>> - * This program is free software; you can redistribute it and/or modify
>> - * it under the terms of the GNU General Public License version 2 and
>> - * only version 2 as published by the Free Software Foundation.
>> - *
>> - * This program is distributed in the hope that it will be useful,
>> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> - * GNU General Public License for more details.
>> - *
>> - * You should have received a copy of the GNU General Public License
>> - * along with this program; if not, write to the Free Software
>> - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
>> - * 02110-1301, USA.
>> - */
>> -#include "gpiomux.h"
>> -
>> -#if defined(CONFIG_MMC_MSM) || defined(CONFIG_MMC_MSM_MODULE)
>> - #define SDCC_DAT_0_3_CMD_ACTV_CFG (GPIOMUX_VALID | GPIOMUX_PULL_UP\
>> - | GPIOMUX_FUNC_1 | GPIOMUX_DRV_8MA)
>> - #define SDCC_CLK_ACTV_CFG (GPIOMUX_VALID | GPIOMUX_PULL_NONE\
>> - | GPIOMUX_FUNC_1 | GPIOMUX_DRV_8MA)
>> -#else
>> - #define SDCC_DAT_0_3_CMD_ACTV_CFG 0
>> - #define SDCC_CLK_ACTV_CFG 0
>> -#endif
>> -
>> -#define SDC1_SUSPEND_CONFIG (GPIOMUX_VALID | GPIOMUX_PULL_DOWN\
>> - | GPIOMUX_FUNC_GPIO | GPIOMUX_DRV_2MA)
>> -
>> -struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {
>> - [86] = { /* UART3 RX */
>> - .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
>> - GPIOMUX_FUNC_1 | GPIOMUX_VALID,
>> - },
>> - [87] = { /* UART3 TX */
>> - .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
>> - GPIOMUX_FUNC_1 | GPIOMUX_VALID,
>> - },
>> - /* SDC1 data[3:0]& CMD */
>> - [51 ... 55] = {
>> - .active = SDCC_DAT_0_3_CMD_ACTV_CFG,
>> - .suspended = SDC1_SUSPEND_CONFIG
>> - },
>> - /* SDC1 CLK */
>> - [56] = {
>> - .active = SDCC_CLK_ACTV_CFG,
>> - .suspended = SDC1_SUSPEND_CONFIG
>> - },
>> -};
>> diff --git a/arch/arm/mach-msm/gpiomux-8x60.c
>> b/arch/arm/mach-msm/gpiomux-8x60.c
>> deleted file mode 100644
>> index 7b380b3..0000000
>> --- a/arch/arm/mach-msm/gpiomux-8x60.c
>> +++ /dev/null
>> @@ -1,19 +0,0 @@
>> -/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
>> - *
>> - * This program is free software; you can redistribute it and/or modify
>> - * it under the terms of the GNU General Public License version 2 and
>> - * only version 2 as published by the Free Software Foundation.
>> - *
>> - * This program is distributed in the hope that it will be useful,
>> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> - * GNU General Public License for more details.
>> - *
>> - * You should have received a copy of the GNU General Public License
>> - * along with this program; if not, write to the Free Software
>> - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
>> - * 02110-1301, USA.
>> - */
>> -#include "gpiomux.h"
>> -
>> -struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {};
>> --
>> 1.7.3.3
>>
>> Thanks,
>> Rohit Vaswani
>>
>> --
>> Sent by an employee of the Qualcomm Innovation Center, Inc.
>> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
>>
>>
Thanks,
Rohit Vaswani
--
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
^ permalink raw reply
* [PATCH] msm: Remove arch-specific gpiomux tables
From: David Brown @ 2011-02-09 21:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <AANLkTimOAOirgH7haDJjf265zdbvoei=f=GGxQEh+5dh@mail.gmail.com>
On Wed, Feb 09 2011, Dima Zavin wrote:
> I don't like this solution of putting the magicly named array into the
> board file. What if I want multiple boards to be built into the same
> kernel? What if I want multiple tables in case I have different
> revisions of the board?
Especially since there is a push by some to be able to build everything
into a single kernel.
> The more correct way would be to add a function to gpiomux.c to be
> able to apply a list of gpiomux configs, something like:
>
> int msm_gpiomux_config_table(struct msm_gpiomux_cfg *table, int num);
Good idea. Although, I think a name like msm_gpiomux_add_configs()
might fit better with other namings.
David
^ permalink raw reply
* [PATCH 1/5] dmaengine: mxs-dma: add dma support for i.MX23/28
From: Shawn Guo @ 2011-02-09 21:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110209083400.GK9041@pengutronix.de>
On Wed, Feb 09, 2011 at 09:34:00AM +0100, Sascha Hauer wrote:
> Shawn,
>
> On Wed, Feb 09, 2011 at 07:28:34AM +0800, Shawn Guo wrote:
> > > > +
> > > > + if (direction == DMA_NONE) {
> > > > + ccw = &mxs_chan->ccw[0];
> > > > + pio = (u32 *) sgl;
> > > > +
> > > > + for (j = 0; j < sg_len;)
> > > > + ccw->pio_words[j++] = *pio++;
> > > > +
> > > > + ccw->next = 0;
> > > > + ccw->bits.chain = 0;
> > > > + ccw->bits.irq = 1;
> > > > + ccw->bits.dec_sem = 1;
> > > > + ccw->bits.wait4end = flags;
> > > > + ccw->bits.halt_on_terminate = 1;
> > > > + ccw->bits.terminate_flush = 1;
> > > > + ccw->bits.pio_num = sg_len;
> > > > + ccw->bits.command = MXS_DMA_NO_XFER;
> > >
> > > Does this have a valid usecase? I would just return some error code
> > > here. pio_num and pio_words are unused in the driver and I don't think
> > > a dmaengine driver should have some kind of PIO fallback.
> > >
> > If you happen to have a look at mxs-mmc patch set, you could find it.
>
> As Russell already pointed out, the (mmc-) driver should handle this.
>
> > > > +
> > > > + /*
> > > > + * dmaengine clients have to use dma_device.dev_id to filter
> > > > + * dma device between apbh and apbx, so need to ensure it is
> > > > + * identical to mxs_dma_engine.dev_id.
> > > > + */
> > > > + if (mxs_dma->dma_device.dev_id != mxs_dma->dev_id) {
> > > > + dev_err(&pdev->dev, "dev_id of dma_device %d differs from mxs_dma_engine %d\n",
> > > > + mxs_dma->dma_device.dev_id, mxs_dma->dev_id);
> > > > + goto err_init;
> > > > + }
> > >
> > > I think it makes more sense to match against device names (apbh vs.
> > > apbx) in the client's filter function than to rely on exact numbering.
> > >
> > I agree, if there is already a member like dev_name in dma_device.
> > There is dev_id but no dev_name. Suggestion on how to use device
> > name for matching?
>
> Have a look at the implementation of imx_dma_is_general_purpose() and
> imx_dma_is_ipu().
>
Great example. Thanks.
Regards
Shawn
^ permalink raw reply
* [PATCH] ARM: mm: enforce pageblock alignment when freeing memmap entries at init
From: Dima Zavin @ 2011-02-09 21:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110203133053.GG11958@csn.ul.ie>
Mel,
> Sorry for the long delay. I'm in the process of changing jobs at the
> moment and my schedule is heavily disrupted. It's likely to be a mess
> for at least a month.
I totally understand. Good luck with the new job :)
> No, the description and patch comment is just misleading. Clarify that
> you are catching the situation where a node boundary is in the middle of a
> MAX_ORDER_NR_PAGES block of pages and you are preventing memmap belonging
> to another node being freed and it's fine.
Will resend with new description.
Thanks
--Dima
^ permalink raw reply
* Machine ID question
From: John Linn @ 2011-02-09 21:23 UTC (permalink / raw)
To: linux-arm-kernel
I used the form to create a new machine ID for the new Xilinx platform
in anticipation of
the code making it into the mainline sometime in the future.
The proposed patches are using ARCH_XILINX in the Kconfig.
Below is the line that it created when I clicked on this link:
http://www.arm.linux.org.uk/developer/machines/download.php
xilinx MACH_XILINX XILINX
3343
Did I hose it up as the form wasn't completely clear to me (if I needed
to enter ARCH_XILINX)?
Thanks,
John
This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately.
^ permalink raw reply
* [PATCH v2] tty: Add msm_smd_tty driver
From: Alan Cox @ 2011-02-09 21:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297278994-22155-1-git-send-email-nvishwan@codeaurora.org>
On Wed, 9 Feb 2011 11:16:34 -0800
Niranjana Vishwanathapura <nvishwan@codeaurora.org> wrote:
> msm_smd_tty driver provides tty device interface
> to 'DS' and 'GPSNMEA' streaming SMD ports.
>
> Cc: Brian Swetland <swetland@google.com>
> Signed-off-by: Niranjana Vishwanathapura <nvishwan@codeaurora.org>
Acked-by: Alan Cox <alan@linux.intel.com>
Thanks for reworking it for the current refcount/port stuff
Alan
^ permalink raw reply
* [PATCH 1/5] dmaengine: mxs-dma: add dma support for i.MX23/28
From: Shawn Guo @ 2011-02-09 21:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110209090915.GL9041@pengutronix.de>
On Wed, Feb 09, 2011 at 10:09:15AM +0100, Sascha Hauer wrote:
> On Tue, Feb 08, 2011 at 03:41:55PM +0100, Lothar Wa?mann wrote:
> > Hi,
> >
> > > On Sat, Feb 05, 2011 at 10:08:12AM +0800, Shawn Guo wrote:
> > >> This patch adds dma support for Freescale MXS-based SoC i.MX23/28,
> > >> including apbh-dma and apbx-dma.
> > >>
> > >> * apbh-dma and apbx-dma are supported in the driver as two instances,
> > >> and have to be filtered by dma clients via device id. It becomes
> > >> the convention that apbh-dma always gets registered prior to
> > >> apbx-dma.
> > >>
> > >> * apbh-dma is different between mx23 and mx28, hardware version
> > >> register is used to handle the differences.
> > >>
> > >> * Every the mxs dma channel is statically assigned to client device
> > >> by soc design with fixed irq. The irq number is being passed by
> > >> alloc_chan function with mxs_dma_data, and client driver has to
> > >> filter the correct channel by its channel id.
> > >>
> > >> * mxs-dma supports pio function besides data transfer. The driver
> > >> uses dma_data_direction DMA_NONE to identify the pio mode, and
> > >> steals sgl and sg_len to get pio words and numbers from clients.
> > >>
> > >> * mxs dmaengine has some very specific features, like sense function
> > >> and the special NAND support (nand_lock, nand_wait4ready). These
> > >> are too specific to implemented in generic dmaengine driver.
> > >>
> > >> * The parameter "flags" of prep functions is currently being used to
> > >> pass wait4end flag from clients.
> > >>
> > >> * The driver refers to imx-sdma and only a single descriptor is
> > >> statically assigned to each channel.
> > >>
> > >> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
> > >> ---
> > >> arch/arm/mach-mxs/include/mach/dma.h | 16 +
> > >> drivers/dma/Kconfig | 8 +
> > >> drivers/dma/Makefile | 1 +
> > >> drivers/dma/mxs-dma.c | 702 ++++++++++++++++++++++++++++++++++
> > >> 4 files changed, 727 insertions(+), 0 deletions(-)
> > >> create mode 100644 arch/arm/mach-mxs/include/mach/dma.h
> > >> create mode 100644 drivers/dma/mxs-dma.c
> > >>
> > >> diff --git a/arch/arm/mach-mxs/include/mach/dma.h b/arch/arm/mach-mxs/include/mach/dma.h
> > >> new file mode 100644
> > >> index 0000000..429f431
> > >> --- /dev/null
> > >> +++ b/arch/arm/mach-mxs/include/mach/dma.h
> > >> +
> > >> +static struct dma_async_tx_descriptor *mxs_dma_prep_slave_sg(
> > >> + struct dma_chan *chan, struct scatterlist *sgl,
> > >> + unsigned int sg_len, enum dma_data_direction direction,
> > >> + unsigned long flags)
> > >> +{
> > >> + struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
> > >> + struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
> > >> + struct mxs_dma_ccw *ccw;
> > >> + struct scatterlist *sg;
> > >> + int ret, i, j;
> > >> + u32 *pio;
> > >> +
> > >> + dev_dbg(mxs_dma->dev, "%s: channel %d\n", __func__, chan->chan_id);
> > >> +
> > >> + if (mxs_chan->status == DMA_IN_PROGRESS)
> > >> + return NULL;
> > >> +
> > >> + mxs_chan->status = DMA_IN_PROGRESS;
> > >> + mxs_chan->flags = 0;
> > >> +
> > >> + dev_dbg(mxs_dma->dev, "%s: setting up %d entries\n", __func__, sg_len);
> > >> +
> > >> + if (sg_len > ((direction == DMA_NONE) ? MXS_PIO_WORDS : NUM_CCW)) {
> > >> + dev_err(mxs_dma->dev, "maximum number of sg exceeded: %d > %d\n",
> > >> + sg_len, NUM_CCW);
> > >> + ret = -EINVAL;
> > >> + goto err_out;
> > >> + }
> > >> +
> > >> + if (direction == DMA_NONE) {
> > >> + ccw = &mxs_chan->ccw[0];
> > >> + pio = (u32 *) sgl;
> > >> +
> > >> + for (j = 0; j < sg_len;)
> > >> + ccw->pio_words[j++] = *pio++;
> > >> +
> > >> + ccw->next = 0;
> > >> + ccw->bits.chain = 0;
> > >> + ccw->bits.irq = 1;
> > >> + ccw->bits.dec_sem = 1;
> > >> + ccw->bits.wait4end = flags;
> > >> + ccw->bits.halt_on_terminate = 1;
> > >> + ccw->bits.terminate_flush = 1;
> > >> + ccw->bits.pio_num = sg_len;
> > >> + ccw->bits.command = MXS_DMA_NO_XFER;
> > >
> > > Does this have a valid usecase? I would just return some error code
> > > here. pio_num and pio_words are unused in the driver and I don't think
> > > a dmaengine driver should have some kind of PIO fallback.
> > >
> > Actually 'PIO' is a misnomer here. It's the free scaled way of
> > implementing a simple feature (chained DMA with mixed transfer modes)
> > in a complicated and obfuscated way.
> >
> > What's behinde the 'PIO' transfers is programming controller registers
> > via DMA along with the actual DMA data transfer. DMA_NONE simply
> > means, that the DMA transfer does only the register programming but
> > does not transfer any payload. The 'pio_words' are the values that are
> > being written to consecutive locations of e.g. the SPI controller
> > register address space.
> > The programming is actually done by DMA, in any case.
>
> OK, got it now.
>
> The NAND programming example in the reference manual looks...
> interesting. So it's possible to program the DMA engine in a way that it
> autonomously sends commands to the NAND controller, reads blocks from
> NAND, polls for status, make branches depending on status bits...
This is what sense command does. I scanned the dma client drivers
implemented in Freescale BSP and found only NAND driver uses it.
All others use pio and data transfer.
> This looks more like a DMA programming language.
>
> I think it does not make much sense to try to implement these features
> in the dmaengine API. What the dmaengine offers is only a special
> usecase of what the controller provides. Also these features are so
> hardware specific that it won't make sense to extend the dmaengine API
> for them.
>
> So what should we do? Not use these features at all? Create a bypass to
> the dmaengine API? Make the dmaengine driver a user of another, i.MX28
> specific driver which provides the additional features?
>
My preference is not use these NAND specific features at all. And
I think NAND driver can also be implemented with pio and data
commands only.
Regards,
Shawn
^ permalink raw reply
* [PATCH] msm: Remove arch-specific gpiomux tables
From: Dima Zavin @ 2011-02-09 20:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4D4CAB63.4050301@codeaurora.org>
I don't like this solution of putting the magicly named array into the
board file. What if I want multiple boards to be built into the same
kernel? What if I want multiple tables in case I have different
revisions of the board?
The more correct way would be to add a function to gpiomux.c to be
able to apply a list of gpiomux configs, something like:
int msm_gpiomux_config_table(struct msm_gpiomux_cfg *table, int num);
--Dima
On Fri, Feb 4, 2011 at 5:44 PM, Rohit Vaswani <rvaswani@codeaurora.org> wrote:
> The gpiomux configs are board-specific and thus should be
> a part of the board file.
>
> Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
> ---
> ?arch/arm/mach-msm/Makefile ? ? ? ?| ? ?4 +-
> ?arch/arm/mach-msm/board-msm8x60.c | ? ?3 ++
> ?arch/arm/mach-msm/board-qsd8x50.c | ? 12 ++++++++
> ?arch/arm/mach-msm/gpiomux-8x50.c ?| ? 51
> -------------------------------------
> ?arch/arm/mach-msm/gpiomux-8x60.c ?| ? 19 -------------
> ?5 files changed, 17 insertions(+), 72 deletions(-)
> ?delete mode 100644 arch/arm/mach-msm/gpiomux-8x50.c
> ?delete mode 100644 arch/arm/mach-msm/gpiomux-8x60.c
>
> diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
> index ea8c74f..b6c6ec8 100644
> --- a/arch/arm/mach-msm/Makefile
> +++ b/arch/arm/mach-msm/Makefile
> @@ -30,8 +30,8 @@ obj-$(CONFIG_ARCH_MSM8X60) += board-msm8x60.o
> ?obj-$(CONFIG_ARCH_MSM8960) += board-msm8960.o devices-msm8960.o
>
> ?obj-$(CONFIG_ARCH_MSM7X30) += gpiomux-v1.o gpiomux.o
> -obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o gpiomux-v1.o gpiomux.o
> -obj-$(CONFIG_ARCH_MSM8X60) += gpiomux-8x60.o gpiomux-v2.o gpiomux.o
> +obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-v1.o gpiomux.o
> +obj-$(CONFIG_ARCH_MSM8X60) += gpiomux-v2.o gpiomux.o
> ?ifdef CONFIG_MSM_V2_TLMM
> ?ifndef CONFIG_ARCH_MSM8960
> ?# TODO: TLMM Mapping issues need to be resolved
> diff --git a/arch/arm/mach-msm/board-msm8x60.c
> b/arch/arm/mach-msm/board-msm8x60.c
> index b3c55f1..6c0b868 100644
> --- a/arch/arm/mach-msm/board-msm8x60.c
> +++ b/arch/arm/mach-msm/board-msm8x60.c
> @@ -27,6 +27,9 @@
>
> ?#include <mach/board.h>
> ?#include <mach/msm_iomap.h>
> +#include "gpiomux.h"
> +
> +struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {};
>
>
> ?static void __init msm8x60_map_io(void)
> diff --git a/arch/arm/mach-msm/board-qsd8x50.c
> b/arch/arm/mach-msm/board-qsd8x50.c
> index b464d48..b63b7c4 100644
> --- a/arch/arm/mach-msm/board-qsd8x50.c
> +++ b/arch/arm/mach-msm/board-qsd8x50.c
> @@ -36,9 +36,21 @@
> ?#include <mach/mmc.h>
>
> ?#include "devices.h"
> +#include "gpiomux.h"
>
> ?extern struct sys_timer msm_timer;
>
> +struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {
> + ? ?[86] = { /* UART3 RX */
> + ? ? ? ?.suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
> + ? ? ? ? ? ? ? ? GPIOMUX_FUNC_1 | GPIOMUX_VALID,
> + ? ?},
> + ? ?[87] = { /* UART3 TX */
> + ? ? ? ?.suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
> + ? ? ? ? ? ? ? ? GPIOMUX_FUNC_1 | GPIOMUX_VALID,
> + ? ?},
> +};
> +
> ?static const resource_size_t qsd8x50_surf_smc91x_base __initdata =
> 0x70000300;
> ?static const unsigned ? ? ? ?qsd8x50_surf_smc91x_gpio __initdata = 156;
>
> diff --git a/arch/arm/mach-msm/gpiomux-8x50.c
> b/arch/arm/mach-msm/gpiomux-8x50.c
> deleted file mode 100644
> index f7a4ea5..0000000
> --- a/arch/arm/mach-msm/gpiomux-8x50.c
> +++ /dev/null
> @@ -1,51 +0,0 @@
> -/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License version 2 and
> - * only version 2 as published by the Free Software Foundation.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
> - * GNU General Public License for more details.
> - *
> - * You should have received a copy of the GNU General Public License
> - * along with this program; if not, write to the Free Software
> - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
> - * 02110-1301, USA.
> - */
> -#include "gpiomux.h"
> -
> -#if defined(CONFIG_MMC_MSM) || defined(CONFIG_MMC_MSM_MODULE)
> - ? ?#define SDCC_DAT_0_3_CMD_ACTV_CFG (GPIOMUX_VALID | GPIOMUX_PULL_UP\
> - ? ? ? ? ? ? ? ? ? ?| GPIOMUX_FUNC_1 | GPIOMUX_DRV_8MA)
> - ? ?#define SDCC_CLK_ACTV_CFG (GPIOMUX_VALID | GPIOMUX_PULL_NONE\
> - ? ? ? ? ? ? ? ? ? ?| GPIOMUX_FUNC_1 | GPIOMUX_DRV_8MA)
> -#else
> - ? ?#define SDCC_DAT_0_3_CMD_ACTV_CFG 0
> - ? ?#define SDCC_CLK_ACTV_CFG 0
> -#endif
> -
> -#define SDC1_SUSPEND_CONFIG (GPIOMUX_VALID | GPIOMUX_PULL_DOWN\
> - ? ? ? ? ? ? ? ?| GPIOMUX_FUNC_GPIO | GPIOMUX_DRV_2MA)
> -
> -struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {
> - ? ?[86] = { /* UART3 RX */
> - ? ? ? ?.suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
> - ? ? ? ? ? ? ? ? GPIOMUX_FUNC_1 | GPIOMUX_VALID,
> - ? ?},
> - ? ?[87] = { /* UART3 TX */
> - ? ? ? ?.suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
> - ? ? ? ? ? ? ? ? GPIOMUX_FUNC_1 | GPIOMUX_VALID,
> - ? ?},
> - ? ?/* SDC1 data[3:0] & CMD */
> - ? ?[51 ... 55] = {
> - ? ? ? ?.active = SDCC_DAT_0_3_CMD_ACTV_CFG,
> - ? ? ? ?.suspended = SDC1_SUSPEND_CONFIG
> - ? ?},
> - ? ?/* SDC1 CLK */
> - ? ?[56] = {
> - ? ? ? ?.active = SDCC_CLK_ACTV_CFG,
> - ? ? ? ?.suspended = SDC1_SUSPEND_CONFIG
> - ? ?},
> -};
> diff --git a/arch/arm/mach-msm/gpiomux-8x60.c
> b/arch/arm/mach-msm/gpiomux-8x60.c
> deleted file mode 100644
> index 7b380b3..0000000
> --- a/arch/arm/mach-msm/gpiomux-8x60.c
> +++ /dev/null
> @@ -1,19 +0,0 @@
> -/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License version 2 and
> - * only version 2 as published by the Free Software Foundation.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
> - * GNU General Public License for more details.
> - *
> - * You should have received a copy of the GNU General Public License
> - * along with this program; if not, write to the Free Software
> - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
> - * 02110-1301, USA.
> - */
> -#include "gpiomux.h"
> -
> -struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {};
> --
> 1.7.3.3
>
> Thanks,
> Rohit Vaswani
>
> --
> Sent by an employee of the Qualcomm Innovation Center, Inc.
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
>
>
^ permalink raw reply
* [PATCH 1/5] dmaengine: mxs-dma: add dma support for i.MX23/28
From: Shawn Guo @ 2011-02-09 20:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <19794.19192.351501.395360@ipc1.ka-ro>
On Wed, Feb 09, 2011 at 09:06:16AM +0100, Lothar Wa?mann wrote:
> Hi Shawn,
>
> Shawn Guo writes:
> > On Tue, Feb 08, 2011 at 03:41:55PM +0100, Lothar Wa?mann wrote:
> [...]
> > > What's behinde the 'PIO' transfers is programming controller registers
> > > via DMA along with the actual DMA data transfer. DMA_NONE simply
> > > means, that the DMA transfer does only the register programming but
> > > does not transfer any payload. The 'pio_words' are the values that are
> > > being written to consecutive locations of e.g. the SPI controller
> > > register address space.
> > > The programming is actually done by DMA, in any case.
> > >
> > I'm waiting for this reply ;)
> >
> > i.MX23/28 Reference Manual uses word "PIO" for the working mode that
> > Lothar has explained. It seems that "PIO" in mxs-dma needs some more
> > documents.
> >
> > It's true that mxs dma hardware is designed to program peripheral
> > registers along with data transfer with ccw chain. But it's hard
> > for generic dmaengine model to implement that. The client device
> > driver gets the data in scatter-gather list to transfer. It requires
> > client driver to manipulate the sgl to get pio ccw inserted properly
> > to get the "along with" implemented. This is not a reasonable
> > implementation to me.
> >
> > I still chose to keep the pio mode in the implementation in "single
> > step" rather than "along with" way. That means client driver has to
> > issue one dma request to program client device registers, and issue
> > another one to transfer data. The natural thought is that the pio
> >
> which defeats the purpose of the whole thing. If the software has to
> issue a single request for DMA to program the registers it could as
> well directly write the registers without any DMA. The purpose of the
> embedded 'PIO' transfers is, that you can set up a whole chain of
> commands and associated data transfers and have that executed
> without any further software intervention.
>
> > support can totally be saved with cpu programming. But looking at
> > any mxs dma client device in reference manual, you will find it gets
> > two irq lines, irq_dma and irq_error. For ssp (mmc) example, when
> > one mmc command is issued and completed without error, you have to
> > either polling ssp status register or use pio dma and irq_dma
> > interrupt to know the completion. That's to say I keep the pio
> >
> You could use the SSP IRQ as well.
>
No, I could not. The SSP IRQ (e.g. MX28_INT_SSP0_ERROR) is designed
to indicate an error condition than the completion of mmc command.
Regards,
Shawn
^ permalink raw reply
* [RFC,PATCH 1/3] Add a common struct clk
From: Ryan Mallon @ 2011-02-09 20:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110209203900.GT27982@pengutronix.de>
On 02/10/2011 09:39 AM, Uwe Kleine-K?nig wrote:
> Hi Ryan,
>
> On Thu, Feb 10, 2011 at 09:21:14AM +1300, Ryan Mallon wrote:
>>> +int clk_enable(struct clk *clk)
>>> +{
>>> + unsigned long flags;
>>> + int ret = 0;
>>> +
>>> + spin_lock_irqsave(&clk->enable_lock, flags);
>>
>> WARN_ON(clk->prepare_count == 0); ?
> This is added in patch 3/3
Ah, missed that. I still think that patch 3 should just be rolled into
patch 1. I don't see why we should add a new file in one patch and then
randomly add some warning code to it in another patch. It makes
reviewing harder for one thing :-).
~Ryan
--
Bluewater Systems Ltd - ARM Technology Solution Centre
Ryan Mallon 5 Amuri Park, 404 Barbadoes St
ryan at bluewatersys.com PO Box 13 889, Christchurch 8013
http://www.bluewatersys.com New Zealand
Phone: +64 3 3779127 Freecall: Australia 1800 148 751
Fax: +64 3 3779135 USA 1800 261 2934
^ permalink raw reply
* [PATCH 4/4] wip: fix section mismatches in omap1_defconfig
From: Uwe Kleine-König @ 2011-02-09 20:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110209192727.GC20795@atomide.com>
after these changes omap1_defconfig and omap2plus_defconfig don't have any
section mismatches any more, making it plausible that the patches earlier
in this series are OK.
Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>
---
arch/arm/mach-omap1/board-ams-delta.c | 4 ++--
arch/arm/mach-omap1/board-fsample.c | 2 +-
drivers/usb/otg/isp1301_omap.c | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
index 22cc8c8..560e33f 100644
--- a/arch/arm/mach-omap1/board-ams-delta.c
+++ b/arch/arm/mach-omap1/board-ams-delta.c
@@ -175,7 +175,7 @@ static struct omap_usb_config ams_delta_usb_config __initdata = {
.pins[0] = 2,
};
-static struct omap_board_config_kernel ams_delta_config[] = {
+static struct omap_board_config_kernel ams_delta_config[] __initdata = {
{ OMAP_TAG_LCD, &ams_delta_lcd_config },
};
@@ -259,7 +259,7 @@ static int ams_delta_camera_power(struct device *dev, int power)
#define ams_delta_camera_power NULL
#endif
-static struct soc_camera_link __initdata ams_delta_iclink = {
+static struct soc_camera_link ams_delta_iclink = {
.bus_id = 0, /* OMAP1 SoC camera bus */
.i2c_adapter_id = 1,
.board_info = &ams_delta_camera_board_info[0],
diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c
index 0efb9db..6b98eef 100644
--- a/arch/arm/mach-omap1/board-fsample.c
+++ b/arch/arm/mach-omap1/board-fsample.c
@@ -291,7 +291,7 @@ static struct omap_lcd_config fsample_lcd_config __initdata = {
.ctrl_name = "internal",
};
-static struct omap_board_config_kernel fsample_config[] = {
+static struct omap_board_config_kernel fsample_config[] __initdata = {
{ OMAP_TAG_LCD, &fsample_lcd_config },
};
diff --git a/drivers/usb/otg/isp1301_omap.c b/drivers/usb/otg/isp1301_omap.c
index e00fa1b..8c6fdef 100644
--- a/drivers/usb/otg/isp1301_omap.c
+++ b/drivers/usb/otg/isp1301_omap.c
@@ -1510,7 +1510,7 @@ isp1301_start_hnp(struct otg_transceiver *dev)
/*-------------------------------------------------------------------------*/
-static int __init
+static int __devinit
isp1301_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
{
int status;
--
1.7.2.3
^ permalink raw reply related
* [PATCH 3/4] ARM: omap: move omap_board_config_kernel to .init.data
From: Uwe Kleine-König @ 2011-02-09 20:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110209192727.GC20795@atomide.com>
This variable is only assigned in __init functions and never used later.
Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>
---
arch/arm/plat-omap/common.c | 5 +++--
1 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index 30c698e..d9f10a3 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -24,10 +24,11 @@
#define NO_LENGTH_CHECK 0xffffffff
-struct omap_board_config_kernel *omap_board_config;
+struct omap_board_config_kernel *omap_board_config __initdata;
int omap_board_config_size;
-static const void *get_config(u16 tag, size_t len, int skip, size_t *len_out)
+static const void *__init get_config(u16 tag, size_t len,
+ int skip, size_t *len_out)
{
struct omap_board_config_kernel *kinfo = NULL;
int i;
--
1.7.2.3
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