* compiling 2.6.37 kernel in THUMB2 mode
From: Nicolas Pitre @ 2011-02-16 4:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <AANLkTi=bJwvTMk0B9N5AAbkNXEh_Wmvu75qrdHeL2Rrh@mail.gmail.com>
On Tue, 15 Feb 2011, vb at vsbe.com wrote:
> hello all,
>
> I am trying to compile the 2.6.37 kernel in THUMB2 mode and am
> experiencing some compilation problems. Some inline assembly in some
> files uses commands inappropriate for THUMB2 mode.
>
> I wonder if the kernel is expected to compile cleanly when
> CONFIG_THUMB2_KERNEL is enabled (and I am doing something wrong), or
> is it know not to compile/work in Thumb2 node for any reason?
It is known not to compile in mainline right now depending on your
target, but fixes are slowly being merged upstream.
Dave Martin is maintaining a Git tree with all the fixes required for
Thumb2 here (see the Thumb2 related branches):
http://git.linaro.org/gitweb?p=people/dmart/linux-2.6-arm.git;a=summary
Beware that some patches might not be final yet.
Nicolas
^ permalink raw reply
* The p2v branch
From: Nicolas Pitre @ 2011-02-16 4:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110213114050.GB4799@n2100.arm.linux.org.uk>
On Sun, 13 Feb 2011, Russell King - ARM Linux wrote:
> On Sat, Feb 12, 2011 at 04:01:14PM -0500, Nicolas Pitre wrote:
> > I've rebased my 2 patches on top of your latest p2v branch. You may
> > pull them from:
> >
> > git://git.linaro.org/people/nico/linux p2v
> >
> > Or if you prefer I can put them in the patch system.
>
> I'd like to wait for Catalin to respond on the phys_addr_t patch - which
> allows 64-bit phys addresses. Obviously that's going to have an impact
> on the p2v code and I'd rather someone else had the job of working out
> what to do about the T2 code.
I rebased my revised patches on top of Will's in your p2v branch and
pushed the result to the above repository.
Nicolas
^ permalink raw reply
* Question about ARM function graph tracing
From: Frederic Weisbecker @ 2011-02-16 4:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297821945.23343.136.camel@gandalf.stny.rr.com>
On Tue, Feb 15, 2011 at 09:05:45PM -0500, Steven Rostedt wrote:
> On Tue, 2011-02-15 at 17:39 -0800, Tim Bird wrote:
> I've had to debug things that broke in the function graph tracer like
> this before. Is dynamic ftrace available in arm?
>
> Hmm, from arch/arm/Kconfig:
>
> select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
>
>
> I guess so. If you are running something other than this XIP_KERNEL, I
> would suggest using the dynamic functions to binary search the issue.
>
> cat available_filter_functions > /tmp/funcs
>
> Then copy half the funcs to /tmp/funcs1 and the other half
> to /tmp/funcs2
>
> cat /tmp/funcs1 > set_ftrace_filter
>
> This may take a while, as setting the filter one by one is slow.
>
> then run the function graph tracer. If it locks up, try it again
> with /tmp/funcs2. If it locks up, you may have two issues or it could be
> something wrong with the function graph tracer itself. But I'm betting
> one will work and one wont.
>
> Then just keep chopping these funcs files until you get down to a set of
> functions that are causing issues. Then it should point out the problem.
>
> This is the procedure I used to find out why a kvm guest was locking up
> with function graph tracer.
>
> See commit:
>
> 258af47479980d8238a04568b94a4e55aa1cb537
>
> Something tells me you may have a similar issue ;)
That's a very nice idea to debug ftrace recursions!
As a last resort, in case the binary search doesn't work, you can try:
1) do a local_irq_save() in asm (to avoid possible recursions with common funcs)
2) test recursion, if so, printk_once() the traced func
3) exit recursion
3) local_irq_restore() in asm
^ permalink raw reply
* [RFC,PATCH 1/3] Add a common struct clk
From: Saravana Kannan @ 2011-02-16 4:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4D5A100F.9000809@codeaurora.org>
On 02/14/2011 09:33 PM, Saravana Kannan wrote:
> Russell, A question for you further down this email. Please take a look.
Russell, Ping... I will snip the rest of the discussion so that it's
easy to spot the question.
>>>> +int clk_set_parent(struct clk *clk, struct clk *parent)
>>>> +{
>>>> + if (clk->ops->set_parent)
>>>> + return clk->ops->set_parent(clk, parent);
>>>
>>> I'm not sure on this one. If the prepare ops for a clock also calls the
>>> prepare ops on the parent, shouldn't we prevent changing the parent
>>> while the prepare/unprepare is going on?
>>
>> Again, this is related to set_rate during enable/disable or
>> prepare/unprepare;
>> we don't have defined semantics for this at present.
>
> After thinking about this the past couple of days, this looks like a
> location where the locking is more necessary than inside set rate. I
> always saw the parent clock as the clock that generates the clock signal
> from which this clock derives (divide, etc) it's clock signal from.
>
> Assuming Russell and/or the community agrees on the semantics of
> "parent", without the generic implementation grabbing the prepare_lock
> while setting the parent, there is no way for the specific clock driver
> implementations to cleanly ensure correctness. The only option for them
> would be to peek into the generic clock struct and grab the prepare lock
> -- to me that would be an ugly hack and/or layering violation that would
> cause problems later on.
>
> Russell/All,
>
> What's the meaning of a parent clock? Do you agree with my definition --
> "the parent clock is the clock that generates the clock signal from
> which the child clock derives (divide, etc) it's clock signal from."? Or
> is it open to interpretation by each implementation?
Thanks,
Saravana
--
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
^ permalink raw reply
* [PATCH] ARM: errata: pl310 cache sync operation may be faulty
From: Srinidhi KASAGAR @ 2011-02-16 5:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <AANLkTikPGwcm-_j-NzW2UixaEx_ekJMjJcrTO1SUy7Ao@mail.gmail.com>
On Tue, Feb 15, 2011 at 17:38:52 +0100, Catalin Marinas wrote:
> On 15 February 2011 11:18, srinidhi kasagar
> <srinidhi.kasagar@stericsson.com> wrote:
> > +config ARM_ERRATA_753970
> > + ? ? ? bool "ARM errata: cache sync operation may be faulty"
> > + ? ? ? depends on CACHE_PL310
> > + ? ? ? help
> > + ? ? ? ? This option enables the workaround for the 753970 PL310 erratum.
>
> Is this number correct? I couldn't find it in ARM's internal database.
yes, we got this errata notice from ARM recently (10-feb-11), document
revision 12.1
>
> > + ? ? ? ? Under some condition the effect of cache sync operation on
> > + ? ? ? ? the store buffer still remains when the operation completes.
> > + ? ? ? ? This means that the store buffer is always asked to drain and
> > + ? ? ? ? this prevents it from merging any further writes. The workaround
> > + ? ? ? ? is to replace the normal offset of cache sync operation (0x730)
> > + ? ? ? ? by another offset targeting an unmapped PL310 register 0x740.
> > + ? ? ? ? This has the same effect as the cache sync operation: store buffer
> > + ? ? ? ? drain and waiting for all buffers empty.
>
> You may want to specify the revision number this applies to so that
> people to enable it if not needed.
OK, will include this revision number
srinidhi
^ permalink raw reply
* [PATCH] ARM: errata: pl310 cache sync operation may be faulty
From: Srinidhi KASAGAR @ 2011-02-16 5:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110215113422.GE4152@n2100.arm.linux.org.uk>
On Tue, Feb 15, 2011 at 12:34:22 +0100, Russell King - ARM Linux wrote:
> On Tue, Feb 15, 2011 at 04:48:03PM +0530, srinidhi kasagar wrote:
> > +#ifdef ARM_ERRATA_753970
> > +#define L2X0_DUMMY_REG 0x740
> > + /* write to an unmmapped register */
> > + writel_relaxed(0, base + L2X0_DUMMY_REG);
> > + cache_wait(base + L2X0_CACHE_SYNC, 1);
> > +#else
> > writel_relaxed(0, base + L2X0_CACHE_SYNC);
> > cache_wait(base + L2X0_CACHE_SYNC, 1);
> > +#endif
>
> So why wrap cache_wait() up in that horrible ifdef as well - and why not
> put the dummy register definition along side the other register definitions?
OK. In fact cache_wait need not have to be under ifdef
as this bug found only on PL310 where the sync operations
are atomic. I will send out a new patch.
srinidhi
^ permalink raw reply
* [PATCH V4] OMAP3: PM: Set/clear T2 bit for Smartreflex on TWL
From: Gulati, Shweta @ 2011-02-16 5:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <bf1e2a72d8f16365df684cd5add00eee@mail.gmail.com>
Hi,
On Tue, Feb 15, 2011 at 10:00 PM, Vishwanath Sripathy
<vishwanath.bs@ti.com> wrote:
>> -----Original Message-----
>> From: linux-arm-kernel-bounces at lists.infradead.org [mailto:linux-arm-
>> kernel-bounces at lists.infradead.org] On Behalf Of Jarkko Nikula
>> Sent: Tuesday, February 15, 2011 8:47 PM
>> To: Shweta Gulati
>> Cc: Nishanth Menon; Thara Gopinath; linux-omap at vger.kernel.org;
>> linux-arm-kernel at lists.infradead.org
>> Subject: Re: [PATCH V4] OMAP3: PM: Set/clear T2 bit for Smartreflex on
>> TWL
>>
>> On Tue, 15 Feb 2011 13:28:58 +0530
>> Shweta Gulati <shweta.gulati@ti.com> wrote:
>>
>> > This patch is based on LO PM Branch and Smartreflex has been
>> > tested on OMAP3430 SDP, OMAP3630 SDP and boot tested on
>> > OMAP2430 SDP.
>> >
>> I saw this was working on N900 (kind of special instrumentation
>> setup) after enabling /sys/kernel/debug/voltage/[vdd_core |
>> vdd_mpu]/smartreflex/autocomp. Few comments below.
>>
>> > @@ -269,6 +276,18 @@ int __init omap3_twl_init(void)
>> > ? ? ? ? ? ? omap3_core_volt_info.vp_vddmax =
>> OMAP3630_VP2_VLIMITTO_VDDMAX;
>> > ? ? }
>> ...
>> > + ? if (!twl_sr_enable_autoinit)
>> > + ? ? ? ? ? omap3_twl_set_sr_bit(true);
>> ...
>> > +int __init omap3_twl_set_sr_bit(bool enable)
>> > +{
>> > + ? u8 temp;
>> > + ? int ret;
>> > + ? if (twl_sr_enable_autoinit)
>> > + ? ? ? ? ? pr_warning("%s: unexpected multiple calls\n", __func__);
>> > +
>> > + ? ret = twl_i2c_read_u8(TWL4030_MODULE_PM_RECEIVER, &temp,
>> > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? TWL4030_DCDC_GLOBAL_CFG);
>> > + ? if (ret)
>> > + ? ? ? ? ? goto err;
>> > +
>> > + ? if (enable)
>> > + ? ? ? ? ? temp |= SMARTREFLEX_ENABLE;
>> > + ? else
>> > + ? ? ? ? ? temp &= ~SMARTREFLEX_ENABLE;
>> > +
>> > + ? ret = twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, temp,
>> > + ? ? ? ? ? ? ? ? ? ? ? ? ? TWL4030_DCDC_GLOBAL_CFG);
>>
>> Would it make more sense to set only the flag here and do the register
>> writes when omap3_twl_init is executing? Then it's not so strict when
>> the board code calls this function.
> What if board code calls this function after twl_init is executed? Then
> you will not clear the bit right?
> Intention of this function is to make sure the bit is set/cleared when it
> is called.
ompa3_twl_init is called from 'omap2_common_pm_late_init' which is
late_initcall.
So it would be called after board specific initializations are
completed in 'init' process.
> vishwa
>>
>> > + ? if (!ret) {
>> > + ? ? ? ? ? twl_sr_enable_autoinit = true;
>> > + ? ? ? ? ? return 0;
>>
>> Should this be twl_sr_enable_autoinit = enable (if going to do
>> register write here)?
>>
>> --
>> Jarkko
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
--
Thanks,
Regards,
Shweta
^ permalink raw reply
* [PATCH V4] OMAP3: PM: Set/clear T2 bit for Smartreflex on TWL
From: Gulati, Shweta @ 2011-02-16 5:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110215172931.3a6e45a8.jhnikula@gmail.com>
On Tue, Feb 15, 2011 at 8:59 PM, Jarkko Nikula <jhnikula@gmail.com> wrote:
> On Tue, 15 Feb 2011 17:16:52 +0200
> Jarkko Nikula <jhnikula@gmail.com> wrote:
>
>> Would it make more sense to set only the flag here and do the register
>> writes when omap3_twl_init is executing? Then it's not so strict when
>> the board code calls this function.
>>
> Probably discussed earlier but would it make more sense to have flag in
> struct twl4030_platform_data and to do registers writes in twl-core?
> Looks suspicious to have i2c_writes under arch/arm/.
twl_i2c_read/write APIs are used from arch/arm in many board files,
so I think it should not cause any issue.
> --
> Jarkko
>
--
Thanks,
Regards,
Shweta
^ permalink raw reply
* [PATCH] ARM: errata: pl310 cache sync operation may be faulty
From: Srinidhi KASAGAR @ 2011-02-16 6:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110215113422.GE4152@n2100.arm.linux.org.uk>
On Tue, Feb 15, 2011 at 12:34:22 +0100, Russell King - ARM Linux wrote:
> On Tue, Feb 15, 2011 at 04:48:03PM +0530, srinidhi kasagar wrote:
> > +#ifdef ARM_ERRATA_753970
> > +#define L2X0_DUMMY_REG 0x740
> > + /* write to an unmmapped register */
> > + writel_relaxed(0, base + L2X0_DUMMY_REG);
> > + cache_wait(base + L2X0_CACHE_SYNC, 1);
> > +#else
> > writel_relaxed(0, base + L2X0_CACHE_SYNC);
> > cache_wait(base + L2X0_CACHE_SYNC, 1);
> > +#endif
>
> So why wrap cache_wait() up in that horrible ifdef as well - and why not
> put the dummy register definition along side the other register definitions?
updated patch below
^ permalink raw reply
* [RFC] Inter-processor Mailboxes Drivers
From: Hiroshi DOYU @ 2011-02-16 6:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <DD7A9A95166BF4418C4C1EB2033B6EE2038FAAF0@na3-mail.mgc.mentorg.com>
From: "ext Blanchard, Hollis" <Hollis_Blanchard@mentor.com>
Subject: Re: [RFC] Inter-processor Mailboxes Drivers
Date: Tue, 15 Feb 2011 15:38:25 -0800
> On 02/15/2011 01:58 PM, Meador Inge wrote:
>> On 02/14/2011 04:01 AM, Jamie Iles wrote:
>>> On Fri, Feb 11, 2011 at 03:19:51PM -0600, Meador Inge wrote:
>>>> 1. Hardware specific bits somewhere under '.../arch/*'. Drivers
>>>> for the MPIC message registers on Power and OMAP4 mailboxes,
>>>> for
>>>> example.
>>>> 2. A higher level driver under '.../drivers/mailbox/*'. That the
>>>> pieces in (1) would register with. This piece would expose the
>>>> main kernel API.
>>>> 3. Userspace interfaces for accessing the mailboxes. A
>>>> '/dev/mailbox1', '/dev/mailbox2', etc... mapping, for example.
>>>
>>> How about using virtio for all of this and having the mailbox as a
>>> notification/message passing driver for the virtio backend? There are
>>> already virtio console and network drivers that could be useful for the
>>> userspace part of it. drivers/virtio/virtio_ring.c might be a good
>>> starting point if you thought there was some mileage in this approach.
>>
>> To be honest, I am not that familiar with 'virtio', but I will take a
>> look. Thanks for the pointer. Maybe Hollis can speak to this idea more.
> My opinion is that virtio is (over?) complicated.
Considering the case of omap mailbox H/W, it is just a simple one way
4 slot x 32bit H/W FIFO, I also may think that this may be a bit too
much...
> I've looked into it in the past, and I'm definitely open to using it if
> somebody can demonstrate how easy it is, but adopting it wouldn't have
> helped OpenMCAPI with our use cases, and would have incurred extra pain,
> so we didn't.
>
> Hollis Blanchard
> Mentor Graphics, Embedded Systems Division
>
^ permalink raw reply
* [PATCH 00/11] OMAP2+: clock: add clockfw autoidle for iclks, OMAP2xxx
From: Paul Walmsley @ 2011-02-16 6:52 UTC (permalink / raw)
To: linux-arm-kernel
Hello,
This patch series adds clock framework-controlled autoidle support for
the OMAP2xxx DPLL, APLLs, and OMAP2/3 interface clocks. The old
direct register writes in the PM code to enable clock autoidle have been
removed.
This series also ensures that all clock autoidle is disabled during
boot and only re-enabled if CONFIG_PM is enabled.
The series applies on the 'clk_autoidle_a_2.6.39' branch of
git://git.pwsan.com/linux-2.6.
Boot-tested on N800, and dynamic idle-tested on OMAP3430 Beagleboard.
Compile-tested with omap1_defconfig, omap2plus_defconfig, a 5912
OSK-only config, an N8x0-only config, an OMAP3-only config, and an OMAP4-only
config.
- Paul
---
clk_autoidle_b_2.6.39
text data bss dec hex filename
5530703 330544 5594520 11455767 aecd17 vmlinux.omap2plus_defconfig.orig
5531167 330544 5594520 11456231 aecee7 vmlinux.omap2plus_defconfig.patched
Paul Walmsley (11):
OMAP2+: clock: disable autoidle on all clocks during clock init
OMAP2: clock: add DPLL autoidle support
OMAP2xxx: clock: add clockfw autoidle support for APLLs
OMAP2+: clock: comment that osc_ck/osc_sys_ck should use clockfw autoidle control
OMAP2+: clock: add interface clock type code with autoidle support
OMAP2420: clock: add sdrc_ick
OMAP2420: clock: use autoidle clkops for all autoidle-controllable interface clocks
OMAP2430/3xxx: clock: add modem clock autoidle support
OMAP2430: clock: use autoidle clkops for all autoidle-controllable interface clocks
OMAP3: clock: use autoidle clkops for all autoidle-controllable interface clocks
OMAP2/3: PM: remove manual CM_AUTOIDLE bit setting in mach-omap2/pm*xx.c
arch/arm/mach-omap2/Makefile | 7 +
arch/arm/mach-omap2/clkt2xxx_apll.c | 24 +++++
arch/arm/mach-omap2/clkt2xxx_dpll.c | 63 +++++++++++++
arch/arm/mach-omap2/clkt2xxx_osc.c | 14 +++
arch/arm/mach-omap2/clkt_iclk.c | 82 +++++++++++++++++
arch/arm/mach-omap2/clock.h | 11 ++
arch/arm/mach-omap2/clock2420_data.c | 130 +++++++++++++++++-----------
arch/arm/mach-omap2/clock2430_data.c | 130 ++++++++++++++++------------
arch/arm/mach-omap2/clock34xx.c | 29 ++++++
arch/arm/mach-omap2/clock34xx.h | 5 +
arch/arm/mach-omap2/clock3517.c | 4 +
arch/arm/mach-omap2/clock3xxx.c | 3 -
arch/arm/mach-omap2/clock3xxx_data.c | 155 +++++++++++++++++----------------
arch/arm/mach-omap2/clock44xx_data.c | 3 +
arch/arm/mach-omap2/cm-regbits-24xx.h | 3 +
arch/arm/mach-omap2/cm2xxx_3xxx.c | 69 +++++++++++++++
arch/arm/mach-omap2/cm2xxx_3xxx.h | 8 ++
arch/arm/mach-omap2/pm24xx.c | 69 +--------------
arch/arm/mach-omap2/pm34xx.c | 105 ----------------------
19 files changed, 557 insertions(+), 357 deletions(-)
create mode 100644 arch/arm/mach-omap2/clkt2xxx_dpll.c
create mode 100644 arch/arm/mach-omap2/clkt_iclk.c
^ permalink raw reply
* [PATCH 01/11] OMAP2+: clock: disable autoidle on all clocks during clock init
From: Paul Walmsley @ 2011-02-16 6:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110216065030.22089.61217.stgit@twilight.localdomain>
Disable autoidle on all clocks during clock framework initialization.
(If CONFIG_PM is set, autoidle is re-enabled for all clocks later in
the boot process.)
The principle behind this patch, and some similar patches, is that the
kernel should start with all power management features disabled.
Later in the boot process, the PM code, if compiled in with CONFIG_PM,
enables or re-enables power management features.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/clock2420_data.c | 3 +++
arch/arm/mach-omap2/clock2430_data.c | 3 +++
arch/arm/mach-omap2/clock3xxx.c | 3 ---
arch/arm/mach-omap2/clock3xxx_data.c | 6 +++++-
arch/arm/mach-omap2/clock44xx_data.c | 3 +++
5 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
index 0a992bc..ee73e14 100644
--- a/arch/arm/mach-omap2/clock2420_data.c
+++ b/arch/arm/mach-omap2/clock2420_data.c
@@ -1913,6 +1913,9 @@ int __init omap2420_clk_init(void)
omap2_init_clk_clkdm(c->lk.clk);
}
+ /* Disable autoidle on all clocks; let the PM code enable it later */
+ omap_clk_disable_autoidle_all();
+
/* Check the MPU rate set by bootloader */
clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);
for (prcm = rate_table; prcm->mpu_speed; prcm++) {
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
index c047dcd..a1298e5 100644
--- a/arch/arm/mach-omap2/clock2430_data.c
+++ b/arch/arm/mach-omap2/clock2430_data.c
@@ -2028,6 +2028,9 @@ int __init omap2430_clk_init(void)
omap2_init_clk_clkdm(c->lk.clk);
}
+ /* Disable autoidle on all clocks; let the PM code enable it later */
+ omap_clk_disable_autoidle_all();
+
/* Check the MPU rate set by bootloader */
clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);
for (prcm = rate_table; prcm->mpu_speed; prcm++) {
diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c
index e9f66b6..952c3e0 100644
--- a/arch/arm/mach-omap2/clock3xxx.c
+++ b/arch/arm/mach-omap2/clock3xxx.c
@@ -65,9 +65,6 @@ void __init omap3_clk_lock_dpll5(void)
clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST);
clk_enable(dpll5_clk);
- /* Enable autoidle to allow it to enter low power bypass */
- omap3_dpll_allow_idle(dpll5_clk);
-
/* Program dpll5_m2_clk divider for no division */
dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");
clk_enable(dpll5_m2_clk);
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 7cf89f8..0021559 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -3535,6 +3535,9 @@ int __init omap3xxx_clk_init(void)
omap2_init_clk_clkdm(c->lk.clk);
}
+ /* Disable autoidle on all clocks; let the PM code enable it later */
+ omap_clk_disable_autoidle_all();
+
recalculate_root_clocks();
pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
@@ -3548,7 +3551,8 @@ int __init omap3xxx_clk_init(void)
clk_enable_init_clocks();
/*
- * Lock DPLL5 and put it in autoidle.
+ * Lock DPLL5 -- here only until other device init code can
+ * handle this
*/
if (omap_rev() >= OMAP3430_REV_ES2_0)
omap3_clk_lock_dpll5();
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index dcbe105..2795342 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -3309,6 +3309,9 @@ int __init omap4xxx_clk_init(void)
omap2_init_clk_clkdm(c->lk.clk);
}
+ /* Disable autoidle on all clocks; let the PM code enable it later */
+ omap_clk_disable_autoidle_all();
+
recalculate_root_clocks();
/*
^ permalink raw reply related
* [PATCH 02/11] OMAP2: clock: add DPLL autoidle support
From: Paul Walmsley @ 2011-02-16 6:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110216065030.22089.61217.stgit@twilight.localdomain>
Add the necessary code and data to allow the clock framework to enable
and disable the OMAP2 DPLL autoidle state. This is so the direct
register access can be moved out of the mach-omap2/pm24xx.c code, and other
code that needs to control this (e.g., CPUIdle) can do so via an API.
As part of this patch, remove the pm24xx.c code that formerly wrote
directly to the autoidle bits.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@ti.com>
---
arch/arm/mach-omap2/Makefile | 3 +-
arch/arm/mach-omap2/clkt2xxx_dpll.c | 63 ++++++++++++++++++++++++++++++++++
arch/arm/mach-omap2/clock.h | 1 +
arch/arm/mach-omap2/clock2420_data.c | 2 +
arch/arm/mach-omap2/clock2430_data.c | 2 +
arch/arm/mach-omap2/cm2xxx_3xxx.c | 27 +++++++++++++++
arch/arm/mach-omap2/cm2xxx_3xxx.h | 3 ++
arch/arm/mach-omap2/pm24xx.c | 12 ++++--
8 files changed, 105 insertions(+), 8 deletions(-)
create mode 100644 arch/arm/mach-omap2/clkt2xxx_dpll.c
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 3a798ef..41cb404 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -112,7 +112,8 @@ obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o \
clkt2xxx_sys.o \
clkt2xxx_dpllcore.o \
clkt2xxx_virt_prcm_set.o \
- clkt2xxx_apll.o clkt2xxx_osc.o
+ clkt2xxx_apll.o clkt2xxx_osc.o \
+ clkt2xxx_dpll.o
obj-$(CONFIG_ARCH_OMAP2420) += clock2420_data.o
obj-$(CONFIG_ARCH_OMAP2430) += clock2430.o clock2430_data.o
obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o \
diff --git a/arch/arm/mach-omap2/clkt2xxx_dpll.c b/arch/arm/mach-omap2/clkt2xxx_dpll.c
new file mode 100644
index 0000000..1502a7b
--- /dev/null
+++ b/arch/arm/mach-omap2/clkt2xxx_dpll.c
@@ -0,0 +1,63 @@
+/*
+ * OMAP2-specific DPLL control functions
+ *
+ * Copyright (C) 2011 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <plat/clock.h>
+
+#include "clock.h"
+#include "cm2xxx_3xxx.h"
+#include "cm-regbits-24xx.h"
+
+/* Private functions */
+
+/**
+ * _allow_idle - enable DPLL autoidle bits
+ * @clk: struct clk * of the DPLL to operate on
+ *
+ * Enable DPLL automatic idle control. The DPLL will enter low-power
+ * stop when its downstream clocks are gated. No return value.
+ * REVISIT: DPLL can optionally enter low-power bypass by writing 0x1
+ * instead. Add some mechanism to optionally enter this mode.
+ */
+static void _allow_idle(struct clk *clk)
+{
+ if (!clk || !clk->dpll_data)
+ return;
+
+ omap2xxx_cm_set_dpll_auto_low_power_stop();
+}
+
+/**
+ * _deny_idle - prevent DPLL from automatically idling
+ * @clk: struct clk * of the DPLL to operate on
+ *
+ * Disable DPLL automatic idle control. No return value.
+ */
+static void _deny_idle(struct clk *clk)
+{
+ if (!clk || !clk->dpll_data)
+ return;
+
+ omap2xxx_cm_set_dpll_disable_autoidle();
+}
+
+
+/* Public data */
+
+const struct clkops clkops_omap2xxx_dpll_ops = {
+ .allow_idle = _allow_idle,
+ .deny_idle = _deny_idle,
+};
+
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 0725a6a..9972d89 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -148,6 +148,7 @@ extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table)
#define omap2_clk_exit_cpufreq_table 0
#endif
+extern const struct clkops clkops_omap2xxx_dpll_ops;
extern const struct clkops clkops_omap3_noncore_dpll_ops;
extern const struct clkops clkops_omap3_core_dpll_ops;
extern const struct clkops clkops_omap4_dpllmx_ops;
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
index ee73e14..30fbcbd 100644
--- a/arch/arm/mach-omap2/clock2420_data.c
+++ b/arch/arm/mach-omap2/clock2420_data.c
@@ -125,7 +125,7 @@ static struct dpll_data dpll_dd = {
*/
static struct clk dpll_ck = {
.name = "dpll_ck",
- .ops = &clkops_null,
+ .ops = &clkops_omap2xxx_dpll_ops,
.parent = &sys_ck, /* Can be func_32k also */
.dpll_data = &dpll_dd,
.clkdm_name = "wkup_clkdm",
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
index a1298e5..1ff150a 100644
--- a/arch/arm/mach-omap2/clock2430_data.c
+++ b/arch/arm/mach-omap2/clock2430_data.c
@@ -125,7 +125,7 @@ static struct dpll_data dpll_dd = {
*/
static struct clk dpll_ck = {
.name = "dpll_ck",
- .ops = &clkops_null,
+ .ops = &clkops_omap2xxx_dpll_ops,
.parent = &sys_ck, /* Can be func_32k also */
.dpll_data = &dpll_dd,
.clkdm_name = "wkup_clkdm",
diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.c b/arch/arm/mach-omap2/cm2xxx_3xxx.c
index 96954aa..6b0c7c8 100644
--- a/arch/arm/mach-omap2/cm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/cm2xxx_3xxx.c
@@ -25,6 +25,10 @@
#include "cm-regbits-24xx.h"
#include "cm-regbits-34xx.h"
+/* CM_AUTOIDLE_PLL.AUTO_* bit values */
+#define DPLL_AUTOIDLE_DISABLE 0x0
+#define OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP 0x3
+
static const u8 cm_idlest_offs[] = {
CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3
};
@@ -125,6 +129,29 @@ void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask)
_write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, module, mask);
}
+/*
+ * DPLL autoidle control
+ */
+
+static void _omap2xxx_set_dpll_autoidle(u8 m)
+{
+ u32 v;
+
+ v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
+ v &= ~OMAP24XX_AUTO_DPLL_MASK;
+ v |= m << OMAP24XX_AUTO_DPLL_SHIFT;
+ omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
+}
+
+void omap2xxx_cm_set_dpll_disable_autoidle(void)
+{
+ _omap2xxx_set_dpll_autoidle(OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP);
+}
+
+void omap2xxx_cm_set_dpll_auto_low_power_stop(void)
+{
+ _omap2xxx_set_dpll_autoidle(DPLL_AUTOIDLE_DISABLE);
+}
/*
*
diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.h b/arch/arm/mach-omap2/cm2xxx_3xxx.h
index 5e9ea5b..5f4df1c 100644
--- a/arch/arm/mach-omap2/cm2xxx_3xxx.h
+++ b/arch/arm/mach-omap2/cm2xxx_3xxx.h
@@ -122,6 +122,9 @@ extern void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask);
extern void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask);
extern void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask);
+extern void omap2xxx_cm_set_dpll_disable_autoidle(void);
+extern void omap2xxx_cm_set_dpll_auto_low_power_stop(void);
+
#endif
/* CM register bits shared between 24XX and 3430 */
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index 97feb3a..23b4607 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -378,6 +378,7 @@ static void __init prcm_setup_regs(void)
{
int i, num_mem_banks;
struct powerdomain *pwrdm;
+ u32 v;
/* Enable autoidle */
omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
@@ -468,11 +469,12 @@ static void __init prcm_setup_regs(void)
omap2_cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI_MASK, OMAP24XX_DSP_MOD,
CM_AUTOIDLE);
- /* Put DPLL and both APLLs into autoidle mode */
- omap2_cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) |
- (0x03 << OMAP24XX_AUTO_96M_SHIFT) |
- (0x03 << OMAP24XX_AUTO_54M_SHIFT),
- PLL_MOD, CM_AUTOIDLE);
+ /* Put both APLLs into autoidle mode */
+ v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
+ v &= ~(OMAP24XX_AUTO_96M_MASK | OMAP24XX_AUTO_54M_SHIFT);
+ v |= (0x03 << OMAP24XX_AUTO_96M_SHIFT) |
+ (0x03 << OMAP24XX_AUTO_54M_SHIFT);
+ omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
omap2_cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL_MASK |
OMAP24XX_AUTO_WDT1_MASK |
^ permalink raw reply related
* [PATCH 03/11] OMAP2xxx: clock: add clockfw autoidle support for APLLs
From: Paul Walmsley @ 2011-02-16 6:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110216065030.22089.61217.stgit@twilight.localdomain>
OMAP2xxx devices have two on-chip APLLs. These APLLs can
automatically enter idle when not in use. Connect the APLL autoidle
code to the clock code, so that the clock framework can handle this
process. As part of this patch, remove the code in mach-omap2/pm24xx.c
that previously handled APLL autoidle control.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@ti.com>
---
arch/arm/mach-omap2/clkt2xxx_apll.c | 24 +++++++++++++++++++
arch/arm/mach-omap2/cm2xxx_3xxx.c | 44 ++++++++++++++++++++++++++++++++++-
arch/arm/mach-omap2/cm2xxx_3xxx.h | 5 ++++
arch/arm/mach-omap2/pm24xx.c | 8 ------
4 files changed, 72 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c
index f51cffd..b19a1f7 100644
--- a/arch/arm/mach-omap2/clkt2xxx_apll.c
+++ b/arch/arm/mach-omap2/clkt2xxx_apll.c
@@ -78,6 +78,26 @@ static int omap2_clk_apll54_enable(struct clk *clk)
return omap2_clk_apll_enable(clk, OMAP24XX_ST_54M_APLL_MASK);
}
+static void _apll96_allow_idle(struct clk *clk)
+{
+ omap2xxx_cm_set_apll96_auto_low_power_stop();
+}
+
+static void _apll96_deny_idle(struct clk *clk)
+{
+ omap2xxx_cm_set_apll96_disable_autoidle();
+}
+
+static void _apll54_allow_idle(struct clk *clk)
+{
+ omap2xxx_cm_set_apll54_auto_low_power_stop();
+}
+
+static void _apll54_deny_idle(struct clk *clk)
+{
+ omap2xxx_cm_set_apll54_disable_autoidle();
+}
+
/* Stop APLL */
static void omap2_clk_apll_disable(struct clk *clk)
{
@@ -93,11 +113,15 @@ static void omap2_clk_apll_disable(struct clk *clk)
const struct clkops clkops_apll96 = {
.enable = omap2_clk_apll96_enable,
.disable = omap2_clk_apll_disable,
+ .allow_idle = _apll96_allow_idle,
+ .deny_idle = _apll96_deny_idle,
};
const struct clkops clkops_apll54 = {
.enable = omap2_clk_apll54_enable,
.disable = omap2_clk_apll_disable,
+ .allow_idle = _apll54_allow_idle,
+ .deny_idle = _apll54_deny_idle,
};
/* Public functions */
diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.c b/arch/arm/mach-omap2/cm2xxx_3xxx.c
index 6b0c7c8..9d0dec8 100644
--- a/arch/arm/mach-omap2/cm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/cm2xxx_3xxx.c
@@ -25,10 +25,14 @@
#include "cm-regbits-24xx.h"
#include "cm-regbits-34xx.h"
-/* CM_AUTOIDLE_PLL.AUTO_* bit values */
+/* CM_AUTOIDLE_PLL.AUTO_* bit values for DPLLs */
#define DPLL_AUTOIDLE_DISABLE 0x0
#define OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP 0x3
+/* CM_AUTOIDLE_PLL.AUTO_* bit values for APLLs (OMAP2xxx only) */
+#define OMAP2XXX_APLL_AUTOIDLE_DISABLE 0x0
+#define OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP 0x3
+
static const u8 cm_idlest_offs[] = {
CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3
};
@@ -154,6 +158,44 @@ void omap2xxx_cm_set_dpll_auto_low_power_stop(void)
}
/*
+ * APLL autoidle control
+ */
+
+static void _omap2xxx_set_apll_autoidle(u8 m, u32 mask)
+{
+ u32 v;
+
+ v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
+ v &= ~mask;
+ v |= m << __ffs(mask);
+ omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
+}
+
+void omap2xxx_cm_set_apll54_disable_autoidle(void)
+{
+ _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP,
+ OMAP24XX_AUTO_54M_MASK);
+}
+
+void omap2xxx_cm_set_apll54_auto_low_power_stop(void)
+{
+ _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE,
+ OMAP24XX_AUTO_54M_MASK);
+}
+
+void omap2xxx_cm_set_apll96_disable_autoidle(void)
+{
+ _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP,
+ OMAP24XX_AUTO_96M_MASK);
+}
+
+void omap2xxx_cm_set_apll96_auto_low_power_stop(void)
+{
+ _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE,
+ OMAP24XX_AUTO_96M_MASK);
+}
+
+/*
*
*/
diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.h b/arch/arm/mach-omap2/cm2xxx_3xxx.h
index 5f4df1c..088bbad 100644
--- a/arch/arm/mach-omap2/cm2xxx_3xxx.h
+++ b/arch/arm/mach-omap2/cm2xxx_3xxx.h
@@ -125,6 +125,11 @@ extern void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask);
extern void omap2xxx_cm_set_dpll_disable_autoidle(void);
extern void omap2xxx_cm_set_dpll_auto_low_power_stop(void);
+extern void omap2xxx_cm_set_apll54_disable_autoidle(void);
+extern void omap2xxx_cm_set_apll54_auto_low_power_stop(void);
+extern void omap2xxx_cm_set_apll96_disable_autoidle(void);
+extern void omap2xxx_cm_set_apll96_auto_low_power_stop(void);
+
#endif
/* CM register bits shared between 24XX and 3430 */
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index 23b4607..15b0f53 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -378,7 +378,6 @@ static void __init prcm_setup_regs(void)
{
int i, num_mem_banks;
struct powerdomain *pwrdm;
- u32 v;
/* Enable autoidle */
omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
@@ -469,13 +468,6 @@ static void __init prcm_setup_regs(void)
omap2_cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI_MASK, OMAP24XX_DSP_MOD,
CM_AUTOIDLE);
- /* Put both APLLs into autoidle mode */
- v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
- v &= ~(OMAP24XX_AUTO_96M_MASK | OMAP24XX_AUTO_54M_SHIFT);
- v |= (0x03 << OMAP24XX_AUTO_96M_SHIFT) |
- (0x03 << OMAP24XX_AUTO_54M_SHIFT);
- omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
-
omap2_cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL_MASK |
OMAP24XX_AUTO_WDT1_MASK |
OMAP24XX_AUTO_MPU_WDT_MASK |
^ permalink raw reply related
* [PATCH 04/11] OMAP2+: clock: comment that osc_ck/osc_sys_ck should use clockfw autoidle control
From: Paul Walmsley @ 2011-02-16 6:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110216065030.22089.61217.stgit@twilight.localdomain>
Place some comments in the OMAP oscillator clock control code to note that
its autoidle mode should eventually be controlled via the new OMAP clockfw
autoidle control interface.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/clkt2xxx_osc.c | 14 ++++++++++++++
1 files changed, 14 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/clkt2xxx_osc.c b/arch/arm/mach-omap2/clkt2xxx_osc.c
index df7b805..c346092 100644
--- a/arch/arm/mach-omap2/clkt2xxx_osc.c
+++ b/arch/arm/mach-omap2/clkt2xxx_osc.c
@@ -30,6 +30,13 @@
#include "prm2xxx_3xxx.h"
#include "prm-regbits-24xx.h"
+/*
+ * XXX This does not actually enable the osc_ck, since the osc_ck must
+ * be running for this function to be called. Instead, this function
+ * is used to disable an autoidle mode on the osc_ck. The existing
+ * clk_enable/clk_disable()-based usecounting for osc_ck should be
+ * replaced with autoidle-based usecounting.
+ */
static int omap2_enable_osc_ck(struct clk *clk)
{
u32 pcc;
@@ -41,6 +48,13 @@ static int omap2_enable_osc_ck(struct clk *clk)
return 0;
}
+/*
+ * XXX This does not actually disable the osc_ck, since doing so would
+ * immediately halt the system. Instead, this function is used to
+ * enable an autoidle mode on the osc_ck. The existing
+ * clk_enable/clk_disable()-based usecounting for osc_ck should be
+ * replaced with autoidle-based usecounting.
+ */
static void omap2_disable_osc_ck(struct clk *clk)
{
u32 pcc;
^ permalink raw reply related
* [PATCH 05/11] OMAP2+: clock: add interface clock type code with autoidle support
From: Paul Walmsley @ 2011-02-16 6:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110216065030.22089.61217.stgit@twilight.localdomain>
Add interface clock type code with autoidle enable/disable support.
The clkops structures created in this file will be used for all
OMAP2/3 interface clocks with autoidle support. They will enable the
clock framework to control interface clock autoidle directly.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/Makefile | 6 ++-
arch/arm/mach-omap2/clkt_iclk.c | 73 +++++++++++++++++++++++++++++++++++++++
arch/arm/mach-omap2/clock.h | 9 ++++-
3 files changed, 85 insertions(+), 3 deletions(-)
create mode 100644 arch/arm/mach-omap2/clkt_iclk.c
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 41cb404..a28ba5a 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -107,19 +107,21 @@ obj-$(CONFIG_ARCH_OMAP3) += clockdomain.o \
clockdomains2xxx_3xxx_data.o
obj-$(CONFIG_ARCH_OMAP4) += clockdomain.o \
clockdomains44xx_data.o
+
# Clock framework
obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o \
clkt2xxx_sys.o \
clkt2xxx_dpllcore.o \
clkt2xxx_virt_prcm_set.o \
clkt2xxx_apll.o clkt2xxx_osc.o \
- clkt2xxx_dpll.o
+ clkt2xxx_dpll.o clkt_iclk.o
obj-$(CONFIG_ARCH_OMAP2420) += clock2420_data.o
obj-$(CONFIG_ARCH_OMAP2430) += clock2430.o clock2430_data.o
obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o \
clock34xx.o clkt34xx_dpll3m2.o \
clock3517.o clock36xx.o \
- dpll3xxx.o clock3xxx_data.o
+ dpll3xxx.o clock3xxx_data.o \
+ clkt_iclk.o
obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) clock44xx_data.o \
dpll3xxx.o dpll44xx.o
diff --git a/arch/arm/mach-omap2/clkt_iclk.c b/arch/arm/mach-omap2/clkt_iclk.c
new file mode 100644
index 0000000..dd8a6d3
--- /dev/null
+++ b/arch/arm/mach-omap2/clkt_iclk.c
@@ -0,0 +1,73 @@
+/*
+ * OMAP2/3 interface clock control
+ *
+ * Copyright (C) 2011 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#undef DEBUG
+
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <plat/clock.h>
+#include <plat/prcm.h>
+
+#include "clock.h"
+#include "clock2xxx.h"
+#include "cm2xxx_3xxx.h"
+#include "cm-regbits-24xx.h"
+
+/* Private functions */
+
+/* XXX */
+void omap2_clkt_iclk_allow_idle(struct clk *clk)
+{
+ u32 v, r;
+
+ r = ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN));
+
+ v = __raw_readl((__force void __iomem *)r);
+ v |= (1 << clk->enable_bit);
+ __raw_writel(v, (__force void __iomem *)r);
+}
+
+/* XXX */
+void omap2_clkt_iclk_deny_idle(struct clk *clk)
+{
+ u32 v, r;
+
+ r = ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN));
+
+ v = __raw_readl((__force void __iomem *)r);
+ v &= ~(1 << clk->enable_bit);
+ __raw_writel(v, (__force void __iomem *)r);
+}
+
+/* Public data */
+
+const struct clkops clkops_omap2_iclk_dflt_wait = {
+ .enable = omap2_dflt_clk_enable,
+ .disable = omap2_dflt_clk_disable,
+ .find_companion = omap2_clk_dflt_find_companion,
+ .find_idlest = omap2_clk_dflt_find_idlest,
+ .allow_idle = omap2_clkt_iclk_allow_idle,
+ .deny_idle = omap2_clkt_iclk_deny_idle,
+};
+
+const struct clkops clkops_omap2_iclk_dflt = {
+ .enable = omap2_dflt_clk_enable,
+ .disable = omap2_dflt_clk_disable,
+ .allow_idle = omap2_clkt_iclk_allow_idle,
+ .deny_idle = omap2_clkt_iclk_deny_idle,
+};
+
+const struct clkops clkops_omap2_iclk_idle_only = {
+ .allow_idle = omap2_clkt_iclk_allow_idle,
+ .deny_idle = omap2_clkt_iclk_deny_idle,
+};
+
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 9972d89..5008f14 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -2,7 +2,7 @@
* linux/arch/arm/mach-omap2/clock.h
*
* Copyright (C) 2005-2009 Texas Instruments, Inc.
- * Copyright (C) 2004-2009 Nokia Corporation
+ * Copyright (C) 2004-2011 Nokia Corporation
*
* Contacts:
* Richard Woodruff <r-woodruff2@ti.com>
@@ -86,6 +86,10 @@ long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent);
+/* clkt_iclk.c public functions */
+extern void omap2_clkt_iclk_allow_idle(struct clk *clk);
+extern void omap2_clkt_iclk_deny_idle(struct clk *clk);
+
u32 omap2_get_dpll_rate(struct clk *clk);
void omap2_init_dpll_parent(struct clk *clk);
@@ -148,6 +152,9 @@ extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table)
#define omap2_clk_exit_cpufreq_table 0
#endif
+extern const struct clkops clkops_omap2_iclk_dflt_wait;
+extern const struct clkops clkops_omap2_iclk_dflt;
+extern const struct clkops clkops_omap2_iclk_idle_only;
extern const struct clkops clkops_omap2xxx_dpll_ops;
extern const struct clkops clkops_omap3_noncore_dpll_ops;
extern const struct clkops clkops_omap3_core_dpll_ops;
^ permalink raw reply related
* [PATCH 06/11] OMAP2420: clock: add sdrc_ick
From: Paul Walmsley @ 2011-02-16 6:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110216065030.22089.61217.stgit@twilight.localdomain>
Add sdrc_ick to the OMAP2420 clock data so the clock code can control
the CM_AUTOIDLE bit associated with this clock.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/clock2420_data.c | 16 ++++++++++++++++
arch/arm/mach-omap2/cm-regbits-24xx.h | 1 +
2 files changed, 17 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
index 30fbcbd..63ed481 100644
--- a/arch/arm/mach-omap2/clock2420_data.c
+++ b/arch/arm/mach-omap2/clock2420_data.c
@@ -1608,6 +1608,21 @@ static struct clk sdma_ick = {
.recalc = &followparent_recalc,
};
+/*
+ * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
+ * accesses derived from this data.
+ */
+static struct clk sdrc_ick = {
+ .name = "sdrc_ick",
+ .ops = &clkops_omap2_iclk_idle_only,
+ .parent = &core_l3_ck,
+ .flags = ENABLE_ON_INIT,
+ .clkdm_name = "core_l3_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+ .enable_bit = OMAP24XX_AUTO_SDRC_SHIFT,
+ .recalc = &followparent_recalc,
+};
+
static struct clk vlynq_ick = {
.name = "vlynq_ick",
.ops = &clkops_omap2_dflt_wait,
@@ -1869,6 +1884,7 @@ static struct omap_clk omap2420_clks[] = {
CLK(NULL, "gpmc_fck", &gpmc_fck, CK_242X),
CLK(NULL, "sdma_fck", &sdma_fck, CK_242X),
CLK(NULL, "sdma_ick", &sdma_ick, CK_242X),
+ CLK(NULL, "sdrc_ick", &sdrc_ick, CK_242X),
CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X),
CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X),
CLK(NULL, "des_ick", &des_ick, CK_242X),
diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h
index d70660e..409c813 100644
--- a/arch/arm/mach-omap2/cm-regbits-24xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-24xx.h
@@ -210,6 +210,7 @@
#define OMAP24XX_AUTO_USB_MASK (1 << 0)
/* CM_AUTOIDLE3_CORE */
+#define OMAP24XX_AUTO_SDRC_SHIFT 2
#define OMAP24XX_AUTO_SDRC_MASK (1 << 2)
#define OMAP24XX_AUTO_GPMC_MASK (1 << 1)
#define OMAP24XX_AUTO_SDMA_MASK (1 << 0)
^ permalink raw reply related
* [PATCH 07/11] OMAP2420: clock: use autoidle clkops for all autoidle-controllable interface clocks
From: Paul Walmsley @ 2011-02-16 6:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110216065030.22089.61217.stgit@twilight.localdomain>
Mark each interface clock with a corresponding CM_AUTOIDLE bit with
a clkops that has the allow_idle/deny_idle function pointers populated.
This allows the OMAP clock framework to enable and disable autoidle for
these clocks.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/clock2420_data.c | 109 ++++++++++++++++++---------------
arch/arm/mach-omap2/cm-regbits-24xx.h | 2 +
2 files changed, 63 insertions(+), 48 deletions(-)
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
index 63ed481..68c0369 100644
--- a/arch/arm/mach-omap2/clock2420_data.c
+++ b/arch/arm/mach-omap2/clock2420_data.c
@@ -2,7 +2,7 @@
* linux/arch/arm/mach-omap2/clock2420_data.c
*
* Copyright (C) 2005-2009 Texas Instruments, Inc.
- * Copyright (C) 2004-2010 Nokia Corporation
+ * Copyright (C) 2004-2011 Nokia Corporation
*
* Contacts:
* Richard Woodruff <r-woodruff2@ti.com>
@@ -481,7 +481,7 @@ static struct clk dsp_irate_ick = {
/* 2420 only */
static struct clk dsp_ick = {
.name = "dsp_ick", /* apparently ipi and isp */
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &dsp_irate_ick,
.enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
.enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */
@@ -579,7 +579,7 @@ static const struct clksel usb_l4_ick_clksel[] = {
/* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
static struct clk usb_l4_ick = { /* FS-USB interface clock */
.name = "usb_l4_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l3_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -661,7 +661,7 @@ static struct clk ssi_ssr_sst_fck = {
*/
static struct clk ssi_l4_ick = {
.name = "ssi_l4_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -716,6 +716,7 @@ static struct clk gfx_2d_fck = {
.recalc = &omap2_clksel_recalc,
};
+/* This interface clock does not have a CM_AUTOIDLE bit */
static struct clk gfx_ick = {
.name = "gfx_ick", /* From l3 */
.ops = &clkops_omap2_dflt_wait,
@@ -763,7 +764,7 @@ static const struct clksel dss1_fck_clksel[] = {
static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
.name = "dss_ick",
- .ops = &clkops_omap2_dflt,
+ .ops = &clkops_omap2_iclk_dflt,
.parent = &l4_ck, /* really both l3 and l4 */
.clkdm_name = "dss_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -845,7 +846,7 @@ static const struct clksel omap24xx_gpt_clksel[] = {
static struct clk gpt1_ick = {
.name = "gpt1_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
@@ -871,7 +872,7 @@ static struct clk gpt1_fck = {
static struct clk gpt2_ick = {
.name = "gpt2_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -895,7 +896,7 @@ static struct clk gpt2_fck = {
static struct clk gpt3_ick = {
.name = "gpt3_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -919,7 +920,7 @@ static struct clk gpt3_fck = {
static struct clk gpt4_ick = {
.name = "gpt4_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -943,7 +944,7 @@ static struct clk gpt4_fck = {
static struct clk gpt5_ick = {
.name = "gpt5_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -967,7 +968,7 @@ static struct clk gpt5_fck = {
static struct clk gpt6_ick = {
.name = "gpt6_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -991,7 +992,7 @@ static struct clk gpt6_fck = {
static struct clk gpt7_ick = {
.name = "gpt7_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP24XX_EN_GPT7_SHIFT,
@@ -1014,7 +1015,7 @@ static struct clk gpt7_fck = {
static struct clk gpt8_ick = {
.name = "gpt8_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1038,7 +1039,7 @@ static struct clk gpt8_fck = {
static struct clk gpt9_ick = {
.name = "gpt9_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1062,7 +1063,7 @@ static struct clk gpt9_fck = {
static struct clk gpt10_ick = {
.name = "gpt10_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1086,7 +1087,7 @@ static struct clk gpt10_fck = {
static struct clk gpt11_ick = {
.name = "gpt11_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1110,7 +1111,7 @@ static struct clk gpt11_fck = {
static struct clk gpt12_ick = {
.name = "gpt12_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1134,7 +1135,7 @@ static struct clk gpt12_fck = {
static struct clk mcbsp1_ick = {
.name = "mcbsp1_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1174,7 +1175,7 @@ static struct clk mcbsp1_fck = {
static struct clk mcbsp2_ick = {
.name = "mcbsp2_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1198,7 +1199,7 @@ static struct clk mcbsp2_fck = {
static struct clk mcspi1_ick = {
.name = "mcspi1_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1218,7 +1219,7 @@ static struct clk mcspi1_fck = {
static struct clk mcspi2_ick = {
.name = "mcspi2_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1238,7 +1239,7 @@ static struct clk mcspi2_fck = {
static struct clk uart1_ick = {
.name = "uart1_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1258,7 +1259,7 @@ static struct clk uart1_fck = {
static struct clk uart2_ick = {
.name = "uart2_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1278,7 +1279,7 @@ static struct clk uart2_fck = {
static struct clk uart3_ick = {
.name = "uart3_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1298,7 +1299,7 @@ static struct clk uart3_fck = {
static struct clk gpios_ick = {
.name = "gpios_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
@@ -1318,7 +1319,7 @@ static struct clk gpios_fck = {
static struct clk mpu_wdt_ick = {
.name = "mpu_wdt_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
@@ -1338,7 +1339,7 @@ static struct clk mpu_wdt_fck = {
static struct clk sync_32k_ick = {
.name = "sync_32k_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.flags = ENABLE_ON_INIT,
.clkdm_name = "core_l4_clkdm",
@@ -1349,7 +1350,7 @@ static struct clk sync_32k_ick = {
static struct clk wdt1_ick = {
.name = "wdt1_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
@@ -1359,7 +1360,7 @@ static struct clk wdt1_ick = {
static struct clk omapctrl_ick = {
.name = "omapctrl_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.flags = ENABLE_ON_INIT,
.clkdm_name = "core_l4_clkdm",
@@ -1370,7 +1371,7 @@ static struct clk omapctrl_ick = {
static struct clk cam_ick = {
.name = "cam_ick",
- .ops = &clkops_omap2_dflt,
+ .ops = &clkops_omap2_iclk_dflt,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1395,7 +1396,7 @@ static struct clk cam_fck = {
static struct clk mailboxes_ick = {
.name = "mailboxes_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1405,7 +1406,7 @@ static struct clk mailboxes_ick = {
static struct clk wdt4_ick = {
.name = "wdt4_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1425,7 +1426,7 @@ static struct clk wdt4_fck = {
static struct clk wdt3_ick = {
.name = "wdt3_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1445,7 +1446,7 @@ static struct clk wdt3_fck = {
static struct clk mspro_ick = {
.name = "mspro_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1465,7 +1466,7 @@ static struct clk mspro_fck = {
static struct clk mmc_ick = {
.name = "mmc_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1485,7 +1486,7 @@ static struct clk mmc_fck = {
static struct clk fac_ick = {
.name = "fac_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1505,7 +1506,7 @@ static struct clk fac_fck = {
static struct clk eac_ick = {
.name = "eac_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1525,7 +1526,7 @@ static struct clk eac_fck = {
static struct clk hdq_ick = {
.name = "hdq_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1545,7 +1546,7 @@ static struct clk hdq_fck = {
static struct clk i2c2_ick = {
.name = "i2c2_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1565,7 +1566,7 @@ static struct clk i2c2_fck = {
static struct clk i2c1_ick = {
.name = "i2c1_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1583,12 +1584,18 @@ static struct clk i2c1_fck = {
.recalc = &followparent_recalc,
};
+/*
+ * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
+ * accesses derived from this data.
+ */
static struct clk gpmc_fck = {
.name = "gpmc_fck",
- .ops = &clkops_null, /* RMK: missing? */
+ .ops = &clkops_omap2_iclk_idle_only,
.parent = &core_l3_ck,
.flags = ENABLE_ON_INIT,
.clkdm_name = "core_l3_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+ .enable_bit = OMAP24XX_AUTO_GPMC_SHIFT,
.recalc = &followparent_recalc,
};
@@ -1600,11 +1607,17 @@ static struct clk sdma_fck = {
.recalc = &followparent_recalc,
};
+/*
+ * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
+ * accesses derived from this data.
+ */
static struct clk sdma_ick = {
.name = "sdma_ick",
- .ops = &clkops_null, /* RMK: missing? */
+ .ops = &clkops_omap2_iclk_idle_only,
.parent = &l4_ck,
.clkdm_name = "core_l3_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+ .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT,
.recalc = &followparent_recalc,
};
@@ -1625,7 +1638,7 @@ static struct clk sdrc_ick = {
static struct clk vlynq_ick = {
.name = "vlynq_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l3_ck,
.clkdm_name = "core_l3_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1674,7 +1687,7 @@ static struct clk vlynq_fck = {
static struct clk des_ick = {
.name = "des_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@@ -1684,7 +1697,7 @@ static struct clk des_ick = {
static struct clk sha_ick = {
.name = "sha_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@@ -1694,7 +1707,7 @@ static struct clk sha_ick = {
static struct clk rng_ick = {
.name = "rng_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@@ -1704,7 +1717,7 @@ static struct clk rng_ick = {
static struct clk aes_ick = {
.name = "aes_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@@ -1714,7 +1727,7 @@ static struct clk aes_ick = {
static struct clk pka_ick = {
.name = "pka_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h
index 409c813..6862904 100644
--- a/arch/arm/mach-omap2/cm-regbits-24xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-24xx.h
@@ -212,7 +212,9 @@
/* CM_AUTOIDLE3_CORE */
#define OMAP24XX_AUTO_SDRC_SHIFT 2
#define OMAP24XX_AUTO_SDRC_MASK (1 << 2)
+#define OMAP24XX_AUTO_GPMC_SHIFT 1
#define OMAP24XX_AUTO_GPMC_MASK (1 << 1)
+#define OMAP24XX_AUTO_SDMA_SHIFT 0
#define OMAP24XX_AUTO_SDMA_MASK (1 << 0)
/* CM_AUTOIDLE4_CORE */
^ permalink raw reply related
* [PATCH 08/11] OMAP2430/3xxx: clock: add modem clock autoidle support
From: Paul Walmsley @ 2011-02-16 6:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110216065030.22089.61217.stgit@twilight.localdomain>
OMAP2430 and OMAP3xxx have modem autoidle bits that are actually
attached to clocks with CM_FCLKEN bits; add the code and data to
handle these.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/clkt_iclk.c | 9 +++++++++
arch/arm/mach-omap2/clock.h | 1 +
2 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/clkt_iclk.c b/arch/arm/mach-omap2/clkt_iclk.c
index dd8a6d3..3d43fba 100644
--- a/arch/arm/mach-omap2/clkt_iclk.c
+++ b/arch/arm/mach-omap2/clkt_iclk.c
@@ -71,3 +71,12 @@ const struct clkops clkops_omap2_iclk_idle_only = {
.deny_idle = omap2_clkt_iclk_deny_idle,
};
+const struct clkops clkops_omap2_mdmclk_dflt_wait = {
+ .enable = omap2_dflt_clk_enable,
+ .disable = omap2_dflt_clk_disable,
+ .find_companion = omap2_clk_dflt_find_companion,
+ .find_idlest = omap2_clk_dflt_find_idlest,
+ .allow_idle = omap2_clkt_iclk_allow_idle,
+ .deny_idle = omap2_clkt_iclk_deny_idle,
+};
+
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 5008f14..70f8b07 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -155,6 +155,7 @@ extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table)
extern const struct clkops clkops_omap2_iclk_dflt_wait;
extern const struct clkops clkops_omap2_iclk_dflt;
extern const struct clkops clkops_omap2_iclk_idle_only;
+extern const struct clkops clkops_omap2_mdmclk_dflt_wait;
extern const struct clkops clkops_omap2xxx_dpll_ops;
extern const struct clkops clkops_omap3_noncore_dpll_ops;
extern const struct clkops clkops_omap3_core_dpll_ops;
^ permalink raw reply related
* [PATCH 09/11] OMAP2430: clock: use autoidle clkops for all autoidle-controllable interface clocks
From: Paul Walmsley @ 2011-02-16 6:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110216065030.22089.61217.stgit@twilight.localdomain>
Mark each interface clock with a corresponding CM_AUTOIDLE bit with
a clkops that has the allow_idle/deny_idle function pointers populated.
This allows the OMAP clock framework to enable and disable autoidle for
these clocks.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/clock2430_data.c | 125 +++++++++++++++++++---------------
1 files changed, 69 insertions(+), 56 deletions(-)
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
index 1ff150a..34daed9 100644
--- a/arch/arm/mach-omap2/clock2430_data.c
+++ b/arch/arm/mach-omap2/clock2430_data.c
@@ -2,7 +2,7 @@
* linux/arch/arm/mach-omap2/clock2430_data.c
*
* Copyright (C) 2005-2009 Texas Instruments, Inc.
- * Copyright (C) 2004-2010 Nokia Corporation
+ * Copyright (C) 2004-2011 Nokia Corporation
*
* Contacts:
* Richard Woodruff <r-woodruff2@ti.com>
@@ -525,7 +525,7 @@ static const struct clksel usb_l4_ick_clksel[] = {
/* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
static struct clk usb_l4_ick = { /* FS-USB interface clock */
.name = "usb_l4_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l3_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -606,7 +606,7 @@ static struct clk ssi_ssr_sst_fck = {
*/
static struct clk ssi_l4_ick = {
.name = "ssi_l4_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -661,6 +661,7 @@ static struct clk gfx_2d_fck = {
.recalc = &omap2_clksel_recalc,
};
+/* This interface clock does not have a CM_AUTOIDLE bit */
static struct clk gfx_ick = {
.name = "gfx_ick", /* From l3 */
.ops = &clkops_omap2_dflt_wait,
@@ -693,7 +694,7 @@ static const struct clksel mdm_ick_clksel[] = {
static struct clk mdm_ick = { /* used both as a ick and fck */
.name = "mdm_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_ck,
.clkdm_name = "mdm_clkdm",
.enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
@@ -706,7 +707,7 @@ static struct clk mdm_ick = { /* used both as a ick and fck */
static struct clk mdm_osc_ck = {
.name = "mdm_osc_ck",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_mdmclk_dflt_wait,
.parent = &osc_ck,
.clkdm_name = "mdm_clkdm",
.enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
@@ -751,7 +752,7 @@ static const struct clksel dss1_fck_clksel[] = {
static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
.name = "dss_ick",
- .ops = &clkops_omap2_dflt,
+ .ops = &clkops_omap2_iclk_dflt,
.parent = &l4_ck, /* really both l3 and l4 */
.clkdm_name = "dss_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -833,7 +834,7 @@ static const struct clksel omap24xx_gpt_clksel[] = {
static struct clk gpt1_ick = {
.name = "gpt1_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
@@ -859,7 +860,7 @@ static struct clk gpt1_fck = {
static struct clk gpt2_ick = {
.name = "gpt2_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -883,7 +884,7 @@ static struct clk gpt2_fck = {
static struct clk gpt3_ick = {
.name = "gpt3_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -907,7 +908,7 @@ static struct clk gpt3_fck = {
static struct clk gpt4_ick = {
.name = "gpt4_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -931,7 +932,7 @@ static struct clk gpt4_fck = {
static struct clk gpt5_ick = {
.name = "gpt5_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -955,7 +956,7 @@ static struct clk gpt5_fck = {
static struct clk gpt6_ick = {
.name = "gpt6_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -979,7 +980,7 @@ static struct clk gpt6_fck = {
static struct clk gpt7_ick = {
.name = "gpt7_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP24XX_EN_GPT7_SHIFT,
@@ -1002,7 +1003,7 @@ static struct clk gpt7_fck = {
static struct clk gpt8_ick = {
.name = "gpt8_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1026,7 +1027,7 @@ static struct clk gpt8_fck = {
static struct clk gpt9_ick = {
.name = "gpt9_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1050,7 +1051,7 @@ static struct clk gpt9_fck = {
static struct clk gpt10_ick = {
.name = "gpt10_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1074,7 +1075,7 @@ static struct clk gpt10_fck = {
static struct clk gpt11_ick = {
.name = "gpt11_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1098,7 +1099,7 @@ static struct clk gpt11_fck = {
static struct clk gpt12_ick = {
.name = "gpt12_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1122,7 +1123,7 @@ static struct clk gpt12_fck = {
static struct clk mcbsp1_ick = {
.name = "mcbsp1_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1162,7 +1163,7 @@ static struct clk mcbsp1_fck = {
static struct clk mcbsp2_ick = {
.name = "mcbsp2_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1186,7 +1187,7 @@ static struct clk mcbsp2_fck = {
static struct clk mcbsp3_ick = {
.name = "mcbsp3_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1210,7 +1211,7 @@ static struct clk mcbsp3_fck = {
static struct clk mcbsp4_ick = {
.name = "mcbsp4_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1234,7 +1235,7 @@ static struct clk mcbsp4_fck = {
static struct clk mcbsp5_ick = {
.name = "mcbsp5_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1258,7 +1259,7 @@ static struct clk mcbsp5_fck = {
static struct clk mcspi1_ick = {
.name = "mcspi1_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1278,7 +1279,7 @@ static struct clk mcspi1_fck = {
static struct clk mcspi2_ick = {
.name = "mcspi2_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1298,7 +1299,7 @@ static struct clk mcspi2_fck = {
static struct clk mcspi3_ick = {
.name = "mcspi3_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1318,7 +1319,7 @@ static struct clk mcspi3_fck = {
static struct clk uart1_ick = {
.name = "uart1_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1338,7 +1339,7 @@ static struct clk uart1_fck = {
static struct clk uart2_ick = {
.name = "uart2_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1358,7 +1359,7 @@ static struct clk uart2_fck = {
static struct clk uart3_ick = {
.name = "uart3_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1378,7 +1379,7 @@ static struct clk uart3_fck = {
static struct clk gpios_ick = {
.name = "gpios_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
@@ -1398,7 +1399,7 @@ static struct clk gpios_fck = {
static struct clk mpu_wdt_ick = {
.name = "mpu_wdt_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
@@ -1418,7 +1419,7 @@ static struct clk mpu_wdt_fck = {
static struct clk sync_32k_ick = {
.name = "sync_32k_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.flags = ENABLE_ON_INIT,
.clkdm_name = "core_l4_clkdm",
@@ -1429,7 +1430,7 @@ static struct clk sync_32k_ick = {
static struct clk wdt1_ick = {
.name = "wdt1_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
@@ -1439,7 +1440,7 @@ static struct clk wdt1_ick = {
static struct clk omapctrl_ick = {
.name = "omapctrl_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.flags = ENABLE_ON_INIT,
.clkdm_name = "core_l4_clkdm",
@@ -1450,7 +1451,7 @@ static struct clk omapctrl_ick = {
static struct clk icr_ick = {
.name = "icr_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
@@ -1460,7 +1461,7 @@ static struct clk icr_ick = {
static struct clk cam_ick = {
.name = "cam_ick",
- .ops = &clkops_omap2_dflt,
+ .ops = &clkops_omap2_iclk_dflt,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1485,7 +1486,7 @@ static struct clk cam_fck = {
static struct clk mailboxes_ick = {
.name = "mailboxes_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1495,7 +1496,7 @@ static struct clk mailboxes_ick = {
static struct clk wdt4_ick = {
.name = "wdt4_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1515,7 +1516,7 @@ static struct clk wdt4_fck = {
static struct clk mspro_ick = {
.name = "mspro_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1535,7 +1536,7 @@ static struct clk mspro_fck = {
static struct clk fac_ick = {
.name = "fac_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1555,7 +1556,7 @@ static struct clk fac_fck = {
static struct clk hdq_ick = {
.name = "hdq_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1579,7 +1580,7 @@ static struct clk hdq_fck = {
*/
static struct clk i2c2_ick = {
.name = "i2c2_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1603,7 +1604,7 @@ static struct clk i2chs2_fck = {
*/
static struct clk i2c1_ick = {
.name = "i2c1_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1621,12 +1622,18 @@ static struct clk i2chs1_fck = {
.recalc = &followparent_recalc,
};
+/*
+ * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
+ * accesses derived from this data.
+ */
static struct clk gpmc_fck = {
.name = "gpmc_fck",
- .ops = &clkops_null, /* RMK: missing? */
+ .ops = &clkops_omap2_iclk_idle_only,
.parent = &core_l3_ck,
.flags = ENABLE_ON_INIT,
.clkdm_name = "core_l3_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+ .enable_bit = OMAP24XX_AUTO_GPMC_SHIFT,
.recalc = &followparent_recalc,
};
@@ -1638,17 +1645,23 @@ static struct clk sdma_fck = {
.recalc = &followparent_recalc,
};
+/*
+ * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
+ * accesses derived from this data.
+ */
static struct clk sdma_ick = {
.name = "sdma_ick",
- .ops = &clkops_null, /* RMK: missing? */
+ .ops = &clkops_omap2_iclk_idle_only,
.parent = &l4_ck,
.clkdm_name = "core_l3_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+ .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT,
.recalc = &followparent_recalc,
};
static struct clk sdrc_ick = {
.name = "sdrc_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_idle_only,
.parent = &l4_ck,
.flags = ENABLE_ON_INIT,
.clkdm_name = "core_l4_clkdm",
@@ -1659,7 +1672,7 @@ static struct clk sdrc_ick = {
static struct clk des_ick = {
.name = "des_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@@ -1669,7 +1682,7 @@ static struct clk des_ick = {
static struct clk sha_ick = {
.name = "sha_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@@ -1679,7 +1692,7 @@ static struct clk sha_ick = {
static struct clk rng_ick = {
.name = "rng_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@@ -1689,7 +1702,7 @@ static struct clk rng_ick = {
static struct clk aes_ick = {
.name = "aes_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@@ -1699,7 +1712,7 @@ static struct clk aes_ick = {
static struct clk pka_ick = {
.name = "pka_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@@ -1719,7 +1732,7 @@ static struct clk usb_fck = {
static struct clk usbhs_ick = {
.name = "usbhs_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l3_ck,
.clkdm_name = "core_l3_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1729,7 +1742,7 @@ static struct clk usbhs_ick = {
static struct clk mmchs1_ick = {
.name = "mmchs1_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1749,7 +1762,7 @@ static struct clk mmchs1_fck = {
static struct clk mmchs2_ick = {
.name = "mmchs2_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1768,7 +1781,7 @@ static struct clk mmchs2_fck = {
static struct clk gpio5_ick = {
.name = "gpio5_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1788,7 +1801,7 @@ static struct clk gpio5_fck = {
static struct clk mdm_intc_ick = {
.name = "mdm_intc_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
^ permalink raw reply related
* [PATCH 10/11] OMAP3: clock: use autoidle clkops for all autoidle-controllable interface clocks
From: Paul Walmsley @ 2011-02-16 6:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110216065030.22089.61217.stgit@twilight.localdomain>
Mark each interface clock with a corresponding CM_AUTOIDLE bit with
a clkops that has the allow_idle/deny_idle function pointers populated.
This allows the OMAP clock framework to enable and disable autoidle for
these clocks.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/clock34xx.c | 29 ++++++-
arch/arm/mach-omap2/clock34xx.h | 5 +
arch/arm/mach-omap2/clock3517.c | 4 +
arch/arm/mach-omap2/clock3xxx_data.c | 149 ++++++++++++++++++----------------
4 files changed, 112 insertions(+), 75 deletions(-)
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 287abc4..1fc96b9 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -2,7 +2,7 @@
* OMAP3-specific clock framework functions
*
* Copyright (C) 2007-2008 Texas Instruments, Inc.
- * Copyright (C) 2007-2010 Nokia Corporation
+ * Copyright (C) 2007-2011 Nokia Corporation
*
* Paul Walmsley
* Jouni H?gander
@@ -59,6 +59,15 @@ const struct clkops clkops_omap3430es2_ssi_wait = {
.find_companion = omap2_clk_dflt_find_companion,
};
+const struct clkops clkops_omap3430es2_iclk_ssi_wait = {
+ .enable = omap2_dflt_clk_enable,
+ .disable = omap2_dflt_clk_disable,
+ .find_idlest = omap3430es2_clk_ssi_find_idlest,
+ .find_companion = omap2_clk_dflt_find_companion,
+ .allow_idle = omap2_clkt_iclk_allow_idle,
+ .deny_idle = omap2_clkt_iclk_deny_idle,
+};
+
/**
* omap3430es2_clk_dss_usbhost_find_idlest - CM_IDLEST info for DSS, USBHOST
* @clk: struct clk * being enabled
@@ -94,6 +103,15 @@ const struct clkops clkops_omap3430es2_dss_usbhost_wait = {
.find_companion = omap2_clk_dflt_find_companion,
};
+const struct clkops clkops_omap3430es2_iclk_dss_usbhost_wait = {
+ .enable = omap2_dflt_clk_enable,
+ .disable = omap2_dflt_clk_disable,
+ .find_idlest = omap3430es2_clk_dss_usbhost_find_idlest,
+ .find_companion = omap2_clk_dflt_find_companion,
+ .allow_idle = omap2_clkt_iclk_allow_idle,
+ .deny_idle = omap2_clkt_iclk_deny_idle,
+};
+
/**
* omap3430es2_clk_hsotgusb_find_idlest - return CM_IDLEST info for HSOTGUSB
* @clk: struct clk * being enabled
@@ -124,3 +142,12 @@ const struct clkops clkops_omap3430es2_hsotgusb_wait = {
.find_idlest = omap3430es2_clk_hsotgusb_find_idlest,
.find_companion = omap2_clk_dflt_find_companion,
};
+
+const struct clkops clkops_omap3430es2_iclk_hsotgusb_wait = {
+ .enable = omap2_dflt_clk_enable,
+ .disable = omap2_dflt_clk_disable,
+ .find_idlest = omap3430es2_clk_hsotgusb_find_idlest,
+ .find_companion = omap2_clk_dflt_find_companion,
+ .allow_idle = omap2_clkt_iclk_allow_idle,
+ .deny_idle = omap2_clkt_iclk_deny_idle,
+};
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 628e8de..084ba71 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -2,14 +2,17 @@
* OMAP34xx clock function prototypes and macros
*
* Copyright (C) 2007-2010 Texas Instruments, Inc.
- * Copyright (C) 2007-2010 Nokia Corporation
+ * Copyright (C) 2007-2011 Nokia Corporation
*/
#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
#define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
extern const struct clkops clkops_omap3430es2_ssi_wait;
+extern const struct clkops clkops_omap3430es2_iclk_ssi_wait;
extern const struct clkops clkops_omap3430es2_hsotgusb_wait;
+extern const struct clkops clkops_omap3430es2_iclk_hsotgusb_wait;
extern const struct clkops clkops_omap3430es2_dss_usbhost_wait;
+extern const struct clkops clkops_omap3430es2_iclk_dss_usbhost_wait;
#endif
diff --git a/arch/arm/mach-omap2/clock3517.c b/arch/arm/mach-omap2/clock3517.c
index 74116a3..2e97d08 100644
--- a/arch/arm/mach-omap2/clock3517.c
+++ b/arch/arm/mach-omap2/clock3517.c
@@ -2,7 +2,7 @@
* OMAP3517/3505-specific clock framework functions
*
* Copyright (C) 2010 Texas Instruments, Inc.
- * Copyright (C) 2010 Nokia Corporation
+ * Copyright (C) 2011 Nokia Corporation
*
* Ranjith Lohithakshan
* Paul Walmsley
@@ -119,6 +119,8 @@ const struct clkops clkops_am35xx_ipss_wait = {
.disable = omap2_dflt_clk_disable,
.find_idlest = am35xx_clk_ipss_find_idlest,
.find_companion = omap2_clk_dflt_find_companion,
+ .allow_idle = omap2_clkt_iclk_allow_idle,
+ .deny_idle = omap2_clkt_iclk_deny_idle,
};
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 0021559..58db368 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -2,7 +2,7 @@
* OMAP3 clock data
*
* Copyright (C) 2007-2010 Texas Instruments, Inc.
- * Copyright (C) 2007-2010 Nokia Corporation
+ * Copyright (C) 2007-2011 Nokia Corporation
*
* Written by Paul Walmsley
* With many device clock fixes by Kevin Hilman and Jouni H?gander
@@ -1205,7 +1205,10 @@ static const struct clksel gfx_l3_clksel[] = {
{ .parent = NULL }
};
-/* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
+/*
+ * Virtual parent clock for gfx_l3_ick and gfx_l3_fck
+ * This interface clock does not have a CM_AUTOIDLE bit
+ */
static struct clk gfx_l3_ck = {
.name = "gfx_l3_ck",
.ops = &clkops_omap2_dflt_wait,
@@ -1304,6 +1307,7 @@ static struct clk sgx_fck = {
.round_rate = &omap2_clksel_round_rate
};
+/* This interface clock does not have a CM_AUTOIDLE bit */
static struct clk sgx_ick = {
.name = "sgx_ick",
.ops = &clkops_omap2_dflt_wait,
@@ -1328,7 +1332,7 @@ static struct clk d2d_26m_fck = {
static struct clk modem_fck = {
.name = "modem_fck",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_mdmclk_dflt_wait,
.parent = &sys_ck,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_MODEM_SHIFT,
@@ -1338,7 +1342,7 @@ static struct clk modem_fck = {
static struct clk sad2d_ick = {
.name = "sad2d_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l3_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_SAD2D_SHIFT,
@@ -1348,7 +1352,7 @@ static struct clk sad2d_ick = {
static struct clk mad2d_ick = {
.name = "mad2d_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l3_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
.enable_bit = OMAP3430_EN_MAD2D_SHIFT,
@@ -1718,7 +1722,7 @@ static struct clk core_l3_ick = {
static struct clk hsotgusb_ick_3430es1 = {
.name = "hsotgusb_ick",
- .ops = &clkops_omap2_dflt,
+ .ops = &clkops_omap2_iclk_dflt,
.parent = &core_l3_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
@@ -1728,7 +1732,7 @@ static struct clk hsotgusb_ick_3430es1 = {
static struct clk hsotgusb_ick_3430es2 = {
.name = "hsotgusb_ick",
- .ops = &clkops_omap3430es2_hsotgusb_wait,
+ .ops = &clkops_omap3430es2_iclk_hsotgusb_wait,
.parent = &core_l3_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
@@ -1736,6 +1740,7 @@ static struct clk hsotgusb_ick_3430es2 = {
.recalc = &followparent_recalc,
};
+/* This interface clock does not have a CM_AUTOIDLE bit */
static struct clk sdrc_ick = {
.name = "sdrc_ick",
.ops = &clkops_omap2_dflt_wait,
@@ -1767,7 +1772,7 @@ static struct clk security_l3_ick = {
static struct clk pka_ick = {
.name = "pka_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &security_l3_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
.enable_bit = OMAP3430_EN_PKA_SHIFT,
@@ -1786,7 +1791,7 @@ static struct clk core_l4_ick = {
static struct clk usbtll_ick = {
.name = "usbtll_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
.enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
@@ -1796,7 +1801,7 @@ static struct clk usbtll_ick = {
static struct clk mmchs3_ick = {
.name = "mmchs3_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
@@ -1807,7 +1812,7 @@ static struct clk mmchs3_ick = {
/* Intersystem Communication Registers - chassis mode only */
static struct clk icr_ick = {
.name = "icr_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_ICR_SHIFT,
@@ -1817,7 +1822,7 @@ static struct clk icr_ick = {
static struct clk aes2_ick = {
.name = "aes2_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_AES2_SHIFT,
@@ -1827,7 +1832,7 @@ static struct clk aes2_ick = {
static struct clk sha12_ick = {
.name = "sha12_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_SHA12_SHIFT,
@@ -1837,7 +1842,7 @@ static struct clk sha12_ick = {
static struct clk des2_ick = {
.name = "des2_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_DES2_SHIFT,
@@ -1847,7 +1852,7 @@ static struct clk des2_ick = {
static struct clk mmchs2_ick = {
.name = "mmchs2_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MMC2_SHIFT,
@@ -1857,7 +1862,7 @@ static struct clk mmchs2_ick = {
static struct clk mmchs1_ick = {
.name = "mmchs1_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MMC1_SHIFT,
@@ -1867,7 +1872,7 @@ static struct clk mmchs1_ick = {
static struct clk mspro_ick = {
.name = "mspro_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MSPRO_SHIFT,
@@ -1877,7 +1882,7 @@ static struct clk mspro_ick = {
static struct clk hdq_ick = {
.name = "hdq_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_HDQ_SHIFT,
@@ -1887,7 +1892,7 @@ static struct clk hdq_ick = {
static struct clk mcspi4_ick = {
.name = "mcspi4_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
@@ -1897,7 +1902,7 @@ static struct clk mcspi4_ick = {
static struct clk mcspi3_ick = {
.name = "mcspi3_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
@@ -1907,7 +1912,7 @@ static struct clk mcspi3_ick = {
static struct clk mcspi2_ick = {
.name = "mcspi2_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
@@ -1917,7 +1922,7 @@ static struct clk mcspi2_ick = {
static struct clk mcspi1_ick = {
.name = "mcspi1_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
@@ -1927,7 +1932,7 @@ static struct clk mcspi1_ick = {
static struct clk i2c3_ick = {
.name = "i2c3_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_I2C3_SHIFT,
@@ -1937,7 +1942,7 @@ static struct clk i2c3_ick = {
static struct clk i2c2_ick = {
.name = "i2c2_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_I2C2_SHIFT,
@@ -1947,7 +1952,7 @@ static struct clk i2c2_ick = {
static struct clk i2c1_ick = {
.name = "i2c1_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_I2C1_SHIFT,
@@ -1957,7 +1962,7 @@ static struct clk i2c1_ick = {
static struct clk uart2_ick = {
.name = "uart2_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_UART2_SHIFT,
@@ -1967,7 +1972,7 @@ static struct clk uart2_ick = {
static struct clk uart1_ick = {
.name = "uart1_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_UART1_SHIFT,
@@ -1977,7 +1982,7 @@ static struct clk uart1_ick = {
static struct clk gpt11_ick = {
.name = "gpt11_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_GPT11_SHIFT,
@@ -1987,7 +1992,7 @@ static struct clk gpt11_ick = {
static struct clk gpt10_ick = {
.name = "gpt10_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_GPT10_SHIFT,
@@ -1997,7 +2002,7 @@ static struct clk gpt10_ick = {
static struct clk mcbsp5_ick = {
.name = "mcbsp5_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
@@ -2007,7 +2012,7 @@ static struct clk mcbsp5_ick = {
static struct clk mcbsp1_ick = {
.name = "mcbsp1_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
@@ -2017,7 +2022,7 @@ static struct clk mcbsp1_ick = {
static struct clk fac_ick = {
.name = "fac_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
@@ -2027,7 +2032,7 @@ static struct clk fac_ick = {
static struct clk mailboxes_ick = {
.name = "mailboxes_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
@@ -2037,7 +2042,7 @@ static struct clk mailboxes_ick = {
static struct clk omapctrl_ick = {
.name = "omapctrl_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
@@ -2057,7 +2062,7 @@ static struct clk ssi_l4_ick = {
static struct clk ssi_ick_3430es1 = {
.name = "ssi_ick",
- .ops = &clkops_omap2_dflt,
+ .ops = &clkops_omap2_iclk_dflt,
.parent = &ssi_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_SSI_SHIFT,
@@ -2067,7 +2072,7 @@ static struct clk ssi_ick_3430es1 = {
static struct clk ssi_ick_3430es2 = {
.name = "ssi_ick",
- .ops = &clkops_omap3430es2_ssi_wait,
+ .ops = &clkops_omap3430es2_iclk_ssi_wait,
.parent = &ssi_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_SSI_SHIFT,
@@ -2085,7 +2090,7 @@ static const struct clksel usb_l4_clksel[] = {
static struct clk usb_l4_ick = {
.name = "usb_l4_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &l4_ick,
.init = &omap2_init_clksel_parent,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -2107,7 +2112,7 @@ static struct clk security_l4_ick2 = {
static struct clk aes1_ick = {
.name = "aes1_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &security_l4_ick2,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
.enable_bit = OMAP3430_EN_AES1_SHIFT,
@@ -2116,7 +2121,7 @@ static struct clk aes1_ick = {
static struct clk rng_ick = {
.name = "rng_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &security_l4_ick2,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
.enable_bit = OMAP3430_EN_RNG_SHIFT,
@@ -2125,7 +2130,7 @@ static struct clk rng_ick = {
static struct clk sha11_ick = {
.name = "sha11_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &security_l4_ick2,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
.enable_bit = OMAP3430_EN_SHA11_SHIFT,
@@ -2134,7 +2139,7 @@ static struct clk sha11_ick = {
static struct clk des1_ick = {
.name = "des1_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &security_l4_ick2,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
.enable_bit = OMAP3430_EN_DES1_SHIFT,
@@ -2195,7 +2200,7 @@ static struct clk dss2_alwon_fck = {
static struct clk dss_ick_3430es1 = {
/* Handles both L3 and L4 clocks */
.name = "dss_ick",
- .ops = &clkops_omap2_dflt,
+ .ops = &clkops_omap2_iclk_dflt,
.parent = &l4_ick,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
@@ -2206,7 +2211,7 @@ static struct clk dss_ick_3430es1 = {
static struct clk dss_ick_3430es2 = {
/* Handles both L3 and L4 clocks */
.name = "dss_ick",
- .ops = &clkops_omap3430es2_dss_usbhost_wait,
+ .ops = &clkops_omap3430es2_iclk_dss_usbhost_wait,
.parent = &l4_ick,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
@@ -2229,7 +2234,7 @@ static struct clk cam_mclk = {
static struct clk cam_ick = {
/* Handles both L3 and L4 clocks */
.name = "cam_ick",
- .ops = &clkops_omap2_dflt,
+ .ops = &clkops_omap2_iclk_dflt,
.parent = &l4_ick,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_CAM_SHIFT,
@@ -2272,7 +2277,7 @@ static struct clk usbhost_48m_fck = {
static struct clk usbhost_ick = {
/* Handles both L3 and L4 clocks */
.name = "usbhost_ick",
- .ops = &clkops_omap3430es2_dss_usbhost_wait,
+ .ops = &clkops_omap3430es2_iclk_dss_usbhost_wait,
.parent = &l4_ick,
.enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
.enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
@@ -2372,7 +2377,7 @@ static struct clk wkup_l4_ick = {
/* Never specifically named in the TRM, so we have to infer a likely name */
static struct clk usim_ick = {
.name = "usim_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &wkup_l4_ick,
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
@@ -2382,7 +2387,7 @@ static struct clk usim_ick = {
static struct clk wdt2_ick = {
.name = "wdt2_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &wkup_l4_ick,
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_WDT2_SHIFT,
@@ -2392,7 +2397,7 @@ static struct clk wdt2_ick = {
static struct clk wdt1_ick = {
.name = "wdt1_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &wkup_l4_ick,
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_WDT1_SHIFT,
@@ -2402,7 +2407,7 @@ static struct clk wdt1_ick = {
static struct clk gpio1_ick = {
.name = "gpio1_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &wkup_l4_ick,
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPIO1_SHIFT,
@@ -2412,7 +2417,7 @@ static struct clk gpio1_ick = {
static struct clk omap_32ksync_ick = {
.name = "omap_32ksync_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &wkup_l4_ick,
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
@@ -2423,7 +2428,7 @@ static struct clk omap_32ksync_ick = {
/* XXX This clock no longer exists in 3430 TRM rev F */
static struct clk gpt12_ick = {
.name = "gpt12_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &wkup_l4_ick,
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT12_SHIFT,
@@ -2433,7 +2438,7 @@ static struct clk gpt12_ick = {
static struct clk gpt1_ick = {
.name = "gpt1_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &wkup_l4_ick,
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT1_SHIFT,
@@ -2663,7 +2668,7 @@ static struct clk per_l4_ick = {
static struct clk gpio6_ick = {
.name = "gpio6_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &per_l4_ick,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPIO6_SHIFT,
@@ -2673,7 +2678,7 @@ static struct clk gpio6_ick = {
static struct clk gpio5_ick = {
.name = "gpio5_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &per_l4_ick,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPIO5_SHIFT,
@@ -2683,7 +2688,7 @@ static struct clk gpio5_ick = {
static struct clk gpio4_ick = {
.name = "gpio4_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &per_l4_ick,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPIO4_SHIFT,
@@ -2693,7 +2698,7 @@ static struct clk gpio4_ick = {
static struct clk gpio3_ick = {
.name = "gpio3_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &per_l4_ick,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPIO3_SHIFT,
@@ -2703,7 +2708,7 @@ static struct clk gpio3_ick = {
static struct clk gpio2_ick = {
.name = "gpio2_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &per_l4_ick,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPIO2_SHIFT,
@@ -2713,7 +2718,7 @@ static struct clk gpio2_ick = {
static struct clk wdt3_ick = {
.name = "wdt3_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &per_l4_ick,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_WDT3_SHIFT,
@@ -2723,7 +2728,7 @@ static struct clk wdt3_ick = {
static struct clk uart3_ick = {
.name = "uart3_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &per_l4_ick,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_UART3_SHIFT,
@@ -2733,7 +2738,7 @@ static struct clk uart3_ick = {
static struct clk uart4_ick = {
.name = "uart4_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &per_l4_ick,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3630_EN_UART4_SHIFT,
@@ -2743,7 +2748,7 @@ static struct clk uart4_ick = {
static struct clk gpt9_ick = {
.name = "gpt9_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &per_l4_ick,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT9_SHIFT,
@@ -2753,7 +2758,7 @@ static struct clk gpt9_ick = {
static struct clk gpt8_ick = {
.name = "gpt8_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &per_l4_ick,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT8_SHIFT,
@@ -2763,7 +2768,7 @@ static struct clk gpt8_ick = {
static struct clk gpt7_ick = {
.name = "gpt7_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &per_l4_ick,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT7_SHIFT,
@@ -2773,7 +2778,7 @@ static struct clk gpt7_ick = {
static struct clk gpt6_ick = {
.name = "gpt6_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &per_l4_ick,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT6_SHIFT,
@@ -2783,7 +2788,7 @@ static struct clk gpt6_ick = {
static struct clk gpt5_ick = {
.name = "gpt5_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &per_l4_ick,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT5_SHIFT,
@@ -2793,7 +2798,7 @@ static struct clk gpt5_ick = {
static struct clk gpt4_ick = {
.name = "gpt4_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &per_l4_ick,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT4_SHIFT,
@@ -2803,7 +2808,7 @@ static struct clk gpt4_ick = {
static struct clk gpt3_ick = {
.name = "gpt3_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &per_l4_ick,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT3_SHIFT,
@@ -2813,7 +2818,7 @@ static struct clk gpt3_ick = {
static struct clk gpt2_ick = {
.name = "gpt2_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &per_l4_ick,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT2_SHIFT,
@@ -2823,7 +2828,7 @@ static struct clk gpt2_ick = {
static struct clk mcbsp2_ick = {
.name = "mcbsp2_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &per_l4_ick,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
@@ -2833,7 +2838,7 @@ static struct clk mcbsp2_ick = {
static struct clk mcbsp3_ick = {
.name = "mcbsp3_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &per_l4_ick,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
@@ -2843,7 +2848,7 @@ static struct clk mcbsp3_ick = {
static struct clk mcbsp4_ick = {
.name = "mcbsp4_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &per_l4_ick,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
@@ -3186,7 +3191,7 @@ static struct clk vpfe_fck = {
*/
static struct clk uart4_ick_am35xx = {
.name = "uart4_ick",
- .ops = &clkops_omap2_dflt_wait,
+ .ops = &clkops_omap2_iclk_dflt_wait,
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = AM35XX_EN_UART4_SHIFT,
^ permalink raw reply related
* [PATCH 11/11] OMAP2/3: PM: remove manual CM_AUTOIDLE bit setting in mach-omap2/pm*xx.c
From: Paul Walmsley @ 2011-02-16 6:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110216065030.22089.61217.stgit@twilight.localdomain>
These CM_AUTOIDLE bits are now set by the clock code via the common PM
code in mach-omap2/pm.c.
N.B.: The pm24xx.c code that this patch removes didn't ensure that the
CM_AUTOIDLE bits were set for several 2430-only modules, such as
GPIO5, MDM_INTC, MMCHS1/2, the modem oscillator clock, and USBHS.
Similarly, the pm34xx.c code that this patch removes didn't ensure
that the CM_AUTOIDLE bits were set for USIM and the AM3517 UART4.
Those cases should now be handled.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@ti.com>
---
arch/arm/mach-omap2/pm24xx.c | 63 ++-----------------------
arch/arm/mach-omap2/pm34xx.c | 105 ------------------------------------------
2 files changed, 5 insertions(+), 163 deletions(-)
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index 15b0f53..a168730 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -379,7 +379,10 @@ static void __init prcm_setup_regs(void)
int i, num_mem_banks;
struct powerdomain *pwrdm;
- /* Enable autoidle */
+ /*
+ * Enable autoidle
+ * XXX This should be handled by hwmod code or PRCM init code
+ */
omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
OMAP2_PRCM_SYSCONFIG_OFFSET);
@@ -418,64 +421,6 @@ static void __init prcm_setup_regs(void)
clkdm_for_each(clkdms_setup, NULL);
clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
- /* Enable clock autoidle for all domains */
- omap2_cm_write_mod_reg(OMAP24XX_AUTO_CAM_MASK |
- OMAP24XX_AUTO_MAILBOXES_MASK |
- OMAP24XX_AUTO_WDT4_MASK |
- OMAP2420_AUTO_WDT3_MASK |
- OMAP24XX_AUTO_MSPRO_MASK |
- OMAP2420_AUTO_MMC_MASK |
- OMAP24XX_AUTO_FAC_MASK |
- OMAP2420_AUTO_EAC_MASK |
- OMAP24XX_AUTO_HDQ_MASK |
- OMAP24XX_AUTO_UART2_MASK |
- OMAP24XX_AUTO_UART1_MASK |
- OMAP24XX_AUTO_I2C2_MASK |
- OMAP24XX_AUTO_I2C1_MASK |
- OMAP24XX_AUTO_MCSPI2_MASK |
- OMAP24XX_AUTO_MCSPI1_MASK |
- OMAP24XX_AUTO_MCBSP2_MASK |
- OMAP24XX_AUTO_MCBSP1_MASK |
- OMAP24XX_AUTO_GPT12_MASK |
- OMAP24XX_AUTO_GPT11_MASK |
- OMAP24XX_AUTO_GPT10_MASK |
- OMAP24XX_AUTO_GPT9_MASK |
- OMAP24XX_AUTO_GPT8_MASK |
- OMAP24XX_AUTO_GPT7_MASK |
- OMAP24XX_AUTO_GPT6_MASK |
- OMAP24XX_AUTO_GPT5_MASK |
- OMAP24XX_AUTO_GPT4_MASK |
- OMAP24XX_AUTO_GPT3_MASK |
- OMAP24XX_AUTO_GPT2_MASK |
- OMAP2420_AUTO_VLYNQ_MASK |
- OMAP24XX_AUTO_DSS_MASK,
- CORE_MOD, CM_AUTOIDLE1);
- omap2_cm_write_mod_reg(OMAP24XX_AUTO_UART3_MASK |
- OMAP24XX_AUTO_SSI_MASK |
- OMAP24XX_AUTO_USB_MASK,
- CORE_MOD, CM_AUTOIDLE2);
- omap2_cm_write_mod_reg(OMAP24XX_AUTO_SDRC_MASK |
- OMAP24XX_AUTO_GPMC_MASK |
- OMAP24XX_AUTO_SDMA_MASK,
- CORE_MOD, CM_AUTOIDLE3);
- omap2_cm_write_mod_reg(OMAP24XX_AUTO_PKA_MASK |
- OMAP24XX_AUTO_AES_MASK |
- OMAP24XX_AUTO_RNG_MASK |
- OMAP24XX_AUTO_SHA_MASK |
- OMAP24XX_AUTO_DES_MASK,
- CORE_MOD, OMAP24XX_CM_AUTOIDLE4);
-
- omap2_cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI_MASK, OMAP24XX_DSP_MOD,
- CM_AUTOIDLE);
-
- omap2_cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL_MASK |
- OMAP24XX_AUTO_WDT1_MASK |
- OMAP24XX_AUTO_MPU_WDT_MASK |
- OMAP24XX_AUTO_GPIOS_MASK |
- OMAP24XX_AUTO_32KSYNC_MASK |
- OMAP24XX_AUTO_GPT1_MASK,
- WKUP_MOD, CM_AUTOIDLE);
-
/* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
* stabilisation */
omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 1fe2e73..76e9f9a 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -688,14 +688,11 @@ static void __init omap3_d2d_idle(void)
static void __init prcm_setup_regs(void)
{
- u32 omap3630_auto_uart4_mask = cpu_is_omap3630() ?
- OMAP3630_AUTO_UART4_MASK : 0;
u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
OMAP3630_EN_UART4_MASK : 0;
u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
OMAP3630_GRPSEL_UART4_MASK : 0;
-
/* XXX Reset all wkdeps. This should be done when initializing
* powerdomains */
omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
@@ -710,107 +707,7 @@ static void __init prcm_setup_regs(void)
} else
omap2_prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
- /*
- * Enable interface clock autoidle for all modules.
- * Note that in the long run this should be done by clockfw
- */
- omap2_cm_write_mod_reg(
- OMAP3430_AUTO_MODEM_MASK |
- OMAP3430ES2_AUTO_MMC3_MASK |
- OMAP3430ES2_AUTO_ICR_MASK |
- OMAP3430_AUTO_AES2_MASK |
- OMAP3430_AUTO_SHA12_MASK |
- OMAP3430_AUTO_DES2_MASK |
- OMAP3430_AUTO_MMC2_MASK |
- OMAP3430_AUTO_MMC1_MASK |
- OMAP3430_AUTO_MSPRO_MASK |
- OMAP3430_AUTO_HDQ_MASK |
- OMAP3430_AUTO_MCSPI4_MASK |
- OMAP3430_AUTO_MCSPI3_MASK |
- OMAP3430_AUTO_MCSPI2_MASK |
- OMAP3430_AUTO_MCSPI1_MASK |
- OMAP3430_AUTO_I2C3_MASK |
- OMAP3430_AUTO_I2C2_MASK |
- OMAP3430_AUTO_I2C1_MASK |
- OMAP3430_AUTO_UART2_MASK |
- OMAP3430_AUTO_UART1_MASK |
- OMAP3430_AUTO_GPT11_MASK |
- OMAP3430_AUTO_GPT10_MASK |
- OMAP3430_AUTO_MCBSP5_MASK |
- OMAP3430_AUTO_MCBSP1_MASK |
- OMAP3430ES1_AUTO_FAC_MASK | /* This is es1 only */
- OMAP3430_AUTO_MAILBOXES_MASK |
- OMAP3430_AUTO_OMAPCTRL_MASK |
- OMAP3430ES1_AUTO_FSHOSTUSB_MASK |
- OMAP3430_AUTO_HSOTGUSB_MASK |
- OMAP3430_AUTO_SAD2D_MASK |
- OMAP3430_AUTO_SSI_MASK,
- CORE_MOD, CM_AUTOIDLE1);
-
- omap2_cm_write_mod_reg(
- OMAP3430_AUTO_PKA_MASK |
- OMAP3430_AUTO_AES1_MASK |
- OMAP3430_AUTO_RNG_MASK |
- OMAP3430_AUTO_SHA11_MASK |
- OMAP3430_AUTO_DES1_MASK,
- CORE_MOD, CM_AUTOIDLE2);
-
- if (omap_rev() > OMAP3430_REV_ES1_0) {
- omap2_cm_write_mod_reg(
- OMAP3430_AUTO_MAD2D_MASK |
- OMAP3430ES2_AUTO_USBTLL_MASK,
- CORE_MOD, CM_AUTOIDLE3);
- }
-
- omap2_cm_write_mod_reg(
- OMAP3430_AUTO_WDT2_MASK |
- OMAP3430_AUTO_WDT1_MASK |
- OMAP3430_AUTO_GPIO1_MASK |
- OMAP3430_AUTO_32KSYNC_MASK |
- OMAP3430_AUTO_GPT12_MASK |
- OMAP3430_AUTO_GPT1_MASK,
- WKUP_MOD, CM_AUTOIDLE);
-
- omap2_cm_write_mod_reg(
- OMAP3430_AUTO_DSS_MASK,
- OMAP3430_DSS_MOD,
- CM_AUTOIDLE);
-
- omap2_cm_write_mod_reg(
- OMAP3430_AUTO_CAM_MASK,
- OMAP3430_CAM_MOD,
- CM_AUTOIDLE);
-
- omap2_cm_write_mod_reg(
- omap3630_auto_uart4_mask |
- OMAP3430_AUTO_GPIO6_MASK |
- OMAP3430_AUTO_GPIO5_MASK |
- OMAP3430_AUTO_GPIO4_MASK |
- OMAP3430_AUTO_GPIO3_MASK |
- OMAP3430_AUTO_GPIO2_MASK |
- OMAP3430_AUTO_WDT3_MASK |
- OMAP3430_AUTO_UART3_MASK |
- OMAP3430_AUTO_GPT9_MASK |
- OMAP3430_AUTO_GPT8_MASK |
- OMAP3430_AUTO_GPT7_MASK |
- OMAP3430_AUTO_GPT6_MASK |
- OMAP3430_AUTO_GPT5_MASK |
- OMAP3430_AUTO_GPT4_MASK |
- OMAP3430_AUTO_GPT3_MASK |
- OMAP3430_AUTO_GPT2_MASK |
- OMAP3430_AUTO_MCBSP4_MASK |
- OMAP3430_AUTO_MCBSP3_MASK |
- OMAP3430_AUTO_MCBSP2_MASK,
- OMAP3430_PER_MOD,
- CM_AUTOIDLE);
-
- if (omap_rev() > OMAP3430_REV_ES1_0) {
- omap2_cm_write_mod_reg(
- OMAP3430ES2_AUTO_USBHOST_MASK,
- OMAP3430ES2_USBHOST_MOD,
- CM_AUTOIDLE);
- }
-
+ /* XXX This should be handled by hwmod code or SCM init code */
omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
/*
^ permalink raw reply related
* [PATCH v2 1/2] ARM: IMX5: cpuidle driver
From: Yong Shen @ 2011-02-16 8:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110215182752.GD2027@pengutronix.de>
Hi Sascha,
On Tue, Feb 15, 2011 at 7:27 PM, Sascha Hauer <s.hauer@pengutronix.de>wrote:
> On Fri, Feb 11, 2011 at 10:36:12AM +0100, yong.shen at linaro.org wrote:
> > From: Yong Shen <yong.shen@freescale.com>
> >
> > implement cpuidle driver for iMX5 SOCs, leave cpuidle params to board
> > related code.
> >
> > Signed-off-by: Yong Shen <yong.shen@freescale.com>
> > ---
> > arch/arm/mach-mx5/Makefile | 1 +
> > arch/arm/mach-mx5/cpuidle.c | 113
> +++++++++++++++++++++++++++++++++++++++++++
> > arch/arm/mach-mx5/cpuidle.h | 26 ++++++++++
> > 3 files changed, 140 insertions(+), 0 deletions(-)
> > create mode 100644 arch/arm/mach-mx5/cpuidle.c
> > create mode 100644 arch/arm/mach-mx5/cpuidle.h
> >
> > diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile
> > index 0d43be9..12239e0 100644
> > --- a/arch/arm/mach-mx5/Makefile
> > +++ b/arch/arm/mach-mx5/Makefile
> > @@ -7,6 +7,7 @@ obj-y := cpu.o mm.o clock-mx51-mx53.o devices.o
> > obj-$(CONFIG_SOC_IMX50) += mm-mx50.o
> >
> > obj-$(CONFIG_CPU_FREQ_IMX) += cpu_op-mx51.o
> > +obj-$(CONFIG_CPU_IDLE) += cpuidle.o
> > obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o
> > obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o
> > obj-$(CONFIG_MACH_MX53_EVK) += board-mx53_evk.o
> > diff --git a/arch/arm/mach-mx5/cpuidle.c b/arch/arm/mach-mx5/cpuidle.c
> > new file mode 100644
> > index 0000000..9d77c47
> > --- /dev/null
> > +++ b/arch/arm/mach-mx5/cpuidle.c
> > @@ -0,0 +1,113 @@
> > +/*
> > + * arch/arm/mach-mx5/cpuidle.c
> > + *
> > + * This file is licensed under the terms of the GNU General Public
> > + * License version 2. This program is licensed "as is" without any
> > + * warranty of any kind, whether express or implied.
> > + */
> > +
> > +#include <linux/io.h>
> > +#include <linux/cpuidle.h>
> > +#include <asm/proc-fns.h>
> > +#include <mach/hardware.h>
> > +#include "cpuidle.h"
> > +#include "crm_regs.h"
> > +
> > +static struct imx_cpuidle_params *imx_cpuidle_params;
> > +void imx_cpuidle_board_params(struct imx_cpuidle_params *cpuidle_params)
> > +{
> > + imx_cpuidle_params = cpuidle_params;
> > +}
> > +
> > +extern int tzic_enable_wake(int is_idle);
>
> Please put this into a header file.
>
Ok, but I guess I should do it in another patch before this patch set.
>
> > +static int imx_enter_idle(struct cpuidle_device *dev,
> > + struct cpuidle_state *state)
> > +{
> > + struct timeval before, after;
> > + int idle_time;
> > + u32 plat_lpc, arm_srpgcr, ccm_clpcr;
> > + u32 empgc0, empgc1;
> > +
> > + local_irq_disable();
> > + do_gettimeofday(&before);
> > +
> > + plat_lpc = __raw_readl(MXC_CORTEXA8_PLAT_LPC) &
> > + ~(MXC_CORTEXA8_PLAT_LPC_DSM);
> > + ccm_clpcr = __raw_readl(MXC_CCM_CLPCR) & ~(MXC_CCM_CLPCR_LPM_MASK);
> > + arm_srpgcr = __raw_readl(MXC_SRPG_ARM_SRPGCR) & ~(MXC_SRPGCR_PCR);
> > + empgc0 = __raw_readl(MXC_SRPG_EMPGC0_SRPGCR) & ~(MXC_SRPGCR_PCR);
> > + empgc1 = __raw_readl(MXC_SRPG_EMPGC1_SRPGCR) & ~(MXC_SRPGCR_PCR);
> > +
> > + if (state == &dev->states[WAIT_CLK_ON])
> > + ;
>
> An if without code? This looks strange.
>
Yes, a little bit. I meant to treat this like a explanation for different
cases, and I also can remove it and put a comments here.
>
> > + else if (state == &dev->states[WAIT_CLK_OFF])
> > + ccm_clpcr |= (0x1 << MXC_CCM_CLPCR_LPM_OFFSET);
> > + else if (state == &dev->states[WAIT_CLK_OFF_POWER_OFF]) {
> > + /* Wait unclocked, power off */
> > + plat_lpc |= MXC_CORTEXA8_PLAT_LPC_DSM
> > + | MXC_CORTEXA8_PLAT_LPC_DBG_DSM;
> > + arm_srpgcr |= MXC_SRPGCR_PCR;
> > + ccm_clpcr |= (0x1 << MXC_CCM_CLPCR_LPM_OFFSET);
> > + ccm_clpcr &= ~MXC_CCM_CLPCR_VSTBY;
> > + ccm_clpcr &= ~MXC_CCM_CLPCR_SBYOS;
> > + if (tzic_enable_wake(1) != 0) {
> > + local_irq_enable();
> > + return 0;
> > + }
> > + }
> > +
> > + __raw_writel(plat_lpc, MXC_CORTEXA8_PLAT_LPC);
> > + __raw_writel(ccm_clpcr, MXC_CCM_CLPCR);
> > + __raw_writel(arm_srpgcr, MXC_SRPG_ARM_SRPGCR);
> > +
> > + cpu_do_idle();
> > +
> > + do_gettimeofday(&after);
> > + local_irq_enable();
> > + idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
> > + (after.tv_usec - before.tv_usec);
> > + return idle_time;
> > +}
> > +
> > +static struct cpuidle_driver imx_cpuidle_driver = {
> > + .name = "imx_idle",
> > + .owner = THIS_MODULE,
> > +};
> > +
> > +static DEFINE_PER_CPU(struct cpuidle_device, imx_cpuidle_device);
> > +
> > +static int __init imx_cpuidle_init(void)
> > +{
> > + struct cpuidle_device *device;
> > + int i;
> > +
> > + if (imx_cpuidle_params == NULL)
> > + return -ENODEV;
> > +
> > + cpuidle_register_driver(&imx_cpuidle_driver);
> > +
> > + device = &per_cpu(imx_cpuidle_device, smp_processor_id());
> > + device->state_count = IMX_MAX_CPUIDLE_STATE;
> > +
> > + for (i = 0; i < IMX_MAX_CPUIDLE_STATE && i < CPUIDLE_STATE_MAX;
> i++) {
> > + device->states[i].enter = imx_enter_idle;
> > + device->states[i].exit_latency =
> imx_cpuidle_params[i].latency;
> > + device->states[i].flags = CPUIDLE_FLAG_TIME_VALID;
> > + }
> > +
> > + strcpy(device->states[WAIT_CLK_ON].name, "WFI 0");
> > + strcpy(device->states[WAIT_CLK_ON].desc, "Wait with clock on");
> > + strcpy(device->states[WAIT_CLK_OFF].name, "WFI 1");
> > + strcpy(device->states[WAIT_CLK_OFF].desc, "Wait with clock off");
> > + strcpy(device->states[WAIT_CLK_OFF_POWER_OFF].name, "WFI 2");
> > + strcpy(device->states[WAIT_CLK_OFF_POWER_OFF].desc,
> > + "Wait with clock off and power gating");
> > +
> > + if (cpuidle_register_device(device)) {
> > + printk(KERN_ERR "imx_cpuidle_init: Failed registering\n");
> > + return -ENODEV;
> > + }
> > + return 0;
> > +}
> > +
> > +late_initcall(imx_cpuidle_init);
>
> We have a late_initcall here which needs to be protected from other
> cpus. On the other hand we depend on board code calling
> imx_cpuidle_board_params() before this initcall. I think the board code
> should call a imx_cpuidle_init(struct imx_cpuidle_params
> *cpuidle_params) instead which makes the flow of execution more clear.
> Also, the function should be named mx51_cpuidle_init().
>
Then, I assume the best way might be that remove imx_cpuidle_board_params(),
and let board code call mx51_cpuidle_init(), at the same time the params can
be passed in by the same funciton.
>
> > diff --git a/arch/arm/mach-mx5/cpuidle.h b/arch/arm/mach-mx5/cpuidle.h
> > new file mode 100644
> > index 0000000..e5ba495
> > --- /dev/null
> > +++ b/arch/arm/mach-mx5/cpuidle.h
> > @@ -0,0 +1,26 @@
> > +/*
> > + * arch/arm/mach-mx5/cpuidle.h
> > + *
> > + * This file is licensed under the terms of the GNU General Public
> > + * License version 2. This program is licensed "as is" without any
> > + * warranty of any kind, whether express or implied.
> > + */
> > +
> > +enum {
> > + WAIT_CLK_ON, /* c1 */
> > + WAIT_CLK_OFF, /* c2 */
> > + WAIT_CLK_OFF_POWER_OFF, /* c3 */
> > + IMX_MAX_CPUIDLE_STATE,
> > +};
> > +
> > +struct imx_cpuidle_params {
> > + unsigned int latency;
> > +};
> > +
> > +#ifdef CONFIG_CPU_IDLE
> > +extern void imx_cpuidle_board_params(struct imx_cpuidle_params
> *cpuidle_params);
> > +#else
> > +inline void imx_cpuidle_board_params(struct imx_cpuidle_params
> *cpuidle_params)
> > +{}
> > +#endif
> > +
> > --
> > 1.7.1
> >
> >
> > _______________________________________________
> > linux-arm-kernel mailing list
> > linux-arm-kernel at lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> >
>
> --
> Pengutronix e.K. | |
> Industrial Linux Solutions | http://www.pengutronix.de/ |
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
> Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
>
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* [PATCH 1/3] mach-ux500: move MOP500 pins to separate file
From: Linus Walleij @ 2011-02-16 8:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Rabin Vincent <rabin.vincent@stericsson.com>
Split off pin definitions for the MOP500 board family to its
own file.
Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/mach-ux500/Makefile | 3 +-
arch/arm/mach-ux500/board-mop500-pins.c | 80 +++++++++++++++++++++++++++++++
arch/arm/mach-ux500/board-mop500.c | 63 +------------------------
arch/arm/mach-ux500/board-mop500.h | 1 +
4 files changed, 84 insertions(+), 63 deletions(-)
create mode 100644 arch/arm/mach-ux500/board-mop500-pins.c
diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
index eec3279..b549a8f 100644
--- a/arch/arm/mach-ux500/Makefile
+++ b/arch/arm/mach-ux500/Makefile
@@ -9,7 +9,8 @@ obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o prcmu.o
obj-$(CONFIG_MACH_U8500) += board-mop500.o board-mop500-sdi.o \
board-mop500-regulators.o \
board-mop500-uib.o board-mop500-stuib.o \
- board-mop500-u8500uib.o
+ board-mop500-u8500uib.o \
+ board-mop500-pins.o
obj-$(CONFIG_MACH_U5500) += board-u5500.o board-u5500-sdi.o
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c
new file mode 100644
index 0000000..edd3a6b
--- /dev/null
+++ b/arch/arm/mach-ux500/board-mop500-pins.c
@@ -0,0 +1,80 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/gpio.h>
+
+#include <plat/pincfg.h>
+
+#include <mach/hardware.h>
+
+#include "pins-db8500.h"
+
+static pin_cfg_t mop500_pins[] = {
+ /* SSP0 */
+ GPIO143_SSP0_CLK,
+ GPIO144_SSP0_FRM,
+ GPIO145_SSP0_RXD,
+ GPIO146_SSP0_TXD,
+
+ /* I2C */
+ GPIO147_I2C0_SCL,
+ GPIO148_I2C0_SDA,
+ GPIO16_I2C1_SCL,
+ GPIO17_I2C1_SDA,
+ GPIO10_I2C2_SDA,
+ GPIO11_I2C2_SCL,
+ GPIO229_I2C3_SDA,
+ GPIO230_I2C3_SCL,
+
+ /* SKE keypad */
+ GPIO153_KP_I7,
+ GPIO154_KP_I6,
+ GPIO155_KP_I5,
+ GPIO156_KP_I4,
+ GPIO157_KP_O7,
+ GPIO158_KP_O6,
+ GPIO159_KP_O5,
+ GPIO160_KP_O4,
+ GPIO161_KP_I3,
+ GPIO162_KP_I2,
+ GPIO163_KP_I1,
+ GPIO164_KP_I0,
+ GPIO165_KP_O3,
+ GPIO166_KP_O2,
+ GPIO167_KP_O1,
+ GPIO168_KP_O0,
+
+ /* GPIO_EXP_INT */
+ GPIO217_GPIO,
+
+ /* STMPE1601 IRQ */
+ GPIO218_GPIO | PIN_INPUT_PULLUP,
+
+ /* touch screen */
+ GPIO84_GPIO | PIN_INPUT_PULLUP,
+
+ /* USB OTG */
+ GPIO256_USB_NXT | PIN_PULL_DOWN,
+ GPIO257_USB_STP | PIN_PULL_UP,
+ GPIO258_USB_XCLK | PIN_PULL_DOWN,
+ GPIO259_USB_DIR | PIN_PULL_DOWN,
+ GPIO260_USB_DAT7 | PIN_PULL_DOWN,
+ GPIO261_USB_DAT6 | PIN_PULL_DOWN,
+ GPIO262_USB_DAT5 | PIN_PULL_DOWN,
+ GPIO263_USB_DAT4 | PIN_PULL_DOWN,
+ GPIO264_USB_DAT3 | PIN_PULL_DOWN,
+ GPIO265_USB_DAT2 | PIN_PULL_DOWN,
+ GPIO266_USB_DAT1 | PIN_PULL_DOWN,
+ GPIO267_USB_DAT0 | PIN_PULL_DOWN,
+};
+
+void __init mop500_pins_init(void)
+{
+ nmk_config_pins(mop500_pins,
+ ARRAY_SIZE(mop500_pins));
+}
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 67d9c63..72448e1 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -28,7 +28,6 @@
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
-#include <plat/pincfg.h>
#include <plat/i2c.h>
#include <plat/ste_dma40.h>
@@ -39,69 +38,9 @@
#include "ste-dma40-db8500.h"
#include "devices-db8500.h"
-#include "pins-db8500.h"
#include "board-mop500.h"
#include "board-mop500-regulators.h"
-static pin_cfg_t mop500_pins[] = {
- /* SSP0 */
- GPIO143_SSP0_CLK,
- GPIO144_SSP0_FRM,
- GPIO145_SSP0_RXD,
- GPIO146_SSP0_TXD,
-
- /* I2C */
- GPIO147_I2C0_SCL,
- GPIO148_I2C0_SDA,
- GPIO16_I2C1_SCL,
- GPIO17_I2C1_SDA,
- GPIO10_I2C2_SDA,
- GPIO11_I2C2_SCL,
- GPIO229_I2C3_SDA,
- GPIO230_I2C3_SCL,
-
- /* SKE keypad */
- GPIO153_KP_I7,
- GPIO154_KP_I6,
- GPIO155_KP_I5,
- GPIO156_KP_I4,
- GPIO157_KP_O7,
- GPIO158_KP_O6,
- GPIO159_KP_O5,
- GPIO160_KP_O4,
- GPIO161_KP_I3,
- GPIO162_KP_I2,
- GPIO163_KP_I1,
- GPIO164_KP_I0,
- GPIO165_KP_O3,
- GPIO166_KP_O2,
- GPIO167_KP_O1,
- GPIO168_KP_O0,
-
- /* GPIO_EXP_INT */
- GPIO217_GPIO,
-
- /* STMPE1601 IRQ */
- GPIO218_GPIO | PIN_INPUT_PULLUP,
-
- /* touch screen */
- GPIO84_GPIO | PIN_INPUT_PULLUP,
-
- /* USB OTG */
- GPIO256_USB_NXT | PIN_PULL_DOWN,
- GPIO257_USB_STP | PIN_PULL_UP,
- GPIO258_USB_XCLK | PIN_PULL_DOWN,
- GPIO259_USB_DIR | PIN_PULL_DOWN,
- GPIO260_USB_DAT7 | PIN_PULL_DOWN,
- GPIO261_USB_DAT6 | PIN_PULL_DOWN,
- GPIO262_USB_DAT5 | PIN_PULL_DOWN,
- GPIO263_USB_DAT4 | PIN_PULL_DOWN,
- GPIO264_USB_DAT3 | PIN_PULL_DOWN,
- GPIO265_USB_DAT2 | PIN_PULL_DOWN,
- GPIO266_USB_DAT1 | PIN_PULL_DOWN,
- GPIO267_USB_DAT0 | PIN_PULL_DOWN,
-};
-
static struct ab8500_platform_data ab8500_platdata = {
.irq_base = MOP500_AB8500_IRQ_BASE,
.regulator = ab8500_regulators,
@@ -444,7 +383,7 @@ static void __init u8500_init_machine(void)
{
u8500_init_devices();
- nmk_config_pins(mop500_pins, ARRAY_SIZE(mop500_pins));
+ mop500_pins_init();
platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index 19b6c27..48abca7 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -22,6 +22,7 @@ extern void mop500_sdi_init(void);
extern void mop500_sdi_tc35892_init(void);
void __init mop500_u8500uib_init(void);
void __init mop500_stuib_init(void);
+void __init mop500_pins_init(void);
void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info,
unsigned n);
--
1.7.3.2
^ permalink raw reply related
* [PATCH 2/3] mach-ux500: add hrefv60 GPIO pins
From: Linus Walleij @ 2011-02-16 8:07 UTC (permalink / raw)
To: linux-arm-kernel
From: Bibek Basu <bibek.basu@stericsson.com>
This will centralize all GPIO pin muxing for the different boards
in the MOP500 family to a single file. It also kills off the
deprecated support for the ED (Early Drop) ASIC, this should
never be spotted in the open and ST-Ericsson have internally
deprecated this hardware.
Signed-off-by: Bibek Basu <bibek.basu@stericsson.com>
[Rebasing and kill old ASIC support]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/mach-ux500/board-mop500-pins.c | 225 ++++++++++++++++++++++++++-----
arch/arm/mach-ux500/board-mop500-sdi.c | 65 +--------
2 files changed, 200 insertions(+), 90 deletions(-)
diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c
index edd3a6b..fd4cf1c 100644
--- a/arch/arm/mach-ux500/board-mop500-pins.c
+++ b/arch/arm/mach-ux500/board-mop500-pins.c
@@ -8,19 +8,13 @@
#include <linux/init.h>
#include <linux/gpio.h>
+#include <asm/mach-types.h>
#include <plat/pincfg.h>
-
#include <mach/hardware.h>
#include "pins-db8500.h"
-static pin_cfg_t mop500_pins[] = {
- /* SSP0 */
- GPIO143_SSP0_CLK,
- GPIO144_SSP0_FRM,
- GPIO145_SSP0_RXD,
- GPIO146_SSP0_TXD,
-
+static pin_cfg_t mop500_pins_common[] = {
/* I2C */
GPIO147_I2C0_SCL,
GPIO148_I2C0_SDA,
@@ -31,6 +25,72 @@ static pin_cfg_t mop500_pins[] = {
GPIO229_I2C3_SDA,
GPIO230_I2C3_SCL,
+ /* MSP0 */
+ GPIO12_MSP0_TXD,
+ GPIO13_MSP0_TFS,
+ GPIO14_MSP0_TCK,
+ GPIO15_MSP0_RXD,
+
+ /* MSP2: HDMI */
+ GPIO193_MSP2_TXD,
+ GPIO194_MSP2_TCK,
+ GPIO195_MSP2_TFS,
+ GPIO196_MSP2_RXD | PIN_OUTPUT_LOW,
+
+ /* Touch screen INTERFACE */
+ GPIO84_GPIO | PIN_INPUT_PULLUP, /* TOUCH_INT1 */
+
+ /* STMPE1601/tc35893 keypad IRQ */
+ GPIO218_GPIO | PIN_INPUT_PULLUP,
+
+ /* MMC0 (MicroSD card) */
+ GPIO18_MC0_CMDDIR | PIN_OUTPUT_HIGH,
+ GPIO19_MC0_DAT0DIR | PIN_OUTPUT_HIGH,
+ GPIO20_MC0_DAT2DIR | PIN_OUTPUT_HIGH,
+
+ GPIO22_MC0_FBCLK | PIN_INPUT_NOPULL,
+ GPIO23_MC0_CLK | PIN_OUTPUT_LOW,
+ GPIO24_MC0_CMD | PIN_INPUT_PULLUP,
+ GPIO25_MC0_DAT0 | PIN_INPUT_PULLUP,
+ GPIO26_MC0_DAT1 | PIN_INPUT_PULLUP,
+ GPIO27_MC0_DAT2 | PIN_INPUT_PULLUP,
+ GPIO28_MC0_DAT3 | PIN_INPUT_PULLUP,
+
+ /* SDI1 (SDIO) */
+ GPIO208_MC1_CLK | PIN_OUTPUT_LOW,
+ GPIO209_MC1_FBCLK | PIN_INPUT_NOPULL,
+ GPIO210_MC1_CMD | PIN_INPUT_PULLUP,
+ GPIO211_MC1_DAT0 | PIN_INPUT_PULLUP,
+ GPIO212_MC1_DAT1 | PIN_INPUT_PULLUP,
+ GPIO213_MC1_DAT2 | PIN_INPUT_PULLUP,
+ GPIO214_MC1_DAT3 | PIN_INPUT_PULLUP,
+
+ /* MMC2 (On-board DATA INTERFACE eMMC) */
+ GPIO128_MC2_CLK | PIN_OUTPUT_LOW,
+ GPIO129_MC2_CMD | PIN_INPUT_PULLUP,
+ GPIO130_MC2_FBCLK | PIN_INPUT_NOPULL,
+ GPIO131_MC2_DAT0 | PIN_INPUT_PULLUP,
+ GPIO132_MC2_DAT1 | PIN_INPUT_PULLUP,
+ GPIO133_MC2_DAT2 | PIN_INPUT_PULLUP,
+ GPIO134_MC2_DAT3 | PIN_INPUT_PULLUP,
+ GPIO135_MC2_DAT4 | PIN_INPUT_PULLUP,
+ GPIO136_MC2_DAT5 | PIN_INPUT_PULLUP,
+ GPIO137_MC2_DAT6 | PIN_INPUT_PULLUP,
+ GPIO138_MC2_DAT7 | PIN_INPUT_PULLUP,
+
+ /* MMC4 (On-board STORAGE INTERFACE eMMC) */
+ GPIO197_MC4_DAT3 | PIN_INPUT_PULLUP,
+ GPIO198_MC4_DAT2 | PIN_INPUT_PULLUP,
+ GPIO199_MC4_DAT1 | PIN_INPUT_PULLUP,
+ GPIO200_MC4_DAT0 | PIN_INPUT_PULLUP,
+ GPIO201_MC4_CMD | PIN_INPUT_PULLUP,
+ GPIO202_MC4_FBCLK | PIN_INPUT_NOPULL,
+ GPIO203_MC4_CLK | PIN_OUTPUT_LOW,
+ GPIO204_MC4_DAT7 | PIN_INPUT_PULLUP,
+ GPIO205_MC4_DAT6 | PIN_INPUT_PULLUP,
+ GPIO206_MC4_DAT5 | PIN_INPUT_PULLUP,
+ GPIO207_MC4_DAT4 | PIN_INPUT_PULLUP,
+
/* SKE keypad */
GPIO153_KP_I7,
GPIO154_KP_I6,
@@ -49,32 +109,133 @@ static pin_cfg_t mop500_pins[] = {
GPIO167_KP_O1,
GPIO168_KP_O0,
- /* GPIO_EXP_INT */
- GPIO217_GPIO,
-
- /* STMPE1601 IRQ */
- GPIO218_GPIO | PIN_INPUT_PULLUP,
-
- /* touch screen */
- GPIO84_GPIO | PIN_INPUT_PULLUP,
-
- /* USB OTG */
- GPIO256_USB_NXT | PIN_PULL_DOWN,
- GPIO257_USB_STP | PIN_PULL_UP,
- GPIO258_USB_XCLK | PIN_PULL_DOWN,
- GPIO259_USB_DIR | PIN_PULL_DOWN,
- GPIO260_USB_DAT7 | PIN_PULL_DOWN,
- GPIO261_USB_DAT6 | PIN_PULL_DOWN,
- GPIO262_USB_DAT5 | PIN_PULL_DOWN,
- GPIO263_USB_DAT4 | PIN_PULL_DOWN,
- GPIO264_USB_DAT3 | PIN_PULL_DOWN,
- GPIO265_USB_DAT2 | PIN_PULL_DOWN,
- GPIO266_USB_DAT1 | PIN_PULL_DOWN,
- GPIO267_USB_DAT0 | PIN_PULL_DOWN,
+ /* UART */
+ GPIO0_U0_CTSn | PIN_INPUT_PULLUP,
+ GPIO1_U0_RTSn | PIN_OUTPUT_HIGH,
+ GPIO2_U0_RXD | PIN_INPUT_PULLUP,
+ GPIO3_U0_TXD | PIN_OUTPUT_HIGH,
+
+ GPIO29_U2_RXD | PIN_INPUT_PULLUP,
+ GPIO30_U2_TXD | PIN_OUTPUT_HIGH,
+ GPIO31_U2_CTSn | PIN_INPUT_PULLUP,
+ GPIO32_U2_RTSn | PIN_OUTPUT_HIGH,
+
+ /* Display & HDMI HW sync */
+ GPIO68_LCD_VSI0 | PIN_INPUT_PULLUP,
+ GPIO69_LCD_VSI1 | PIN_INPUT_PULLUP,
+};
+
+static pin_cfg_t mop500_pins_default[] = {
+ /* SSP0 */
+ GPIO143_SSP0_CLK,
+ GPIO144_SSP0_FRM,
+ GPIO145_SSP0_RXD | PIN_PULL_DOWN,
+ GPIO146_SSP0_TXD,
+
+
+ GPIO217_GPIO | PIN_INPUT_PULLUP, /* TC35892 IRQ */
+
+ /* SDI0 (MicroSD card) */
+ GPIO21_MC0_DAT31DIR | PIN_OUTPUT_HIGH,
+
+ /* UART */
+ GPIO4_U1_RXD | PIN_INPUT_PULLUP,
+ GPIO5_U1_TXD | PIN_OUTPUT_HIGH,
+ GPIO6_U1_CTSn | PIN_INPUT_PULLUP,
+ GPIO7_U1_RTSn | PIN_OUTPUT_HIGH,
+};
+
+static pin_cfg_t mop500_pins_hrefv60[] = {
+ /* WLAN */
+ GPIO4_GPIO | PIN_INPUT_PULLUP,/* WLAN_IRQ */
+ GPIO85_GPIO | PIN_OUTPUT_LOW,/* WLAN_ENA */
+
+ /* XENON Flashgun INTERFACE */
+ GPIO6_IP_GPIO0 | PIN_INPUT_PULLUP,/* XENON_FLASH_ID */
+ GPIO7_IP_GPIO1 | PIN_INPUT_PULLUP,/* XENON_READY */
+ GPIO170_GPIO | PIN_OUTPUT_LOW, /* XENON_CHARGE */
+
+ /* Assistant LED INTERFACE */
+ GPIO21_GPIO | PIN_OUTPUT_LOW, /* XENON_EN1 */
+ GPIO64_IP_GPIO4 | PIN_OUTPUT_LOW, /* XENON_EN2 */
+
+ /* Magnetometer */
+ GPIO31_GPIO | PIN_INPUT_PULLUP, /* magnetometer_INT */
+ GPIO32_GPIO | PIN_INPUT_PULLDOWN, /* Magnetometer DRDY */
+
+ /* Display Interface */
+ GPIO65_GPIO | PIN_OUTPUT_LOW, /* DISP1 RST */
+ GPIO66_GPIO | PIN_OUTPUT_LOW, /* DISP2 RST */
+
+ /* Touch screen INTERFACE */
+ GPIO143_GPIO | PIN_OUTPUT_LOW,/*TOUCH_RST1 */
+
+ /* Touch screen INTERFACE 2 */
+ GPIO67_GPIO | PIN_INPUT_PULLUP, /* TOUCH_INT2 */
+ GPIO146_GPIO | PIN_OUTPUT_LOW,/*TOUCH_RST2 */
+
+ /* ETM_PTM_TRACE INTERFACE */
+ GPIO70_GPIO | PIN_OUTPUT_LOW,/* ETM_PTM_DATA23 */
+ GPIO71_GPIO | PIN_OUTPUT_LOW,/* ETM_PTM_DATA22 */
+ GPIO72_GPIO | PIN_OUTPUT_LOW,/* ETM_PTM_DATA21 */
+ GPIO73_GPIO | PIN_OUTPUT_LOW,/* ETM_PTM_DATA20 */
+ GPIO74_GPIO | PIN_OUTPUT_LOW,/* ETM_PTM_DATA19 */
+
+ /* NAHJ INTERFACE */
+ GPIO76_GPIO | PIN_OUTPUT_LOW,/* NAHJ_CTRL */
+ GPIO216_GPIO | PIN_OUTPUT_HIGH,/* NAHJ_CTRL_INV */
+
+ /* NFC INTERFACE */
+ GPIO77_GPIO | PIN_OUTPUT_LOW, /* NFC_ENA */
+ GPIO144_GPIO | PIN_INPUT_PULLDOWN, /* NFC_IRQ */
+ GPIO142_GPIO | PIN_OUTPUT_LOW, /* NFC_RESET */
+
+ /* Keyboard MATRIX INTERFACE */
+ GPIO90_MC5_CMD | PIN_OUTPUT_LOW, /* KP_O_1 */
+ GPIO87_MC5_DAT1 | PIN_OUTPUT_LOW, /* KP_O_2 */
+ GPIO86_MC5_DAT0 | PIN_OUTPUT_LOW, /* KP_O_3 */
+ GPIO96_KP_O6 | PIN_OUTPUT_LOW, /* KP_O_6 */
+ GPIO94_KP_O7 | PIN_OUTPUT_LOW, /* KP_O_7 */
+ GPIO93_MC5_DAT4 | PIN_INPUT_PULLUP, /* KP_I_0 */
+ GPIO89_MC5_DAT3 | PIN_INPUT_PULLUP, /* KP_I_2 */
+ GPIO88_MC5_DAT2 | PIN_INPUT_PULLUP, /* KP_I_3 */
+ GPIO91_GPIO | PIN_INPUT_PULLUP, /* FORCE_SENSING_INT */
+ GPIO92_GPIO | PIN_OUTPUT_LOW, /* FORCE_SENSING_RST */
+ GPIO97_GPIO | PIN_OUTPUT_LOW, /* FORCE_SENSING_WU */
+
+ /* DiPro Sensor Interface */
+ GPIO139_GPIO | PIN_INPUT_PULLUP, /* DIPRO_INT */
+
+ /* HAL SWITCH INTERFACE */
+ GPIO145_GPIO | PIN_INPUT_PULLDOWN,/* HAL_SW */
+
+ /* Audio Amplifier Interface */
+ GPIO149_GPIO | PIN_OUTPUT_LOW, /* VAUDIO_HF_EN */
+
+ /* GBF INTERFACE */
+ GPIO171_GPIO | PIN_OUTPUT_LOW, /* GBF_ENA_RESET */
+
+ /* MSP : HDTV INTERFACE */
+ GPIO192_GPIO | PIN_INPUT_PULLDOWN,
+
+ /* ACCELEROMETER_INTERFACE */
+ GPIO82_GPIO | PIN_INPUT_PULLUP, /* ACC_INT1 */
+ GPIO83_GPIO | PIN_INPUT_PULLUP, /* ACC_INT2 */
+
+ /* Proximity Sensor */
+ GPIO217_GPIO | PIN_INPUT_PULLUP,
+
+
};
void __init mop500_pins_init(void)
{
- nmk_config_pins(mop500_pins,
- ARRAY_SIZE(mop500_pins));
+ nmk_config_pins(mop500_pins_common,
+ ARRAY_SIZE(mop500_pins_common));
+ if (machine_is_hrefv60())
+ nmk_config_pins(mop500_pins_hrefv60,
+ ARRAY_SIZE(mop500_pins_hrefv60));
+ else
+ nmk_config_pins(mop500_pins_default,
+ ARRAY_SIZE(mop500_pins_default));
}
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
index d1ae6a0..68c8375 100644
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -12,59 +12,14 @@
#include <linux/mmc/host.h>
#include <linux/platform_device.h>
-#include <plat/pincfg.h>
#include <plat/ste_dma40.h>
#include <mach/devices.h>
#include <mach/hardware.h>
#include "devices-db8500.h"
-#include "pins-db8500.h"
#include "board-mop500.h"
#include "ste-dma40-db8500.h"
-static pin_cfg_t mop500_sdi_pins[] = {
- /* SDI0 (MicroSD slot) */
- GPIO18_MC0_CMDDIR,
- GPIO19_MC0_DAT0DIR,
- GPIO20_MC0_DAT2DIR,
- GPIO21_MC0_DAT31DIR,
- GPIO22_MC0_FBCLK,
- GPIO23_MC0_CLK,
- GPIO24_MC0_CMD,
- GPIO25_MC0_DAT0,
- GPIO26_MC0_DAT1,
- GPIO27_MC0_DAT2,
- GPIO28_MC0_DAT3,
-
- /* SDI4 (on-board eMMC) */
- GPIO197_MC4_DAT3,
- GPIO198_MC4_DAT2,
- GPIO199_MC4_DAT1,
- GPIO200_MC4_DAT0,
- GPIO201_MC4_CMD,
- GPIO202_MC4_FBCLK,
- GPIO203_MC4_CLK,
- GPIO204_MC4_DAT7,
- GPIO205_MC4_DAT6,
- GPIO206_MC4_DAT5,
- GPIO207_MC4_DAT4,
-};
-
-static pin_cfg_t mop500_sdi2_pins[] = {
- /* SDI2 (POP eMMC) */
- GPIO128_MC2_CLK,
- GPIO129_MC2_CMD,
- GPIO130_MC2_FBCLK,
- GPIO131_MC2_DAT0,
- GPIO132_MC2_DAT1,
- GPIO133_MC2_DAT2,
- GPIO134_MC2_DAT3,
- GPIO135_MC2_DAT4,
- GPIO136_MC2_DAT5,
- GPIO137_MC2_DAT6,
- GPIO138_MC2_DAT7,
-};
-
/*
* SDI 0 (MicroSD slot)
*/
@@ -216,22 +171,16 @@ static struct mmci_platform_data mop500_sdi4_data = {
void __init mop500_sdi_init(void)
{
- nmk_config_pins(mop500_sdi_pins, ARRAY_SIZE(mop500_sdi_pins));
+ /* PoP:ed eMMC on top of DB8500 v1.0 has problems with high speed */
+ if (!cpu_is_u8500v10())
+ mop500_sdi2_data.capabilities |= MMC_CAP_MMC_HIGHSPEED;
+ db8500_add_sdi2(&mop500_sdi2_data);
+
+ /* On-board eMMC */
+ db8500_add_sdi4(&mop500_sdi4_data);
/*
* sdi0 will finally be added when the TC35892 initializes and calls
* mop500_sdi_tc35892_init() above.
*/
-
- /* PoP:ed eMMC */
- if (!cpu_is_u8500ed()) {
- nmk_config_pins(mop500_sdi2_pins, ARRAY_SIZE(mop500_sdi2_pins));
- /* POP eMMC on v1.0 has problems with high speed */
- if (!cpu_is_u8500v10())
- mop500_sdi2_data.capabilities |= MMC_CAP_MMC_HIGHSPEED;
- db8500_add_sdi2(&mop500_sdi2_data);
- }
-
- /* On-board eMMC */
- db8500_add_sdi4(&mop500_sdi4_data);
}
--
1.7.3.2
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