* [PATCH v2 13/18] omap3+: sr: introduce notifiers flags
From: Nishanth Menon @ 2011-03-02 10:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1299063331-27968-1-git-send-email-nm@ti.com>
SmartReflex IP v1 and v2 have different registers and offsets.
Currently, we pass the status as is to the class driver. However,
since we dont pass the version of the underlying SR hardware
to the Class driver, it will not be unable to make consistent
sense of the status bits coming over to it.
A class driver should be able to function without dependency
on the exact IP version it is actually running on. We hence
introduce our own translation in s/w level for a generic
notification flag.
As part of this change, we will now call the notifier iff we get
a match with the notifier flags that the class driver requested.
Signed-off-by: Nishanth Menon <nm@ti.com>
---
arch/arm/mach-omap2/smartreflex.c | 73 ++++++++++++++++++++++++-
arch/arm/plat-omap/include/plat/smartreflex.h | 6 ++
2 files changed, 76 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
index 4fc679e..2657ba1 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -123,27 +123,94 @@ static struct omap_sr *_sr_lookup(struct voltagedomain *voltdm)
return ERR_PTR(-ENODATA);
}
+static inline u32 notifier_to_irqen_v1(u8 notify_flags)
+{
+ u32 val;
+ val = (notify_flags & SR_NOTIFY_MCUACCUM) ?
+ ERRCONFIG_MCUACCUMINTEN : 0;
+ val |= (notify_flags & SR_NOTIFY_MCUVALID) ?
+ ERRCONFIG_MCUVALIDINTEN : 0;
+ val |= (notify_flags & SR_NOTIFY_MCUBOUND) ?
+ ERRCONFIG_MCUBOUNDINTEN : 0;
+ val |= (notify_flags & SR_NOTIFY_MCUDISACK) ?
+ ERRCONFIG_MCUDISACKINTEN : 0;
+ return val;
+}
+
+static inline u32 notifier_to_irqen_v2(u8 notify_flags)
+{
+ u32 val;
+ val = (notify_flags & SR_NOTIFY_MCUACCUM) ?
+ IRQENABLE_MCUACCUMINT : 0;
+ val |= (notify_flags & SR_NOTIFY_MCUVALID) ?
+ IRQENABLE_MCUVALIDINT : 0;
+ val |= (notify_flags & SR_NOTIFY_MCUBOUND) ?
+ IRQENABLE_MCUBOUNDSINT : 0;
+ val |= (notify_flags & SR_NOTIFY_MCUDISACK) ?
+ IRQENABLE_MCUDISABLEACKINT : 0;
+ return val;
+}
+
+static inline u8 irqstat_to_notifier_v1(u32 status)
+{
+ u8 val;
+ val = (status & ERRCONFIG_MCUACCUMINTST) ?
+ SR_NOTIFY_MCUACCUM : 0;
+ val |= (status & ERRCONFIG_MCUVALIDINTEN) ?
+ SR_NOTIFY_MCUVALID : 0;
+ val |= (status & ERRCONFIG_MCUBOUNDINTEN) ?
+ SR_NOTIFY_MCUBOUND : 0;
+ val |= (status & ERRCONFIG_MCUDISACKINTEN) ?
+ SR_NOTIFY_MCUDISACK : 0;
+ return val;
+}
+
+static inline u8 irqstat_to_notifier_v2(u32 status)
+{
+ u8 val;
+ val = (status & IRQENABLE_MCUACCUMINT) ?
+ SR_NOTIFY_MCUACCUM : 0;
+ val |= (status & IRQENABLE_MCUVALIDINT) ?
+ SR_NOTIFY_MCUVALID : 0;
+ val |= (status & IRQENABLE_MCUBOUNDSINT) ?
+ SR_NOTIFY_MCUBOUND : 0;
+ val |= (status & IRQENABLE_MCUDISABLEACKINT) ?
+ SR_NOTIFY_MCUDISACK : 0;
+ return val;
+}
+
+
static irqreturn_t sr_interrupt(int irq, void *data)
{
struct omap_sr *sr_info = (struct omap_sr *)data;
u32 status = 0;
+ u32 value = 0;
if (sr_info->ip_type == SR_TYPE_V1) {
+ /* Status bits are one bit before enable bits in v1 */
+ value = notifier_to_irqen_v1(sr_class->notify_flags) >> 1;
+
/* Read the status bits */
status = sr_read_reg(sr_info, ERRCONFIG_V1);
+ status &= value;
/* Clear them by writing back */
- sr_write_reg(sr_info, ERRCONFIG_V1, status);
+ sr_modify_reg(sr_info, ERRCONFIG_V1, value, status);
+
+ value = irqstat_to_notifier_v1(status);
} else if (sr_info->ip_type == SR_TYPE_V2) {
+ value = notifier_to_irqen_v2(sr_class->notify_flags);
/* Read the status bits */
- sr_read_reg(sr_info, IRQSTATUS);
+ status = sr_read_reg(sr_info, IRQSTATUS);
+ status &= value;
/* Clear them by writing back */
sr_write_reg(sr_info, IRQSTATUS, status);
+ value = irqstat_to_notifier_v2(status);
}
if (sr_class->notify)
- sr_class->notify(sr_info->voltdm, status);
+ sr_class->notify(sr_info->voltdm, value);
return IRQ_HANDLED;
}
diff --git a/arch/arm/plat-omap/include/plat/smartreflex.h b/arch/arm/plat-omap/include/plat/smartreflex.h
index 8b6ecd9..ff07d1e 100644
--- a/arch/arm/plat-omap/include/plat/smartreflex.h
+++ b/arch/arm/plat-omap/include/plat/smartreflex.h
@@ -141,6 +141,12 @@
#define OMAP3430_SR_ERRWEIGHT 0x04
#define OMAP3430_SR_ERRMAXLIMIT 0x02
+/* Smart reflex notifiers for class drivers to use */
+#define SR_NOTIFY_MCUACCUM (0x1 << 0)
+#define SR_NOTIFY_MCUVALID (0x1 << 1)
+#define SR_NOTIFY_MCUBOUND (0x1 << 2)
+#define SR_NOTIFY_MCUDISACK (0x1 << 3)
+
/**
* struct omap_sr_pmic_data - Strucutre to be populated by pmic code to pass
* pmic specific info to smartreflex driver
--
1.7.1
^ permalink raw reply related
* [PATCH v2 14/18] omap3+: sr: introduce notifier_control
From: Nishanth Menon @ 2011-03-02 10:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1299063331-27968-1-git-send-email-nm@ti.com>
We need some mechanism from class drivers to control when notifiers
should be triggered and when not, currently we have none, which makes
Class driver usage of the interrupt events almost impossible.
Introduce an smartreflex driver api for doing the same.
Signed-off-by: Nishanth Menon <nm@ti.com>
---
arch/arm/mach-omap2/smartreflex.c | 57 +++++++++++++++++++++++++
arch/arm/plat-omap/include/plat/smartreflex.h | 8 ++++
2 files changed, 65 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
index 2657ba1..49a04ea 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -704,6 +704,63 @@ void sr_disable(struct voltagedomain *voltdm)
}
/**
+ * sr_notifier_control() - control the notifier mechanism
+ * @voltdm: VDD pointer to which the SR module to be configured belongs to.
+ * @enable: true to enable notifiers and false to disable the same
+ *
+ * SR modules allow an MCU interrupt mechanism that vary based on the IP
+ * revision, we allow the system to generate interrupt if the class driver
+ * has capability to handle the same. it is upto the class driver to ensure
+ * the proper sequencing and handling for a clean implementation. returns
+ * 0 if all goes fine, else returns failure results
+ */
+int sr_notifier_control(struct voltagedomain *voltdm, bool enable)
+{
+ struct omap_sr *sr = _sr_lookup(voltdm);
+ u32 value = 0;
+ if (IS_ERR_OR_NULL(sr)) {
+ pr_warning("%s: sr corresponding to domain not found\n",
+ __func__);
+ return -EINVAL;
+ }
+ if (!sr->autocomp_active)
+ return -EINVAL;
+
+ /* if I could never register an isr, why bother?? */
+ if (!(sr_class && sr_class->notify && sr_class->notify_flags &&
+ sr->irq)) {
+ dev_warn(&sr->pdev->dev,
+ "%s: unable to setup irq without handling mechanism\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ switch (sr->ip_type) {
+ case SR_TYPE_V1:
+ value = notifier_to_irqen_v1(sr_class->notify_flags);
+ sr_modify_reg(sr, ERRCONFIG_V1, value,
+ (enable) ? value : 0);
+ break;
+ case SR_TYPE_V2:
+ value = notifier_to_irqen_v2(sr_class->notify_flags);
+ sr_write_reg(sr, (enable) ? IRQENABLE_SET : IRQENABLE_CLR,
+ value);
+ break;
+ default:
+ dev_warn(&sr->pdev->dev, "%s: unknown type of sr??\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ if (enable)
+ enable_irq(sr->irq);
+ else
+ disable_irq_nosync(sr->irq);
+
+ return 0;
+}
+
+/**
* sr_register_class() - API to register a smartreflex class parameters.
* @class_data: The structure containing various sr class specific data.
*
diff --git a/arch/arm/plat-omap/include/plat/smartreflex.h b/arch/arm/plat-omap/include/plat/smartreflex.h
index ff07d1e..d420f44 100644
--- a/arch/arm/plat-omap/include/plat/smartreflex.h
+++ b/arch/arm/plat-omap/include/plat/smartreflex.h
@@ -242,6 +242,7 @@ void omap_sr_register_pmic(struct omap_sr_pmic_data *pmic_data);
/* Smartreflex driver hooks to be called from Smartreflex class driver */
int sr_enable(struct voltagedomain *voltdm, unsigned long volt);
void sr_disable(struct voltagedomain *voltdm);
+int sr_notifier_control(struct voltagedomain *voltdm, bool enable);
int sr_configure_errgen(struct voltagedomain *voltdm);
int sr_configure_minmax(struct voltagedomain *voltdm);
@@ -250,6 +251,13 @@ int sr_register_class(struct omap_sr_class_data *class_data);
#else
static inline void omap_sr_enable(struct voltagedomain *voltdm) {}
static inline void omap_sr_disable(struct voltagedomain *voltdm) {}
+
+static inline int sr_notifier_control(struct voltagedomain *voltdm,
+ bool enable)
+{
+ return -EINVAL;
+}
+
static inline void omap_sr_disable_reset_volt(
struct voltagedomain *voltdm) {}
static inline void omap_sr_register_pmic(
--
1.7.1
^ permalink raw reply related
* [PATCH v2 15/18] omap3+: sr: disable spamming interrupts
From: Nishanth Menon @ 2011-03-02 10:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1299063331-27968-1-git-send-email-nm@ti.com>
At times with bad SR configurations especially during silicon bringups,
we could get continuous spurious interrupts which end up hanging the
platform in the form of an ISR call for status bits that are
automatically enabled by the h/w without any s/w clearing option.
If we detect scenarios where isr was called without the corresponding
notification bit being set, instead of hanging up the system,
we will disable interrupt after noting the event in the system log
to try and keep system sanity and allow developer to debug and fix
the condition.
Signed-off-by: Nishanth Menon <nm@ti.com>
---
arch/arm/mach-omap2/smartreflex.c | 12 ++++++++++--
1 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
index 49a04ea..d62da3d 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -209,8 +209,16 @@ static irqreturn_t sr_interrupt(int irq, void *data)
value = irqstat_to_notifier_v2(status);
}
- if (sr_class->notify)
- sr_class->notify(sr_info->voltdm, value);
+ /* Attempt some resemblence of recovery! */
+ if (!value) {
+ dev_err(&sr_info->pdev->dev, "%s: Spurious interrupt!"
+ "status = 0x%08x. Disabling to prevent spamming!!\n",
+ __func__, status);
+ disable_irq_nosync(sr_info->irq);
+ } else {
+ if (sr_class->notify)
+ sr_class->notify(sr_info->voltdm, value);
+ }
return IRQ_HANDLED;
}
--
1.7.1
^ permalink raw reply related
* [PATCH v2 16/18] omap3+: sr: make enable path use volt_data pointer
From: Nishanth Menon @ 2011-03-02 10:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1299063331-27968-1-git-send-email-nm@ti.com>
Passing the volt_data pointers accross allows us to save us the effort
of looking up the voltage data pointer from the voltage value at
multiple layers, we need to look at the voltage data in dvfs layer
for further processing, so modify the APIs to pass the voltage data
pointer all the way through to lower layers to the smartreflex class
drivers.
Signed-off-by: Nishanth Menon <nm@ti.com>
---
arch/arm/mach-omap2/smartreflex-class3.c | 13 +++----------
arch/arm/mach-omap2/smartreflex.c | 25 ++++++++++++-------------
arch/arm/plat-omap/include/plat/smartreflex.h | 8 +++++---
3 files changed, 20 insertions(+), 26 deletions(-)
diff --git a/arch/arm/mach-omap2/smartreflex-class3.c b/arch/arm/mach-omap2/smartreflex-class3.c
index 2195668..7ac88da 100644
--- a/arch/arm/mach-omap2/smartreflex-class3.c
+++ b/arch/arm/mach-omap2/smartreflex-class3.c
@@ -13,19 +13,12 @@
#include <plat/smartreflex.h>
-static int sr_class3_enable(struct voltagedomain *voltdm)
+static int sr_class3_enable(struct voltagedomain *voltdm,
+ struct omap_volt_data *volt_data)
{
- unsigned long volt = omap_get_operation_voltage(
- omap_voltage_get_nom_volt(voltdm));
-
- if (!volt) {
- pr_warning("%s: Curr voltage unknown. Cannot enable sr_%s\n",
- __func__, voltdm->name);
- return -ENODATA;
- }
omap_vp_enable(voltdm);
- return sr_enable(voltdm, volt);
+ return sr_enable(voltdm, volt_data);
}
static int sr_class3_disable(struct voltagedomain *voltdm, int is_volt_reset)
diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
index d62da3d..9b9d380 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -302,7 +302,8 @@ static void sr_start_vddautocomp(struct omap_sr *sr)
return;
}
- if (!sr_class->enable(sr->voltdm))
+ if (!sr_class->enable(sr->voltdm,
+ omap_voltage_get_nom_volt(sr->voltdm)))
sr->autocomp_active = true;
}
@@ -618,7 +619,7 @@ int sr_configure_minmax(struct voltagedomain *voltdm)
/**
* sr_enable() - Enables the smartreflex module.
* @voltdm: VDD pointer to which the SR module to be configured belongs to.
- * @volt: The voltage at which the Voltage domain associated with
+ * @volt_data: The voltage at which the Voltage domain associated with
* the smartreflex module is operating at.
* This is required only to program the correct Ntarget value.
*
@@ -626,10 +627,9 @@ int sr_configure_minmax(struct voltagedomain *voltdm)
* enable a smartreflex module. Returns 0 on success. Returns error
* value if the voltage passed is wrong or if ntarget value is wrong.
*/
-int sr_enable(struct voltagedomain *voltdm, unsigned long volt)
+int sr_enable(struct voltagedomain *voltdm, struct omap_volt_data *volt_data)
{
u32 nvalue_reciprocal;
- struct omap_volt_data *volt_data;
struct omap_sr *sr = _sr_lookup(voltdm);
int ret;
@@ -639,19 +639,16 @@ int sr_enable(struct voltagedomain *voltdm, unsigned long volt)
return -EINVAL;
}
- volt_data = omap_voltage_get_voltdata(sr->voltdm, volt);
-
- if (IS_ERR(volt_data)) {
- dev_warn(&sr->pdev->dev, "%s: Unable to get voltage table"
- "for nominal voltage %ld\n", __func__, volt);
- return -ENODATA;
+ if (IS_ERR_OR_NULL(volt_data)) {
+ dev_warn(&sr->pdev->dev, "%s: bad voltage data\n", __func__);
+ return -EINVAL;
}
nvalue_reciprocal = sr_retrieve_nvalue(sr, volt_data->sr_efuse_offs);
if (!nvalue_reciprocal) {
dev_warn(&sr->pdev->dev, "%s: NVALUE = 0 at voltage %ld\n",
- __func__, volt);
+ __func__, omap_get_operation_voltage(volt_data));
return -ENODATA;
}
@@ -808,13 +805,15 @@ int sr_register_class(struct omap_sr_class_data *class_data)
* omap_sr_enable() - API to enable SR clocks and to call into the
* registered smartreflex class enable API.
* @voltdm: VDD pointer to which the SR module to be configured belongs to.
+ * @volt_data: Voltage data to go to
*
* This API is to be called from the kernel in order to enable
* a particular smartreflex module. This API will do the initial
* configurations to turn on the smartreflex module and in turn call
* into the registered smartreflex class enable API.
*/
-void omap_sr_enable(struct voltagedomain *voltdm)
+void omap_sr_enable(struct voltagedomain *voltdm,
+ struct omap_volt_data *volt_data)
{
struct omap_sr *sr = _sr_lookup(voltdm);
@@ -833,7 +832,7 @@ void omap_sr_enable(struct voltagedomain *voltdm)
return;
}
- sr_class->enable(voltdm);
+ sr_class->enable(voltdm, volt_data);
}
/**
diff --git a/arch/arm/plat-omap/include/plat/smartreflex.h b/arch/arm/plat-omap/include/plat/smartreflex.h
index d420f44..07f35b2 100644
--- a/arch/arm/plat-omap/include/plat/smartreflex.h
+++ b/arch/arm/plat-omap/include/plat/smartreflex.h
@@ -185,7 +185,8 @@ struct omap_sr_pmic_data {
* @class_priv_data: Class specific private data (optional)
*/
struct omap_sr_class_data {
- int (*enable)(struct voltagedomain *voltdm);
+ int (*enable)(struct voltagedomain *voltdm,
+ struct omap_volt_data *volt_data);
int (*disable)(struct voltagedomain *voltdm, int is_volt_reset);
int (*class_init)(struct voltagedomain *voltdm, void *class_priv_data);
int (*class_deinit)(struct voltagedomain *voltdm,
@@ -232,7 +233,8 @@ struct omap_sr_data {
};
/* Smartreflex module enable/disable interface */
-void omap_sr_enable(struct voltagedomain *voltdm);
+void omap_sr_enable(struct voltagedomain *voltdm,
+ struct omap_volt_data *volt_data);
void omap_sr_disable(struct voltagedomain *voltdm);
void omap_sr_disable_reset_volt(struct voltagedomain *voltdm);
@@ -240,7 +242,7 @@ void omap_sr_disable_reset_volt(struct voltagedomain *voltdm);
void omap_sr_register_pmic(struct omap_sr_pmic_data *pmic_data);
/* Smartreflex driver hooks to be called from Smartreflex class driver */
-int sr_enable(struct voltagedomain *voltdm, unsigned long volt);
+int sr_enable(struct voltagedomain *voltdm, struct omap_volt_data *volt_data);
void sr_disable(struct voltagedomain *voltdm);
int sr_notifier_control(struct voltagedomain *voltdm, bool enable);
int sr_configure_errgen(struct voltagedomain *voltdm);
--
1.7.1
^ permalink raw reply related
* [PATCH v2 17/18] omap3630+: sr: add support for class 1.5
From: Nishanth Menon @ 2011-03-02 10:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1299063331-27968-1-git-send-email-nm@ti.com>
Traditional SmartReflex AVS(Automatic Voltage Scaling) classes are:
* Class 0 - Product test calibration
Silicon is calibration at production floor and fused with voltages
for each OPP
* Class 1 - Boot time calibration
Silicon is calibrated once at boot time and voltages are stored for
the lifetime of operation.
* Class 2 - continuous s/w calibration
SR module notifies s/w for any change in the system which is desired
and the s/w makes runtime decisions in terms of setting the voltage,
this mechanism could be used in the system which does not have PMIC
capable of SR without using the voltage controller and voltage
processor blocks.
* Class 3 - continuous h/w calibration
SR module is switch on after reaching a voltage level and SR
continuously monitors the system and makes runtime adjustments without
s/w involvement.
OMAP3430 has used SmartReflex AVS and with a a PMIC which understands the SR
protocol, Class 3 has been used. With OMAP3630 onwards, a new SmartReflex AVS
class of operation Class 1.5 was introduced.
* Class 1.5 - periodic s/w calibration
This uses the h/w calibration loop and at the end of calibration
stores the voltages to be used run time, periodic recalibration is
performed as well.
The operational mode is describes as the following:
* SmartReflex AVS h/w calibration loop is essential to identify the optimal
voltage for a given OPP.
* Once this optimal voltage is detected, SmartReflex AVS loop is disabled in
class 1.5 mode of operation.
* Until there is a need for a recalibration, any further transition to an OPP
voltage which is calibrated can use the calibrated voltage and does not
require enabling the SR AVS h/w loop.
* On a periodic basis (recommendation being once approximately every 24 hours),
software is expected to perform a recalibration to find a new optimal
voltage which is compensated for device aging.
- For performing this recalibration, the start voltage does not need to
be the nominal voltage anymore. instead, the system can start with a
voltage which is 50mV higher than the previously calibrated voltage to
identify the new optimal voltage as the aging factor within a period of
1 day is not going to be anywhere close to 50mV.
- This "new starting point" for recalibration is called a dynamic
nominal voltage for that voltage point.
In short, with the introduction of SmartReflex class 1.5, there are three new
voltages possible in a system's dvfs transition:
* Nominal Voltage - The maximum voltage needed for a worst possible device
in the worst possible conditions. This is the voltage we choose as
the starting point for the h/w loop to optimize for the first time
calibration on system bootup.
* Dynamic Nominal Voltage - Worst case voltage for a specific device in
considering the system aging on the worst process device.
* Calibrated Voltage - Best voltage for the current device at a given point
of time.
In terms of the implementation, doing calibration involves waiting for the
smartreflex h/w loop to settle down, and doing this as part of the dvfs flow
itself is to increase the latency of dvfs transition when there is a need to
calibrate that opp. instead, the calibration is performed "out of path" using
a workqueue statemachine. The workqueue waits for the system stabilization,
then enables VP interrupts to monitor for system instability interms of voltage
oscillations that are reported back to the system as interrupts, in case of
prolonged system oscillations, nominal voltage is chosen as a safe voltage and
this event is logged in the system log for developer debug and fixing.
For the recalibration, a common workqueue for all domains is started at the
start of the class initialization and it resets the calibrated voltages
on a periodic basis. For distros that may choose not to do the recommended
periodic recalibration, instead choose to perform boot time calibration,
kconfig configuration option is provided to do so.
TODO:
a) Cpuidle and suspend paths are not integrated with SmartReflex driver at
this point.
b) Since the SR registers are accessed and controlled in parallel to DVFS
some sort of mechanism is necessary to be introduced along with OMAP
dvfs layer to ensure mutual exclusivity
c) Additional debug interfaces for vmin analysis for platform characterization
and addition of system margin needs to be introduced from smartreflex
perspective.
This implementation also includes the following contributors:
Tony Lindgren for suggestion on using interrupt based mechanism instead of
polling to detect voltage oscillations.
Peter 'p2' De Schrijver for debating alternatives on recalibration mechanisms
Paul Walmsey, Eduardo Valentin, Ambresh K, Igor Dmitriev and quiet a few others
for patient review, testing and reporting of issues of a previous incarnation
of this implemenation. Last, but not the least, the TI H/w team in introducing
this new SR AVS class and patiently debating it's various facets.
Cc: Ambresh K <ambresh@ti.com>
Cc: Eduardo Valentin <eduardo.valentin@nokia.com>
Cc: Igor Dmitriev <ext-dmitriev.igor@nokia.com>
Cc: Paul <paul@pwsan.com>
Cc: Peter 'p2' De Schrijver <Peter.De-Schrijver@nokia.com>
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
---
arch/arm/mach-omap2/Makefile | 1 +
arch/arm/mach-omap2/smartreflex-class1p5.c | 582 +++++++++++++++++++++++++
arch/arm/mach-omap2/smartreflex-class3.c | 4 +-
arch/arm/mach-omap2/smartreflex.c | 34 ++-
arch/arm/mach-omap2/voltage.c | 79 ++++
arch/arm/plat-omap/Kconfig | 17 +
arch/arm/plat-omap/include/plat/smartreflex.h | 13 +-
arch/arm/plat-omap/include/plat/voltage.h | 23 +-
8 files changed, 745 insertions(+), 8 deletions(-)
create mode 100644 arch/arm/mach-omap2/smartreflex-class1p5.c
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 1c0c2b0..1a82e6d 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -66,6 +66,7 @@ obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o voltage.o pm_bus.o
obj-$(CONFIG_PM_DEBUG) += pm-debug.o
obj-$(CONFIG_OMAP_SMARTREFLEX) += sr_device.o smartreflex.o
obj-$(CONFIG_OMAP_SMARTREFLEX_CLASS3) += smartreflex-class3.o
+obj-$(CONFIG_OMAP_SMARTREFLEX_CLASS1P5) += smartreflex-class1p5.o
AFLAGS_sleep24xx.o :=-Wa,-march=armv6
AFLAGS_sleep34xx.o :=-Wa,-march=armv7-a
diff --git a/arch/arm/mach-omap2/smartreflex-class1p5.c b/arch/arm/mach-omap2/smartreflex-class1p5.c
new file mode 100644
index 0000000..14ddb42
--- /dev/null
+++ b/arch/arm/mach-omap2/smartreflex-class1p5.c
@@ -0,0 +1,582 @@
+/*
+ * Smart reflex Class 1.5 specific implementations
+ *
+ * Copyright (C) 2010-2011 Texas Instruments, Inc.
+ * Nishanth Menon <nm@ti.com>
+ *
+ * Smart reflex class 1.5 is also called periodic SW Calibration
+ * Some of the highlights are as follows:
+ * ??? Host CPU triggers OPP calibration when transitioning to non calibrated
+ * OPP
+ * ??? SR-AVS + VP modules are used to perform calibration
+ * ??? Once completed, the SmartReflex-AVS module can be disabled
+ * ??? Enables savings based on process, supply DC accuracy and aging
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/fs.h>
+#include <linux/string.h>
+#include <linux/uaccess.h>
+#include <linux/kobject.h>
+#include <linux/workqueue.h>
+#include <linux/opp.h>
+
+#include <plat/smartreflex.h>
+#include <plat/voltage.h>
+
+#define MAX_VDDS 3
+#define SR1P5_SAMPLING_DELAY_MS 1
+#define SR1P5_STABLE_SAMPLES 5
+#define SR1P5_MAX_TRIGGERS 5
+
+/*
+ * we expect events in 10uS, if we dont get 2wice times as much,
+ * we could kind of ignore this as a missed event.
+ */
+#define MAX_CHECK_VPTRANS_US 20
+
+/**
+ * struct sr_class1p5_work_data - data meant to be used by calibration work
+ * @work: calibration work
+ * @voltdm: voltage domain for which we are triggering
+ * @vdata: voltage data we are calibrating
+ * @num_calib_triggers: number of triggers from calibration loop
+ * @num_osc_samples: number of samples collected by isr
+ * @work_active: have we scheduled a work item?
+ */
+struct sr_class1p5_work_data {
+ struct delayed_work work;
+ struct voltagedomain *voltdm;
+ struct omap_volt_data *vdata;
+ u8 num_calib_triggers;
+ u8 num_osc_samples;
+ bool work_active;
+};
+
+#if CONFIG_OMAP_SR_CLASS1P5_RECALIBRATION_DELAY
+/* recal_work: recalibration calibration work */
+static struct delayed_work recal_work;
+#endif
+
+/**
+ * struct sr_class1p5_data - private data for class 1p5
+ * @work_data: work item data per voltage domain
+ */
+struct sr_class1p5_data {
+ struct sr_class1p5_work_data work_data[MAX_VDDS];
+};
+
+static void sr_class1p5_reset_calib(struct voltagedomain *voltdm, bool reset,
+ bool recal);
+
+/* our instance of class 1p5 private data */
+static struct sr_class1p5_data class_1p5_data;
+
+static struct sr_class1p5_work_data *get_sr1p5_work(struct voltagedomain
+ *voltdm)
+{
+ int idx;
+ for (idx = 0; idx < MAX_VDDS; idx++) {
+ if (class_1p5_data.work_data[idx].voltdm && !strcmp
+ (class_1p5_data.work_data[idx].voltdm->name, voltdm->name))
+ return &class_1p5_data.work_data[idx];
+ }
+ return ERR_PTR(-ENODATA);
+}
+
+/**
+ * sr_class1p5_notify() - isr notifier for status events
+ * @voltdm: voltage domain for which we were triggered
+ * @status: notifier event to use
+ *
+ * This basically collects data for the work to use.
+ */
+static int sr_class1p5_notify(struct voltagedomain *voltdm, u32 status)
+{
+ struct sr_class1p5_work_data *work_data;
+ int idx = 0;
+
+ if (IS_ERR_OR_NULL(voltdm)) {
+ pr_err("%s: bad parameters!\n", __func__);
+ return -EINVAL;
+ }
+
+ work_data = get_sr1p5_work(voltdm);
+ if (unlikely(!work_data)) {
+ pr_err("%s:%s no work data!!\n", __func__, voltdm->name);
+ return -EINVAL;
+ }
+
+ /* Wait for transdone so that we know the voltage to read */
+ do {
+ if (omap_vp_is_transdone(voltdm))
+ break;
+ idx++;
+ /* get some constant delay */
+ udelay(1);
+ } while (idx < MAX_CHECK_VPTRANS_US);
+
+ /*
+ * If we timeout, we still read the data,
+ * if we are oscillating+irq latencies are too high, we could
+ * have scenarios where we miss transdone event. since
+ * we waited long enough, it is still safe to read the voltage
+ * as we would have waited long enough - still flag it..
+ */
+ if (idx >= MAX_CHECK_VPTRANS_US)
+ pr_warning("%s: timed out waiting for transdone!!\n", __func__);
+
+ omap_vp_clear_transdone(voltdm);
+
+ idx = (work_data->num_osc_samples) % SR1P5_STABLE_SAMPLES;
+ work_data->num_osc_samples++;
+
+ return 0;
+}
+
+/**
+ * do_calibrate() - work which actually does the calibration
+ * @work: pointer to the work
+ *
+ * calibration routine uses the following logic:
+ * on the first trigger, we start the isr to collect sr voltages
+ * wait for stabilization delay (reschdule self instead of sleeping)
+ * after the delay, see if we collected any isr events
+ * if none, we have calibrated voltage.
+ * if there are any, we retry untill we giveup.
+ * on retry timeout, select a voltage to use as safe voltage.
+ */
+static void do_calibrate(struct work_struct *work)
+{
+ struct sr_class1p5_work_data *work_data =
+ container_of(work, struct sr_class1p5_work_data, work.work);
+ unsigned long u_volt_safe = 0, u_volt_current = 0;
+ struct omap_volt_data *volt_data;
+ struct voltagedomain *voltdm;
+
+ if (unlikely(!work_data)) {
+ pr_err("%s: ooops.. null work_data?\n", __func__);
+ return;
+ }
+
+ /*
+ * TODO:Handle the case where we might have just been scheduled AND
+ * 1.5 disable was called. check and HOLD dvfs
+ */
+
+ voltdm = work_data->voltdm;
+ /*
+ * In the unlikely case that we did get through when unplanned,
+ * flag and return.
+ */
+ if (unlikely(!work_data->work_active)) {
+ pr_err("%s:%s unplanned work invocation!\n", __func__,
+ voltdm->name);
+ /* TODO release the dvfs */
+ return;
+ }
+
+ work_data->num_calib_triggers++;
+ /* if we are triggered first time, we need to start isr to sample */
+ if (work_data->num_calib_triggers == 1)
+ goto start_sampling;
+
+ /* Stop isr from interrupting our measurements :) */
+ sr_notifier_control(voltdm, false);
+
+ volt_data = work_data->vdata;
+
+ /* if there are no samples captured.. SR is silent, aka stability! */
+ if (!work_data->num_osc_samples) {
+ u_volt_safe = omap_vp_get_curr_volt(voltdm);
+ u_volt_current = u_volt_safe;
+ goto done_calib;
+ }
+ if (work_data->num_calib_triggers == SR1P5_MAX_TRIGGERS) {
+ pr_warning("%s: %s recalib timeout!\n", __func__,
+ work_data->voltdm->name);
+ goto oscillating_calib;
+ }
+
+ /* we have potential oscillations/first sample */
+start_sampling:
+ work_data->num_osc_samples = 0;
+ /* Clear pending events */
+ sr_notifier_control(voltdm, false);
+ /* Clear all transdones */
+ while (omap_vp_is_transdone(voltdm))
+ omap_vp_clear_transdone(voltdm);
+ /* trigger sampling */
+ sr_notifier_control(voltdm, true);
+ schedule_delayed_work(&work_data->work,
+ msecs_to_jiffies(SR1P5_SAMPLING_DELAY_MS *
+ SR1P5_STABLE_SAMPLES));
+ /* TODO: release dvfs */
+ return;
+
+oscillating_calib:
+ /* Use the nominal voltage as the safe voltage */
+ u_volt_safe = volt_data->volt_nominal;
+ /* pick up current voltage to switch if needed */
+ u_volt_current = omap_vp_get_curr_volt(voltdm);
+
+ /* Fall through to close up common stuff */
+done_calib:
+ omap_vp_disable(voltdm);
+ sr_disable(voltdm);
+
+ volt_data->volt_calibrated = u_volt_safe;
+ /* Setup my dynamic voltage for the next calibration for this opp */
+ volt_data->volt_dynamic_nominal = omap_get_dyn_nominal(volt_data);
+
+ /*
+ * if the voltage we decided as safe is not the current voltage,
+ * switch
+ */
+ if (volt_data->volt_calibrated != u_volt_current) {
+ pr_debug("%s:%s reconfiguring to voltage %d\n",
+ __func__, voltdm->name, volt_data->volt_calibrated);
+ omap_voltage_scale_vdd(voltdm, volt_data);
+ }
+
+ /*
+ * TODO: Setup my wakeup voltage to allow immediate going to OFF and
+ * on - Pending twl and voltage layer cleanups.
+ * This is necessary, as this is not done as part of regular
+ * Dvfs flow.
+ * vc_setup_on_voltage(voltdm, volt_data->volt_calibrated);
+ */
+ work_data->work_active = false;
+ /* TODO: release dvfs */
+}
+
+#if CONFIG_OMAP_SR_CLASS1P5_RECALIBRATION_DELAY
+/**
+ * do_recalibrate() - work which actually does the calibration
+ * @work: pointer to the work
+ *
+ * on a periodic basis, we come and reset our calibration setup
+ * so that a recalibration of the OPPs take place. This takes
+ * care of aging factor in the system.
+ */
+static void do_recalibrate(struct work_struct *work)
+{
+ struct voltagedomain *voltdm;
+ int idx;
+ static struct sr_class1p5_work_data *work_data;
+
+ for (idx = 0; idx < MAX_VDDS; idx++) {
+ work_data = &class_1p5_data.work_data[idx];
+ voltdm = work_data->voltdm;
+ if (voltdm) {
+ /* if sr is not enabled, we check later */
+ if (!is_sr_enabled(voltdm))
+ continue;
+ /* TODO: Pause the dvfs transitions */
+ /* if sr is not enabled, we check later */
+
+ /* Reset and force a recalibration for current opp */
+ sr_class1p5_reset_calib(voltdm, true, true);
+
+ /* TODO: unpause DVFS transitions */
+ }
+ }
+ /* We come back again after time the usual delay */
+ schedule_delayed_work(&recal_work,
+ msecs_to_jiffies(CONFIG_OMAP_SR_CLASS1P5_RECALIBRATION_DELAY));
+}
+#endif /* CONFIG_OMAP_SR_CLASS1P5_RECALIBRATION_DELAY */
+
+/**
+ * sr_class1p5_enable() - class 1.5 mode of enable
+ * @voltdm: voltage domain to enable SR for
+ * @volt_data: voltdata to the voltage transition taking place
+ *
+ * when this gets called, we use the h/w loop to setup our voltages
+ * to an calibrated voltage, detect any oscillations, recover from the same
+ * and finally store the optimized voltage as the calibrated voltage in the
+ * system
+ */
+static int sr_class1p5_enable(struct voltagedomain *voltdm,
+ struct omap_volt_data *volt_data)
+{
+ int r;
+ struct sr_class1p5_work_data *work_data;
+
+ if (IS_ERR_OR_NULL(voltdm) || IS_ERR_OR_NULL(volt_data)) {
+ pr_err("%s: bad parameters!\n", __func__);
+ return -EINVAL;
+ }
+
+ /* if already calibrated, nothing to do here.. */
+ if (volt_data->volt_calibrated)
+ return 0;
+
+ work_data = get_sr1p5_work(voltdm);
+ if (unlikely(!work_data)) {
+ pr_err("%s: aieeee.. bad work data??\n", __func__);
+ return -EINVAL;
+ }
+
+ if (work_data->work_active)
+ return 0;
+
+ omap_vp_enable(voltdm);
+ r = sr_enable(voltdm, volt_data);
+ if (r) {
+ pr_err("%s: sr[%s] failed\n", __func__, voltdm->name);
+ omap_vp_disable(voltdm);
+ return r;
+ }
+ work_data->vdata = volt_data;
+ work_data->work_active = true;
+ work_data->num_calib_triggers = 0;
+ /* program the workqueue and leave it to calibrate offline.. */
+ schedule_delayed_work(&work_data->work,
+ msecs_to_jiffies(SR1P5_SAMPLING_DELAY_MS *
+ SR1P5_STABLE_SAMPLES));
+
+ return 0;
+}
+
+/**
+ * sr_class1p5_disable() - disable for class 1p5
+ * @voltdm: voltage domain for the sr which needs disabling
+ * @volt_data: voltagedata to disable
+ * @is_volt_reset: reset the voltage?
+ *
+ * we dont do anything if the class 1p5 is being used. this is because we
+ * already disable sr at the end of calibration and no h/w loop is actually
+ * active when this is called.
+ */
+static int sr_class1p5_disable(struct voltagedomain *voltdm,
+ struct omap_volt_data *volt_data,
+ int is_volt_reset)
+{
+ struct sr_class1p5_work_data *work_data;
+
+ if (IS_ERR_OR_NULL(voltdm) || IS_ERR_OR_NULL(volt_data)) {
+ pr_err("%s: bad parameters!\n", __func__);
+ return -EINVAL;
+ }
+
+ work_data = get_sr1p5_work(voltdm);
+ if (work_data->work_active) {
+ /* if volt reset and work is active, we dont allow this */
+ if (is_volt_reset)
+ return -EBUSY;
+ /* flag work is dead and remove the old work */
+ work_data->work_active = false;
+ cancel_delayed_work_sync(&work_data->work);
+ sr_notifier_control(voltdm, false);
+ omap_vp_disable(voltdm);
+ sr_disable(voltdm);
+ }
+
+ /* if already calibrated, nothin special to do here.. */
+ if (volt_data->volt_calibrated)
+ return 0;
+
+ if (is_volt_reset)
+ omap_voltage_reset(voltdm);
+ return 0;
+}
+
+/**
+ * sr_class1p5_configure() - configuration function
+ * @voldm: configure for which voltage domain
+ *
+ * we dont do much here other than setup some registers for
+ * the sr module involved.
+ */
+static int sr_class1p5_configure(struct voltagedomain *voltdm)
+{
+ if (IS_ERR_OR_NULL(voltdm)) {
+ pr_err("%s: bad parameters!\n", __func__);
+ return -EINVAL;
+ }
+
+ return sr_configure_errgen(voltdm);
+}
+
+/**
+ * sr_class1p5_reset_calib() - reset all calibrated voltages
+ * @srid: srid to reset the calibration for
+ * @reset: reset voltage before we recal?
+ * @recal: should I recalibrate my current opp?
+ *
+ * if we call this, it means either periodic calibration trigger was
+ * fired(either from sysfs or other mechanisms) or we have disabled class 1p5,
+ * meaning we cant trust the calib voltages anymore, it is better to use
+ * nominal in the system
+ */
+static void sr_class1p5_reset_calib(struct voltagedomain *voltdm, bool reset,
+ bool recal)
+{
+ struct sr_class1p5_work_data *work_data;
+
+ /* I dont need to go further if sr is not present */
+ if (!is_sr_enabled(voltdm))
+ return;
+
+ work_data = get_sr1p5_work(voltdm);
+
+ if (work_data->work_active)
+ sr_class1p5_disable(voltdm, work_data->vdata, 0);
+
+ omap_voltage_calib_reset(voltdm);
+
+ /*
+ * I should now reset the voltages to my nominal to be safe
+ */
+ if (reset)
+ omap_voltage_reset(voltdm);
+
+ /*
+ * I should fire a recalibration for current opp if needed
+ * Note: i have just reset my calibrated voltages, and if
+ * i call sr_enable equivalent, I will cause a recalibration
+ * loop, even though the function is called sr_enable.. we
+ * are in class 1.5 ;)
+ */
+ if (reset && recal)
+ sr_class1p5_enable(voltdm, work_data->vdata);
+}
+
+/**
+ * sr_class1p5_cinit() - class 1p5 init
+ * @voltdm: sr voltage domain
+ * @class_priv_data: private data for the class
+ *
+ * we do class specific initialization like creating sysfs/debugfs entries
+ * needed, spawning of a kthread if needed etc.
+ */
+static int sr_class1p5_cinit(struct voltagedomain *voltdm,
+ void *class_priv_data)
+{
+ struct sr_class1p5_work_data *work_data;
+ int idx;
+
+ if (IS_ERR_OR_NULL(voltdm) || IS_ERR_OR_NULL(class_priv_data)) {
+ pr_err("%s: bad parameters!\n", __func__);
+ return -EINVAL;
+ }
+
+ /* setup our work params */
+ work_data = get_sr1p5_work(voltdm);
+ if (!IS_ERR_OR_NULL(work_data)) {
+ pr_err("%s: ooopps.. class already initialized for %s! bug??\n",
+ __func__, voltdm->name);
+ return -EINVAL;
+ }
+ work_data = NULL;
+ /* get the next spare work_data */
+ for (idx = 0; idx < MAX_VDDS; idx++) {
+ if (!class_1p5_data.work_data[idx].voltdm) {
+ work_data = &class_1p5_data.work_data[idx];
+ break;
+ }
+ }
+ if (!work_data) {
+ pr_err("%s: no more space for work data for domains!\n",
+ __func__);
+ return -ENOMEM;
+ }
+ work_data->voltdm = voltdm;
+ INIT_DELAYED_WORK_DEFERRABLE(&work_data->work, do_calibrate);
+ return 0;
+}
+
+/**
+ * sr_class1p5_cdeinit() - class 1p5 deinitialization
+ * @voltdm: voltage domain for which to do this.
+ * @class_priv_data: class private data for deinitialiation
+ *
+ * currently only resets the calibrated voltage forcing dvfs voltages
+ * to be used in the system
+ */
+static int sr_class1p5_cdeinit(struct voltagedomain *voltdm,
+ void *class_priv_data)
+{
+ struct sr_class1p5_work_data *work_data;
+
+ if (IS_ERR_OR_NULL(voltdm) || IS_ERR_OR_NULL(class_priv_data)) {
+ pr_err("%s: bad parameters!\n", __func__);
+ return -EINVAL;
+ }
+
+ /* setup our work params */
+ work_data = get_sr1p5_work(voltdm);
+ if (IS_ERR_OR_NULL(work_data)) {
+ pr_err("%s: ooopps.. class not initialized for %s! bug??\n",
+ __func__, voltdm->name);
+ return -EINVAL;
+ }
+
+ /*
+ * we dont have SR periodic calib anymore.. so reset calibs
+ * we are already protected by sr debugfs lock, so no lock needed
+ * here.
+ */
+ sr_class1p5_reset_calib(voltdm, true, false);
+
+ /* reset all data for this work data */
+ memset(work_data, 0, sizeof(*work_data));
+
+ return 0;
+}
+
+/* SR class1p5 structure */
+static struct omap_sr_class_data class1p5_data = {
+ .enable = sr_class1p5_enable,
+ .disable = sr_class1p5_disable,
+ .configure = sr_class1p5_configure,
+ .class_type = SR_CLASS1P5,
+ .class_init = sr_class1p5_cinit,
+ .class_deinit = sr_class1p5_cdeinit,
+ .notify = sr_class1p5_notify,
+ /*
+ * trigger for bound - this tells VP that SR has a voltage
+ * change. we should ensure transdone is set before reading
+ * vp voltage.
+ */
+ .notify_flags = SR_NOTIFY_MCUBOUND,
+ .class_priv_data = (void *)&class_1p5_data,
+};
+
+/**
+ * sr_class1p5_init() - register class 1p5 as default
+ *
+ * board files call this function to use class 1p5, we register with the
+ * smartreflex subsystem
+ */
+static int __init sr_class1p5_init(void)
+{
+ int r;
+
+ /* Enable this class only for OMAP3630 and OMAP4 */
+ if (!(cpu_is_omap3630() || cpu_is_omap44xx()))
+ return -EINVAL;
+
+ r = sr_register_class(&class1p5_data);
+ if (r) {
+ pr_err("SmartReflex class 1.5 driver: "
+ "failed to register with %d\n", r);
+ } else {
+#if CONFIG_OMAP_SR_CLASS1P5_RECALIBRATION_DELAY
+ INIT_DELAYED_WORK_DEFERRABLE(&recal_work, do_recalibrate);
+ schedule_delayed_work(&recal_work, msecs_to_jiffies(
+ CONFIG_OMAP_SR_CLASS1P5_RECALIBRATION_DELAY));
+#endif
+ pr_info("SmartReflex class 1.5 driver: initialized (%dms)\n",
+ CONFIG_OMAP_SR_CLASS1P5_RECALIBRATION_DELAY);
+ }
+ return r;
+}
+late_initcall(sr_class1p5_init);
diff --git a/arch/arm/mach-omap2/smartreflex-class3.c b/arch/arm/mach-omap2/smartreflex-class3.c
index 7ac88da..5f7a33e 100644
--- a/arch/arm/mach-omap2/smartreflex-class3.c
+++ b/arch/arm/mach-omap2/smartreflex-class3.c
@@ -21,7 +21,9 @@ static int sr_class3_enable(struct voltagedomain *voltdm,
return sr_enable(voltdm, volt_data);
}
-static int sr_class3_disable(struct voltagedomain *voltdm, int is_volt_reset)
+static int sr_class3_disable(struct voltagedomain *voltdm,
+ struct omap_volt_data *vdata,
+ int is_volt_reset)
{
omap_vp_disable(voltdm);
sr_disable(voltdm);
diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
index 9b9d380..2e74b1e 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -317,7 +317,9 @@ static void sr_stop_vddautocomp(struct omap_sr *sr)
}
if (sr->autocomp_active) {
- sr_class->disable(sr->voltdm, 1);
+ sr_class->disable(sr->voltdm,
+ omap_voltage_get_nom_volt(sr->voltdm),
+ 1);
if (sr_class->class_deinit &&
sr_class->class_deinit(sr->voltdm,
sr_class->class_priv_data)) {
@@ -471,6 +473,28 @@ static u32 sr_retrieve_nvalue(struct omap_sr *sr, u32 efuse_offs)
/* Public Functions */
/**
+ * is_sr_enabled() - is Smart reflex enabled for this domain?
+ * @voltdm: voltage domain to check
+ *
+ * Returns 0 if SR is enabled for this domain, else returns err
+ */
+bool is_sr_enabled(struct voltagedomain *voltdm)
+{
+ struct omap_sr *sr;
+ if (IS_ERR_OR_NULL(voltdm)) {
+ pr_warning("%s: invalid param voltdm\n", __func__);
+ return false;
+ }
+ sr = _sr_lookup(voltdm);
+ if (IS_ERR(sr)) {
+ pr_warning("%s: omap_sr struct for sr_%s not found\n",
+ __func__, voltdm->name);
+ return false;
+ }
+ return sr->autocomp_active;
+}
+
+/**
* sr_configure_errgen() - Configures the smrtreflex to perform AVS using the
* error generator module.
* @voltdm: VDD pointer to which the SR module to be configured belongs to.
@@ -839,6 +863,7 @@ void omap_sr_enable(struct voltagedomain *voltdm,
* omap_sr_disable() - API to disable SR without resetting the voltage
* processor voltage
* @voltdm: VDD pointer to which the SR module to be configured belongs to.
+ * @volt_data: Voltage data to go to
*
* This API is to be called from the kernel in order to disable
* a particular smartreflex module. This API will in turn call
@@ -846,7 +871,8 @@ void omap_sr_enable(struct voltagedomain *voltdm,
* the smartreflex class disable not to reset the VP voltage after
* disabling smartreflex.
*/
-void omap_sr_disable(struct voltagedomain *voltdm)
+void omap_sr_disable(struct voltagedomain *voltdm,
+ struct omap_volt_data *vdata)
{
struct omap_sr *sr = _sr_lookup(voltdm);
@@ -865,7 +891,7 @@ void omap_sr_disable(struct voltagedomain *voltdm)
return;
}
- sr_class->disable(voltdm, 0);
+ sr_class->disable(voltdm, vdata, 0);
}
/**
@@ -898,7 +924,7 @@ void omap_sr_disable_reset_volt(struct voltagedomain *voltdm)
return;
}
- sr_class->disable(voltdm, 1);
+ sr_class->disable(voltdm, omap_voltage_get_nom_volt(voltdm), 1);
}
/**
diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
index 3cbe450..da0129b 100644
--- a/arch/arm/mach-omap2/voltage.c
+++ b/arch/arm/mach-omap2/voltage.c
@@ -379,9 +379,55 @@ static int nom_volt_debug_get(void *data, u64 *val)
return 0;
}
+static int dyn_volt_debug_get(void *data, u64 *val)
+{
+ struct omap_vdd_info *vdd = (struct omap_vdd_info *) data;
+ struct omap_volt_data *volt_data;
+
+ if (!vdd) {
+ pr_warning("Wrong paramater passed\n");
+ return -EINVAL;
+ }
+
+ volt_data = omap_voltage_get_nom_volt(&vdd->voltdm);
+ if (IS_ERR_OR_NULL(volt_data)) {
+ pr_warning("%s: No voltage/domain?\n", __func__);
+ return -ENODEV;
+ }
+
+ *val = volt_data->volt_dynamic_nominal;
+
+ return 0;
+}
+
+static int calib_volt_debug_get(void *data, u64 *val)
+{
+ struct omap_vdd_info *vdd = (struct omap_vdd_info *) data;
+ struct omap_volt_data *volt_data;
+
+ if (!vdd) {
+ pr_warning("Wrong paramater passed\n");
+ return -EINVAL;
+ }
+
+ volt_data = omap_voltage_get_nom_volt(&vdd->voltdm);
+ if (IS_ERR_OR_NULL(volt_data)) {
+ pr_warning("%s: No voltage/domain?\n", __func__);
+ return -ENODEV;
+ }
+
+ *val = volt_data->volt_calibrated;
+
+ return 0;
+}
+
DEFINE_SIMPLE_ATTRIBUTE(vp_volt_debug_fops, vp_volt_debug_get, NULL, "%llu\n");
DEFINE_SIMPLE_ATTRIBUTE(nom_volt_debug_fops, nom_volt_debug_get, NULL,
"%llu\n");
+DEFINE_SIMPLE_ATTRIBUTE(dyn_volt_debug_fops, dyn_volt_debug_get, NULL,
+ "%llu\n");
+DEFINE_SIMPLE_ATTRIBUTE(calib_volt_debug_fops, calib_volt_debug_get, NULL,
+ "%llu\n");
static void vp_latch_vsel(struct omap_vdd_info *vdd)
{
u32 vpconfig;
@@ -509,6 +555,12 @@ static void __init vdd_debugfs_init(struct omap_vdd_info *vdd)
(void) debugfs_create_file("curr_nominal_volt", S_IRUGO,
vdd->debug_dir, (void *) vdd,
&nom_volt_debug_fops);
+ (void) debugfs_create_file("curr_dyn_nominal_volt", S_IRUGO,
+ vdd->debug_dir, (void *) vdd,
+ &dyn_volt_debug_fops);
+ (void) debugfs_create_file("curr_calibrated_volt", S_IRUGO,
+ vdd->debug_dir, (void *) vdd,
+ &calib_volt_debug_fops);
}
/* Voltage scale and accessory APIs */
@@ -1137,6 +1189,33 @@ struct omap_volt_data *omap_voltage_get_nom_volt(struct voltagedomain *voltdm)
}
/**
+ * omap_voltage_calib_reset() - reset the calibrated voltage entries
+ * @voltdm: voltage domain to reset the entries for
+ *
+ * when the calibrated entries are no longer valid, this api allows
+ * the calibrated voltages to be reset.
+ */
+int omap_voltage_calib_reset(struct voltagedomain *voltdm)
+{
+ struct omap_vdd_info *vdd;
+ struct omap_volt_data *volt_data;
+
+ if (IS_ERR_OR_NULL(voltdm)) {
+ pr_warning("%s: VDD specified does not exist!\n", __func__);
+ return -EINVAL;
+ }
+
+ vdd = container_of(voltdm, struct omap_vdd_info, voltdm);
+ volt_data = vdd->volt_data;
+ /* reset the calibrated voltages as 0 */
+ while (volt_data->volt_nominal) {
+ volt_data->volt_calibrated = 0;
+ volt_data++;
+ }
+ return 0;
+}
+
+/**
* omap_vp_get_curr_volt() - API to get the current vp voltage.
* @voltdm: pointer to the VDD.
*
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index b6333ae..dba7939 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -67,6 +67,23 @@ config OMAP_SMARTREFLEX_CLASS3
Class 3 implementation of Smartreflex employs continuous hardware
voltage calibration.
+config OMAP_SMARTREFLEX_CLASS1P5
+ bool "Class 1.5 mode of Smartreflex Implementation"
+ depends on OMAP_SMARTREFLEX && TWL4030_CORE
+ help
+ Say Y to enable Class 1.5 implementation of Smartreflex
+ Class 1.5 implementation of Smartreflex employs software controlled
+ hardware voltage calibration.
+
+config OMAP_SR_CLASS1P5_RECALIBRATION_DELAY
+ int "Class 1.5 mode recalibration recalibration delay(ms)"
+ depends on OMAP_SMARTREFLEX_CLASS1P5
+ default 86400000
+ help
+ Setup the recalibration delay in milliseconds. Use 0 for never doing
+ a recalibration. Defaults to recommended recalibration every 24hrs.
+ If you do not understand this, use the default.
+
config OMAP_RESET_CLOCKS
bool "Reset unused clocks during boot"
depends on ARCH_OMAP
diff --git a/arch/arm/plat-omap/include/plat/smartreflex.h b/arch/arm/plat-omap/include/plat/smartreflex.h
index 07f35b2..ee5c58f 100644
--- a/arch/arm/plat-omap/include/plat/smartreflex.h
+++ b/arch/arm/plat-omap/include/plat/smartreflex.h
@@ -167,6 +167,7 @@ struct omap_sr_pmic_data {
#define SR_CLASS1 0x1
#define SR_CLASS2 0x2
#define SR_CLASS3 0x3
+#define SR_CLASS1P5 0x4
/**
* struct omap_sr_class_data - Smartreflex class driver info
@@ -187,7 +188,9 @@ struct omap_sr_pmic_data {
struct omap_sr_class_data {
int (*enable)(struct voltagedomain *voltdm,
struct omap_volt_data *volt_data);
- int (*disable)(struct voltagedomain *voltdm, int is_volt_reset);
+ int (*disable)(struct voltagedomain *voltdm,
+ struct omap_volt_data *volt_data,
+ int is_volt_reset);
int (*class_init)(struct voltagedomain *voltdm, void *class_priv_data);
int (*class_deinit)(struct voltagedomain *voltdm,
void *class_priv_data);
@@ -235,7 +238,8 @@ struct omap_sr_data {
/* Smartreflex module enable/disable interface */
void omap_sr_enable(struct voltagedomain *voltdm,
struct omap_volt_data *volt_data);
-void omap_sr_disable(struct voltagedomain *voltdm);
+void omap_sr_disable(struct voltagedomain *voltdm,
+ struct omap_volt_data *volt_data);
void omap_sr_disable_reset_volt(struct voltagedomain *voltdm);
/* API to register the pmic specific data with the smartreflex driver. */
@@ -250,6 +254,7 @@ int sr_configure_minmax(struct voltagedomain *voltdm);
/* API to register the smartreflex class driver with the smartreflex driver */
int sr_register_class(struct omap_sr_class_data *class_data);
+bool is_sr_enabled(struct voltagedomain *voltdm);
#else
static inline void omap_sr_enable(struct voltagedomain *voltdm) {}
static inline void omap_sr_disable(struct voltagedomain *voltdm) {}
@@ -264,5 +269,9 @@ static inline void omap_sr_disable_reset_volt(
struct voltagedomain *voltdm) {}
static inline void omap_sr_register_pmic(
struct omap_sr_pmic_data *pmic_data) {}
+static inline bool is_sr_enabled(struct voltagedomain *voltdm)
+{
+ return false;
+}
#endif
#endif
diff --git a/arch/arm/plat-omap/include/plat/voltage.h b/arch/arm/plat-omap/include/plat/voltage.h
index 816a785..a11b7c3 100644
--- a/arch/arm/plat-omap/include/plat/voltage.h
+++ b/arch/arm/plat-omap/include/plat/voltage.h
@@ -58,6 +58,8 @@
#define OMAP4430_VDD_CORE_OPP50_UV 930000
#define OMAP4430_VDD_CORE_OPP100_UV 1100000
+#define OMAP3PLUS_DYNAMIC_NOMINAL_MARGIN_UV 50000
+
/**
* struct voltagedomain - omap voltage domain global structure.
* @name: Name of the voltage domain which can be used as a unique
@@ -81,6 +83,8 @@ struct voltagedomain {
*/
struct omap_volt_data {
u32 volt_nominal;
+ u32 volt_calibrated;
+ u32 volt_dynamic_nominal;
u32 sr_efuse_offs;
u8 sr_errminlimit;
u8 vp_errgain;
@@ -127,6 +131,7 @@ struct omap_volt_data *omap_voltage_get_nom_volt(struct voltagedomain *voltdm);
bool omap_vp_is_transdone(struct voltagedomain *voltdm);
bool omap_vp_clear_transdone(struct voltagedomain *voltdm);
struct dentry *omap_voltage_get_dbgdir(struct voltagedomain *voltdm);
+int omap_voltage_calib_reset(struct voltagedomain *voltdm);
#ifdef CONFIG_PM
int omap_voltage_register_pmic(struct voltagedomain *voltdm,
struct omap_volt_pmic_info *pmic_info);
@@ -160,7 +165,23 @@ static inline unsigned long omap_get_operation_voltage(
{
if (IS_ERR_OR_NULL(vdata))
return 0;
- return vdata->volt_nominal;
+ return (vdata->volt_calibrated) ? vdata->volt_calibrated :
+ (vdata->volt_dynamic_nominal) ? vdata->volt_dynamic_nominal :
+ vdata->volt_nominal;
}
+/* what is my dynamic nominal? */
+static inline unsigned long omap_get_dyn_nominal(struct omap_volt_data *vdata)
+{
+ if (IS_ERR_OR_NULL(vdata))
+ return 0;
+ if (vdata->volt_calibrated) {
+ unsigned long v = vdata->volt_calibrated +
+ OMAP3PLUS_DYNAMIC_NOMINAL_MARGIN_UV;
+ if (v > vdata->volt_nominal)
+ return vdata->volt_nominal;
+ return v;
+ }
+ return vdata->volt_nominal;
+}
#endif
--
1.7.1
^ permalink raw reply related
* [PATCH v2 18/18] omap3430: sr: class3: restrict cpu to run on
From: Nishanth Menon @ 2011-03-02 10:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1299063331-27968-1-git-send-email-nm@ti.com>
Use SmartReflex AVS Class3 initialization only for OMAP343x family of
processors.
Signed-off-by: Nishanth Menon <nm@ti.com>
---
arch/arm/mach-omap2/smartreflex-class3.c | 5 +++++
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/smartreflex-class3.c b/arch/arm/mach-omap2/smartreflex-class3.c
index 5f7a33e..f99e517 100644
--- a/arch/arm/mach-omap2/smartreflex-class3.c
+++ b/arch/arm/mach-omap2/smartreflex-class3.c
@@ -11,6 +11,7 @@
* published by the Free Software Foundation.
*/
+#include <plat/cpu.h>
#include <plat/smartreflex.h>
static int sr_class3_enable(struct voltagedomain *voltdm,
@@ -49,6 +50,10 @@ static struct omap_sr_class_data class3_data = {
/* Smartreflex Class3 init API to be called from board file */
static int __init sr_class3_init(void)
{
+ /* Enable this class only for OMAP343x */
+ if (!cpu_is_omap343x())
+ return -EINVAL;
+
pr_info("SmartReflex Class3 initialized\n");
return sr_register_class(&class3_data);
}
--
1.7.1
^ permalink raw reply related
* [patch v2 0/3] arm: pmu: support pmu/perf on OMAP4
From: tom.leiming at gmail.com @ 2011-03-02 10:56 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
This patches support pmu irq routed from CTI, such as implemented
on OMAP4:
- introduce some CTI helpers and registers' definition
- introduce .enable_irq and .disable_irq into platform_data,
so perf irq handler can handle irq correctly if it is
routed from CTI on OMAP4
- configure CTI on OMAP4 so that perf can work on OMAP4
The patches have been tested Ok on Pandaboard, and 'perf' does work
after applying them.
v2:
- move cti related code out of perf_event.c
- introduce .enable_irq and .disable_irq into platform_data
as suggested by Will.
v1:
- rebase the patch set against 2.6.38-rc6-next-20110301, fix
conflicts, which is pointed out by Will Deacon
arch/arm/include/asm/cti.h | 177 +++++++++++++++++++++++++++++++++++++++++
arch/arm/include/asm/pmu.h | 15 +++-
arch/arm/kernel/perf_event.c | 15 +++-
arch/arm/mach-omap2/dbg44xx.h | 18 ++++
arch/arm/mach-omap2/devices.c | 83 ++++++++++++++++++-
5 files changed, 299 insertions(+), 9 deletions(-)
thanks,
--
Lei Ming
^ permalink raw reply
* [patch v2 1/3] arm: introduce cross trigger interface helpers
From: tom.leiming at gmail.com @ 2011-03-02 10:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1299063420-22203-1-git-send-email-tom.leiming@gmail.com>
From: Ming Lei <tom.leiming@gmail.com>
OMAP4 uses cross trigger interface(CTI) to route
performance monitor irq to GIC, so introduce cti
helpers to make access for cti easily.
Signed-off-by: Ming Lei <tom.leiming@gmail.com>
---
arch/arm/include/asm/cti.h | 177 ++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 177 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/include/asm/cti.h
diff --git a/arch/arm/include/asm/cti.h b/arch/arm/include/asm/cti.h
new file mode 100644
index 0000000..c9addd3
--- /dev/null
+++ b/arch/arm/include/asm/cti.h
@@ -0,0 +1,177 @@
+/*
+ * arch/arm/include/asm/cti.h
+ */
+#ifndef __ASMARM_CTI_H
+#define __ASMARM_CTI_H
+
+#include <asm/io.h>
+
+/*The registers' definition is from section 3.2 of
+ * Embedded Cross Trigger Revision: r0p0
+ **/
+#define CTICONTROL 0x000
+#define CTISTATUS 0x004
+#define CTILOCK 0x008
+#define CTIPROTECTION 0x00C
+#define CTIINTACK 0x010
+#define CTIAPPSET 0x014
+#define CTIAPPCLEAR 0x018
+#define CTIAPPPULSE 0x01c
+#define CTIINEN 0x020
+#define CTIOUTEN 0x0A0
+#define CTITRIGINSTATUS 0x130
+#define CTITRIGOUTSTATUS 0x134
+#define CTICHINSTATUS 0x138
+#define CTICHOUTSTATUS 0x13c
+#define CTIPERIPHID0 0xFE0
+#define CTIPERIPHID1 0xFE4
+#define CTIPERIPHID2 0xFE8
+#define CTIPERIPHID3 0xFEC
+#define CTIPCELLID0 0xFF0
+#define CTIPCELLID1 0xFF4
+#define CTIPCELLID2 0xFF8
+#define CTIPCELLID3 0xFFC
+
+/*The two below are from section 3.6.4 of
+ * CoreSight v1.0 Architecture Specification
+ **/
+#define LOCKACCESS 0xFB0
+#define LOCKSTATUS 0xFB4
+
+/**
+ * struct cti - cross trigger interface struct
+ * @base: mapped virtual address for the cti base
+ * @irq: irq number for the cti
+ * @trig_out_for_irq: triger out number which will cause
+ * the @irq happen
+ *
+ * cti struct used to operate cti registers.
+ */
+struct cti {
+ void *base;
+ int irq;
+ int trig_out_for_irq;
+};
+
+/**
+ * cti_init - initialize the cti instance
+ * @cti: cti instance
+ * @base: mapped virtual address for the cti base
+ * @irq: irq number for the cti
+ * @trig_out: triger out number which will cause
+ * the @irq happen
+ *
+ * called by machine code to pass the board dependent
+ * @base, @irq and @trig_out to cti.
+ */
+static inline void cti_init(struct cti *cti,
+ void *base, int irq, int trig_out)
+{
+ cti->base = base;
+ cti->irq = irq;
+ cti->trig_out_for_irq = trig_out;
+}
+
+/**
+ * cti_map_trigger - use the @chan to map @trig_in to @trig_out
+ * @cti: cti instance
+ * @trig_in: trigger in number
+ * @trig_out: trigger out number
+ * @channel: channel number
+ *
+ * This function maps one trigger in of @trig_in to one trigger
+ * out of @trig_out using the channel @chan.
+ */
+static inline void cti_map_trigger(struct cti *cti,
+ int trig_in, int trig_out, int chan)
+{
+ void *base = cti->base;
+ unsigned long val;
+
+ val = __raw_readl(base + CTIINEN + trig_in * 4);
+ val |= 1 << chan;
+ __raw_writel(val, base + CTIINEN + trig_in * 4);
+
+ val = __raw_readl(base + CTIOUTEN + trig_out * 4);
+ val |= 1 << chan;
+ __raw_writel(val, base + CTIOUTEN + trig_out * 4);
+}
+
+/**
+ * cti_enable - enable the cti module
+ * @cti: cti instance
+ *
+ * enable the cti module
+ */
+static inline void cti_enable(struct cti *cti)
+{
+ __raw_writel(0x1, cti->base);
+}
+
+/**
+ * cti_disable - disable the cti module
+ * @cti: cti instance
+ *
+ * enable the cti module
+ */
+static inline void cti_disable(struct cti *cti)
+{
+ __raw_writel(0, cti->base);
+}
+
+/**
+ * cti_irq_ack - clear the cti irq
+ * @cti: cti instance
+ *
+ * clear the cti irq
+ */
+static inline void cti_irq_ack(struct cti *cti)
+{
+ void *base = cti->base;
+ unsigned long val;
+
+ val = __raw_readl(base + CTIINTACK);
+ val |= 1 << cti->trig_out_for_irq;
+ __raw_writel(val, base + CTIINTACK);
+}
+
+/**
+ * cti_unlock - unlock cti module
+ * @cti: cti instance
+ *
+ * unlock the cti module, or else any writes to the cti
+ * module is not allowed.
+ */
+static inline void cti_unlock(struct cti *cti)
+{
+ void *base = cti->base;
+ unsigned long val;
+
+ val = __raw_readl(base + LOCKSTATUS);
+
+ if (val & 1) {
+ val = 0xC5ACCE55;
+ __raw_writel(val, base + LOCKACCESS);
+ }
+}
+
+/**
+ * cti_unlock - lock cti module
+ * @cti: cti instance
+ *
+ * lock the cti module, so any writes to the cti
+ * module will be not allowed.
+ */
+static inline void cti_lock(struct cti *cti)
+{
+ void *base = cti->base;
+ unsigned long val;
+
+ val = __raw_readl(base + LOCKSTATUS);
+
+ if (!(val & 1)) {
+ val = ~0xC5ACCE55;
+ __raw_writel(val, base + LOCKACCESS);
+ }
+}
+#endif
--
1.7.3
^ permalink raw reply related
* [patch v2 2/3] arm: pmu: allow platform specifc irq enable/disable handling
From: tom.leiming at gmail.com @ 2011-03-02 10:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1299063420-22203-1-git-send-email-tom.leiming@gmail.com>
From: Ming Lei <tom.leiming@gmail.com>
This patch introduces .enable_irq and .disable_irq into
struct arm_pmu_platdata, so platform specific irq enablement
can be handled after request_irq, and platform specific irq
disablement can be handled before free_irq.
This patch is for support of pmu irq routed from CTI on omap4.
Signed-off-by: Ming Lei <tom.leiming@gmail.com>
---
arch/arm/include/asm/pmu.h | 15 ++++++++++++---
arch/arm/kernel/perf_event.c | 15 ++++++++++++---
2 files changed, 24 insertions(+), 6 deletions(-)
diff --git a/arch/arm/include/asm/pmu.h b/arch/arm/include/asm/pmu.h
index 7544ce6..e50c542 100644
--- a/arch/arm/include/asm/pmu.h
+++ b/arch/arm/include/asm/pmu.h
@@ -22,13 +22,22 @@ enum arm_pmu_type {
/*
* struct arm_pmu_platdata - ARM PMU platform data
*
- * @handle_irq: an optional handler which will be called from the interrupt and
- * passed the address of the low level handler, and can be used to implement
- * any platform specific handling before or after calling it.
+ * @handle_irq: an optional handler which will be called from the
+ * interrupt and passed the address of the low level handler,
+ * and can be used to implement any platform specific handling
+ * before or after calling it.
+ * @enable_irq: an optional handler which will be called after
+ * request_irq and be used to handle some platform specific
+ * irq enablement
+ * @disable_irq: an optional handler which will be called before
+ * free_irq and be used to handle some platform specific
+ * irq disablement
*/
struct arm_pmu_platdata {
irqreturn_t (*handle_irq)(int irq, void *dev,
irq_handler_t pmu_handler);
+ void (*enable_irq)(int irq);
+ void (*disable_irq)(int irq);
};
#ifdef CONFIG_CPU_HAS_PMU
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index 22e194eb..61ff471 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -422,14 +422,18 @@ armpmu_reserve_hardware(void)
pr_warning("unable to request IRQ%d for ARM perf "
"counters\n", irq);
break;
- }
+ } else if (plat->enable_irq)
+ plat->enable_irq(irq);
}
if (err) {
for (i = i - 1; i >= 0; --i) {
irq = platform_get_irq(pmu_device, i);
- if (irq >= 0)
+ if (irq >= 0) {
+ if (plat->disable_irq)
+ plat->disable_irq(irq);
free_irq(irq, NULL);
+ }
}
release_pmu(pmu_device);
pmu_device = NULL;
@@ -442,11 +446,16 @@ static void
armpmu_release_hardware(void)
{
int i, irq;
+ struct arm_pmu_platdata *plat =
+ dev_get_platdata(&pmu_device->dev);
for (i = pmu_device->num_resources - 1; i >= 0; --i) {
irq = platform_get_irq(pmu_device, i);
- if (irq >= 0)
+ if (irq >= 0) {
+ if (plat->disable_irq)
+ plat->disable_irq(irq);
free_irq(irq, NULL);
+ }
}
armpmu->stop();
--
1.7.3
^ permalink raw reply related
* [patch v2 3/3] arm: omap4: support pmu
From: tom.leiming at gmail.com @ 2011-03-02 10:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1299063420-22203-1-git-send-email-tom.leiming@gmail.com>
From: Ming Lei <tom.leiming@gmail.com>
This patch supports pmu irq routed from CTI, so
make pmu/perf working on OMAP4.
The idea is from Woodruff Richard in the disscussion
about "Oprofile on Pandaboard / Omap4" on pandaboard at googlegroups.com.
Cc: Woodruff Richard <r-woodruff2@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: linux-omap at vger.kernel.org
Signed-off-by: Ming Lei <tom.leiming@gmail.com>
---
arch/arm/mach-omap2/dbg44xx.h | 18 +++++++++
arch/arm/mach-omap2/devices.c | 83 +++++++++++++++++++++++++++++++++++++++-
2 files changed, 98 insertions(+), 3 deletions(-)
create mode 100644 arch/arm/mach-omap2/dbg44xx.h
diff --git a/arch/arm/mach-omap2/dbg44xx.h b/arch/arm/mach-omap2/dbg44xx.h
new file mode 100644
index 0000000..e447ad5
--- /dev/null
+++ b/arch/arm/mach-omap2/dbg44xx.h
@@ -0,0 +1,18 @@
+/*
+ * OMAP44xx on-chip debug support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX",
+ * or "OMAP4430".
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_DBG44XX_H
+#define __ARCH_ARM_MACH_OMAP2_DBG44XX_H
+
+#define OMAP44XX_CTI0_BASE 0x54148000
+#define OMAP44XX_CTI1_BASE 0x54149000
+
+#endif
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index d216976..bae02d5 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -22,6 +22,7 @@
#include <asm/mach-types.h>
#include <asm/mach/map.h>
#include <asm/pmu.h>
+#include <asm/cti.h>
#include <plat/tc.h>
#include <plat/board.h>
@@ -35,6 +36,7 @@
#include "mux.h"
#include "control.h"
+#include "dbg44xx.h"
#if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
@@ -322,20 +324,95 @@ static struct resource omap3_pmu_resource = {
.flags = IORESOURCE_IRQ,
};
+static struct resource omap4_pmu_resource[] = {
+ {
+ .start = OMAP44XX_IRQ_CTI0,
+ .end = OMAP44XX_IRQ_CTI0,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = OMAP44XX_IRQ_CTI1,
+ .end = OMAP44XX_IRQ_CTI1,
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
static struct platform_device omap_pmu_device = {
.name = "arm-pmu",
.id = ARM_PMU_DEVICE_CPU,
.num_resources = 1,
};
+static struct arm_pmu_platdata omap4_pmu_data;
+static struct cti omap4_cti[2];
+
+static void omap4_enable_cti(int irq)
+{
+ if (irq == OMAP44XX_IRQ_CTI0)
+ cti_enable(&omap4_cti[0]);
+ else if (irq == OMAP44XX_IRQ_CTI1)
+ cti_enable(&omap4_cti[1]);
+}
+
+static void omap4_disable_cti(int irq)
+{
+ if (irq == OMAP44XX_IRQ_CTI0)
+ cti_disable(&omap4_cti[0]);
+ else if (irq == OMAP44XX_IRQ_CTI1)
+ cti_disable(&omap4_cti[1]);
+}
+
+static irqreturn_t omap4_pmu_handler(int irq, void *dev, irq_handler_t handler)
+{
+ if (irq == OMAP44XX_IRQ_CTI0)
+ cti_irq_ack(&omap4_cti[0]);
+ else if (irq == OMAP44XX_IRQ_CTI1)
+ cti_irq_ack(&omap4_cti[1]);
+
+ return handler(irq, dev);
+}
+
+static void omap4_configure_pmu_irq(void)
+{
+ void *base0;
+ void *base1;
+
+ base0 = ioremap(OMAP44XX_CTI0_BASE, 4096);
+ base1 = ioremap(OMAP44XX_CTI1_BASE, 4096);
+ if (!base0 && !base1) {
+ pr_err("ioremap for omap4 CTI failed\n");
+ return;
+ }
+
+ /*configure CTI0 for pmu irq routing*/
+ cti_init(&omap4_cti[0], base0, OMAP44XX_IRQ_CTI0, 6);
+ cti_unlock(&omap4_cti[0]);
+ cti_map_trigger(&omap4_cti[0], 1, 6, 2);
+
+ /*configure CTI1 for pmu irq routing*/
+ cti_init(&omap4_cti[1], base1, OMAP44XX_IRQ_CTI1, 6);
+ cti_unlock(&omap4_cti[1]);
+ cti_map_trigger(&omap4_cti[1], 1, 6, 2);
+
+ omap4_pmu_data.handle_irq = omap4_pmu_handler;
+ omap4_pmu_data.enable_irq = omap4_enable_cti;
+ omap4_pmu_data.disable_irq = omap4_disable_cti;
+}
+
static void omap_init_pmu(void)
{
- if (cpu_is_omap24xx())
+ if (cpu_is_omap24xx()) {
omap_pmu_device.resource = &omap2_pmu_resource;
- else if (cpu_is_omap34xx())
+ } else if (cpu_is_omap34xx()) {
omap_pmu_device.resource = &omap3_pmu_resource;
- else
+ } else if (cpu_is_omap44xx()) {
+ omap_pmu_device.resource = omap4_pmu_resource;
+ omap_pmu_device.num_resources = 2;
+ omap_pmu_device.dev.platform_data = &omap4_pmu_data;
+ omap4_configure_pmu_irq();
+ } else {
return;
+ }
platform_device_register(&omap_pmu_device);
}
--
1.7.3
^ permalink raw reply related
* [RFC PATCH] ARM: Use generic BUG() handler
From: Dave Martin @ 2011-03-02 10:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <AANLkTinMnZAupxn7oYFhqkN1Y0OD-eyN=UeRpw96no9r@mail.gmail.com>
On Tue, Mar 01, 2011 at 08:34:37AM -0800, Simon Glass wrote:
[...]
>
> It seems I am lucky with the gcc I am using. I would have thought this
> would be a pretty fundamental feature, but yes I did notice that %c
> wasn't used anywhere.
>
> Would this kernel feature be acceptable as a selectable config option
> on ARM then?
>
> Thanks,
> Simon
+/* A suitable undefined instruction to use for ARM bug handling */
+#define BUG_INSTR ".word 0xec000000"
^ This needs to be changed, since it's not an architecturally
undefined encoding -- i.e., it may get used in the future to
mean something real.
See arch/arm/kernel/{ptrace,kprobes}.c for examples of
suitable encodings.
Rather than relying on the %c inline asm feature, can we work
around it?
Since we are writing a macro anyway, we can paste most of the
arguments in when the macro is expanded, rather than relying on
the inline assembler to do it.
This works for everything except sizeof (struct bug_entry)
which the preprocessor obviously can't understand. But I suspect
we don't really need that: we need to keep the directives that
generate the bug entry in sync with the definition of struct bug_entry
anyway (don't we?) -- so the amount of extra padding needed is
currently zero and should always be a constant.
So, maybe something like this would work:
(Note -- I haven't tested this!)
+
+#ifdef CONFIG_DEBUG_BUGVERBOSE
+#define BUG() __BUG(__FILE__, __LINE__, BUG_INSTR)
+#define __BUG(__file, __line, __bug_instr) \
+do { \
+ asm volatile("1:\t" __bug_instr "\n" q \
+ ".pushsection .rodata.str, \"a\"\n" \
+ "2:\t.asciz \"" #__file "\"\n" \
+ ".popsection\n" \
+ ".pushsection __bug_table,\"a\"\n" \
+ "3:\t.word 1b, 2b\n" \
+ "\t.hword " #__line ", 0\n" \
+ ".popsection" \
+ unreachable(); \
+} while (0)
Cheers
---Dave
^ permalink raw reply
* [PATCH] i.MX some patches
From: Sascha Hauer @ 2011-03-02 11:01 UTC (permalink / raw)
To: linux-arm-kernel
The following are some cleanup patches to save ifdefs in i.MX code.
Sascha
Sascha Hauer (4):
ARM i.MX: Move gpio initialization to SoC specific files
ARM i.MX: iomux v1 initialization away from initcall
ARM i.MX31 lilly: remove incomplete otg support
ARM i.MX: introduce imx_otg_ulpi_create to create ULPI transceivers
arch/arm/mach-imx/mach-cpuimx27.c | 24 +++----
arch/arm/mach-imx/mach-mx27_3ds.c | 13 ++--
arch/arm/mach-imx/mach-pca100.c | 21 +++---
arch/arm/mach-imx/mm-imx1.c | 14 +++-
arch/arm/mach-imx/mm-imx21.c | 16 ++++-
arch/arm/mach-imx/mm-imx25.c | 11 +++-
arch/arm/mach-imx/mm-imx27.c | 16 ++++-
arch/arm/mach-mx3/mach-armadillo5x0.c | 20 +++---
arch/arm/mach-mx3/mach-mx31_3ds.c | 20 +++---
arch/arm/mach-mx3/mach-mx31lilly.c | 68 ++----------------
arch/arm/mach-mx3/mach-mx31lite.c | 12 +--
arch/arm/mach-mx3/mach-mx31moboard.c | 11 +--
arch/arm/mach-mx3/mach-pcm037.c | 19 ++---
arch/arm/mach-mx3/mach-pcm043.c | 12 +--
arch/arm/mach-mx3/mm.c | 20 ++++-
arch/arm/mach-mx3/mx31moboard-smartbot.c | 6 +-
arch/arm/mach-mx5/board-mx51_efikasb.c | 8 +-
arch/arm/mach-mx5/mm-mx50.c | 13 +++-
arch/arm/mach-mx5/mx51_efika.c | 8 +-
arch/arm/plat-mxc/gpio.c | 110 -----------------------------
arch/arm/plat-mxc/include/mach/gpio.h | 15 ++++
arch/arm/plat-mxc/include/mach/iomux-v1.h | 2 +
arch/arm/plat-mxc/include/mach/ulpi.h | 9 +++
arch/arm/plat-mxc/iomux-v1.c | 24 +------
arch/arm/plat-mxc/ulpi.c | 5 ++
25 files changed, 190 insertions(+), 307 deletions(-)
^ permalink raw reply
* [PATCH 1/4] ARM i.MX: Move gpio initialization to SoC specific files
From: Sascha Hauer @ 2011-03-02 11:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1299063683-24903-1-git-send-email-s.hauer@pengutronix.de>
This saves us from soc level dispatching in generic files
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-imx/mm-imx1.c | 11 +++-
arch/arm/mach-imx/mm-imx21.c | 13 +++-
arch/arm/mach-imx/mm-imx25.c | 11 +++-
arch/arm/mach-imx/mm-imx27.c | 13 +++-
arch/arm/mach-mx3/mm.c | 20 +++++-
arch/arm/mach-mx5/mm-mx50.c | 13 +++-
arch/arm/plat-mxc/gpio.c | 110 ---------------------------------
arch/arm/plat-mxc/include/mach/gpio.h | 15 +++++
8 files changed, 82 insertions(+), 124 deletions(-)
diff --git a/arch/arm/mach-imx/mm-imx1.c b/arch/arm/mach-imx/mm-imx1.c
index 378c61b..8613e44 100644
--- a/arch/arm/mach-imx/mm-imx1.c
+++ b/arch/arm/mach-imx/mm-imx1.c
@@ -23,6 +23,8 @@
#include <mach/common.h>
#include <mach/hardware.h>
+#include <mach/gpio.h>
+#include <mach/irqs.h>
static struct map_desc imx_io_desc[] __initdata = {
imx_map_entry(MX1, IO, MT_DEVICE),
@@ -39,10 +41,15 @@ void __init imx1_init_early(void)
mxc_arch_reset_init(MX1_IO_ADDRESS(MX1_WDT_BASE_ADDR));
}
-int imx1_register_gpios(void);
+static struct mxc_gpio_port imx1_gpio_ports[] = {
+ DEFINE_IMX_GPIO_PORT_IRQ(MX1, 0, 1, MX1_GPIO_INT_PORTA),
+ DEFINE_IMX_GPIO_PORT_IRQ(MX1, 1, 2, MX1_GPIO_INT_PORTB),
+ DEFINE_IMX_GPIO_PORT_IRQ(MX1, 2, 3, MX1_GPIO_INT_PORTC),
+ DEFINE_IMX_GPIO_PORT_IRQ(MX1, 3, 4, MX1_GPIO_INT_PORTD),
+};
void __init mx1_init_irq(void)
{
mxc_init_irq(MX1_IO_ADDRESS(MX1_AVIC_BASE_ADDR));
- imx1_register_gpios();
+ mxc_gpio_init(imx1_gpio_ports, ARRAY_SIZE(imx1_gpio_ports));
}
diff --git a/arch/arm/mach-imx/mm-imx21.c b/arch/arm/mach-imx/mm-imx21.c
index b6152c6..6027e35 100644
--- a/arch/arm/mach-imx/mm-imx21.c
+++ b/arch/arm/mach-imx/mm-imx21.c
@@ -24,6 +24,8 @@
#include <mach/common.h>
#include <asm/pgtable.h>
#include <asm/mach/map.h>
+#include <mach/gpio.h>
+#include <mach/irqs.h>
/* MX21 memory map definition */
static struct map_desc imx21_io_desc[] __initdata = {
@@ -65,10 +67,17 @@ void __init imx21_init_early(void)
mxc_arch_reset_init(MX21_IO_ADDRESS(MX21_WDOG_BASE_ADDR));
}
-int imx21_register_gpios(void);
+static struct mxc_gpio_port imx21_gpio_ports[] = {
+ DEFINE_IMX_GPIO_PORT_IRQ(MX21, 0, 1, MX21_INT_GPIO),
+ DEFINE_IMX_GPIO_PORT(MX21, 1, 2),
+ DEFINE_IMX_GPIO_PORT(MX21, 2, 3),
+ DEFINE_IMX_GPIO_PORT(MX21, 3, 4),
+ DEFINE_IMX_GPIO_PORT(MX21, 4, 5),
+ DEFINE_IMX_GPIO_PORT(MX21, 5, 6),
+};
void __init mx21_init_irq(void)
{
mxc_init_irq(MX21_IO_ADDRESS(MX21_AVIC_BASE_ADDR));
- imx21_register_gpios();
+ mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports));
}
diff --git a/arch/arm/mach-imx/mm-imx25.c b/arch/arm/mach-imx/mm-imx25.c
index 09dd8d4..02f7b5c 100644
--- a/arch/arm/mach-imx/mm-imx25.c
+++ b/arch/arm/mach-imx/mm-imx25.c
@@ -27,6 +27,8 @@
#include <mach/hardware.h>
#include <mach/mx25.h>
#include <mach/iomux-v3.h>
+#include <mach/gpio.h>
+#include <mach/irqs.h>
/*
* This table defines static virtual address mappings for I/O regions.
@@ -55,11 +57,16 @@ void __init imx25_init_early(void)
mxc_arch_reset_init(MX25_IO_ADDRESS(MX25_WDOG_BASE_ADDR));
}
-int imx25_register_gpios(void);
+static struct mxc_gpio_port imx25_gpio_ports[] = {
+ DEFINE_IMX_GPIO_PORT_IRQ(MX25, 0, 1, MX25_INT_GPIO1),
+ DEFINE_IMX_GPIO_PORT_IRQ(MX25, 1, 2, MX25_INT_GPIO2),
+ DEFINE_IMX_GPIO_PORT_IRQ(MX25, 2, 3, MX25_INT_GPIO3),
+ DEFINE_IMX_GPIO_PORT_IRQ(MX25, 3, 4, MX25_INT_GPIO4),
+};
void __init mx25_init_irq(void)
{
mxc_init_irq(MX25_IO_ADDRESS(MX25_AVIC_BASE_ADDR));
- imx25_register_gpios();
+ mxc_gpio_init(imx25_gpio_ports, ARRAY_SIZE(imx25_gpio_ports));
}
diff --git a/arch/arm/mach-imx/mm-imx27.c b/arch/arm/mach-imx/mm-imx27.c
index bcaa3b6..e172e3e 100644
--- a/arch/arm/mach-imx/mm-imx27.c
+++ b/arch/arm/mach-imx/mm-imx27.c
@@ -24,6 +24,8 @@
#include <mach/common.h>
#include <asm/pgtable.h>
#include <asm/mach/map.h>
+#include <mach/gpio.h>
+#include <mach/irqs.h>
/* MX27 memory map definition */
static struct map_desc imx27_io_desc[] __initdata = {
@@ -65,10 +67,17 @@ void __init imx27_init_early(void)
mxc_arch_reset_init(MX27_IO_ADDRESS(MX27_WDOG_BASE_ADDR));
}
-int imx27_register_gpios(void);
+static struct mxc_gpio_port imx27_gpio_ports[] = {
+ DEFINE_IMX_GPIO_PORT_IRQ(MX27, 0, 1, MX27_INT_GPIO),
+ DEFINE_IMX_GPIO_PORT(MX27, 1, 2),
+ DEFINE_IMX_GPIO_PORT(MX27, 2, 3),
+ DEFINE_IMX_GPIO_PORT(MX27, 3, 4),
+ DEFINE_IMX_GPIO_PORT(MX27, 4, 5),
+ DEFINE_IMX_GPIO_PORT(MX27, 5, 6),
+};
void __init mx27_init_irq(void)
{
mxc_init_irq(MX27_IO_ADDRESS(MX27_AVIC_BASE_ADDR));
- imx27_register_gpios();
+ mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports));
}
diff --git a/arch/arm/mach-mx3/mm.c b/arch/arm/mach-mx3/mm.c
index eefd4cf..54d7174 100644
--- a/arch/arm/mach-mx3/mm.c
+++ b/arch/arm/mach-mx3/mm.c
@@ -27,6 +27,8 @@
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-v3.h>
+#include <mach/gpio.h>
+#include <mach/irqs.h>
#ifdef CONFIG_SOC_IMX31
static struct map_desc mx31_io_desc[] __initdata = {
@@ -53,11 +55,16 @@ void __init imx31_init_early(void)
mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
}
-int imx31_register_gpios(void);
+static struct mxc_gpio_port imx31_gpio_ports[] = {
+ DEFINE_IMX_GPIO_PORT_IRQ(MX31, 0, 1, MX31_INT_GPIO1),
+ DEFINE_IMX_GPIO_PORT_IRQ(MX31, 1, 2, MX31_INT_GPIO2),
+ DEFINE_IMX_GPIO_PORT_IRQ(MX31, 2, 3, MX31_INT_GPIO3),
+};
+
void __init mx31_init_irq(void)
{
mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
- imx31_register_gpios();
+ mxc_gpio_init(imx31_gpio_ports, ARRAY_SIZE(imx31_gpio_ports));
}
#endif /* ifdef CONFIG_SOC_IMX31 */
@@ -82,11 +89,16 @@ void __init imx35_init_early(void)
mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
}
-int imx35_register_gpios(void);
+static struct mxc_gpio_port imx35_gpio_ports[] = {
+ DEFINE_IMX_GPIO_PORT_IRQ(MX35, 0, 1, MX35_INT_GPIO1),
+ DEFINE_IMX_GPIO_PORT_IRQ(MX35, 1, 2, MX35_INT_GPIO2),
+ DEFINE_IMX_GPIO_PORT_IRQ(MX35, 2, 3, MX35_INT_GPIO3),
+};
+
void __init mx35_init_irq(void)
{
mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
- imx35_register_gpios();
+ mxc_gpio_init(imx35_gpio_ports, ARRAY_SIZE(imx35_gpio_ports));
}
#endif /* ifdef CONFIG_SOC_IMX35 */
diff --git a/arch/arm/mach-mx5/mm-mx50.c b/arch/arm/mach-mx5/mm-mx50.c
index 69b3426..b9c363b 100644
--- a/arch/arm/mach-mx5/mm-mx50.c
+++ b/arch/arm/mach-mx5/mm-mx50.c
@@ -26,6 +26,8 @@
#include <mach/hardware.h>
#include <mach/common.h>
#include <mach/iomux-v3.h>
+#include <mach/gpio.h>
+#include <mach/irqs.h>
/*
* Define the MX50 memory map.
@@ -54,10 +56,17 @@ void __init imx50_init_early(void)
mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR));
}
-int imx50_register_gpios(void);
+static struct mxc_gpio_port imx50_gpio_ports[] = {
+ DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 0, 1, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH),
+ DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 1, 2, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH),
+ DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 2, 3, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
+ DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 3, 4, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
+ DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 4, 5, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
+ DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 5, 6, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
+};
void __init mx50_init_irq(void)
{
tzic_init_irq(MX50_IO_ADDRESS(MX50_TZIC_BASE_ADDR));
- imx50_register_gpios();
+ mxc_gpio_init(imx50_gpio_ports, ARRAY_SIZE(imx50_gpio_ports));
}
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c
index e396df8..57d5985 100644
--- a/arch/arm/plat-mxc/gpio.c
+++ b/arch/arm/plat-mxc/gpio.c
@@ -350,113 +350,3 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
return 0;
}
-
-#define DEFINE_IMX_GPIO_PORT_IRQ_HIGH(soc, _id, _hwid, _irq, _irq_high) \
- { \
- .chip.label = "gpio-" #_id, \
- .irq = _irq, \
- .irq_high = _irq_high, \
- .base = soc ## _IO_ADDRESS( \
- soc ## _GPIO ## _hwid ## _BASE_ADDR), \
- .virtual_irq_start = MXC_GPIO_IRQ_START + (_id) * 32, \
- }
-
-#define DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, _irq) \
- DEFINE_IMX_GPIO_PORT_IRQ_HIGH(soc, _id, _hwid, _irq, 0)
-#define DEFINE_IMX_GPIO_PORT(soc, _id, _hwid) \
- DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, 0)
-
-#define DEFINE_REGISTER_FUNCTION(prefix) \
-int __init prefix ## _register_gpios(void) \
-{ \
- return mxc_gpio_init(prefix ## _gpio_ports, \
- ARRAY_SIZE(prefix ## _gpio_ports)); \
-}
-
-#if defined(CONFIG_SOC_IMX1)
-static struct mxc_gpio_port imx1_gpio_ports[] = {
- DEFINE_IMX_GPIO_PORT_IRQ(MX1, 0, 1, MX1_GPIO_INT_PORTA),
- DEFINE_IMX_GPIO_PORT_IRQ(MX1, 1, 2, MX1_GPIO_INT_PORTB),
- DEFINE_IMX_GPIO_PORT_IRQ(MX1, 2, 3, MX1_GPIO_INT_PORTC),
- DEFINE_IMX_GPIO_PORT_IRQ(MX1, 3, 4, MX1_GPIO_INT_PORTD),
-};
-
-DEFINE_REGISTER_FUNCTION(imx1)
-
-#endif /* if defined(CONFIG_SOC_IMX1) */
-
-#if defined(CONFIG_SOC_IMX21)
-static struct mxc_gpio_port imx21_gpio_ports[] = {
- DEFINE_IMX_GPIO_PORT_IRQ(MX21, 0, 1, MX21_INT_GPIO),
- DEFINE_IMX_GPIO_PORT(MX21, 1, 2),
- DEFINE_IMX_GPIO_PORT(MX21, 2, 3),
- DEFINE_IMX_GPIO_PORT(MX21, 3, 4),
- DEFINE_IMX_GPIO_PORT(MX21, 4, 5),
- DEFINE_IMX_GPIO_PORT(MX21, 5, 6),
-};
-
-DEFINE_REGISTER_FUNCTION(imx21)
-
-#endif /* if defined(CONFIG_SOC_IMX21) */
-
-#if defined(CONFIG_SOC_IMX25)
-static struct mxc_gpio_port imx25_gpio_ports[] = {
- DEFINE_IMX_GPIO_PORT_IRQ(MX25, 0, 1, MX25_INT_GPIO1),
- DEFINE_IMX_GPIO_PORT_IRQ(MX25, 1, 2, MX25_INT_GPIO2),
- DEFINE_IMX_GPIO_PORT_IRQ(MX25, 2, 3, MX25_INT_GPIO3),
- DEFINE_IMX_GPIO_PORT_IRQ(MX25, 3, 4, MX25_INT_GPIO4),
-};
-
-DEFINE_REGISTER_FUNCTION(imx25)
-
-#endif /* if defined(CONFIG_SOC_IMX25) */
-
-#if defined(CONFIG_SOC_IMX27)
-static struct mxc_gpio_port imx27_gpio_ports[] = {
- DEFINE_IMX_GPIO_PORT_IRQ(MX27, 0, 1, MX27_INT_GPIO),
- DEFINE_IMX_GPIO_PORT(MX27, 1, 2),
- DEFINE_IMX_GPIO_PORT(MX27, 2, 3),
- DEFINE_IMX_GPIO_PORT(MX27, 3, 4),
- DEFINE_IMX_GPIO_PORT(MX27, 4, 5),
- DEFINE_IMX_GPIO_PORT(MX27, 5, 6),
-};
-
-DEFINE_REGISTER_FUNCTION(imx27)
-
-#endif /* if defined(CONFIG_SOC_IMX27) */
-
-#if defined(CONFIG_SOC_IMX31)
-static struct mxc_gpio_port imx31_gpio_ports[] = {
- DEFINE_IMX_GPIO_PORT_IRQ(MX31, 0, 1, MX31_INT_GPIO1),
- DEFINE_IMX_GPIO_PORT_IRQ(MX31, 1, 2, MX31_INT_GPIO2),
- DEFINE_IMX_GPIO_PORT_IRQ(MX31, 2, 3, MX31_INT_GPIO3),
-};
-
-DEFINE_REGISTER_FUNCTION(imx31)
-
-#endif /* if defined(CONFIG_SOC_IMX31) */
-
-#if defined(CONFIG_SOC_IMX35)
-static struct mxc_gpio_port imx35_gpio_ports[] = {
- DEFINE_IMX_GPIO_PORT_IRQ(MX35, 0, 1, MX35_INT_GPIO1),
- DEFINE_IMX_GPIO_PORT_IRQ(MX35, 1, 2, MX35_INT_GPIO2),
- DEFINE_IMX_GPIO_PORT_IRQ(MX35, 2, 3, MX35_INT_GPIO3),
-};
-
-DEFINE_REGISTER_FUNCTION(imx35)
-
-#endif /* if defined(CONFIG_SOC_IMX35) */
-
-#if defined(CONFIG_SOC_IMX50)
-static struct mxc_gpio_port imx50_gpio_ports[] = {
- DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 0, 1, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH),
- DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 1, 2, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH),
- DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 2, 3, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
- DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 3, 4, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
- DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 4, 5, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
- DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 5, 6, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
-};
-
-DEFINE_REGISTER_FUNCTION(imx50)
-
-#endif /* if defined(CONFIG_SOC_IMX50) */
diff --git a/arch/arm/plat-mxc/include/mach/gpio.h b/arch/arm/plat-mxc/include/mach/gpio.h
index 0044e2f..a2747f1 100644
--- a/arch/arm/plat-mxc/include/mach/gpio.h
+++ b/arch/arm/plat-mxc/include/mach/gpio.h
@@ -46,6 +46,21 @@ struct mxc_gpio_port {
spinlock_t lock;
};
+#define DEFINE_IMX_GPIO_PORT_IRQ_HIGH(soc, _id, _hwid, _irq, _irq_high) \
+ { \
+ .chip.label = "gpio-" #_id, \
+ .irq = _irq, \
+ .irq_high = _irq_high, \
+ .base = soc ## _IO_ADDRESS( \
+ soc ## _GPIO ## _hwid ## _BASE_ADDR), \
+ .virtual_irq_start = MXC_GPIO_IRQ_START + (_id) * 32, \
+ }
+
+#define DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, _irq) \
+ DEFINE_IMX_GPIO_PORT_IRQ_HIGH(soc, _id, _hwid, _irq, 0)
+#define DEFINE_IMX_GPIO_PORT(soc, _id, _hwid) \
+ DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, 0)
+
int mxc_gpio_init(struct mxc_gpio_port*, int);
#endif
--
1.7.2.3
^ permalink raw reply related
* [PATCH 2/4] ARM i.MX: iomux v1 initialization away from initcall
From: Sascha Hauer @ 2011-03-02 11:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1299063683-24903-1-git-send-email-s.hauer@pengutronix.de>
This saves us from soc level dispatching in generic files
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-imx/mm-imx1.c | 3 +++
arch/arm/mach-imx/mm-imx21.c | 3 +++
arch/arm/mach-imx/mm-imx27.c | 3 +++
arch/arm/plat-mxc/include/mach/iomux-v1.h | 2 ++
arch/arm/plat-mxc/iomux-v1.c | 24 +++---------------------
5 files changed, 14 insertions(+), 21 deletions(-)
diff --git a/arch/arm/mach-imx/mm-imx1.c b/arch/arm/mach-imx/mm-imx1.c
index 8613e44..2e482ba 100644
--- a/arch/arm/mach-imx/mm-imx1.c
+++ b/arch/arm/mach-imx/mm-imx1.c
@@ -25,6 +25,7 @@
#include <mach/hardware.h>
#include <mach/gpio.h>
#include <mach/irqs.h>
+#include <mach/iomux-v1.h>
static struct map_desc imx_io_desc[] __initdata = {
imx_map_entry(MX1, IO, MT_DEVICE),
@@ -39,6 +40,8 @@ void __init imx1_init_early(void)
{
mxc_set_cpu_type(MXC_CPU_MX1);
mxc_arch_reset_init(MX1_IO_ADDRESS(MX1_WDT_BASE_ADDR));
+ imx_iomuxv1_init(MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR),
+ MX1_NUM_GPIO_PORT);
}
static struct mxc_gpio_port imx1_gpio_ports[] = {
diff --git a/arch/arm/mach-imx/mm-imx21.c b/arch/arm/mach-imx/mm-imx21.c
index 6027e35..7a0c500 100644
--- a/arch/arm/mach-imx/mm-imx21.c
+++ b/arch/arm/mach-imx/mm-imx21.c
@@ -26,6 +26,7 @@
#include <asm/mach/map.h>
#include <mach/gpio.h>
#include <mach/irqs.h>
+#include <mach/iomux-v1.h>
/* MX21 memory map definition */
static struct map_desc imx21_io_desc[] __initdata = {
@@ -65,6 +66,8 @@ void __init imx21_init_early(void)
{
mxc_set_cpu_type(MXC_CPU_MX21);
mxc_arch_reset_init(MX21_IO_ADDRESS(MX21_WDOG_BASE_ADDR));
+ imx_iomuxv1_init(MX21_IO_ADDRESS(MX21_GPIO_BASE_ADDR),
+ MX21_NUM_GPIO_PORT);
}
static struct mxc_gpio_port imx21_gpio_ports[] = {
diff --git a/arch/arm/mach-imx/mm-imx27.c b/arch/arm/mach-imx/mm-imx27.c
index e172e3e..a6761a3 100644
--- a/arch/arm/mach-imx/mm-imx27.c
+++ b/arch/arm/mach-imx/mm-imx27.c
@@ -26,6 +26,7 @@
#include <asm/mach/map.h>
#include <mach/gpio.h>
#include <mach/irqs.h>
+#include <mach/iomux-v1.h>
/* MX27 memory map definition */
static struct map_desc imx27_io_desc[] __initdata = {
@@ -65,6 +66,8 @@ void __init imx27_init_early(void)
{
mxc_set_cpu_type(MXC_CPU_MX27);
mxc_arch_reset_init(MX27_IO_ADDRESS(MX27_WDOG_BASE_ADDR));
+ imx_iomuxv1_init(MX27_IO_ADDRESS(MX27_GPIO_BASE_ADDR),
+ MX27_NUM_GPIO_PORT);
}
static struct mxc_gpio_port imx27_gpio_ports[] = {
diff --git a/arch/arm/plat-mxc/include/mach/iomux-v1.h b/arch/arm/plat-mxc/include/mach/iomux-v1.h
index 884f575..c07d302 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-v1.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-v1.h
@@ -100,4 +100,6 @@ extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
const char *label);
extern void mxc_gpio_release_multiple_pins(const int *pin_list, int count);
+extern int __init imx_iomuxv1_init(void __iomem *base, int numports);
+
#endif /* __MACH_IOMUX_V1_H__ */
diff --git a/arch/arm/plat-mxc/iomux-v1.c b/arch/arm/plat-mxc/iomux-v1.c
index 960a02c..3238c10 100644
--- a/arch/arm/plat-mxc/iomux-v1.c
+++ b/arch/arm/plat-mxc/iomux-v1.c
@@ -211,28 +211,10 @@ void mxc_gpio_release_multiple_pins(const int *pin_list, int count)
}
EXPORT_SYMBOL(mxc_gpio_release_multiple_pins);
-static int imx_iomuxv1_init(void)
+int __init imx_iomuxv1_init(void __iomem *base, int numports)
{
-#ifdef CONFIG_ARCH_MX1
- if (cpu_is_mx1()) {
- imx_iomuxv1_baseaddr = MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR);
- imx_iomuxv1_numports = MX1_NUM_GPIO_PORT;
- } else
-#endif
-#ifdef CONFIG_MACH_MX21
- if (cpu_is_mx21()) {
- imx_iomuxv1_baseaddr = MX21_IO_ADDRESS(MX21_GPIO_BASE_ADDR);
- imx_iomuxv1_numports = MX21_NUM_GPIO_PORT;
- } else
-#endif
-#ifdef CONFIG_MACH_MX27
- if (cpu_is_mx27()) {
- imx_iomuxv1_baseaddr = MX27_IO_ADDRESS(MX27_GPIO_BASE_ADDR);
- imx_iomuxv1_numports = MX27_NUM_GPIO_PORT;
- } else
-#endif
- return -ENODEV;
+ imx_iomuxv1_baseaddr = base;
+ imx_iomuxv1_numports = numports;
return 0;
}
-pure_initcall(imx_iomuxv1_init);
--
1.7.2.3
^ permalink raw reply related
* [PATCH 3/4] ARM i.MX31 lilly: remove incomplete otg support
From: Sascha Hauer @ 2011-03-02 11:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1299063683-24903-1-git-send-email-s.hauer@pengutronix.de>
The platform data for the otg port is present but never used, so
remove it.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Daniel Mack <daniel@caiaq.de>
---
arch/arm/mach-mx3/mach-mx31lilly.c | 53 ------------------------------------
1 files changed, 0 insertions(+), 53 deletions(-)
diff --git a/arch/arm/mach-mx3/mach-mx31lilly.c b/arch/arm/mach-mx3/mach-mx31lilly.c
index be79a0d..e2f9de1 100644
--- a/arch/arm/mach-mx3/mach-mx31lilly.c
+++ b/arch/arm/mach-mx3/mach-mx31lilly.c
@@ -116,52 +116,6 @@ static struct platform_device physmap_flash_device = {
#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
-static int usbotg_init(struct platform_device *pdev)
-{
- unsigned int pins[] = {
- MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
- MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
- MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
- MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
- MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
- MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
- MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
- MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
- MX31_PIN_USBOTG_CLK__USBOTG_CLK,
- MX31_PIN_USBOTG_DIR__USBOTG_DIR,
- MX31_PIN_USBOTG_NXT__USBOTG_NXT,
- MX31_PIN_USBOTG_STP__USBOTG_STP,
- };
-
- mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB OTG");
-
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG);
-
- mxc_iomux_set_gpr(MUX_PGP_USB_4WIRE, true);
- mxc_iomux_set_gpr(MUX_PGP_USB_COMMON, true);
-
- /* chip select */
- mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_DTR_DCE2, IOMUX_CONFIG_GPIO),
- "USBOTG_CS");
- gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE2), "USBH1 CS");
- gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE2), 0);
-
- mdelay(10);
-
- return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
-}
-
static int usbh1_init(struct platform_device *pdev)
{
int pins[] = {
@@ -231,11 +185,6 @@ static int usbh2_init(struct platform_device *pdev)
return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
}
-static struct mxc_usbh_platform_data usbotg_pdata = {
- .init = usbotg_init,
- .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
-};
-
static const struct mxc_usbh_platform_data usbh1_pdata __initconst = {
.init = usbh1_init,
.portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL,
@@ -248,8 +197,6 @@ static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
static void lilly1131_usb_init(void)
{
- usbotg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
- ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
--
1.7.2.3
^ permalink raw reply related
* [PATCH 4/4] ARM i.MX: introduce imx_otg_ulpi_create to create ULPI transceivers
From: Sascha Hauer @ 2011-03-02 11:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1299063683-24903-1-git-send-email-s.hauer@pengutronix.de>
The boards are currently using otg_ulpi_create and mxc_ulpi_access_ops,
both are only present if CONFIG_USB_ULPI is set. To remove the need of
ifdefs in the board code introduce a imx_otg_ulpi_create functions
which expands to a static inline function if compiled without ulpi.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-imx/mach-cpuimx27.c | 24 ++++++++++--------------
arch/arm/mach-imx/mach-mx27_3ds.c | 13 ++++++-------
arch/arm/mach-imx/mach-pca100.c | 21 +++++++++------------
arch/arm/mach-mx3/mach-armadillo5x0.c | 20 +++++++++-----------
arch/arm/mach-mx3/mach-mx31_3ds.c | 20 +++++++++-----------
arch/arm/mach-mx3/mach-mx31lilly.c | 15 +++++----------
arch/arm/mach-mx3/mach-mx31lite.c | 12 ++++--------
arch/arm/mach-mx3/mach-mx31moboard.c | 11 ++++-------
arch/arm/mach-mx3/mach-pcm037.c | 19 ++++++++-----------
arch/arm/mach-mx3/mach-pcm043.c | 12 ++++--------
arch/arm/mach-mx3/mx31moboard-smartbot.c | 6 ++++--
arch/arm/mach-mx5/board-mx51_efikasb.c | 8 ++++----
arch/arm/mach-mx5/mx51_efika.c | 8 ++++----
arch/arm/plat-mxc/include/mach/ulpi.h | 9 +++++++++
arch/arm/plat-mxc/ulpi.c | 5 +++++
15 files changed, 94 insertions(+), 109 deletions(-)
diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c
index 6b724c2..759299b 100644
--- a/arch/arm/mach-imx/mach-cpuimx27.c
+++ b/arch/arm/mach-imx/mach-cpuimx27.c
@@ -209,7 +209,6 @@ static struct platform_device serial_device = {
};
#endif
-#if defined(CONFIG_USB_ULPI)
static int eukrea_cpuimx27_otg_init(struct platform_device *pdev)
{
return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
@@ -229,7 +228,6 @@ static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
.init = eukrea_cpuimx27_usbh2_init,
.portsc = MXC_EHCI_MODE_ULPI,
};
-#endif
static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
.operating_mode = FSL_USB2_DR_DEVICE,
@@ -283,21 +281,19 @@ static void __init eukrea_cpuimx27_init(void)
platform_device_register(&serial_device);
#endif
-#if defined(CONFIG_USB_ULPI)
if (otg_mode_host) {
- otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
- ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
-
- imx27_add_mxc_ehci_otg(&otg_pdata);
+ otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
+ ULPI_OTG_DRVVBUS_EXT);
+ if (otg_pdata.otg)
+ imx27_add_mxc_ehci_otg(&otg_pdata);
+ } else {
+ imx27_add_fsl_usb2_udc(&otg_device_pdata);
}
- usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
- ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
-
- imx27_add_mxc_ehci_hs(2, &usbh2_pdata);
-#endif
- if (!otg_mode_host)
- imx27_add_fsl_usb2_udc(&otg_device_pdata);
+ usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
+ ULPI_OTG_DRVVBUS_EXT);
+ if (usbh2_pdata.otg)
+ imx27_add_mxc_ehci_hs(2, &usbh2_pdata);
#ifdef CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD
eukrea_mbimx27_baseboard_init();
diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c
index f4f2725..614b3c0 100644
--- a/arch/arm/mach-imx/mach-mx27_3ds.c
+++ b/arch/arm/mach-imx/mach-mx27_3ds.c
@@ -162,7 +162,6 @@ static int otg_phy_init(void)
return 0;
}
-#if defined(CONFIG_USB_ULPI)
static int mx27_3ds_otg_init(struct platform_device *pdev)
{
return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
@@ -172,7 +171,6 @@ static struct mxc_usbh_platform_data otg_pdata __initdata = {
.init = mx27_3ds_otg_init,
.portsc = MXC_EHCI_MODE_ULPI,
};
-#endif
static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
.operating_mode = FSL_USB2_DR_DEVICE,
@@ -275,14 +273,15 @@ static void __init mx27pdk_init(void)
imx27_add_mxc_mmc(0, &sdhc1_pdata);
imx27_add_imx2_wdt(NULL);
otg_phy_init();
-#if defined(CONFIG_USB_ULPI)
+
if (otg_mode_host) {
- otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
- ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
+ otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
+ ULPI_OTG_DRVVBUS_EXT);
- imx27_add_mxc_ehci_otg(&otg_pdata);
+ if (otg_pdata.otg)
+ imx27_add_mxc_ehci_otg(&otg_pdata);
}
-#endif
+
if (!otg_mode_host)
imx27_add_fsl_usb2_udc(&otg_device_pdata);
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index f754bab..63e1825 100644
--- a/arch/arm/mach-imx/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -267,7 +267,6 @@ static const struct imxmmc_platform_data sdhc_pdata __initconst = {
.exit = pca100_sdhc2_exit,
};
-#if defined(CONFIG_USB_ULPI)
static int otg_phy_init(struct platform_device *pdev)
{
gpio_set_value(OTG_PHY_CS_GPIO, 0);
@@ -295,7 +294,6 @@ static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
.init = usbh2_phy_init,
.portsc = MXC_EHCI_MODE_ULPI,
};
-#endif
static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
.operating_mode = FSL_USB2_DR_DEVICE,
@@ -402,23 +400,22 @@ static void __init pca100_init(void)
gpio_request(USBH2_PHY_CS_GPIO, "usb-host2-cs");
gpio_direction_output(USBH2_PHY_CS_GPIO, 1);
-#if defined(CONFIG_USB_ULPI)
if (otg_mode_host) {
- otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
- ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
+ otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
+ ULPI_OTG_DRVVBUS_EXT);
- imx27_add_mxc_ehci_otg(&otg_pdata);
+ if (otg_pdata.otg)
+ imx27_add_mxc_ehci_otg(&otg_pdata);
+ } else {
+ gpio_set_value(OTG_PHY_CS_GPIO, 0);
+ imx27_add_fsl_usb2_udc(&otg_device_pdata);
}
usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
- imx27_add_mxc_ehci_hs(2, &usbh2_pdata);
-#endif
- if (!otg_mode_host) {
- gpio_set_value(OTG_PHY_CS_GPIO, 0);
- imx27_add_fsl_usb2_udc(&otg_device_pdata);
- }
+ if (usbh2_pdata.otg)
+ imx27_add_mxc_ehci_hs(2, &usbh2_pdata);
imx27_add_imx_fb(&pca100_fb_data);
diff --git a/arch/arm/mach-mx3/mach-armadillo5x0.c b/arch/arm/mach-mx3/mach-armadillo5x0.c
index 34e619e..226829b 100644
--- a/arch/arm/mach-mx3/mach-armadillo5x0.c
+++ b/arch/arm/mach-mx3/mach-armadillo5x0.c
@@ -133,7 +133,6 @@ static int armadillo5x0_pins[] = {
};
/* USB */
-#if defined(CONFIG_USB_ULPI)
#define OTG_RESET IOMUX_TO_GPIO(MX31_PIN_STXD4)
#define USBH2_RESET IOMUX_TO_GPIO(MX31_PIN_SCK6)
@@ -256,7 +255,6 @@ static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
.init = usbh2_init,
.portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
};
-#endif /* CONFIG_USB_ULPI */
/* RTC over I2C*/
#define ARMADILLO5X0_RTC_GPIO IOMUX_TO_GPIO(MX31_PIN_SRXD4)
@@ -549,15 +547,15 @@ static void __init armadillo5x0_init(void)
i2c_register_board_info(1, &armadillo5x0_i2c_rtc, 1);
/* USB */
-#if defined(CONFIG_USB_ULPI)
- usbotg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
- ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
- usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
- ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
-
- imx31_add_mxc_ehci_otg(&usbotg_pdata);
- imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
-#endif
+
+ usbotg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
+ ULPI_OTG_DRVVBUS_EXT);
+ if (usbotg_pdata.otg)
+ imx31_add_mxc_ehci_otg(&usbotg_pdata);
+ usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
+ ULPI_OTG_DRVVBUS_EXT);
+ if (usbh2_pdata.otg)
+ imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
}
static void __init armadillo5x0_timer_init(void)
diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c
index 35fdb2a..f1dbb9d 100644
--- a/arch/arm/mach-mx3/mach-mx31_3ds.c
+++ b/arch/arm/mach-mx3/mach-mx31_3ds.c
@@ -244,7 +244,6 @@ usbotg_free_reset:
return err;
}
-#if defined(CONFIG_USB_ULPI)
static int mx31_3ds_otg_init(struct platform_device *pdev)
{
return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
@@ -300,7 +299,6 @@ static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
.init = mx31_3ds_host2_init,
.portsc = MXC_EHCI_MODE_ULPI,
};
-#endif
static const struct fsl_usb2_platform_data usbotg_pdata __initconst = {
.operating_mode = FSL_USB2_DR_DEVICE,
@@ -345,17 +343,17 @@ static void __init mx31_3ds_init(void)
imx31_add_imx_keypad(&mx31_3ds_keymap_data);
mx31_3ds_usbotg_init();
-#if defined(CONFIG_USB_ULPI)
if (otg_mode_host) {
- otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
- ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
-
- imx31_add_mxc_ehci_otg(&otg_pdata);
+ otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
+ ULPI_OTG_DRVVBUS_EXT);
+ if (otg_pdata.otg)
+ imx31_add_mxc_ehci_otg(&otg_pdata);
}
- usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
- ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
- imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
-#endif
+ usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
+ ULPI_OTG_DRVVBUS_EXT);
+ if (usbh2_pdata.otg)
+ imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
+
if (!otg_mode_host)
imx31_add_fsl_usb2_udc(&usbotg_pdata);
diff --git a/arch/arm/mach-mx3/mach-mx31lilly.c b/arch/arm/mach-mx3/mach-mx31lilly.c
index e2f9de1..ed95745 100644
--- a/arch/arm/mach-mx3/mach-mx31lilly.c
+++ b/arch/arm/mach-mx3/mach-mx31lilly.c
@@ -111,8 +111,6 @@ static struct platform_device physmap_flash_device = {
/* USB */
-#if defined(CONFIG_USB_ULPI)
-
#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
@@ -197,16 +195,13 @@ static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
static void lilly1131_usb_init(void)
{
- usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
- ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
-
imx31_add_mxc_ehci_hs(1, &usbh1_pdata);
- imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
-}
-#else
-static inline void lilly1131_usb_init(void) {}
-#endif /* CONFIG_USB_ULPI */
+ usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
+ ULPI_OTG_DRVVBUS_EXT);
+ if (usbh2_pdata.otg)
+ imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
+}
/* SPI */
diff --git a/arch/arm/mach-mx3/mach-mx31lite.c b/arch/arm/mach-mx3/mach-mx31lite.c
index 81021bf..24a21a3 100644
--- a/arch/arm/mach-mx3/mach-mx31lite.c
+++ b/arch/arm/mach-mx3/mach-mx31lite.c
@@ -130,7 +130,6 @@ static struct spi_board_info mc13783_spi_dev __initdata = {
* USB
*/
-#if defined(CONFIG_USB_ULPI)
#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
@@ -177,7 +176,6 @@ static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
.init = usbh2_init,
.portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
};
-#endif
/*
* NOR flash
@@ -254,13 +252,11 @@ static void __init mx31lite_init(void)
imx31_add_spi_imx1(&spi1_pdata);
spi_register_board_info(&mc13783_spi_dev, 1);
-#if defined(CONFIG_USB_ULPI)
/* USB */
- usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
- ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
-
- imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
-#endif
+ usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
+ ULPI_OTG_DRVVBUS_EXT);
+ if (usbh2_pdata.otg)
+ imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
/* SMSC9117 IRQ pin */
ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_SFS6), "sms9117-irq");
diff --git a/arch/arm/mach-mx3/mach-mx31moboard.c b/arch/arm/mach-mx3/mach-mx31moboard.c
index 845d0b6..6f3692b 100644
--- a/arch/arm/mach-mx3/mach-mx31moboard.c
+++ b/arch/arm/mach-mx3/mach-mx31moboard.c
@@ -400,7 +400,6 @@ static void usb_xcvr_reset(void)
mdelay(1);
}
-#if defined(CONFIG_USB_ULPI)
static int moboard_usbh2_init_hw(struct platform_device *pdev)
{
return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
@@ -415,8 +414,10 @@ static int __init moboard_usbh2_init(void)
{
struct platform_device *pdev;
- usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
- ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
+ usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
+ ULPI_OTG_DRVVBUS_EXT);
+ if (!usbh2_pdata.otg)
+ return -ENODEV;
pdev = imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
if (IS_ERR(pdev))
@@ -424,10 +425,6 @@ static int __init moboard_usbh2_init(void)
return 0;
}
-#else
-static inline int moboard_usbh2_init(void) { return 0; }
-#endif
-
static struct gpio_led mx31moboard_leds[] = {
{
diff --git a/arch/arm/mach-mx3/mach-pcm037.c b/arch/arm/mach-mx3/mach-pcm037.c
index 783d31b..f07d3bd 100644
--- a/arch/arm/mach-mx3/mach-pcm037.c
+++ b/arch/arm/mach-mx3/mach-pcm037.c
@@ -533,7 +533,6 @@ static struct platform_device pcm970_sja1000 = {
.num_resources = ARRAY_SIZE(pcm970_sja1000_resources),
};
-#if defined(CONFIG_USB_ULPI)
static int pcm037_otg_init(struct platform_device *pdev)
{
return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
@@ -553,7 +552,6 @@ static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
.init = pcm037_usbh2_init,
.portsc = MXC_EHCI_MODE_ULPI,
};
-#endif
static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
.operating_mode = FSL_USB2_DR_DEVICE,
@@ -656,19 +654,18 @@ static void __init pcm037_init(void)
platform_device_register(&pcm970_sja1000);
-#if defined(CONFIG_USB_ULPI)
if (otg_mode_host) {
- otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
- ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
-
- imx31_add_mxc_ehci_otg(&otg_pdata);
+ otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
+ ULPI_OTG_DRVVBUS_EXT);
+ if (otg_pdata.otg)
+ imx31_add_mxc_ehci_otg(&otg_pdata);
}
- usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
- ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
+ usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
+ ULPI_OTG_DRVVBUS_EXT);
+ if (usbh2_pdata.otg)
+ imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
- imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
-#endif
if (!otg_mode_host)
imx31_add_fsl_usb2_udc(&otg_device_pdata);
diff --git a/arch/arm/mach-mx3/mach-pcm043.c b/arch/arm/mach-mx3/mach-pcm043.c
index 262af17..b3ecfb2 100644
--- a/arch/arm/mach-mx3/mach-pcm043.c
+++ b/arch/arm/mach-mx3/mach-pcm043.c
@@ -305,7 +305,6 @@ pcm037_nand_board_info __initconst = {
.hw_ecc = 1,
};
-#if defined(CONFIG_USB_ULPI)
static int pcm043_otg_init(struct platform_device *pdev)
{
return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
@@ -315,7 +314,6 @@ static struct mxc_usbh_platform_data otg_pdata __initdata = {
.init = pcm043_otg_init,
.portsc = MXC_EHCI_MODE_UTMI,
};
-#endif
static int pcm043_usbh1_init(struct platform_device *pdev)
{
@@ -385,14 +383,12 @@ static void __init pcm043_init(void)
mxc_register_device(&mx3_ipu, &mx3_ipu_data);
mxc_register_device(&mx3_fb, &mx3fb_pdata);
-#if defined(CONFIG_USB_ULPI)
if (otg_mode_host) {
- otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
- ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
-
- imx35_add_mxc_ehci_otg(&otg_pdata);
+ otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
+ ULPI_OTG_DRVVBUS_EXT);
+ if (otg_pdata.otg)
+ imx35_add_mxc_ehci_otg(&otg_pdata);
}
-#endif
imx35_add_mxc_ehci_hs(&usbh1_pdata);
if (!otg_mode_host)
diff --git a/arch/arm/mach-mx3/mx31moboard-smartbot.c b/arch/arm/mach-mx3/mx31moboard-smartbot.c
index 87d556f..35f806e 100644
--- a/arch/arm/mach-mx3/mx31moboard-smartbot.c
+++ b/arch/arm/mach-mx3/mx31moboard-smartbot.c
@@ -137,8 +137,10 @@ static int __init smartbot_otg_host_init(void)
{
struct platform_device *pdev;
- otg_host_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
- ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
+ otg_host_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
+ ULPI_OTG_DRVVBUS_EXT);
+ if (!otg_host_pdata.otg)
+ return -ENODEV;
pdev = imx31_add_mxc_ehci_otg(&otg_host_pdata);
if (IS_ERR(pdev))
diff --git a/arch/arm/mach-mx5/board-mx51_efikasb.c b/arch/arm/mach-mx5/board-mx51_efikasb.c
index 18e29b9..db04ce8 100644
--- a/arch/arm/mach-mx5/board-mx51_efikasb.c
+++ b/arch/arm/mach-mx5/board-mx51_efikasb.c
@@ -129,10 +129,10 @@ static struct mxc_usbh_platform_data usbh2_config = {
static void __init mx51_efikasb_usb(void)
{
- usbh2_config.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
- ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT |
- ULPI_OTG_EXTVBUSIND);
- mxc_register_device(&mxc_usbh2_device, &usbh2_config);
+ usbh2_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
+ ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND);
+ if (usbh2_config.otg)
+ mxc_register_device(&mxc_usbh2_device, &usbh2_config);
}
static struct gpio_led mx51_efikasb_leds[] = {
diff --git a/arch/arm/mach-mx5/mx51_efika.c b/arch/arm/mach-mx5/mx51_efika.c
index 74991c9..51a67fc 100644
--- a/arch/arm/mach-mx5/mx51_efika.c
+++ b/arch/arm/mach-mx5/mx51_efika.c
@@ -218,12 +218,12 @@ static void __init mx51_efika_usb(void)
msleep(1);
gpio_set_value(EFIKA_USB_PHY_RESET, 1);
- usbh1_config.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
- ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT |
- ULPI_OTG_EXTVBUSIND);
+ usbh1_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
+ ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND);
mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
- mxc_register_device(&mxc_usbh1_device, &usbh1_config);
+ if (usbh1_config.otg)
+ mxc_register_device(&mxc_usbh1_device, &usbh1_config);
}
static struct mtd_partition mx51_efika_spi_nor_partitions[] = {
diff --git a/arch/arm/plat-mxc/include/mach/ulpi.h b/arch/arm/plat-mxc/include/mach/ulpi.h
index 96b6ab4..f9161c9 100644
--- a/arch/arm/plat-mxc/include/mach/ulpi.h
+++ b/arch/arm/plat-mxc/include/mach/ulpi.h
@@ -1,6 +1,15 @@
#ifndef __MACH_ULPI_H
#define __MACH_ULPI_H
+#ifdef CONFIG_USB_ULPI
+struct otg_transceiver *imx_otg_ulpi_create(unsigned int flags);
+#else
+static inline struct otg_transceiver *imx_otg_ulpi_create(unsigned int flags)
+{
+ return NULL;
+}
+#endif
+
extern struct otg_io_access_ops mxc_ulpi_access_ops;
#endif /* __MACH_ULPI_H */
diff --git a/arch/arm/plat-mxc/ulpi.c b/arch/arm/plat-mxc/ulpi.c
index 582c6df..477e45b 100644
--- a/arch/arm/plat-mxc/ulpi.c
+++ b/arch/arm/plat-mxc/ulpi.c
@@ -22,6 +22,7 @@
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/usb/otg.h>
+#include <linux/usb/ulpi.h>
#include <mach/ulpi.h>
@@ -111,3 +112,7 @@ struct otg_io_access_ops mxc_ulpi_access_ops = {
};
EXPORT_SYMBOL_GPL(mxc_ulpi_access_ops);
+struct otg_transceiver *imx_otg_ulpi_create(unsigned int flags)
+{
+ return otg_ulpi_create(&mxc_ulpi_access_ops, flags);
+}
--
1.7.2.3
^ permalink raw reply related
* [PATCH] ARM: imx/mx25_3ds: Fix build failure
From: Sascha Hauer @ 2011-03-02 11:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1299028552-13186-1-git-send-email-festevam@gmail.com>
On Tue, Mar 01, 2011 at 10:15:52PM -0300, Fabio Estevam wrote:
> Commit
> ca8d906 (ARM: mach-imx: mx25_3ds: add write-protect and card-detect for SD)
>
> assigned a non-existing member .cd_gpio in a struct esdhc_platform_data.
> This field can be added later after the esdhc patches are merged.
> Fix the build for now.
I skipped the patch causing the issue instead. Please resend once the
dependencies are merged into mainline.
Sascha
>
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
> ---
> arch/arm/mach-imx/mach-mx25_3ds.c | 1 -
> 1 files changed, 0 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-imx/mach-mx25_3ds.c b/arch/arm/mach-imx/mach-mx25_3ds.c
> index 561f07f..11c25f9 100644
> --- a/arch/arm/mach-imx/mach-mx25_3ds.c
> +++ b/arch/arm/mach-imx/mach-mx25_3ds.c
> @@ -208,7 +208,6 @@ static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
>
> static const struct esdhc_platform_data mx25pdk_esdhc_pdata __initconst = {
> .wp_gpio = SD1_GPIO_WP,
> - .cd_gpio = SD1_GPIO_CD,
> };
>
> static void __init mx25pdk_init(void)
> --
> 1.6.0.4
>
>
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply
* [PATCH] ARM: mxs/mx28evk: add flexcan devices
From: Sascha Hauer @ 2011-03-02 11:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1299063284-21795-1-git-send-email-shawn.guo@freescale.com>
Hi Shawn,
On Wed, Mar 02, 2011 at 06:54:44PM +0800, Shawn Guo wrote:
> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
> ---
> arch/arm/mach-mxs/Kconfig | 1 +
> arch/arm/mach-mxs/mach-mx28evk.c | 37 +++++++++++++++++++++++++++++++++++++
> 2 files changed, 38 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
> index 55bf075..9a1f2cb 100644
> --- a/arch/arm/mach-mxs/Kconfig
> +++ b/arch/arm/mach-mxs/Kconfig
> @@ -31,6 +31,7 @@ config MACH_MX28EVK
> select MXS_HAVE_AMBA_DUART
> select MXS_HAVE_PLATFORM_AUART
> select MXS_HAVE_PLATFORM_FEC
> + select MXS_HAVE_PLATFORM_FLEXCAN
> select MXS_OCOTP
> default y
> help
> diff --git a/arch/arm/mach-mxs/mach-mx28evk.c b/arch/arm/mach-mxs/mach-mx28evk.c
> index 1f0b708..3cefb73 100644
> --- a/arch/arm/mach-mxs/mach-mx28evk.c
> +++ b/arch/arm/mach-mxs/mach-mx28evk.c
> @@ -28,6 +28,7 @@
> #include "devices-mx28.h"
> #include "gpio.h"
>
> +#define MX28EVK_FLEXCAN_SWITCH MXS_GPIO_NR(2, 13)
> #define MX28EVK_FEC_PHY_POWER MXS_GPIO_NR(2, 15)
> #define MX28EVK_FEC_PHY_RESET MXS_GPIO_NR(4, 13)
>
> @@ -95,6 +96,15 @@ static const iomux_cfg_t mx28evk_pads[] __initconst = {
> /* phy reset line */
> MX28_PAD_ENET0_RX_CLK__GPIO_4_13 |
> (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
> +
> + /* flexcan0 */
> + MX28_PAD_GPMI_RDY2__CAN0_TX,
> + MX28_PAD_GPMI_RDY3__CAN0_RX,
> + /* flexcan1 */
> + MX28_PAD_GPMI_CE2N__CAN1_TX,
> + MX28_PAD_GPMI_CE3N__CAN1_RX,
> + /* transceiver power control */
> + MX28_PAD_SSP1_CMD__GPIO_2_13,
> };
>
> /* fec */
> @@ -178,8 +188,28 @@ error:
> return -ETIMEDOUT;
> }
>
> +/* flexcan */
> +static void mx28evk_flexcan_switch(int enable)
> +{
> + static int count;
> +
> + if (enable) {
> + if (!count++)
> + gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 1);
> + } else {
> + if (!--count)
> + gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 0);
> + }
> +}
Why this count variable? It shouldn't hurt to call gpio_set_value
multiple times.
Sascha
> +
> +static const struct flexcan_platform_data mx28evk_flexcan_pdata __initconst = {
> + .transceiver_switch = mx28evk_flexcan_switch,
> +};
> +
> static void __init mx28evk_init(void)
> {
> + int ret;
> +
> mxs_iomux_setup_multiple_pads(mx28evk_pads, ARRAY_SIZE(mx28evk_pads));
>
> mx28_add_duart();
> @@ -192,6 +222,13 @@ static void __init mx28evk_init(void)
> mx28evk_fec_reset();
> mx28_add_fec(0, &mx28_fec_pdata[0]);
> mx28_add_fec(1, &mx28_fec_pdata[1]);
> +
> + ret = gpio_request_one(MX28EVK_FLEXCAN_SWITCH, GPIOF_DIR_OUT,
> + "flexcan-switch");
> + if (ret)
> + pr_warn("failed to request gpio flexcan-switch: %d\n", ret);
> + mx28_add_flexcan(0, &mx28evk_flexcan_pdata);
> + mx28_add_flexcan(1, &mx28evk_flexcan_pdata);
> }
>
> static void __init mx28evk_timer_init(void)
> --
> 1.7.1
>
>
>
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply
* [PATCH 2/7] OMAP2+: mux: Enable wakeup for wakeup enable requested pads
From: Govindraj.R @ 2011-03-02 11:12 UTC (permalink / raw)
To: linux-arm-kernel
For device pads which have OMAP_DEVICE_PAD_WAKEUP set (which means they
are wakeup capable) enable the IO-daisy wakeup capability.
During re-muxing avoid direct write with val as this can disturb if any
mux done at bootloader level so read the pad then write back.
Also add an API to fetch the wake-up status bit is set for given omap-hwmod
device using available mux info which is added during omap_hwmod_mux_init.
Wakeup status bit is needed for uart_resume_idle call from sram_idle path
based on wake-up event has occurred for given uart we can enable clocks back.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Govindraj.R <govindraj.raja@ti.com>
---
arch/arm/mach-omap2/mux.c | 28 ++++++++++++++++++++++++++
arch/arm/mach-omap2/mux.h | 13 ++++++++++++
arch/arm/mach-omap2/omap_hwmod.c | 13 ++++++++++++
arch/arm/plat-omap/include/plat/omap_hwmod.h | 1 +
4 files changed, 55 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 98148b6..50edcea 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -317,6 +317,29 @@ err1:
return NULL;
}
+/* Gets the wakeup status of given pad from omap-hwmod */
+int omap_hwmod_mux_wakeup(struct omap_hwmod_mux_info *hmux)
+{
+ int i;
+ unsigned int val;
+ u8 ret = 0;
+
+ for (i = 0; i < hmux->nr_pads; i++) {
+ struct omap_device_pad *pad = &hmux->pads[i];
+
+ if (pad->flags & OMAP_DEVICE_PAD_WAKEUP) {
+ val = omap_mux_read(pad->partition,
+ pad->mux->reg_offset);
+ if (val & OMAP_WAKEUP_EVENT) {
+ ret = 1;
+ break;
+ }
+ }
+ }
+
+ return ret;
+}
+
/* Assumes the calling function takes care of locking */
void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state)
{
@@ -342,6 +365,9 @@ void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state)
break;
flags &= ~OMAP_DEVICE_PAD_ENABLED;
val = pad->idle;
+ if (flags & OMAP_DEVICE_PAD_WAKEUP)
+ val |= OMAP_WAKEUP_EN;
+
pr_debug("%s: Idling %s %x\n", __func__,
pad->name, val);
break;
@@ -358,6 +384,8 @@ void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state)
};
if (val >= 0) {
+ val |= omap_mux_read(pad->partition,
+ pad->mux->reg_offset);
omap_mux_write(pad->partition, val,
pad->mux->reg_offset);
pad->flags = flags;
diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h
index a4ab17a..84a8fc2 100644
--- a/arch/arm/mach-omap2/mux.h
+++ b/arch/arm/mach-omap2/mux.h
@@ -220,8 +220,21 @@ omap_hwmod_mux_init(struct omap_device_pad *bpads, int nr_pads);
*/
void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state);
+
+/**
+ * omap_hwmod_mux_wakeup - omap hwmod check given pad had wakeup event
+ * @hmux: Pads for a hwmod
+ *
+ * Called only from omap_hwmod.c, do not use.
+ */
+int omap_hwmod_mux_wakeup(struct omap_hwmod_mux_info *hmux);
#else
+static inline int omap_hwmod_mux_wakeup(struct omap_hwmod_mux_info *hmux)
+{
+ return 0;
+}
+
static inline int omap_mux_init_gpio(int gpio, int val)
{
return 0;
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 9e89a58..893dae1 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -2239,3 +2239,16 @@ u32 omap_hwmod_get_context_loss_count(struct omap_hwmod *oh)
return ret;
}
+
+/**
+ * omap_hwmod_pad_wakeup_status - get pad wakeup status if mux is available.
+ * @oh: struct omap_hwmod *
+ *
+ * Returns the wake_up status bit of available pad mux pin.
+ */
+int omap_hmwod_pad_wakeup_status(struct omap_hwmod *oh)
+{
+ if (oh->mux)
+ return omap_hwmod_mux_wakeup(oh->mux);
+ return -EINVAL;
+}
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index fedd829..4100be0 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -588,6 +588,7 @@ int omap_hwmod_for_each_by_class(const char *classname,
int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state);
u32 omap_hwmod_get_context_loss_count(struct omap_hwmod *oh);
+int omap_hmwod_pad_wakeup_status(struct omap_hwmod *oh);
/*
* Chip variant-specific hwmod init routines - XXX should be converted
* to use initcalls once the initial boot ordering is straightened out
--
1.7.1
^ permalink raw reply related
* [PATCH] ARM: SAMSUNG: Include devs.h in dev-uart.c to prototype devices
From: Mark Brown @ 2011-03-02 11:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1299060244-22710-1-git-send-email-broonie@opensource.wolfsonmicro.com>
On Wed, Mar 02, 2011 at 10:04:04AM +0000, Mark Brown wrote:
> Ensures that the declaration agrees with the definition and makes sparse
> happy.
Sorry, this patch is clearly bogus - no idea what's going on there.
^ permalink raw reply
* [RFC PATCH 1/1] ARM: imx5x: clean up ARCH_MX5X
From: Uwe Kleine-König @ 2011-03-02 11:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1299036526-15674-1-git-send-email-richard.zhao@freescale.com>
Hello Richard,
On Wed, Mar 02, 2011 at 11:28:46AM +0800, Richard Zhao wrote:
> Remove legacy support of ARCH_MX5X. Move to SOC_SOC_IMX5X.
>
> My understanding is ARCH_MX5 selects Kconfig in arch/arm/mach-mx5,
> and every board can be selected/unselected, and SOC_XXX be selected
> by the board config. MACH_XXXX/SOC_XXXX then select those HAVE_XXXX.
My intended goal with these ARCH_MX.., MACH_MX.. and SOC_IMX.. symbols is:
- ARCH_MX.. should be only a helper to group all machines together that
can be built in a single image. In the far future it hopefully dies
because we can compile everything together. These IMHO should not be
used in Makefiles or source files at all as the grouping can change
over time. I'm not sure the name ARCH_MX.. is that good. Didn't think
about a better naming scheme, so if you have suggestions don't
hesitate to tell them.
- MACH_MX.. actually are misnomers becauce they clash with the name
space of the machine db. So they should be substituted by SOC_IMX...
(maybe a few by ARCH_MX..) (affected: MACH_MX21 and MACH_MX27)
- SOC_IMX.. are used to differentiate between SoCs.
So a goal is to review all ARCH_MX.. and MACH_MX.. used in .c and .h
files and try to use the SOC_IMX variables instead.
Here I consider important that SOC_IMX... is really only used with
having multi-SoC-kernels in mind. So you can consider ARCH_MX and
MACH_MX as todo-markers for that (and this is the main difference IMHO).
E.g. the Makefile.boots are such a place that are not multi-soc capable
yet as is the selection of PHYS_OFFSET. I'd like to keep them marked
somehow.
I don't know if it's sensible to coordinate this effort, it mainly
depends on how many people are willing to help. I'll start with ARCH_MX2
and MACH_MX2[17] next.
A bit orthogonal to this issue is to clean up mach-mx3 and mach-mx5 to
allow them to be merged into mach-imx. I didn't look at all on mxc91231,
yet.
Comments and patches are welcome. If you want to help and don't know
where to start, here are a few hints:
- git grep -E 'M?AR?CH_MX' drivers
- convert arch/arm/mach-mx[35]/devices.c to dynamically allocation
Richard, having said that, some of your changes look OK, while I'm not
completely happy with the others.
> diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
> index f065a0d..518a39e 100644
> --- a/arch/arm/mach-mx5/Kconfig
> +++ b/arch/arm/mach-mx5/Kconfig
> @@ -1,14 +1,4 @@
> if ARCH_MX5
> -# ARCH_MX51 and ARCH_MX50 are left for compatibility
> -
> -config ARCH_MX50
> - bool
> -
> -config ARCH_MX51
> - bool
> -
> -config ARCH_MX53
> - bool
these are still needed, see below (or you should suggest an alternative marking).
> config SOC_IMX50
> bool
> @@ -16,7 +6,6 @@ config SOC_IMX50
> select ARCH_MXC_IOMUX_V3
> select ARCH_MXC_AUDMUX_V2
> select ARCH_HAS_CPUFREQ
> - select ARCH_MX50
>
> config SOC_IMX51
> bool
> @@ -24,13 +13,11 @@ config SOC_IMX51
> select ARCH_MXC_IOMUX_V3
> select ARCH_MXC_AUDMUX_V2
> select ARCH_HAS_CPUFREQ
> - select ARCH_MX51
>
> config SOC_IMX53
> bool
> select MXC_TZIC
> select ARCH_MXC_IOMUX_V3
> - select ARCH_MX53
>
> comment "MX5 platforms:"
>
> diff --git a/arch/arm/mach-mx5/Makefile.boot b/arch/arm/mach-mx5/Makefile.boot
> index e928be1..cdc70b3 100644
> --- a/arch/arm/mach-mx5/Makefile.boot
> +++ b/arch/arm/mach-mx5/Makefile.boot
> @@ -1,9 +1,9 @@
> - zreladdr-$(CONFIG_ARCH_MX50) := 0x70008000
> -params_phys-$(CONFIG_ARCH_MX50) := 0x70000100
> -initrd_phys-$(CONFIG_ARCH_MX50) := 0x70800000
> - zreladdr-$(CONFIG_ARCH_MX51) := 0x90008000
> -params_phys-$(CONFIG_ARCH_MX51) := 0x90000100
> -initrd_phys-$(CONFIG_ARCH_MX51) := 0x90800000
> - zreladdr-$(CONFIG_ARCH_MX53) := 0x70008000
> -params_phys-$(CONFIG_ARCH_MX53) := 0x70000100
> -initrd_phys-$(CONFIG_ARCH_MX53) := 0x70800000
> + zreladdr-$(CONFIG_SOC_MX50) := 0x70008000
> +params_phys-$(CONFIG_SOC_MX50) := 0x70000100
> +initrd_phys-$(CONFIG_SOC_MX50) := 0x70800000
> + zreladdr-$(CONFIG_SOC_MX51) := 0x90008000
> +params_phys-$(CONFIG_SOC_MX51) := 0x90000100
> +initrd_phys-$(CONFIG_SOC_MX51) := 0x90800000
> + zreladdr-$(CONFIG_SOC_MX53) := 0x70008000
> +params_phys-$(CONFIG_SOC_MX53) := 0x70000100
> +initrd_phys-$(CONFIG_SOC_MX53) := 0x70800000
> diff --git a/arch/arm/plat-mxc/devices/platform-imx-dma.c b/arch/arm/plat-mxc/devices/platform-imx-dma.c
> index 33530d2..be7df13 100644
> --- a/arch/arm/plat-mxc/devices/platform-imx-dma.c
> +++ b/arch/arm/plat-mxc/devices/platform-imx-dma.c
> @@ -194,7 +194,7 @@ static int __init imxXX_add_imx_dma(void)
> } else
> #endif
>
> -#if defined(CONFIG_ARCH_MX51)
> +#if defined(CONFIG_SOC_IMX51)
> if (cpu_is_mx51()) {
> imx51_imx_sdma_data.pdata.script_addrs = &addr_imx51_to1;
> ret = imx_add_imx_sdma(&imx51_imx_sdma_data);
looks OK.
> diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h
> index ba65c92..a3d930d 100644
> --- a/arch/arm/plat-mxc/include/mach/irqs.h
> +++ b/arch/arm/plat-mxc/include/mach/irqs.h
> @@ -23,17 +23,17 @@
> #define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS
>
> /* these are ordered by size to support multi-SoC kernels */
> -#if defined CONFIG_ARCH_MX53
> +#if defined CONFIG_SOC_IMX53
> #define MXC_GPIO_IRQS (32 * 7)
> #elif defined CONFIG_ARCH_MX2
> #define MXC_GPIO_IRQS (32 * 6)
> -#elif defined CONFIG_ARCH_MX50
> +#elif defined CONFIG_SOC_IMX50
> #define MXC_GPIO_IRQS (32 * 6)
> #elif defined CONFIG_ARCH_MX1
> #define MXC_GPIO_IRQS (32 * 4)
> #elif defined CONFIG_ARCH_MX25
> #define MXC_GPIO_IRQS (32 * 4)
> -#elif defined CONFIG_ARCH_MX51
> +#elif defined CONFIG_SOC_IMX51
> #define MXC_GPIO_IRQS (32 * 4)
> #elif defined CONFIG_ARCH_MXC91231
> #define MXC_GPIO_IRQS (32 * 4)
OK
> diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h
> index 8386140..f1e9c0a 100644
> --- a/arch/arm/plat-mxc/include/mach/memory.h
> +++ b/arch/arm/plat-mxc/include/mach/memory.h
> @@ -34,11 +34,11 @@
> # define PHYS_OFFSET MX3x_PHYS_OFFSET
> # elif defined CONFIG_ARCH_MXC91231
> # define PHYS_OFFSET MXC91231_PHYS_OFFSET
> -# elif defined CONFIG_ARCH_MX50
> +# elif defined CONFIG_SOC_IMX50
> # define PHYS_OFFSET MX50_PHYS_OFFSET
> -# elif defined CONFIG_ARCH_MX51
> +# elif defined CONFIG_SOC_IMX51
> # define PHYS_OFFSET MX51_PHYS_OFFSET
> -# elif defined CONFIG_ARCH_MX53
> +# elif defined CONFIG_SOC_IMX53
> # define PHYS_OFFSET MX53_PHYS_OFFSET
> # endif
> #endif
not ok
> diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
> index 04c7a26..3781f2f 100644
> --- a/arch/arm/plat-mxc/include/mach/mxc.h
> +++ b/arch/arm/plat-mxc/include/mach/mxc.h
> @@ -127,7 +127,7 @@ extern unsigned int __mxc_cpu_type;
> # define cpu_is_mx35() (0)
> #endif
>
> -#ifdef CONFIG_ARCH_MX50
> +#ifdef CONFIG_SOC_IMX50
> # ifdef mxc_cpu_type
> # undef mxc_cpu_type
> # define mxc_cpu_type __mxc_cpu_type
> @@ -139,7 +139,7 @@ extern unsigned int __mxc_cpu_type;
> # define cpu_is_mx50() (0)
> #endif
>
> -#ifdef CONFIG_ARCH_MX51
> +#ifdef CONFIG_SOC_IMX51
> # ifdef mxc_cpu_type
> # undef mxc_cpu_type
> # define mxc_cpu_type __mxc_cpu_type
> @@ -151,7 +151,7 @@ extern unsigned int __mxc_cpu_type;
> # define cpu_is_mx51() (0)
> #endif
>
> -#ifdef CONFIG_ARCH_MX53
> +#ifdef CONFIG_SOC_IMX53
> # ifdef mxc_cpu_type
> # undef mxc_cpu_type
> # define mxc_cpu_type __mxc_cpu_type
These are OK, too, I think
> diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
> index c895922..daeafc2 100644
> --- a/drivers/mtd/nand/Kconfig
> +++ b/drivers/mtd/nand/Kconfig
> @@ -476,7 +476,7 @@ config MTD_NAND_MPC5121_NFC
>
> config MTD_NAND_MXC
> tristate "MXC NAND support"
> - depends on ARCH_MX2 || ARCH_MX25 || ARCH_MX3 || ARCH_MX51
> + depends on ARCH_MX2 || ARCH_MX25 || ARCH_MX3 || SOC_IMX51
OK, though I'd prefer having
depends on HAVE_MTD_NAND_MXC
and let the SOC_IMXYZ symbols select this one.
> help
> This enables the driver for the NAND flash controller on the
> MXC processors.
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> index bb233a9..9f9d3f7 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -164,10 +164,10 @@ config SPI_IMX_VER_0_4
> def_bool y if ARCH_MX31
>
> config SPI_IMX_VER_0_7
> - def_bool y if ARCH_MX25 || ARCH_MX35 || ARCH_MX51 || ARCH_MX53
> + def_bool y if ARCH_MX25 || ARCH_MX35 || SOC_IMX51 || SOC_IMX53
>
> config SPI_IMX_VER_2_3
> - def_bool y if ARCH_MX51 || ARCH_MX53
> + def_bool y if SOC_IMX51 || SOC_IMX53
>
> config SPI_IMX
> tristate "Freescale i.MX SPI controllers"
ok
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-K?nig |
Industrial Linux Solutions | http://www.pengutronix.de/ |
^ permalink raw reply
* [PATCH v8 0/1] Add PRUSS UIO driver support
From: Pratheesh Gangadhar @ 2011-03-02 11:38 UTC (permalink / raw)
To: linux-arm-kernel
This patch series add support for PRUSS (Programmable Real-time Unit Sub
System) UIO driver in Texas Instruments DA850, AM18xx and OMAP-L138 processors.
PRUSS is programmable RISC core which can be used to implement Soft IPs
(eg:- DMA, CAN, UART,SmartCard) and Industrial communications data link layers
(eg:- PROFIBUS). UIO driver exposes PRUSS resources like memory and interrupts
to user space application.PRUSS UIO application API can be used to control PRUs
in PRUSS, setup PRU INTC, load firmware to PRUs and implement IPC between Host
processor and PRUs. More information on PRUSS and UIO linux user space API
available in the links below
http://processors.wiki.ti.com/index.php/Programmable_Realtime_Unit_Subsystem
http://processors.wiki.ti.com/index.php/PRU_Linux_Application_Loader
http://processors.wiki.ti.com/index.php/PRU_Linux_Application_Loader_API_Guide
Platform/board specific portion of this patch depends on Mistral patches below
[PATCH 1/1] davinci: changed SRAM allocator to shared ram :
https://patchwork.kernel.org/patch/549351/
[PATCH 1/1] da830: macro rename DA8XX_LPSC0_DMAX to DA8XX_LPSC0_PRUSS :
https://patchwork.kernel.org/patch/549331/
[PATCH v2 01/13] mfd: pruss mfd driver :
https://patchwork.kernel.org/patch/549531/
[PATCH v2 02/13] da850: pruss platform specific additions :
https://patchwork.kernel.org/patch/549521/
I will submit a seperate patch set on top of these patches to support PRUSS
UIO driver.
Pratheesh Gangadhar (1):
PRUSS UIO driver support
drivers/uio/Kconfig | 17 ++++
drivers/uio/Makefile | 1 +
drivers/uio/uio_pruss.c | 226 +++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 244 insertions(+), 0 deletions(-)
create mode 100644 drivers/uio/uio_pruss.c
^ permalink raw reply
* [PATCH v8 1/1] PRUSS UIO driver support
From: Pratheesh Gangadhar @ 2011-03-02 11:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1299065886-30099-1-git-send-email-pratheesh@ti.com>
This patch implements PRUSS (Programmable Real-time Unit Sub System)
UIO driver which exports SOC resources associated with PRUSS like
I/O, memories and IRQs to user space. PRUSS is dual 32-bit RISC
processors which is efficient in performing embedded tasks that
require manipulation of packed memory mapped data structures and
handling system events that have tight real time constraints. This
driver is currently supported on Texas Instruments DA850, AM18xx and
OMAP-L138 devices.
For example, PRUSS runs firmware for real-time critical industrial
communication data link layer and communicates with application stack
running in user space via shared memory and IRQs.
Signed-off-by: Pratheesh Gangadhar <pratheesh@ti.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
---
drivers/uio/Kconfig | 17 ++++
drivers/uio/Makefile | 1 +
drivers/uio/uio_pruss.c | 226 +++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 244 insertions(+), 0 deletions(-)
create mode 100644 drivers/uio/uio_pruss.c
diff --git a/drivers/uio/Kconfig b/drivers/uio/Kconfig
index bb44079..6f3ea9b 100644
--- a/drivers/uio/Kconfig
+++ b/drivers/uio/Kconfig
@@ -94,4 +94,21 @@ config UIO_NETX
To compile this driver as a module, choose M here; the module
will be called uio_netx.
+config UIO_PRUSS
+ tristate "Texas Instruments PRUSS driver"
+ depends on ARCH_DAVINCI_DA850
+ help
+ PRUSS driver for OMAPL138/DA850/AM18XX devices
+ PRUSS driver requires user space components, examples and user space
+ driver is available from below SVN repo - you may use anonymous login
+
+ https://gforge.ti.com/gf/project/pru_sw/
+
+ More info on API is available at below wiki
+
+ http://processors.wiki.ti.com/index.php/PRU_Linux_Application_Loader
+
+ To compile this driver as a module, choose M here: the module
+ will be called uio_pruss.
+
endif
diff --git a/drivers/uio/Makefile b/drivers/uio/Makefile
index 18fd818..d4dd9a5 100644
--- a/drivers/uio/Makefile
+++ b/drivers/uio/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_UIO_AEC) += uio_aec.o
obj-$(CONFIG_UIO_SERCOS3) += uio_sercos3.o
obj-$(CONFIG_UIO_PCI_GENERIC) += uio_pci_generic.o
obj-$(CONFIG_UIO_NETX) += uio_netx.o
+obj-$(CONFIG_UIO_PRUSS) += uio_pruss.o
diff --git a/drivers/uio/uio_pruss.c b/drivers/uio/uio_pruss.c
new file mode 100644
index 0000000..12469ae
--- /dev/null
+++ b/drivers/uio/uio_pruss.c
@@ -0,0 +1,226 @@
+/*
+ * Programmable Real-Time Unit Sub System (PRUSS) UIO driver (uio_pruss)
+ *
+ * This driver exports PRUSS host event out interrupts and PRUSS, L3 RAM,
+ * and DDR RAM to user space for applications interacting with PRUSS firmware
+ *
+ * Copyright (C) 2010-11 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/platform_device.h>
+#include <linux/uio_driver.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/dma-mapping.h>
+#include <linux/slab.h>
+#include <mach/sram.h>
+
+#define DRV_NAME "pruss_uio"
+#define DRV_VERSION "0.50"
+
+static int sram_pool_sz = SZ_16K;
+module_param(sram_pool_sz, int, 0);
+MODULE_PARM_DESC(sram_pool_sz, "sram pool size to allocate ");
+
+static int extram_pool_sz = SZ_256K;
+module_param(extram_pool_sz, int, 0);
+MODULE_PARM_DESC(extram_pool_sz, "external ram pool size to allocate");
+
+/*
+ * Host event IRQ numbers from PRUSS - PRUSS can generate upto 8 interrupt
+ * events to AINTC of ARM host processor - which can be used for IPC b/w PRUSS
+ * firmware and user space application, async notification from PRU firmware
+ * to user space application
+ * 3 PRU_EVTOUT0
+ * 4 PRU_EVTOUT1
+ * 5 PRU_EVTOUT2
+ * 6 PRU_EVTOUT3
+ * 7 PRU_EVTOUT4
+ * 8 PRU_EVTOUT5
+ * 9 PRU_EVTOUT6
+ * 10 PRU_EVTOUT7
+*/
+#define MAX_PRUSS_EVT 8
+
+#define PINTC_HIDISR 0x4038
+#define PINTC_HIPIR 0x4900
+#define HIPIR_NOPEND 0x80000000
+#define PINTC_HIER 0x5500
+
+static struct clk *pruss_clk;
+static struct uio_info *info;
+static dma_addr_t sram_paddr, ddr_paddr;
+static void *prussio_vaddr, *sram_vaddr, *ddr_vaddr;
+
+static irqreturn_t pruss_handler(int irq, struct uio_info *info)
+{
+ int intr_bit = (irq - IRQ_DA8XX_EVTOUT0 + 2);
+ int val, intr_mask = (1 << intr_bit);
+ void __iomem *base = info->mem[0].internal_addr;
+ void __iomem *intren_reg = base + PINTC_HIER;
+ void __iomem *intrdis_reg = base + PINTC_HIDISR;
+ void __iomem *intrstat_reg = base + PINTC_HIPIR + (intr_bit << 2);
+
+ val = ioread32(intren_reg);
+ /* Is interrupt enabled and active ? */
+ if (!(val & intr_mask) && (ioread32(intrstat_reg) & HIPIR_NOPEND))
+ return IRQ_NONE;
+ /* Disable interrupt */
+ iowrite32(intr_bit, intrdis_reg);
+ return IRQ_HANDLED;
+}
+
+static void pruss_cleanup(struct platform_device *dev, struct uio_info *info)
+{
+ int cnt;
+ struct uio_info *p = info;
+
+ for (cnt = 0; cnt < MAX_PRUSS_EVT; cnt++, p++) {
+ uio_unregister_device(p);
+ kfree(p->name);
+ }
+ iounmap(prussio_vaddr);
+ if (ddr_vaddr) {
+ dma_free_coherent(&dev->dev, extram_pool_sz, ddr_vaddr,
+ ddr_paddr);
+ }
+ if (sram_vaddr)
+ sram_free(sram_vaddr, sram_pool_sz);
+ kfree(info);
+ clk_put(pruss_clk);
+}
+
+static int __devinit pruss_probe(struct platform_device *dev)
+{
+ struct uio_info *p;
+ struct resource *regs_prussio;
+ int ret = -ENODEV, cnt = 0, len;
+
+ info = kzalloc(sizeof(struct uio_info) * MAX_PRUSS_EVT, GFP_KERNEL);
+ if (!info)
+ return -ENOMEM;
+ /* Power on PRU in case its not done as part of boot-loader */
+ pruss_clk = clk_get(&dev->dev, "pruss");
+ if (IS_ERR(pruss_clk)) {
+ dev_err(&dev->dev, "Failed to get clock\n");
+ kfree(info);
+ ret = PTR_ERR(pruss_clk);
+ return ret;
+ } else {
+ clk_enable(pruss_clk);
+ }
+
+ regs_prussio = platform_get_resource(dev, IORESOURCE_MEM, 0);
+ if (!regs_prussio) {
+ dev_err(&dev->dev, "No PRUSS I/O resource specified\n");
+ goto out_free;
+ }
+
+ if (!regs_prussio->start) {
+ dev_err(&dev->dev, "Invalid memory resource\n");
+ goto out_free;
+ }
+
+ sram_vaddr = sram_alloc(sram_pool_sz, &sram_paddr);
+ if (!sram_vaddr) {
+ dev_err(&dev->dev, "Could not allocate SRAM pool\n");
+ goto out_free;
+ }
+
+ ddr_vaddr = dma_alloc_coherent(&dev->dev, extram_pool_sz, &ddr_paddr,
+ GFP_KERNEL | GFP_DMA);
+ if (!ddr_vaddr) {
+ dev_err(&dev->dev, "Could not allocate external memory\n");
+ goto out_free;
+ }
+
+ len = resource_size(regs_prussio);
+ prussio_vaddr = ioremap(regs_prussio->start, len);
+ if (!prussio_vaddr) {
+ dev_err(&dev->dev, "Can't remap PRUSS I/O address range\n");
+ goto out_free;
+ }
+
+ for (cnt = 0, p = info; cnt < MAX_PRUSS_EVT; cnt++, p++) {
+ p->mem[0].internal_addr = prussio_vaddr;
+ p->mem[0].addr = regs_prussio->start;
+ p->mem[0].size = resource_size(regs_prussio);
+ p->mem[0].memtype = UIO_MEM_PHYS;
+
+ p->mem[1].internal_addr = sram_vaddr;
+ p->mem[1].addr = sram_paddr;
+ p->mem[1].size = sram_pool_sz;
+ p->mem[1].memtype = UIO_MEM_PHYS;
+
+ p->mem[2].internal_addr = ddr_vaddr;
+ p->mem[2].addr = ddr_paddr;
+ p->mem[2].size = extram_pool_sz;
+ p->mem[2].memtype = UIO_MEM_PHYS;
+
+ p->name = kasprintf(GFP_KERNEL, "pruss_evt%d", cnt);
+ p->version = "0.50";
+
+ /* Register PRUSS IRQ lines */
+ p->irq = IRQ_DA8XX_EVTOUT0 + cnt;
+ p->handler = pruss_handler;
+
+ ret = uio_register_device(&dev->dev, p);
+ if (ret < 0)
+ goto out_free;
+ }
+
+ platform_set_drvdata(dev, info);
+ return 0;
+
+out_free:
+ pruss_cleanup(dev, info);
+ return ret;
+}
+
+static int __devexit pruss_remove(struct platform_device *dev)
+{
+ struct uio_info *info = platform_get_drvdata(dev);
+
+ pruss_cleanup(dev, info);
+ platform_set_drvdata(dev, NULL);
+ return 0;
+}
+
+static struct platform_driver pruss_driver = {
+ .probe = pruss_probe,
+ .remove = __devexit_p(pruss_remove),
+ .driver = {
+ .name = DRV_NAME,
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init pruss_init_module(void)
+{
+ return platform_driver_register(&pruss_driver);
+}
+
+module_init(pruss_init_module);
+
+static void __exit pruss_exit_module(void)
+{
+ platform_driver_unregister(&pruss_driver);
+}
+
+module_exit(pruss_exit_module);
+
+MODULE_LICENSE("GPL v2");
+MODULE_VERSION(DRV_VERSION);
+MODULE_AUTHOR("Amit Chatterjee <amit.chatterjee@ti.com>");
+MODULE_AUTHOR("Pratheesh Gangadhar <pratheesh@ti.com>");
--
1.6.0.6
^ permalink raw reply related
* [PATCHv5 0/3] Introduce the /proc/socinfo and use it to export OMAP data
From: Jamie Iles @ 2011-03-02 11:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <AANLkTimJh_uGP6SYo=9ndz4xiUs1Tbg7z70ng0aFcWyG@mail.gmail.com>
On Wed, Mar 02, 2011 at 11:36:38AM +0100, Linus Walleij wrote:
> On Wed, Mar 2, 2011 at 9:23 AM, Maxime Coquelin
> <maxime.coquelin-nonst@stericsson.com> wrote:
>
> > I think we should have a tree like this :
> >
> > /sys/devices/system/soc/
> > /sys/devices/system/soc/unique_id<- Unified way to export an ID for all machs
>
> Arbitrary number of bits? Some will have a 64-bit ID, some will have 32-bit
> etc.
>
> Should we say it's a hex string of 64 bits?
Could we provide hooks for the platform that takes the buffer and length
and let the platform do the snprintf()? Our devices have a 128-bit
serial number and I'm sure there must be others.
> > /sys/devices/system/soc/mach/
> > /sys/devices/system/soc/mach/name<- Name of the mach
> > /sys/devices/system/soc/mach/foo_id
> > /sys/devices/system/soc/mach/bar_id<- Vendors may have several/different IDs
> > to export (IDCODE for OMAP, Production ID...)
Do we need a way to allow platforms to specify additional attributes to
co into the socinfo? For our devices we can boot in different modes and
how we boot determines how the firmware is upgraded. In the case above
the platform could specify that it needs foo_id and bar_id and the
callbacks to fill them in.
Jamie
^ permalink raw reply
* [PATCH] ARM: mxs/mx28evk: add flexcan devices
From: Shawn Guo @ 2011-03-02 11:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110302111148.GV29521@pengutronix.de>
On Wed, Mar 02, 2011 at 12:11:48PM +0100, Sascha Hauer wrote:
> Hi Shawn,
>
Hi Sascha,
> On Wed, Mar 02, 2011 at 06:54:44PM +0800, Shawn Guo wrote:
> > Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
> > ---
> > arch/arm/mach-mxs/Kconfig | 1 +
> > arch/arm/mach-mxs/mach-mx28evk.c | 37 +++++++++++++++++++++++++++++++++++++
> > 2 files changed, 38 insertions(+), 0 deletions(-)
> >
> > diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
> > index 55bf075..9a1f2cb 100644
> > --- a/arch/arm/mach-mxs/Kconfig
> > +++ b/arch/arm/mach-mxs/Kconfig
> > @@ -31,6 +31,7 @@ config MACH_MX28EVK
> > select MXS_HAVE_AMBA_DUART
> > select MXS_HAVE_PLATFORM_AUART
> > select MXS_HAVE_PLATFORM_FEC
> > + select MXS_HAVE_PLATFORM_FLEXCAN
> > select MXS_OCOTP
> > default y
> > help
> > diff --git a/arch/arm/mach-mxs/mach-mx28evk.c b/arch/arm/mach-mxs/mach-mx28evk.c
> > index 1f0b708..3cefb73 100644
> > --- a/arch/arm/mach-mxs/mach-mx28evk.c
> > +++ b/arch/arm/mach-mxs/mach-mx28evk.c
> > @@ -28,6 +28,7 @@
> > #include "devices-mx28.h"
> > #include "gpio.h"
> >
> > +#define MX28EVK_FLEXCAN_SWITCH MXS_GPIO_NR(2, 13)
> > #define MX28EVK_FEC_PHY_POWER MXS_GPIO_NR(2, 15)
> > #define MX28EVK_FEC_PHY_RESET MXS_GPIO_NR(4, 13)
> >
> > @@ -95,6 +96,15 @@ static const iomux_cfg_t mx28evk_pads[] __initconst = {
> > /* phy reset line */
> > MX28_PAD_ENET0_RX_CLK__GPIO_4_13 |
> > (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
> > +
> > + /* flexcan0 */
> > + MX28_PAD_GPMI_RDY2__CAN0_TX,
> > + MX28_PAD_GPMI_RDY3__CAN0_RX,
> > + /* flexcan1 */
> > + MX28_PAD_GPMI_CE2N__CAN1_TX,
> > + MX28_PAD_GPMI_CE3N__CAN1_RX,
> > + /* transceiver power control */
> > + MX28_PAD_SSP1_CMD__GPIO_2_13,
> > };
> >
> > /* fec */
> > @@ -178,8 +188,28 @@ error:
> > return -ETIMEDOUT;
> > }
> >
> > +/* flexcan */
> > +static void mx28evk_flexcan_switch(int enable)
> > +{
> > + static int count;
> > +
> > + if (enable) {
> > + if (!count++)
> > + gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 1);
> > + } else {
> > + if (!--count)
> > + gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 0);
> > + }
> > +}
>
> Why this count variable? It shouldn't hurt to call gpio_set_value
> multiple times.
>
This gpio controls the power of both flexcan0 and flexcan1
transceivers, and we do not want one power-off really shut the power
down if the other is still on.
--
Regards,
Shawn
^ permalink raw reply
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