* [PATCH v7 13/26] gpio/omap: use pinctrl offset instead of macro
From: Tony Lindgren @ 2011-09-21 14:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1315918979-26173-14-git-send-email-tarun.kanti@ti.com>
* Tarun Kanti DebBarma <tarun.kanti@ti.com> [110913 05:29]:
> From: Charulatha V <charu@ti.com>
>
> Use regs->pinctrl field instead of using the macro OMAP1510_GPIO_PIN_CONTROL
>
> Signed-off-by: Charulatha V <charu@ti.com>
> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
^ permalink raw reply
* [PATCH] ARM: vexpress: initial device tree support
From: Grant Likely @ 2011-09-21 14:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4E79E588.6010703@gmail.com>
On Wed, Sep 21, 2011 at 7:24 AM, Rob Herring <robherring2@gmail.com> wrote:
> On 09/21/2011 04:19 AM, Dave Martin wrote:
>> ? ? ? * arm,amba-bus -- widely used by other boards and patchsets, but
>> ? ? ? ? seems not to be documented.
>>
>
> This should be dropped. There's not really any bus component to an amba
> bus. All the probing info is within the primecell peripherals.
No, if it is an AMBA bus, then it is entirely appropriate to declare
it as an amba bus, but to also be compatible with "simple-bus". In
fact, it would be better to use a compatible string that specifies the
specific implementation of AMBA bus since there are several versions
of the spec.
Don't let Linux's current implementation detail derail what is
considered good practice.
g.
^ permalink raw reply
* [RFC v2 PATCH 1/1] ASoC: soc-core: symmetry checking for each DAIs separately
From: Mark Brown @ 2011-09-21 14:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1314609314-22162-1-git-send-email-b29396@freescale.com>
On Mon, Aug 29, 2011 at 05:15:14PM +0800, Dong Aisheng wrote:
> -static int soc_pcm_apply_symmetry(struct snd_pcm_substream *substream)
> +static int soc_pcm_apply_symmetry(struct snd_pcm_substream *substream,
> + struct snd_soc_dai *soc_dai)
Applied, thanks. But plain dai would have been a better name here.
^ permalink raw reply
* [PATCH v7 13/26] gpio/omap: use pinctrl offset instead of macro
From: Tony Lindgren @ 2011-09-21 15:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1315918979-26173-14-git-send-email-tarun.kanti@ti.com>
* Tarun Kanti DebBarma <tarun.kanti@ti.com> [110913 05:29]:
> From: Charulatha V <charu@ti.com>
>
> Use regs->pinctrl field instead of using the macro OMAP1510_GPIO_PIN_CONTROL
>
> Signed-off-by: Charulatha V <charu@ti.com>
> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
^ permalink raw reply
* [PATCH v7 15/26] gpio/omap: remove bank->method & METHOD_* macros
From: Tony Lindgren @ 2011-09-21 15:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1315918979-26173-16-git-send-email-tarun.kanti@ti.com>
* Tarun Kanti DebBarma <tarun.kanti@ti.com> [110913 05:30]:
> From: Charulatha V <charu@ti.com>
>
> The only bank->type (method) used in the OMAP GPIO driver is MPUIO type as they
> need to be handled separately. Identify the same using a flag and remove all
> METHOD_* macros.
>
> mpuio_init() function is defined under #ifdefs. It is required only in case
> of MPUIO bank type and only when PM operations are supported by it.
> This is applicable only in case of OMAP16xx SoC's MPUIO GPIO bank type.
> For all the other cases it is a dummy function. Hence clean up the same
> and remove all the OMAP SoC specific #ifdefs.
>
> Signed-off-by: Charulatha V <charu@ti.com>
> Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
^ permalink raw reply
* [PATCH v7 16/26] gpio/omap: fix bankwidth for OMAP7xx MPUIO
From: Tony Lindgren @ 2011-09-21 15:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1315918979-26173-17-git-send-email-tarun.kanti@ti.com>
* Tarun Kanti DebBarma <tarun.kanti@ti.com> [110913 05:30]:
> From: Charulatha V <charu@ti.com>
>
> In all OMAP1 SoCs, the MPUIO bank width is 16 bits. But, in OMAP7xx,
> it is wrongly initialised to 32. Fix this.
>
> Signed-off-by: Charulatha V <charu@ti.com>
> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
^ permalink raw reply
* [PATCH v7 26/26] gpio/omap: add dbclk aliases for all gpio modules
From: Tony Lindgren @ 2011-09-21 15:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1315918979-26173-27-git-send-email-tarun.kanti@ti.com>
* Tarun Kanti DebBarma <tarun.kanti@ti.com> [110913 05:29]:
> Unless the dbclk aliases are assigned, clk_get(bank->dev, "dbclk")
> would not fetch the associated clock handle. As a result, we would
> not be able to turn on/off the debounce clock. This was preventing
> the gpio modules going to low power mode whenever dbclk is enabled.
>
> Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
Looks OK to me, Paul should ack this one also:
Acked-by: Tony Lindgren <tony@atomide.com>
> ---
> arch/arm/mach-omap2/clock3xxx_data.c | 6 ++++++
> arch/arm/mach-omap2/clock44xx_data.c | 6 ++++++
> 2 files changed, 12 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
> index ffd55b1..7238ec1 100644
> --- a/arch/arm/mach-omap2/clock3xxx_data.c
> +++ b/arch/arm/mach-omap2/clock3xxx_data.c
> @@ -3462,6 +3462,12 @@ static struct omap_clk omap3xxx_clks[] = {
> CLK("musb-am35x", "fck", &hsotgusb_fck_am35xx, CK_AM35XX),
> CLK(NULL, "hecc_ck", &hecc_ck, CK_AM35XX),
> CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX),
> + CLK("omap_gpio.1", "dbclk", &gpio1_dbck, CK_3XXX),
> + CLK("omap_gpio.2", "dbclk", &gpio2_dbck, CK_3XXX),
> + CLK("omap_gpio.3", "dbclk", &gpio3_dbck, CK_3XXX),
> + CLK("omap_gpio.4", "dbclk", &gpio4_dbck, CK_3XXX),
> + CLK("omap_gpio.5", "dbclk", &gpio5_dbck, CK_3XXX),
> + CLK("omap_gpio.6", "dbclk", &gpio6_dbck, CK_3XXX),
> };
>
>
> diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
> index 2af0e3f..4986069 100644
> --- a/arch/arm/mach-omap2/clock44xx_data.c
> +++ b/arch/arm/mach-omap2/clock44xx_data.c
> @@ -3363,6 +3363,12 @@ static struct omap_clk omap44xx_clks[] = {
> CLK("usbhs-omap.0", "usbhost_ick", &dummy_ck, CK_443X),
> CLK("usbhs-omap.0", "usbtll_fck", &dummy_ck, CK_443X),
> CLK("omap_wdt", "ick", &dummy_ck, CK_443X),
> + CLK("omap_gpio.1", "dbclk", &gpio1_dbclk, CK_443X),
> + CLK("omap_gpio.2", "dbclk", &gpio2_dbclk, CK_443X),
> + CLK("omap_gpio.3", "dbclk", &gpio3_dbclk, CK_443X),
> + CLK("omap_gpio.4", "dbclk", &gpio4_dbclk, CK_443X),
> + CLK("omap_gpio.5", "dbclk", &gpio5_dbclk, CK_443X),
> + CLK("omap_gpio.6", "dbclk", &gpio6_dbclk, CK_443X),
> };
>
> int __init omap4xxx_clk_init(void)
> --
> 1.7.0.4
>
^ permalink raw reply
* [PATCH v2 0/3] ARCH: CSR: basic PM suspend/resume support
From: Barry Song @ 2011-09-21 15:17 UTC (permalink / raw)
To: linux-arm-kernel
-v2:
add acked-by Arnd in changelog;
add necessary changelog for every patch;
don't call l2x0_of_init after resuming as Shawn's patch[1] seems
not to be applied;
since people still need some time to figure out the best way for l2
resume, we move the l2 re-init to bootloader for the moment to keep
things go ahead.
-v1:
it was in thread "ARM: CSR: add rtciobrg and PM support" before. See:
http://www.spinics.net/lists/arm-kernel/msg137375.html
Arnd has pulled rtciobrg into arm-soc next branch. PM should be another
series.
This series has been tested on prima2 Linux 3.1-rc6 with log:
# echo mem > /sys/power/state
PM: Syncing filesystems ... done.
Freezing user space processes ... (elapsed 0.01 seconds) done.
Freezing remaining freezable tasks ... (elapsed 0.01 seconds) done.
Suspending console(s) (use no_console_suspend to debug)
C0PM: suspend of devices complete after 2.083 msecs
PM: late suspend of devices complete after 0.697 msecs
L310 cache controller enabled
l2x0: 8 ways, CACHE_ID 0x410000c7, AUX_CTRL 0x00040000, Cache size: 262144 B
PM: early resume of devices complete after 0.628 msecs
PM: resume of devices complete after 1.804 msecs
Restarting tasks ... done.
Due to L2 cache will lose power and data in suspend cycle, prima2 actually requires
the whole l2 cache flushed while suspending and re-initilized after resuming just
like code boot.
So the "ARM: CSR: PM: add sleep entry for SiRFprimaII" depends on [1]:
[1] Shawn Guo <shawn.guo@linaro.org>'s
[PATCH v2 1/2] ARM: cache-l2x0: remove __init annotation from initialization functions
http://www.spinics.net/lists/arm-kernel/msg139198.html
Barry Song (2):
ARM: CSR: PM: save/restore timer status in suspend cycle
ARM: CSR: PM: save/restore irq status in suspend cycle
Rongjun Ying (1):
ARM: CSR: PM: add sleep entry for SiRFprimaII
arch/arm/mach-prima2/Makefile | 1 +
arch/arm/mach-prima2/irq.c | 40 +++++++++++
arch/arm/mach-prima2/pm.c | 149 +++++++++++++++++++++++++++++++++++++++++
arch/arm/mach-prima2/pm.h | 31 +++++++++
arch/arm/mach-prima2/sleep.S | 64 ++++++++++++++++++
arch/arm/mach-prima2/timer.c | 34 +++++++++
6 files changed, 319 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-prima2/pm.c
create mode 100644 arch/arm/mach-prima2/pm.h
create mode 100644 arch/arm/mach-prima2/sleep.S
^ permalink raw reply
* [PATCH v2 1/3] ARM: CSR: PM: save/restore timer status in suspend cycle
From: Barry Song @ 2011-09-21 15:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1316618267-4348-1-git-send-email-21cnbao@gmail.com>
From: Barry Song <baohua.song@csr.com>
SiRFprimaII will lose power in deepsleep mode except rtc, pmu and sdram
self-refresh.
This patch saves timer-related registers while suspending and restore
them while resuming.
Signed-off-by: Barry Song <baohua.song@csr.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
---
arch/arm/mach-prima2/timer.c | 34 ++++++++++++++++++++++++++++++++++
1 files changed, 34 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-prima2/timer.c b/arch/arm/mach-prima2/timer.c
index ed7ec48..3b15961 100644
--- a/arch/arm/mach-prima2/timer.c
+++ b/arch/arm/mach-prima2/timer.c
@@ -40,6 +40,17 @@
#define SIRFSOC_TIMER_LATCH_BIT BIT(0)
+#define SIRFSOC_TIMER_REG_CNT 11
+
+static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = {
+ SIRFSOC_TIMER_MATCH_0, SIRFSOC_TIMER_MATCH_1, SIRFSOC_TIMER_MATCH_2,
+ SIRFSOC_TIMER_MATCH_3, SIRFSOC_TIMER_MATCH_4, SIRFSOC_TIMER_MATCH_5,
+ SIRFSOC_TIMER_INT_EN, SIRFSOC_TIMER_WATCHDOG_EN, SIRFSOC_TIMER_DIV,
+ SIRFSOC_TIMER_LATCHED_LO, SIRFSOC_TIMER_LATCHED_HI,
+};
+
+static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT];
+
static void __iomem *sirfsoc_timer_base;
static void __init sirfsoc_of_timer_map(void);
@@ -106,6 +117,27 @@ static void sirfsoc_timer_set_mode(enum clock_event_mode mode,
}
}
+static void sirfsoc_clocksource_suspend(struct clocksource *cs)
+{
+ int i;
+
+ writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
+
+ for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++)
+ sirfsoc_timer_reg_val[i] = readl_relaxed(sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
+}
+
+static void sirfsoc_clocksource_resume(struct clocksource *cs)
+{
+ int i;
+
+ for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++)
+ writel_relaxed(sirfsoc_timer_reg_val[i], sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
+
+ writel_relaxed(sirfsoc_timer_reg_val[i - 2], sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO);
+ writel_relaxed(sirfsoc_timer_reg_val[i - 1], sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI);
+}
+
static struct clock_event_device sirfsoc_clockevent = {
.name = "sirfsoc_clockevent",
.rating = 200,
@@ -120,6 +152,8 @@ static struct clocksource sirfsoc_clocksource = {
.mask = CLOCKSOURCE_MASK(64),
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
.read = sirfsoc_timer_read,
+ .suspend = sirfsoc_clocksource_suspend,
+ .resume = sirfsoc_clocksource_resume,
};
static struct irqaction sirfsoc_timer_irq = {
--
1.7.0.4
^ permalink raw reply related
* [PATCH v2 2/3] ARM: CSR: PM: save/restore irq status in suspend cycle
From: Barry Song @ 2011-09-21 15:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1316618267-4348-1-git-send-email-21cnbao@gmail.com>
From: Barry Song <baohua.song@csr.com>
SiRFprimaII will lose power in deepsleep mode except rtc, pmu and sdram
self-refresh. So IRQ controller will lose status in suspend cyle.
This patch saves irq mask/level registers while suspending and restore
them while resuming.
Signed-off-by: Barry Song <baohua.song@csr.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
---
arch/arm/mach-prima2/irq.c | 40 ++++++++++++++++++++++++++++++++++++++++
1 files changed, 40 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-prima2/irq.c b/arch/arm/mach-prima2/irq.c
index cf80a72..d93ceef 100644
--- a/arch/arm/mach-prima2/irq.c
+++ b/arch/arm/mach-prima2/irq.c
@@ -14,6 +14,7 @@
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/irqdomain.h>
+#include <linux/syscore_ops.h>
#define SIRFSOC_INT_RISC_MASK0 0x0018
#define SIRFSOC_INT_RISC_MASK1 0x001C
@@ -73,3 +74,42 @@ void __init sirfsoc_of_irq_init(void)
sirfsoc_irq_init();
}
+
+struct sirfsoc_irq_status {
+ u32 mask0;
+ u32 mask1;
+ u32 level0;
+ u32 level1;
+};
+
+static struct sirfsoc_irq_status sirfsoc_irq_st;
+
+static int sirfsoc_irq_suspend(void)
+{
+ sirfsoc_irq_st.mask0 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0);
+ sirfsoc_irq_st.mask1 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1);
+ sirfsoc_irq_st.level0 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0);
+ sirfsoc_irq_st.level1 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1);
+
+ return 0;
+}
+
+static void sirfsoc_irq_resume(void)
+{
+ writel_relaxed(sirfsoc_irq_st.mask0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0);
+ writel_relaxed(sirfsoc_irq_st.mask1, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1);
+ writel_relaxed(sirfsoc_irq_st.level0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0);
+ writel_relaxed(sirfsoc_irq_st.level1, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1);
+}
+
+static struct syscore_ops sirfsoc_irq_syscore_ops = {
+ .suspend = sirfsoc_irq_suspend,
+ .resume = sirfsoc_irq_resume,
+};
+
+static int __init sirfsoc_irq_pm_init(void)
+{
+ register_syscore_ops(&sirfsoc_irq_syscore_ops);
+ return 0;
+}
+device_initcall(sirfsoc_irq_pm_init);
--
1.7.0.4
^ permalink raw reply related
* [PATCH v2 3/3] ARM: CSR: PM: add sleep entry for SiRFprimaII
From: Barry Song @ 2011-09-21 15:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1316618267-4348-1-git-send-email-21cnbao@gmail.com>
From: Rongjun Ying <rongjun.ying@csr.com>
This patch adds suspend-to-mem support for prima2. It will make prima2
enter DEEPSLEEP mode while accepting PM_SUSPEND_MEM command.
Signed-off-by: Rongjun Ying <baohua.song@csr.com>
Signed-off-by: Barry Song <baohua.song@csr.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
---
-v2:
don't call l2x0_of_init after resuming as Shawn's patch[1] seems
not to be applied;
Since people still need some time to figure out the best way for l2
resume, we move the l2 re-init to bootloader for the moment to keep
things go ahead.
arch/arm/mach-prima2/Makefile | 1 +
arch/arm/mach-prima2/pm.c | 149 +++++++++++++++++++++++++++++++++++++++++
arch/arm/mach-prima2/pm.h | 31 +++++++++
arch/arm/mach-prima2/sleep.S | 64 ++++++++++++++++++
4 files changed, 245 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-prima2/pm.c
create mode 100644 arch/arm/mach-prima2/pm.h
create mode 100644 arch/arm/mach-prima2/sleep.S
diff --git a/arch/arm/mach-prima2/Makefile b/arch/arm/mach-prima2/Makefile
index f49d70b..13dd160 100644
--- a/arch/arm/mach-prima2/Makefile
+++ b/arch/arm/mach-prima2/Makefile
@@ -6,3 +6,4 @@ obj-y += prima2.o
obj-y += rtciobrg.o
obj-$(CONFIG_DEBUG_LL) += lluart.o
obj-$(CONFIG_CACHE_L2X0) += l2x0.o
+obj-$(CONFIG_SUSPEND) += pm.o sleep.o
diff --git a/arch/arm/mach-prima2/pm.c b/arch/arm/mach-prima2/pm.c
new file mode 100644
index 0000000..0ba39f3
--- /dev/null
+++ b/arch/arm/mach-prima2/pm.c
@@ -0,0 +1,149 @@
+/*
+ * power management entry for CSR SiRFprimaII
+ *
+ * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include <linux/kernel.h>
+#include <linux/suspend.h>
+#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/of_platform.h>
+#include <linux/io.h>
+#include <linux/rtc/sirfsoc_rtciobrg.h>
+#include <asm/suspend.h>
+#include <asm/hardware/cache-l2x0.h>
+
+#include "pm.h"
+
+/*
+ * suspend asm codes will access these to make DRAM become self-refresh and
+ * system sleep
+ */
+u32 sirfsoc_pwrc_base;
+void __iomem *sirfsoc_memc_base;
+
+static void sirfsoc_set_wakeup_source(void)
+{
+ u32 pwr_trigger_en_reg;
+ pwr_trigger_en_reg = sirfsoc_rtc_iobrg_readl(sirfsoc_pwrc_base +
+ SIRFSOC_PWRC_TRIGGER_EN);
+#define X_ON_KEY_B (1 << 0)
+ sirfsoc_rtc_iobrg_writel(pwr_trigger_en_reg | X_ON_KEY_B,
+ sirfsoc_pwrc_base + SIRFSOC_PWRC_TRIGGER_EN);
+}
+
+static void sirfsoc_set_sleep_mode(u32 mode)
+{
+ u32 sleep_mode = sirfsoc_rtc_iobrg_readl(sirfsoc_pwrc_base +
+ SIRFSOC_PWRC_PDN_CTRL);
+ sleep_mode &= ~(SIRFSOC_SLEEP_MODE_MASK << 1);
+ sleep_mode |= mode << 1;
+ sirfsoc_rtc_iobrg_writel(sleep_mode, sirfsoc_pwrc_base +
+ SIRFSOC_PWRC_PDN_CTRL);
+}
+
+static int sirfsoc_pre_suspend_power_off(void)
+{
+ u32 wakeup_entry = virt_to_phys(cpu_resume);
+
+ sirfsoc_rtc_iobrg_writel(wakeup_entry, sirfsoc_pwrc_base +
+ SIRFSOC_PWRC_SCRATCH_PAD1);
+
+ sirfsoc_set_wakeup_source();
+
+ sirfsoc_set_sleep_mode(SIRFSOC_DEEP_SLEEP_MODE);
+
+ return 0;
+}
+
+static int sirfsoc_pm_enter(suspend_state_t state)
+{
+ switch (state) {
+ case PM_SUSPEND_MEM:
+ sirfsoc_pre_suspend_power_off();
+
+ outer_flush_all();
+ outer_disable();
+ /* go zzz */
+ cpu_suspend(0, sirfsoc_finish_suspend);
+ break;
+ default:
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static const struct platform_suspend_ops sirfsoc_pm_ops = {
+ .enter = sirfsoc_pm_enter,
+ .valid = suspend_valid_only_mem,
+};
+
+static int __init sirfsoc_pm_init(void)
+{
+ suspend_set_ops(&sirfsoc_pm_ops);
+ return 0;
+}
+late_initcall(sirfsoc_pm_init);
+
+static const struct of_device_id pwrc_ids[] = {
+ { .compatible = "sirf,prima2-pwrc" },
+ {}
+};
+
+static int __init sirfsoc_of_pwrc_init(void)
+{
+ struct device_node *np;
+
+ np = of_find_matching_node(NULL, pwrc_ids);
+ if (!np)
+ panic("unable to find compatible pwrc node in dtb\n");
+
+ /*
+ * pwrc behind rtciobrg is not located in memory space
+ * though the property is named reg. reg only means base
+ * offset for pwrc. then of_iomap is not suitable here.
+ */
+ if (of_property_read_u32(np, "reg", &sirfsoc_pwrc_base))
+ panic("unable to find base address of pwrc node in dtb\n");
+
+ of_node_put(np);
+
+ return 0;
+}
+postcore_initcall(sirfsoc_of_pwrc_init);
+
+static const struct of_device_id memc_ids[] = {
+ { .compatible = "sirf,prima2-memc" },
+ {}
+};
+
+static int __devinit sirfsoc_memc_probe(struct platform_device *op)
+{
+ struct device_node *np = op->dev.of_node;
+
+ sirfsoc_memc_base = of_iomap(np, 0);
+ if (!sirfsoc_memc_base)
+ panic("unable to map memc registers\n");
+
+ return 0;
+}
+
+static struct platform_driver sirfsoc_memc_driver = {
+ .probe = sirfsoc_memc_probe,
+ .driver = {
+ .name = "sirfsoc-memc",
+ .owner = THIS_MODULE,
+ .of_match_table = memc_ids,
+ },
+};
+
+static int __init sirfsoc_memc_init(void)
+{
+ return platform_driver_register(&sirfsoc_memc_driver);
+}
+postcore_initcall(sirfsoc_memc_init);
diff --git a/arch/arm/mach-prima2/pm.h b/arch/arm/mach-prima2/pm.h
new file mode 100644
index 0000000..aa2b428
--- /dev/null
+++ b/arch/arm/mach-prima2/pm.h
@@ -0,0 +1,31 @@
+/*
+ * arch/arm/mach-prima2/pm.h
+ *
+ * Copyright (C) 2011 CSR
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef _MACH_PRIMA2_PM_H_
+#define _MACH_PRIMA2_PM_H_
+
+#define SIRFSOC_PWR_SLEEPFORCE 0x01
+
+#define SIRFSOC_SLEEP_MODE_MASK 0x3
+#define SIRFSOC_DEEP_SLEEP_MODE 0x1
+
+#define SIRFSOC_PWRC_PDN_CTRL 0x0
+#define SIRFSOC_PWRC_PON_OFF 0x4
+#define SIRFSOC_PWRC_TRIGGER_EN 0x8
+#define SIRFSOC_PWRC_PIN_STATUS 0x14
+#define SIRFSOC_PWRC_SCRATCH_PAD1 0x18
+#define SIRFSOC_PWRC_SCRATCH_PAD2 0x1C
+
+#ifndef __ASSEMBLY__
+extern int sirfsoc_finish_suspend(unsigned long);
+#endif
+
+#endif
+
diff --git a/arch/arm/mach-prima2/sleep.S b/arch/arm/mach-prima2/sleep.S
new file mode 100644
index 0000000..0745abc
--- /dev/null
+++ b/arch/arm/mach-prima2/sleep.S
@@ -0,0 +1,64 @@
+/*
+ * sleep mode for CSR SiRFprimaII
+ *
+ * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include <linux/linkage.h>
+#include <asm/ptrace.h>
+#include <asm/assembler.h>
+
+#include "pm.h"
+
+#define DENALI_CTL_22_OFF 0x58
+#define DENALI_CTL_112_OFF 0x1c0
+
+ .text
+
+ENTRY(sirfsoc_finish_suspend)
+ @ r5: mem controller
+ ldr r0, =sirfsoc_memc_base
+ ldr r5, [r0]
+ @ r6: pwrc base offset
+ ldr r0, =sirfsoc_pwrc_base
+ ldr r6, [r0]
+ @ r7: rtc iobrg controller
+ ldr r0, =sirfsoc_rtciobrg_base
+ ldr r7, [r0]
+
+ @ Read the power control register and set the
+ @ sleep force bit.
+ add r0, r6, #SIRFSOC_PWRC_PDN_CTRL
+ bl __sirfsoc_rtc_iobrg_readl
+ orr r0,r0,#SIRFSOC_PWR_SLEEPFORCE
+ add r1, r6, #SIRFSOC_PWRC_PDN_CTRL
+ bl sirfsoc_rtc_iobrg_pre_writel
+ mov r1, #0x1
+
+ @ read the MEM ctl register and set the self
+ @ refresh bit
+
+ ldr r2, [r5, #DENALI_CTL_22_OFF]
+ orr r2, r2, #0x1
+
+ @ Following code has to run from cache since
+ @ the RAM is going to self refresh mode
+ .align 5
+ str r2, [r5, #DENALI_CTL_22_OFF]
+
+1:
+ ldr r4, [r5, #DENALI_CTL_112_OFF]
+ tst r4, #0x1
+ bne 1b
+
+ @ write SLEEPFORCE through rtc iobridge
+
+ str r1, [r7]
+ @ wait rtc io bridge sync
+1:
+ ldr r3, [r7]
+ tst r3, #0x01
+ bne 1b
+ b .
--
1.7.0.4
^ permalink raw reply related
* [PATCH 1/3] fixup! mm: alloc_contig_freed_pages() added
From: Michal Nazarewicz @ 2011-09-21 15:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1315505152.3114.9.camel@nimitz>
From: Michal Nazarewicz <mina86@mina86.com>
Signed-off-by: Michal Nazarewicz <mina86@mina86.com>
---
include/linux/page-isolation.h | 4 ++-
mm/page_alloc.c | 66 ++++++++++++++++++++++++++++++++++-----
2 files changed, 60 insertions(+), 10 deletions(-)
> On Fri, 2011-08-19 at 16:27 +0200, Marek Szyprowski wrote:
>> +unsigned long alloc_contig_freed_pages(unsigned long start, unsigned
>> long end,
>> + gfp_t flag)
>> +{
>> + unsigned long pfn = start, count;
>> + struct page *page;
>> + struct zone *zone;
>> + int order;
>> +
>> + VM_BUG_ON(!pfn_valid(start));
>> + zone = page_zone(pfn_to_page(start));
On Thu, 08 Sep 2011 20:05:52 +0200, Dave Hansen <dave@linux.vnet.ibm.com> wrote:
> This implies that start->end are entirely contained in a single zone.
> What enforces that? If some higher layer enforces that, I think we
> probably need at least a VM_BUG_ON() in here and a comment about who
> enforces it.
>> + spin_lock_irq(&zone->lock);
>> +
>> + page = pfn_to_page(pfn);
>> + for (;;) {
>> + VM_BUG_ON(page_count(page) || !PageBuddy(page));
>> + list_del(&page->lru);
>> + order = page_order(page);
>> + zone->free_area[order].nr_free--;
>> + rmv_page_order(page);
>> + __mod_zone_page_state(zone, NR_FREE_PAGES, -(1UL << order));
>> + pfn += 1 << order;
>> + if (pfn >= end)
>> + break;
>> + VM_BUG_ON(!pfn_valid(pfn));
>> + page += 1 << order;
>> + }
> This 'struct page *'++ stuff is OK, but only for small, aligned areas.
> For at least some of the sparsemem modes (non-VMEMMAP), you could walk
> off of the end of the section_mem_map[] when you cross a MAX_ORDER
> boundary. I'd feel a little bit more comfortable if pfn_to_page() was
> being done each time, or only occasionally when you cross a section
> boundary.
Do the attached changes seem to make sense?
I wanted to avoid calling pfn_to_page() each time as it seem fairly
expensive in sparsemem and disctontig modes. At the same time, the
macro trickery is so that users of sparsemem-vmemmap and flatmem won't
have to pay the price.
diff --git a/include/linux/page-isolation.h b/include/linux/page-isolation.h
index b2a81fd..003c52f 100644
--- a/include/linux/page-isolation.h
+++ b/include/linux/page-isolation.h
@@ -46,11 +46,13 @@ static inline void unset_migratetype_isolate(struct page *page)
{
__unset_migratetype_isolate(page, MIGRATE_MOVABLE);
}
+
+/* The below functions must be run on a range from a single zone. */
extern unsigned long alloc_contig_freed_pages(unsigned long start,
unsigned long end, gfp_t flag);
extern int alloc_contig_range(unsigned long start, unsigned long end,
gfp_t flags, unsigned migratetype);
-extern void free_contig_pages(struct page *page, int nr_pages);
+extern void free_contig_pages(unsigned long pfn, unsigned nr_pages);
/*
* For migration.
diff --git a/mm/page_alloc.c b/mm/page_alloc.c
index 46e78d4..32fda5d 100644
--- a/mm/page_alloc.c
+++ b/mm/page_alloc.c
@@ -5716,9 +5716,41 @@ out:
spin_unlock_irqrestore(&zone->lock, flags);
}
+#if defined(CONFIG_FLATMEM) || defined(CONFIG_SPARSEMEM_VMEMMAP)
+
+/*
+ * In FLATMEM and CONFIG_SPARSEMEM_VMEMMAP we can safely increment the page
+ * pointer and get the same value as if we were to get by calling
+ * pfn_to_page() on incremented pfn counter.
+ */
+#define __contig_next_page(page, pageblock_left, pfn, increment) \
+ ((page) + (increment))
+
+#define __contig_first_page(pageblock_left, pfn) pfn_to_page(pfn)
+
+#else
+
+/*
+ * If we cross pageblock boundary, make sure we get a valid page pointer. If
+ * we are within pageblock, incrementing the pointer is good enough, and is
+ * a bit of an optimisation.
+ */
+#define __contig_next_page(page, pageblock_left, pfn, increment) \
+ (likely((pageblock_left) -= (increment)) ? (page) + (increment) \
+ : (((pageblock_left) = pageblock_nr_pages), pfn_to_page(pfn)))
+
+#define __contig_first_page(pageblock_left, pfn) ( \
+ ((pageblock_left) = pageblock_nr_pages - \
+ ((pfn) & (pageblock_nr_pages - 1))), \
+ pfn_to_page(pfn))
+
+
+#endif
+
unsigned long alloc_contig_freed_pages(unsigned long start, unsigned long end,
gfp_t flag)
{
+ unsigned long pageblock_left __unused;
unsigned long pfn = start, count;
struct page *page;
struct zone *zone;
@@ -5729,27 +5761,37 @@ unsigned long alloc_contig_freed_pages(unsigned long start, unsigned long end,
spin_lock_irq(&zone->lock);
- page = pfn_to_page(pfn);
+ page = __contig_first_page(pageblock_left, pfn);
for (;;) {
- VM_BUG_ON(page_count(page) || !PageBuddy(page));
+ VM_BUG_ON(!page_count(page) || !PageBuddy(page) ||
+ page_zone(page) != zone);
+
list_del(&page->lru);
order = page_order(page);
+ count = 1UL << order;
zone->free_area[order].nr_free--;
rmv_page_order(page);
- __mod_zone_page_state(zone, NR_FREE_PAGES, -(1UL << order));
- pfn += 1 << order;
+ __mod_zone_page_state(zone, NR_FREE_PAGES, -(long)count);
+
+ pfn += count;
if (pfn >= end)
break;
VM_BUG_ON(!pfn_valid(pfn));
- page += 1 << order;
+
+ page = __contig_next_page(page, pageblock_left, pfn, count);
}
spin_unlock_irq(&zone->lock);
/* After this, pages in the range can be freed one be one */
- page = pfn_to_page(start);
- for (count = pfn - start; count; --count, ++page)
+ count = pfn - start;
+ pfn = start;
+ page = __contig_first_page(pageblock_left, pfn);
+ for (; count; --count) {
prep_new_page(page, 0, flag);
+ ++pfn;
+ page = __contig_next_page(page, pageblock_left, pfn, 1);
+ }
return pfn;
}
@@ -5903,10 +5945,16 @@ done:
return ret;
}
-void free_contig_pages(struct page *page, int nr_pages)
+void free_contig_pages(unsigned long pfn, unsigned nr_pages)
{
- for (; nr_pages; --nr_pages, ++page)
+ unsigned long pageblock_left __unused;
+ struct page *page = __contig_first_page(pageblock_left, pfn);
+
+ while (nr_pages--) {
__free_page(page);
+ ++pfn;
+ page = __contig_next_page(page, pageblock_left, pfn, 1);
+ }
}
#ifdef CONFIG_MEMORY_HOTREMOVE
--
1.7.3.1
^ permalink raw reply related
* [PATCH 00/10] hwspinlock-next
From: Tony Lindgren @ 2011-09-21 15:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110920234515.GA16276@kroah.com>
* Greg KH <greg@kroah.com> [110921 07:27]:
> On Tue, Sep 20, 2011 at 04:13:40PM -0700, Tony Lindgren wrote:
> > * Ohad Ben-Cohen <ohad@wizery.com> [110920 01:34]:
> > > On Mon, Sep 12, 2011 at 7:46 PM, Ohad Ben-Cohen <ohad@wizery.com> wrote:
> > >
> > > I'm wondering how hwspinlock updates like this should go upstream.
> > >
> > > The first hwspinlock batch was picked by Tony, because it involved a
> > > bulk of OMAP changes.
> > >
> > > Hwspinlock isn't OMAP-specific anymore though (we gained support for
> > > STE's u8500) and the vast majority of changes are in drivers/. We're
> > > still very much ARM-related, though this may change too at some point
> > > (c6x has a similar "hardware semaphore" peripheral like the u8500
> > > does).
> > >
> > > Tony, if you're still willing to pick up these updates I'd be happy to
> > > send you pull requests of course.
> >
> > I'd prefer for Greg to take these as these are drivers.
>
> What, am I the catch-all for drivers these days?
>
> Oh, right, it looks like I am :)
>
> > If he's not taking it at this point based on it being ARM only,
> > I can take it then.
>
> Please do, I don't even have the ability to build them here, as I don't
> have an arm cross-compiler on this travel laptop.
OK so you're off the hook then :) Now we still need to sort out the
remaining options posted by Arnd.
Tony
^ permalink raw reply
* [PATCH 00/10] hwspinlock-next
From: Tony Lindgren @ 2011-09-21 15:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <201109211612.33504.arnd@arndb.de>
* Arnd Bergmann <arnd@arndb.de> [110921 06:39]:
> On Wednesday 21 September 2011, Tony Lindgren wrote:
> > * Ohad Ben-Cohen <ohad@wizery.com> [110920 01:34]:
> > > On Mon, Sep 12, 2011 at 7:46 PM, Ohad Ben-Cohen <ohad@wizery.com> wrote:
> > >
> > > I'm wondering how hwspinlock updates like this should go upstream.
> > >
> > > The first hwspinlock batch was picked by Tony, because it involved a
> > > bulk of OMAP changes.
> > >
> > > Hwspinlock isn't OMAP-specific anymore though (we gained support for
> > > STE's u8500) and the vast majority of changes are in drivers/. We're
> > > still very much ARM-related, though this may change too at some point
> > > (c6x has a similar "hardware semaphore" peripheral like the u8500
> > > does).
> > >
> > > Tony, if you're still willing to pick up these updates I'd be happy to
> > > send you pull requests of course.
> >
> > I'd prefer for Greg to take these as these are drivers.
> >
> > If he's not taking it at this point based on it being ARM only,
> > I can take it then.
>
> Sorry for replying late, I had accidentally ignored the entire thread.
>
> My feeling is that it would be best for Ohad to send these directly
> to Linus, since it's basically a standalone subsystem and he's listed
> as the maintainer (well, after this series at least).
Ohad can you please try this first? Just please make sure your patches are
first in next tree before sending in the pull request.
> I'm also fine with any of the other paths like
>
> ohad->GregKH->torvalds
Greg does not prefer that as it's ARM only currently.
> ohad->arnd->torvalds
> ohad->tmlind->torvalds
> ohad->tmlind->arnd->torvalds
So as a backup plan any of these are also fine with me too.
Tony
^ permalink raw reply
* [PATCH 8/8] OMAP4: Fix the emif and dmm virtual mapping
From: Santosh Shilimkar @ 2011-09-21 15:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4E78AAD5.6010906@ti.com>
On Tuesday 20 September 2011 08:31 PM, Santosh Shilimkar wrote:
> On Friday 16 September 2011 11:26 PM, Kevin Hilman wrote:
>> Santosh Shilimkar <santosh.shilimkar@ti.com> writes:
>>
[...]
>
>>> #define OMAP44XX_EMIF2_SIZE SZ_1M
>>>
>>> #define OMAP44XX_DMM_PHYS OMAP44XX_DMM_BASE
>>> /* 0x4e000000 --> 0xfd300000 */
>>> -#define OMAP44XX_DMM_VIRT (OMAP44XX_DMM_PHYS + OMAP4_L3_PER_IO_OFFSET)
>>> +#define OMAP44XX_DMM_VIRT (OMAP44XX_EMIF2_VIRT + SZ_1M)
>>
>> and '+ OMAP44XX_EMIF2_SIZE' here.
>>
> Will add OMAP44XX_EMIF_SIZE since 2 EMIFs instaces are and
> suppose to be identical.Almost missed this email in other traffic.
OPPs. It was already there. Dumb of me not using it. Below
is the update what I will do.
diff --git a/arch/arm/plat-omap/include/plat/io.h
b/arch/arm/plat-omap/include/plat/io.h
index d72ec85..db36292 100644
--- a/arch/arm/plat-omap/include/plat/io.h
+++ b/arch/arm/plat-omap/include/plat/io.h
@@ -228,13 +228,13 @@
#define OMAP44XX_EMIF2_PHYS OMAP44XX_EMIF2_BASE
/* 0x4d000000 --> 0xfd200000 */
-#define OMAP44XX_EMIF2_VIRT (OMAP44XX_EMIF2_PHYS + OMAP4_L3_PER_IO_OFFSET)
#define OMAP44XX_EMIF2_SIZE SZ_1M
+#define OMAP44XX_EMIF2_VIRT (OMAP44XX_EMIF1_VIRT + OMAP44XX_EMIF2_SIZE)
#define OMAP44XX_DMM_PHYS OMAP44XX_DMM_BASE
/* 0x4e000000 --> 0xfd300000 */
-#define OMAP44XX_DMM_VIRT (OMAP44XX_DMM_PHYS + OMAP4_L3_PER_IO_OFFSET)
#define OMAP44XX_DMM_SIZE SZ_1M
+#define OMAP44XX_DMM_VIRT (OMAP44XX_EMIF2_VIRT + OMAP44XX_DMM_SIZE)
/*
*
----------------------------------------------------------------------------
* Omap specific register access
--
1.7.4.1
^ permalink raw reply related
* [GIT PULL] CSR prima2 PM support for 3.2
From: Barry Song @ 2011-09-21 15:37 UTC (permalink / raw)
To: linux-arm-kernel
Hi Arnd,
Can you pls pull the prima2 PM support for 3.2? As the patchset
depends on rtciobrg you pulled last time, i didn't rebase it to 3.1-rc
to avoid merge conflict.
The following changes since commit 684f741446f7a3108b4c167faf20214c42b7eeac:
Zhiwu Song (1):
ARM: CSR: add rtc i/o bridge interface for SiRFprimaII
are available in the git repository at:
git://gitorious.org/sirfprima2-kernel/sirfprima2-kernel.git for-arnd
Barry Song (2):
ARM: CSR: PM: save/restore timer status in suspend cycle
ARM: CSR: PM: save/restore irq status in suspend cycle
Rongjun Ying (1):
ARM: CSR: PM: add sleep entry for SiRFprimaII
arch/arm/mach-prima2/Makefile | 1 +
arch/arm/mach-prima2/irq.c | 40 +++++++++++
arch/arm/mach-prima2/pm.c | 149 +++++++++++++++++++++++++++++++++++++++++
arch/arm/mach-prima2/pm.h | 29 ++++++++
arch/arm/mach-prima2/sleep.S | 64 ++++++++++++++++++
arch/arm/mach-prima2/timer.c | 34 +++++++++
6 files changed, 317 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-prima2/pm.c
create mode 100644 arch/arm/mach-prima2/pm.h
create mode 100644 arch/arm/mach-prima2/sleep.S
Thanks
barry
2011/9/11 Barry Song <21cnbao@gmail.com>:
> Hi Arnd,
> can you please pull the 1st patchset of CSR prima2 for next? most of
> them are minor changes except that rtciobrg is new stuff.
>
> The following changes since commit ddf28352b80c86754a6424e3a61e8bdf9213b3c7:
> ?Linus Torvalds (1):
> ? ? ? ?Linux 3.1-rc5
>
> are available in the git repository at:
>
> ?git://gitorious.org/sirfprima2-kernel/sirfprima2-kernel.git for-arnd
>
> Barry Song (3):
> ? ? ?ARM: CSR: add lost Resource Sharing Control(RSC) node in dts
> ? ? ?ARM: CSR: extend the compatibility of gpio controller to pinmux in dts
> ? ? ?ARM: CSR: IRQ: add simple irq_domain so that hw irq can map to Linux
>
> Jamie Iles (1):
> ? ? ?ARM: CSR: add missing sentinels to of_device_id tables
>
> Zhiwu Song (1):
> ? ? ?ARM: CSR: add rtc i/o bridge interface for SiRFprimaII
>
> ?arch/arm/boot/dts/prima2-cb.dts ? ? ?| ? ?9 ++-
> ?arch/arm/mach-prima2/Makefile ? ? ? ?| ? ?1 +
> ?arch/arm/mach-prima2/clock.c ? ? ? ? | ? ?1 +
> ?arch/arm/mach-prima2/irq.c ? ? ? ? ? | ? ?4 +
> ?arch/arm/mach-prima2/rstc.c ? ? ? ? ?| ? ?1 +
> ?arch/arm/mach-prima2/rtciobrg.c ? ? ?| ?139 ++++++++++++++++++++++++++++++++++
> ?arch/arm/mach-prima2/timer.c ? ? ? ? | ? ?1 +
> ?include/linux/rtc/sirfsoc_rtciobrg.h | ? 18 +++++
> ?8 files changed, 172 insertions(+), 2 deletions(-)
> ?create mode 100644 arch/arm/mach-prima2/rtciobrg.c
> ?create mode 100644 include/linux/rtc/sirfsoc_rtciobrg.h
>
> Thanks
> barry
>
^ permalink raw reply
* [PATCH 1/3] fixup! mm: alloc_contig_freed_pages() added
From: Dave Hansen @ 2011-09-21 15:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <ea1bc31120e0670a044de6af7b3c67203c178065.1316617681.git.mina86@mina86.com>
On Wed, 2011-09-21 at 17:19 +0200, Michal Nazarewicz wrote:
> Do the attached changes seem to make sense?
The logic looks OK.
> I wanted to avoid calling pfn_to_page() each time as it seem fairly
> expensive in sparsemem and disctontig modes. At the same time, the
> macro trickery is so that users of sparsemem-vmemmap and flatmem won't
> have to pay the price.
Personally, I'd say the (incredibly minuscule) runtime cost is worth the
cost of making folks' eyes bleed when they see those macros. I think
there are some nicer ways to do it.
Is there a reason you can't logically do?
page = pfn_to_page(pfn);
for (;;) {
if (pfn_to_section_nr(pfn) == pfn_to_section_nr(pfn+1))
page++;
else
page = pfn_to_page(pfn+1);
}
pfn_to_section_nr() is a register shift. Our smallest section size on
x86 is 128MB and on ppc64 16MB. So, at *WORST* (64k pages on ppc64),
you're doing pfn_to_page() one of every 256 loops.
My suggestion would be put put a macro up in the sparsemem headers that
does something like:
#ifdef VMEMMAP
#define zone_pfn_same_memmap(pfn1, pfn2) (1)
#elif SPARSEMEM_OTHER
static inline int zone_pfn_same_memmap(unsigned long pfn1, unsigned long pfn2)
{
return (pfn_to_section_nr(pfn1) == pfn_to_section_nr(pfn2));
}
#else
#define zone_pfn_same_memmap(pfn1, pfn2) (1)
#endif
The zone_ bit is necessary in the naming because DISCONTIGMEM's pfns are
at least contiguous within a zone. Only the non-VMEMMAP sparsemem case
isn't.
Other folks would probably have a use for something like that. Although
most of the previous users have gotten to this point, given up, and just
done pfn_to_page() on each loop. :)
> +#if defined(CONFIG_FLATMEM) || defined(CONFIG_SPARSEMEM_VMEMMAP)
> +
> +/*
> + * In FLATMEM and CONFIG_SPARSEMEM_VMEMMAP we can safely increment the page
> + * pointer and get the same value as if we were to get by calling
> + * pfn_to_page() on incremented pfn counter.
> + */
> +#define __contig_next_page(page, pageblock_left, pfn, increment) \
> + ((page) + (increment))
> +
> +#define __contig_first_page(pageblock_left, pfn) pfn_to_page(pfn)
> +
> +#else
> +
> +/*
> + * If we cross pageblock boundary, make sure we get a valid page pointer. If
> + * we are within pageblock, incrementing the pointer is good enough, and is
> + * a bit of an optimisation.
> + */
> +#define __contig_next_page(page, pageblock_left, pfn, increment) \
> + (likely((pageblock_left) -= (increment)) ? (page) + (increment) \
> + : (((pageblock_left) = pageblock_nr_pages), pfn_to_page(pfn)))
> +
> +#define __contig_first_page(pageblock_left, pfn) ( \
> + ((pageblock_left) = pageblock_nr_pages - \
> + ((pfn) & (pageblock_nr_pages - 1))), \
> + pfn_to_page(pfn))
> +
> +
> +#endif
For the love of Pete, please make those in to functions if you're going
to keep them. They're really unreadable like that.
You might also want to look at mm/internal.h's mem_map_offset() and
mem_map_next(). They're not _quite_ what you need, but they're close.
-- Dave
^ permalink raw reply
* [PATCH] ARM: vexpress: initial device tree support
From: Dave Martin @ 2011-09-21 15:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1316615590.4611.624.camel@hornet.cambridge.arm.com>
On Wed, Sep 21, 2011 at 03:33:10PM +0100, Pawel Moll wrote:
> > OK, I'll try to propose documentation for these:
> > * arm,pl180
>
> You can skip this one - I'll add the description together with the MMCI
> driver bindings (it will be 180 and 181, by the way :-)
Done.
> > > > + // Timer init is hardcoded in v2m_timer_init(), for now.
> > > > + // timer at 11000 {
> > > > + // compatible = "arm,arm-sp804";
> > >
> > > arm,sp804 is more consistent. I believe the sp804 does have the periphid
> > > registers, so arm,primecell should also be added.
> >
> > Do you mean "does not have"? If so, the periphid will be needed -- thanks for
> > pointing it out in that case.
>
> I think Rob meant it should be
> compatible = "arm,sp804", "arm,primecell",
> as SP804 contains the PrimeCell periphid registers, so will be
> recognized by amba bus driver.
Oh, right -- misunderstanding, sorry for that.
> > I will make the names consistent. These were pasted from someone Lorenzo's
> > older patches, and failed to sport e the inconsistency since I wasn't
> > actually making use of these entries yet.
> >
> > > > + // reg = <0x11000 0x1000>;
> > > > + // interrupts = <2>;
> > > > + // };
> > > > +
> > > > + // timer at 12000 {
> > > > + // compatible = "arm,arm-sp804";
> > > > + // reg = <0x12000 0x1000>;
> > > > + // };
> > >
> > > Just because Linux is not using it, doesn't mean you should comment it out.
> >
> > From the point of view of describing the hardware, yes. However, I was
> > a bit worried that if sp804 is turned into a full driver, it will get
> > initialised twice -- once explicitly and once in of_platform_populate()...
> > at least until the baord code is adapted to work properly with the new
> > driver.
> >
> > Commenting these entries out for now seemed a good idea to avoid the flag-day
> > hazard. Am I being too cautious?
>
> I think you are ;-) Besides my static-mapping-rework is already using
> those...
OK, I will uncomment it then.
Cheers
---Dave
^ permalink raw reply
* [PATCH 00/10] hwspinlock-next
From: Linus Walleij @ 2011-09-21 15:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <201109211612.33504.arnd@arndb.de>
On Wed, Sep 21, 2011 at 4:12 PM, Arnd Bergmann <arnd@arndb.de> wrote:
> My feeling is that it would be best for Ohad to send these directly
> to Linus, since it's basically a standalone subsystem and he's listed
> as the maintainer (well, after this series at least).
I agree. That's the path of least resistance and trouble.
If/when ARM-specific driver subsystems need their own zuper-maintainer
we can deal with it, can't we? There aren't many of them yet.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH] spi: Fix builderror in spi-pl022.c
From: Linus Walleij @ 2011-09-21 15:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110921131052.GG17169@n2100.arm.linux.org.uk>
On Wed, Sep 21, 2011 at 3:10 PM, Russell King - ARM Linux
<linux@arm.linux.org.uk> wrote:
> On Tue, Sep 20, 2011 at 10:45:41PM +0200, Linus Walleij wrote:
>> > Grant can you please apply this patch? Right now linux-next is
>> > breaking because of this missing patch...
>>
>> Ping on this... ignore if it's been picked already.
>
> Isn't it already fixed? ?I've had this in my tree for quite some time
> (since 5th September) which should also be in linux-next.
It is, just wasn't getting my linux-next right after all the kernelorg
downtime.
Thanks Russell, and sorry for the fuzz.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH 00/10] hwspinlock-next
From: Ohad Ben-Cohen @ 2011-09-21 15:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110921152812.GE2937@atomide.com>
On Wed, Sep 21, 2011 at 6:28 PM, Tony Lindgren <tony@atomide.com> wrote:
> Ohad can you please try this first? Just please make sure your patches are
> first in next tree before sending in the pull request.
Sure thing.
Stephen, I'll send you the location of my tree in a few.
Thanks,
Ohad.
^ permalink raw reply
* [PATCH] ARM: vexpress: initial device tree support
From: Pawel Moll @ 2011-09-21 16:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACxGe6sTYYXbpXvPb4C+y4JX0eRxLvwjbFycXA8Mjc-XWS1QUA@mail.gmail.com>
On Wed, 2011-09-21 at 15:57 +0100, Grant Likely wrote:
> On Wed, Sep 21, 2011 at 7:24 AM, Rob Herring <robherring2@gmail.com> wrote:
> > On 09/21/2011 04:19 AM, Dave Martin wrote:
> >> * arm,amba-bus -- widely used by other boards and patchsets, but
> >> seems not to be documented.
> >>
> >
> > This should be dropped. There's not really any bus component to an amba
> > bus. All the probing info is within the primecell peripherals.
>
> No, if it is an AMBA bus, then it is entirely appropriate to declare
> it as an amba bus, but to also be compatible with "simple-bus". In
> fact, it would be better to use a compatible string that specifies the
> specific implementation of AMBA bus since there are several versions
> of the spec.
Dave asked me about details of the VE implementation. It's
sort-of-complicated... ;-)
1. Core talks to Static Memory Controller via AMBA (AXI)
SOC { core --AXI--> SMC }
2. SMC generates transaction on Static Memory Bus talking to the IO FPGA
tile/motherboard connector { SMC --SMB--> IOFPGA }
3. Now, depending on the device being accessed:
a) Transactions accessing SMSC9118, ISP1761, NOR Flash and PSRAM are
routed directly to the devices
IOFPGA { SMB --> SMSC9118 et al. }
b) The rest of the traffic is converted back to AMBA (AHB/APB)
transactions and sent to the devices connected to internal AMBA matrix.
IOFPGA { SMB --> AHB/APB bus master --AHB/APB--> PL180 }
I don't believe, though, that the DTS must reflect such level of
details. That's why I think that:
+ motherboard {
+ compatible = "simple-bus";
and
+ peripherals at 7,00000000 {
+ compatible = "arm,amba-bus", "simple-bus";
is the best description of the reality :-)
Cheers!
Pawe?
^ permalink raw reply
* [PATCH v3 0/3] add fec support for imx6q
From: Shawn Guo @ 2011-09-21 16:07 UTC (permalink / raw)
To: linux-arm-kernel
This series adds imx6q enet support. The imx6q enet is a derivative of
imx28 enet controller. It fixed the frame endian issue found on imx28,
and added 1 Gbps support.
Changes since v2:
* Refine patch #1 to get fec_reset_phy() return void
Changes since v1:
* Fix typo pointed out by Francois Romieu
* Drop patch #3 in the v1
* Rebase on net-next tree
Thanks.
Shawn Guo (3):
net/fec: fec_reset_phy() does not need to always succeed
net/fec: fix fec1 check in fec_enet_mii_init()
net/fec: add imx6q enet support
drivers/net/ethernet/freescale/Kconfig | 9 ++--
drivers/net/ethernet/freescale/fec.c | 76 +++++++++++++++++++++++---------
2 files changed, 59 insertions(+), 26 deletions(-)
^ permalink raw reply
* [PATCH v3 1/3] net/fec: fec_reset_phy() does not need to always succeed
From: Shawn Guo @ 2011-09-21 16:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1316621270-27805-1-git-send-email-shawn.guo@linaro.org>
FEC can work without a phy reset on some platforms, which means not
very platform necessarily have a phy-reset gpio encoded in device tree.
Even on the platforms that have the gpio, FEC can work without
resetting phy for some cases, e.g. boot loader has done that.
So it makes more sense to have the phy-reset-gpio request failure as
a debug message rather than a warning, and get fec_reset_phy() return
void since the caller does not check the return anyway.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
drivers/net/ethernet/freescale/fec.c | 13 +++++--------
1 files changed, 5 insertions(+), 8 deletions(-)
diff --git a/drivers/net/ethernet/freescale/fec.c b/drivers/net/ethernet/freescale/fec.c
index 158b82e..9c1d059 100644
--- a/drivers/net/ethernet/freescale/fec.c
+++ b/drivers/net/ethernet/freescale/fec.c
@@ -1411,24 +1411,22 @@ static int __devinit fec_get_phy_mode_dt(struct platform_device *pdev)
return -ENODEV;
}
-static int __devinit fec_reset_phy(struct platform_device *pdev)
+static void __devinit fec_reset_phy(struct platform_device *pdev)
{
int err, phy_reset;
struct device_node *np = pdev->dev.of_node;
if (!np)
- return -ENODEV;
+ return;
phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
err = gpio_request_one(phy_reset, GPIOF_OUT_INIT_LOW, "phy-reset");
if (err) {
- pr_warn("FEC: failed to get gpio phy-reset: %d\n", err);
- return err;
+ pr_debug("FEC: failed to get gpio phy-reset: %d\n", err);
+ return;
}
msleep(1);
gpio_set_value(phy_reset, 1);
-
- return 0;
}
#else /* CONFIG_OF */
static inline int fec_get_phy_mode_dt(struct platform_device *pdev)
@@ -1436,13 +1434,12 @@ static inline int fec_get_phy_mode_dt(struct platform_device *pdev)
return -ENODEV;
}
-static inline int fec_reset_phy(struct platform_device *pdev)
+static inline void fec_reset_phy(struct platform_device *pdev)
{
/*
* In case of platform probe, the reset has been done
* by machine code.
*/
- return 0;
}
#endif /* CONFIG_OF */
--
1.7.4.1
^ permalink raw reply related
* [PATCH v3 2/3] net/fec: fix fec1 check in fec_enet_mii_init()
From: Shawn Guo @ 2011-09-21 16:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1316621270-27805-1-git-send-email-shawn.guo@linaro.org>
In function fec_enet_mii_init(), it uses non-zero pdev->id as part
of the condition to check the second fec instance (fec1). This works
before the driver supports device tree probe. But in case of device
tree probe, pdev->id is -1 which is also non-zero, so the logic becomes
broken when device tree probe gets supported.
The patch change the logic to check "pdev->id > 0" as the part of the
condition for identifying fec1.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
drivers/net/ethernet/freescale/fec.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/net/ethernet/freescale/fec.c b/drivers/net/ethernet/freescale/fec.c
index 9c1d059..2bbe6a5 100644
--- a/drivers/net/ethernet/freescale/fec.c
+++ b/drivers/net/ethernet/freescale/fec.c
@@ -996,7 +996,7 @@ static int fec_enet_mii_init(struct platform_device *pdev)
* mdio interface in board design, and need to be configured by
* fec0 mii_bus.
*/
- if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && pdev->id) {
+ if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && pdev->id > 0) {
/* fec1 uses fec0 mii_bus */
fep->mii_bus = fec0_mii_bus;
return 0;
--
1.7.4.1
^ permalink raw reply related
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox