* [PATCH] mmc: card: modify mmc_getgeo function
From: Russell King - ARM Linux @ 2011-09-26 13:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <m2k48vtr12.fsf@bob.laptop.org>
On Mon, Sep 26, 2011 at 08:41:13AM -0400, Chris Ball wrote:
> Hi,
>
> On Mon, Sep 26 2011, Uwe Kleine-K?nig wrote:
> >> Thanks, pushed to mmc-next for 3.2 with a reworded commit message:
> > This (i.e. ee9e0e0 (mmc: card: Remove duplicated constants) in next)
> > makes gcc emit a reference to __aeabi_uldivmod in one of my nightly
> > builds which isn't defined.
> >
> > The final linking stage fails with:
> >
> > LD .tmp_vmlinux1
> > drivers/built-in.o: In function `mmc_blk_getgeo':
> > clkdev.c:(.text+0xd1528): undefined reference to `__aeabi_uldivmod'
> > make[2]: *** [.tmp_vmlinux1] Error 1
> > make[1]: *** [sub-make] Error 2
> > make: *** [all] Error 2
>
> Interesting, thanks. It builds fine here on my (gcc-4.6) ARM toolchains.
> Looking online, I think you're hitting an old gcc-4.3 bug?
Check your setting of CONFIG_LBDAF - the return type from get_capacity
depends on this (which may be either unsigned long or u64).
Now, the thing about a constant division by (16*4) is that its relatively
easy for gcc to spot that this is the same as a shift - and use a shift
instead of a divide for both the unsigned long and u64 cases.
However, the change may result in gcc no longer realizing that it's a
constant division by a power-of-2, and that optimization can be applied.
If you want to eliminate these constants, I'd suggest two definitions
MMC_GEO_SECTORS
MMC_GEO_HEADS
and just subsituting the '4' and '16' in the function with the appropriate
symbolic constants. That'd avoid causing this regression.
^ permalink raw reply
* [PATCH] ARM i.MX gic: add handle_irq function
From: Russell King - ARM Linux @ 2011-09-26 13:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1316797284-21010-1-git-send-email-shawn.guo@linaro.org>
On Sat, Sep 24, 2011 at 01:01:24AM +0800, Shawn Guo wrote:
> +#ifdef CONFIG_SMP
> + else if (irqnr < 16) {
> + writel_relaxed(irqstat, gic_cpu_base_addr +
> + GIC_CPU_EOI);
> + do_IPI(irqnr, regs);
> + }
> +#endif
> +#ifdef CONFIG_LOCAL_TIMERS
> + else if (irqnr == 29) {
> + writel_relaxed(irqstat, gic_cpu_base_addr +
> + GIC_CPU_EOI);
> + do_local_timer(regs);
Neither of these two functions are designed to be called from C code.
Notice that they are marked __exception or __exception_irq_entry, and
thus they expect to have a pt_regs structure directly above themselves.
^ permalink raw reply
* [PATCH] mmc: card: modify mmc_getgeo function
From: Uwe Kleine-König @ 2011-09-26 13:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <m2k48vtr12.fsf@bob.laptop.org>
On Mon, Sep 26, 2011 at 08:41:13AM -0400, Chris Ball wrote:
> Hi,
>
> On Mon, Sep 26 2011, Uwe Kleine-K?nig wrote:
> >> Thanks, pushed to mmc-next for 3.2 with a reworded commit message:
> > This (i.e. ee9e0e0 (mmc: card: Remove duplicated constants) in next)
> > makes gcc emit a reference to __aeabi_uldivmod in one of my nightly
> > builds which isn't defined.
> >
> > The final linking stage fails with:
> >
> > LD .tmp_vmlinux1
> > drivers/built-in.o: In function `mmc_blk_getgeo':
> > clkdev.c:(.text+0xd1528): undefined reference to `__aeabi_uldivmod'
> > make[2]: *** [.tmp_vmlinux1] Error 1
> > make[1]: *** [sub-make] Error 2
> > make: *** [all] Error 2
>
> Interesting, thanks. It builds fine here on my (gcc-4.6) ARM toolchains.
> Looking online, I think you're hitting an old gcc-4.3 bug?
Yeah, this is gcc 4.3.2. Is it too old to be supported?
Do you think of http://gcc.gnu.org/bugzilla/show_bug.cgi?id=48783? Then
no, that is not the problem. The function is actually used:
00000028 <mmc_blk_getgeo>:
28: e3a03004 mov r3, #4
2c: e3a02010 mov r2, #16
30: e92d4010 push {r4, lr}
34: e1a04001 mov r4, r1
38: e5c13000 strb r3, [r1]
3c: e5c12001 strb r2, [r1, #1]
40: e590c050 ldr ip, [r0, #80] ; 0x50
44: e3a02040 mov r2, #64 ; 0x40
48: e3a03000 mov r3, #0
4c: e1cc04d8 ldrd r0, [ip, #72] ; 0x48
50: ebfffffe bl 0 <__aeabi_uldivmod>
54: e1c400b2 strh r0, [r4, #2]
58: e3a00000 mov r0, #0
5c: e8bd8010 pop {r4, pc}
I thought that the problem is more:
> The kernel doesn't support 64-bit by 64-bit division at all then?
Nope. 64-bit by 64-bit divides are grossly inefficient and should be
avoided.
(taken from http://www.spinics.net/lists/arm/msg13532.html)
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-K?nig |
Industrial Linux Solutions | http://www.pengutronix.de/ |
^ permalink raw reply
* Pull request: removal of most instances of mach/memory.h
From: Russell King - ARM Linux @ 2011-09-26 13:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.LFD.2.00.1109201349400.12663@xanadu.home>
On Tue, Sep 20, 2011 at 01:53:49PM -0400, Nicolas Pitre wrote:
> Re-ping.
>
> Please let me know if there is something wrong with this series as I
> would like to have sufficient time to fix it if needed.
I think it's fairly obvious why I've not taken this (because of the
StrongARM changes which I've still not yet tested.) Once I've sorted
that out I can take it, but not before then. Especially so as my
firewall uses this CPU and I don't want it to break and force me
offline as a result.
However, as you've guessed I don't currently have the bandwidth to
test those changes at the moment - and as the rest of this series
relies on that change, it would be very difficult to revert it later
if it proves to be a problem.
^ permalink raw reply
* [RFC PATCH 10/14] ARM: cns3xxx: convert to CONFIG_MULTI_IRQ_HANDLER
From: Anton Vorontsov @ 2011-09-26 13:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1316796692-15964-11-git-send-email-marc.zyngier@arm.com>
On Fri, Sep 23, 2011 at 05:51:28PM +0100, Marc Zyngier wrote:
> Convert the cns3xxx platform to be using the gic_handle_irq
> function as its primary interrupt handler.
>
> Cc: Anton Vorontsov <avorontsov@mvista.com>
> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Anton Vorontsov <cbouatmailru@gmail.com>
Thanks!
^ permalink raw reply
* [PATCH] ARM i.MX gic: add handle_irq function
From: Shawn Guo @ 2011-09-26 13:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110926084141.GP31404@pengutronix.de>
On Mon, Sep 26, 2011 at 10:41:41AM +0200, Sascha Hauer wrote:
> On Sat, Sep 24, 2011 at 01:01:24AM +0800, Shawn Guo wrote:
> > This is a plain translation of assembly gic irq handler to C function
> > for CONFIG_MULTI_IRQ_HANDLER support on imx family.
> >
> > As the speed of gic_handle_irq() is much more important than code
> > clean, the patch chooses to plug the ifdef in the function to compile
> > out the corresponding codes.
> >
> > Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
> > ---
> > Right, ideally the arch/arm/plat-mxc/gic.c should be merged into
> > arch/arm/common/gic.c. But before rmk asks me to do that, I would
> > let it stay in imx platform.
> >
> > arch/arm/plat-mxc/Makefile | 2 +-
> > arch/arm/plat-mxc/gic.c | 47 ++++++++++++++++++++++++++
> > arch/arm/plat-mxc/include/mach/common.h | 2 +
> > arch/arm/plat-mxc/include/mach/entry-macro.S | 6 +++
> > 4 files changed, 56 insertions(+), 1 deletions(-)
> > create mode 100644 arch/arm/plat-mxc/gic.c
> >
> > diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
> > index d53c35f..b9f0f5f 100644
> > --- a/arch/arm/plat-mxc/Makefile
> > +++ b/arch/arm/plat-mxc/Makefile
> > @@ -5,7 +5,7 @@
> > # Common support
> > obj-y := clock.o time.o devices.o cpu.o system.o irq-common.o
> >
> > -# MX51 uses the TZIC interrupt controller, older platforms use AVIC
> > +obj-$(CONFIG_ARM_GIC) += gic.o
> > obj-$(CONFIG_MXC_TZIC) += tzic.o
> > obj-$(CONFIG_MXC_AVIC) += avic.o
> >
> > diff --git a/arch/arm/plat-mxc/gic.c b/arch/arm/plat-mxc/gic.c
> > new file mode 100644
> > index 0000000..487d12c
> > --- /dev/null
> > +++ b/arch/arm/plat-mxc/gic.c
> > @@ -0,0 +1,47 @@
> > +/*
> > + * Copyright 2011 Freescale Semiconductor, Inc.
> > + * Copyright 2011 Linaro Ltd.
> > + *
> > + * The code contained herein is licensed under the GNU General Public
> > + * License. You may obtain a copy of the GNU General Public License
> > + * Version 2 or later at the following locations:
> > + *
> > + * http://www.opensource.org/licenses/gpl-license.html
> > + * http://www.gnu.org/copyleft/gpl.html
> > + */
> > +
> > +#include <linux/io.h>
> > +#include <asm/localtimer.h>
> > +#include <asm/hardware/gic.h>
> > +#ifdef CONFIG_SMP
> > +#include <asm/smp.h>
> > +#endif
> > +
> > +asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
> > +{
> > + u32 irqstat, irqnr;
> > +
> > + do {
> > + irqstat = readl_relaxed(gic_cpu_base_addr + GIC_CPU_INTACK);
> > + irqnr = irqstat & 0x3ff;
> > + if (irqnr == 1023)
> > + break;
> > +
> > + if (irqnr > 29 && irqnr < 1021)
> > + handle_IRQ(irqnr, regs);
> > +#ifdef CONFIG_SMP
> > + else if (irqnr < 16) {
> > + writel_relaxed(irqstat, gic_cpu_base_addr +
> > + GIC_CPU_EOI);
> > + do_IPI(irqnr, regs);
> > + }
> > +#endif
> > +#ifdef CONFIG_LOCAL_TIMERS
> > + else if (irqnr == 29) {
> > + writel_relaxed(irqstat, gic_cpu_base_addr +
> > + GIC_CPU_EOI);
> > + do_local_timer(regs);
> > + }
> > +#endif
> > + } while (1);
> > +}
>
> Shouldn't this code go to arch/arm/common/gic.c instead? The
> corresponding assembly code is generic so I see no reason to make
> this i.MX specific.
>
Yes. I put some notes below '---' about this. Basically, this patch
is just a way around to have imx6q catch up with your global move on
i.mx CONFIG_MULTI_IRQ_HANDLER support. In the long term, this GIC
support should definitely need to be handled by arch/arm/common/gic.c.
Actually, Marc Zyngier has just started posting CONFIG_MULTI_IRQ_HANDLER
for GIC. But it depends on his own PPI series, which I'm unsure if it
will gets merged in the coming window. I really want to get imx6q
merged in v3.2 window, so I would not have Marc's common GIC support
as a dependency. We can switch to it once it gets merged.
--
Regards,
Shawn
^ permalink raw reply
* [PATCH] mmc: card: modify mmc_getgeo function
From: Russell King - ARM Linux @ 2011-09-26 13:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110926131333.GA20550@pengutronix.de>
On Mon, Sep 26, 2011 at 03:13:33PM +0200, Uwe Kleine-K?nig wrote:
> 00000028 <mmc_blk_getgeo>:
> 28: e3a03004 mov r3, #4
> 2c: e3a02010 mov r2, #16
> 30: e92d4010 push {r4, lr}
> 34: e1a04001 mov r4, r1
> 38: e5c13000 strb r3, [r1]
> 3c: e5c12001 strb r2, [r1, #1]
> 40: e590c050 ldr ip, [r0, #80] ; 0x50
> 44: e3a02040 mov r2, #64 ; 0x40
> 48: e3a03000 mov r3, #0
> 4c: e1cc04d8 ldrd r0, [ip, #72] ; 0x48
> 50: ebfffffe bl 0 <__aeabi_uldivmod>
> 54: e1c400b2 strh r0, [r4, #2]
Yes, this is just silly. A 64-bit by 64-bit division by a power-of-2
value to ultimately store a 16-bit value.
Even truncating the output from get_capacity() would be better and no
less (in)correct (it may look weird but what the assembly shows is that
it really doesn't matter). u64 / 64 will give the same 16-bit result as
u64-truncated-to-u32 / 64.
^ permalink raw reply
* [PATCH v3 4/6] arm/imx6q: add smp and cpu hotplug support
From: Shawn Guo @ 2011-09-26 13:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110926110634.GR31404@pengutronix.de>
On Mon, Sep 26, 2011 at 01:06:34PM +0200, Sascha Hauer wrote:
> On Mon, Sep 26, 2011 at 03:20:49PM +0800, Shawn Guo wrote:
> > It adds smp and cpu hotplug support for imx6q.
> >
> > Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
> > ---
> > arch/arm/mach-imx/Kconfig | 1 +
> > arch/arm/mach-imx/Makefile | 4 ++
> > arch/arm/mach-imx/head-v7.S | 71 ++++++++++++++++++++++++++
> > arch/arm/mach-imx/hotplug.c | 44 ++++++++++++++++
> > arch/arm/mach-imx/localtimer.c | 35 +++++++++++++
> > arch/arm/mach-imx/platsmp.c | 85 +++++++++++++++++++++++++++++++
> > arch/arm/plat-mxc/include/mach/common.h | 5 ++
> > 7 files changed, 245 insertions(+), 0 deletions(-)
> > create mode 100644 arch/arm/mach-imx/head-v7.S
> > create mode 100644 arch/arm/mach-imx/hotplug.c
> > create mode 100644 arch/arm/mach-imx/localtimer.c
> > create mode 100644 arch/arm/mach-imx/platsmp.c
> >
> > diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
> > index af73b3e..6ec758d 100644
> > --- a/arch/arm/mach-imx/Kconfig
> > +++ b/arch/arm/mach-imx/Kconfig
> > @@ -623,6 +623,7 @@ config SOC_IMX6Q
> > bool "i.MX6 Quad support"
> > select ARM_GIC
> > select CPU_V7
> > + select HAVE_ARM_SCU
> > select HAVE_IMX_GPC
> > select HAVE_IMX_MMDC
> > select HAVE_IMX_SRC
> > diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
> > index 8c21fda..d46b2e7 100644
> > --- a/arch/arm/mach-imx/Makefile
> > +++ b/arch/arm/mach-imx/Makefile
> > @@ -66,4 +66,8 @@ obj-$(CONFIG_DEBUG_LL) += lluart.o
> > obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
> > obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o
> > obj-$(CONFIG_HAVE_IMX_SRC) += src.o
> > +obj-$(CONFIG_CPU_V7) += head-v7.o
>
> Can we have a
>
> AFLAGS_head-v7.o :=-Wa,-march=armv7-a
>
> here?
>
> Then you only have to adjust some Kconfig variables and can compile
> i.MX3 and i.MX6 together. I just gave it a test and it works on i.MX3, I
> don't have a i.MX6 platform to test on though.
>
> The following patch could be a starting point. I merged the imx-features
> branch into it so it probably won't apply cleanly on your series.
>
I will try to test and fold it in my series tomorrow.
--
Regards,
Shawn
^ permalink raw reply
* [PATCH] ARM i.MX gic: add handle_irq function
From: Shawn Guo @ 2011-09-26 13:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110926131036.GI22455@n2100.arm.linux.org.uk>
On Mon, Sep 26, 2011 at 02:10:36PM +0100, Russell King - ARM Linux wrote:
> On Sat, Sep 24, 2011 at 01:01:24AM +0800, Shawn Guo wrote:
> > +#ifdef CONFIG_SMP
> > + else if (irqnr < 16) {
> > + writel_relaxed(irqstat, gic_cpu_base_addr +
> > + GIC_CPU_EOI);
> > + do_IPI(irqnr, regs);
> > + }
> > +#endif
> > +#ifdef CONFIG_LOCAL_TIMERS
> > + else if (irqnr == 29) {
> > + writel_relaxed(irqstat, gic_cpu_base_addr +
> > + GIC_CPU_EOI);
> > + do_local_timer(regs);
>
> Neither of these two functions are designed to be called from C code.
> Notice that they are marked __exception or __exception_irq_entry, and
> thus they expect to have a pt_regs structure directly above themselves.
>
Thanks for the points. Since the testing did not tell any problem,
I guess we can use it as a temporary solution before we have a
sophisticated implementation available in GIC common code?
--
Regards,
Shawn
^ permalink raw reply
* Pull request: removal of most instances of mach/memory.h
From: Nicolas Pitre @ 2011-09-26 13:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110926131524.GJ22455@n2100.arm.linux.org.uk>
On Mon, 26 Sep 2011, Russell King - ARM Linux wrote:
> On Tue, Sep 20, 2011 at 01:53:49PM -0400, Nicolas Pitre wrote:
> > Re-ping.
> >
> > Please let me know if there is something wrong with this series as I
> > would like to have sufficient time to fix it if needed.
>
> I think it's fairly obvious why I've not taken this (because of the
> StrongARM changes which I've still not yet tested.) Once I've sorted
> that out I can take it, but not before then. Especially so as my
> firewall uses this CPU and I don't want it to break and force me
> offline as a result.
As I said in that same message:
| I also merged the patch entitled "get rid of a few StrongARM
| cache-related build time constants" as this is a prerequisite for the
| removal of mach/memory.h in mach-ebsa110 and mach-shark (more if the
| sparsemem stuff gets moved). If you don't feel comfortable having
| this patch merged then I can remove it along with those commits that depend
| on it.
So let me remove that and ask you to pull again.
Nicolas
^ permalink raw reply
* [RFC PATCH v3] drivercore: Add driver probe deferral mechanism
From: Mark Brown @ 2011-09-26 14:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110922184614.25419.84606.stgit@ponder>
On Thu, Sep 22, 2011 at 12:51:23PM -0600, Grant Likely wrote:
> Allow drivers to report at probe time that they cannot get all the resources
> required by the device, and should be retried at a later time.
> This should completely solve the problem of getting devices
> initialized in the right order. Right now this is mostly handled by
> mucking about with initcall ordering which is a complete hack, and
> doesn't even remotely handle the case where device drivers are in
> modules. This approach completely sidesteps the issues by allowing
> driver registration to occur in any order, and any driver can request
> to be retried after a few more other drivers get probed.
So, one issue I did think of the other day while putting some support in
the regulator core for using this: what happens with devices which can
optionally use a resource but don't rely on it? One example here is
that a lot of the MMC drivers have an optional regulator to control some
of the supplies for the cards. If the reglator isn't there it won't be
used but it's not a blocker for anything. Devices doing this would need
some way to figure out if they should -EBUSY or fail otherwise.
^ permalink raw reply
* [PATCH v2] mach-integrator: update defconfig
From: Linus Walleij @ 2011-09-26 14:31 UTC (permalink / raw)
To: linux-arm-kernel
Update the Integrator defconfig with some sensible defaults:
- Compile a combined image supporting Integrator/AP and
Integrator/CP, with the core modules CM720, CM920, CM922,
CM926, CM1020, CM1022 and CM1026 in a single image, this
works just fine and gives some nice compilation coverage
- NOHZ (tickless) and HRTIMERS turned on
- Compile using EABI, let's assume recent compilers are used
now (tested using GCC 4.4.1)
- Remove forced 32MiB at command line, the bootloader usually
knows this better, and my U-Boot patches nowadays make that
boot loader pass the correct adjusted value
- Enable the MTD Physmap flash driver, so that the changes done
earlier by Marc Zyngier replacing integrator-flash takes
effect
- Enable the PL030 RTC driver that has not been default-compiled
with any config for a while
This has been tested on the real hardware Integrator AP with
both an ARM920T and ARM926EJ-S core module.
Cc: Marc Zyngier <Marc.Zyngier@arm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/configs/integrator_defconfig | 11 +++++++----
1 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/arch/arm/configs/integrator_defconfig b/arch/arm/configs/integrator_defconfig
index 7196ade..baf4301 100644
--- a/arch/arm/configs/integrator_defconfig
+++ b/arch/arm/configs/integrator_defconfig
@@ -1,5 +1,6 @@
CONFIG_EXPERIMENTAL=y
CONFIG_SYSVIPC=y
+CONFIG_TINY_RCU=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
@@ -11,17 +12,20 @@ CONFIG_ARCH_INTEGRATOR_AP=y
CONFIG_CPU_ARM720T=y
CONFIG_CPU_ARM920T=y
CONFIG_PCI=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
+CONFIG_AEABI=y
CONFIG_LEDS=y
CONFIG_LEDS_CPU=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyAM0,38400n8 root=/dev/nfs ip=bootp mem=32M"
+CONFIG_CMDLINE="console=ttyAM0,38400n8 root=/dev/nfs ip=bootp"
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_FPE_NWFPE=y
-CONFIG_PM=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@@ -32,7 +36,6 @@ CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
# CONFIG_IPV6 is not set
CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_AFS_PARTS=y
CONFIG_MTD_CHAR=y
@@ -40,6 +43,7 @@ CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_PHYSMAP=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=8192
@@ -68,4 +72,3 @@ CONFIG_NFSD_V3=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_ERRORS=y
--
1.7.6
^ permalink raw reply related
* [RFC PATCH 0/3] ARM: mm: add L2 suspend/resume support
From: Lorenzo Pieralisi @ 2011-09-26 14:32 UTC (permalink / raw)
To: linux-arm-kernel
As a follow up to the last L2 resume patch on alkml:
http://www.spinics.net/lists/arm-kernel/msg141881.html
please have a look at this patchset and merge the required bits if needed,
in particular MMU off for L2 retention use case.
Description:
In order to support the deepest C-states on all ARM platforms, code to resume
L2 state could be added to the kernel to avoid reliance on bootloaders.
If L2 RAM is retained on power down, it is not cleaned on shutdown to preserve
its content and improve performance. Hence, L2 state should be restored before
the MMU is turned on, so that CPU resume code can search the data saved on
power down in the L2 cache.
This patch addresses this issue and extends outercache and l2x0 driver to
support L2 resume in a platform independent way, security issues
notwithstanding that must be tackled separately.
Since the L2 should be enabled when the MMU is possibly off,
L2 physical address should be passed from platform code or retrieved from
the device tree so that the code can be made generic and platform
independent. For that purpose, the signature of L2 init function has
to be upgraded.
The resume code should not use the stack and it must fetch data using
program counter relative loads so that it does not matter if it is run
in physical or virtual address space.
This patch depends on three patches:
ARM: 7090/1: CACHE-L2X0: filter start address can be 0 and is often 0
http://www.spinics.net/lists/arm-kernel/msg140126.html
available in rmk/for-next commit 2afda86d91b5f15a744182d7ddacf68f6a6054c9
ARM: 7080/1: l2x0: make sure I&D are not locked down on init
http://www.spinics.net/lists/arm-kernel/msg139119.html
available in rmk/for-next commit bac7e6ecf60933b68af910eb4c83a775a8b20b19
ARM: 7009/1: l2x0: Add OF based initialization
http://www.spinics.net/lists/arm-kernel/msg131123.htm
available in rmk/for-next commit 41c86ff5be44e26978282f86c20598181b999142
Platform code initializing L2 has not been patched (l2x0_init requires
a new parameter which is the physical base address) yet, waiting to
see if there are platforms that can take advantage of this code.
Tested on Samsung Origen within suspend and cpuidle code paths.
DT support compile tested.
Lorenzo Pieralisi (3):
ARM: mm: add outercache resume hook
ARM: mm: add l2x0 physical address parameter to init
ARM: mm: add l2x0 suspend/resume support
arch/arm/include/asm/hardware/cache-l2x0.h | 24 +++++-
arch/arm/include/asm/outercache.h | 7 ++
arch/arm/kernel/asm-offsets.c | 12 +++
arch/arm/mm/Makefile | 3 +
arch/arm/mm/cache-l2x0.c | 17 +++-
arch/arm/mm/l2x0-sleep.S | 136 ++++++++++++++++++++++++++++
6 files changed, 193 insertions(+), 6 deletions(-)
create mode 100644 arch/arm/mm/l2x0-sleep.S
--
1.7.4.4
^ permalink raw reply
* [RFC PATCH 1/3] ARM: mm: add outercache resume hook
From: Lorenzo Pieralisi @ 2011-09-26 14:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1317047561-11020-1-git-send-email-lorenzo.pieralisi@arm.com>
In order to support L2 resume functions in a generic way in the kernel, this
patch adds a resume hook to the outercache layer and a simple wrapper
to simplify the function pointer check and the resume function call.
Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
---
arch/arm/include/asm/outercache.h | 7 +++++++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/arch/arm/include/asm/outercache.h b/arch/arm/include/asm/outercache.h
index d838743..1b70d86 100644
--- a/arch/arm/include/asm/outercache.h
+++ b/arch/arm/include/asm/outercache.h
@@ -34,6 +34,7 @@ struct outer_cache_fns {
void (*sync)(void);
#endif
void (*set_debug)(unsigned long);
+ void (*resume)(void);
};
#ifdef CONFIG_OUTER_CACHE
@@ -74,6 +75,11 @@ static inline void outer_disable(void)
outer_cache.disable();
}
+static inline void outer_resume(void)
+{
+ if (outer_cache.resume)
+ outer_cache.resume();
+}
#else
static inline void outer_inv_range(phys_addr_t start, phys_addr_t end)
@@ -86,6 +92,7 @@ static inline void outer_flush_all(void) { }
static inline void outer_inv_all(void) { }
static inline void outer_disable(void) { }
+static inline void outer_resume(void) { }
#endif
#ifdef CONFIG_OUTER_CACHE_SYNC
--
1.7.4.4
^ permalink raw reply related
* [RFC PATCH 2/3] ARM: mm: add l2x0 physical address parameter to init
From: Lorenzo Pieralisi @ 2011-09-26 14:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1317047561-11020-1-git-send-email-lorenzo.pieralisi@arm.com>
This patch redefines the l2x0_init function, and it adds a
parameter defining the L2 physical base address in preparation
for L2 resume support. The device tree init code retrieves the
physical address from the "reg" array and converts it to a
physical address pointer.
Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
---
arch/arm/include/asm/hardware/cache-l2x0.h | 3 ++-
arch/arm/mm/cache-l2x0.c | 12 ++++++++++--
2 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
index c48cb1e..54bf625 100644
--- a/arch/arm/include/asm/hardware/cache-l2x0.h
+++ b/arch/arm/include/asm/hardware/cache-l2x0.h
@@ -94,7 +94,8 @@
#define L2X0_ADDR_FILTER_EN 1
#ifndef __ASSEMBLY__
-extern void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask);
+extern void __init l2x0_init(void __iomem *base, void __iomem *pbase,
+ __u32 aux_val, __u32 aux_mask);
extern int l2x0_of_init(__u32 aux_val, __u32 aux_mask);
#endif
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 0d85d22..46a507a 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -299,7 +299,8 @@ static void __init l2x0_unlock(__u32 cache_id)
}
}
-void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
+void __init l2x0_init(void __iomem *base, void __iomem *pbase,
+ __u32 aux_val, __u32 aux_mask)
{
__u32 aux;
__u32 cache_id;
@@ -455,6 +456,9 @@ static const struct of_device_id l2x0_ids[] __initconst = {
int __init l2x0_of_init(__u32 aux_val, __u32 aux_mask)
{
struct device_node *np;
+ u32 reg[2];
+ int ret;
+
void (*l2_setup)(const struct device_node *np,
__u32 *aux_val, __u32 *aux_mask);
@@ -465,13 +469,17 @@ int __init l2x0_of_init(__u32 aux_val, __u32 aux_mask)
if (!l2x0_base)
return -ENOMEM;
+ ret = of_property_read_u32_array(np, "reg", reg, ARRAY_SIZE(reg));
+ if (ret < 0)
+ return ret;
+
/* L2 configuration can only be changed if the cache is disabled */
if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
l2_setup = of_match_node(l2x0_ids, np)->data;
if (l2_setup)
l2_setup(np, &aux_val, &aux_mask);
}
- l2x0_init(l2x0_base, aux_val, aux_mask);
+ l2x0_init(l2x0_base, (void __iomem *)reg[0], aux_val, aux_mask);
return 0;
}
#endif
--
1.7.4.4
^ permalink raw reply related
* [RFC PATCH 3/3] ARM: mm: add l2x0 suspend/resume support
From: Lorenzo Pieralisi @ 2011-09-26 14:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1317047561-11020-1-git-send-email-lorenzo.pieralisi@arm.com>
When suspend to RAM or cpuidle require the system to enter the deepest C
states, L2 cache logic can be lost.
This patch adds assembly hooks that allow to restore the context for
l2x0 series of L2 controllers upon system resume.
Context is saved once for all at boot time, along with the L2 physical address
and cache type.
The resume code can be called with MMU either on or off and it executes
specific code accordingly, by checking the MMU status in the SCTRL system
register.
Code is in place to check if L2 is already enabled on resume to
avoid writing L2 registers that would cause faults.
The resume hook avoids using the stack since it might be called
before the C environment is up and running and fetches data using
program counter relative addressing so that it can be run both
with MMU on or off to simplify its adoption.
Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
---
arch/arm/include/asm/hardware/cache-l2x0.h | 21 ++++-
arch/arm/kernel/asm-offsets.c | 12 +++
arch/arm/mm/Makefile | 3 +
arch/arm/mm/cache-l2x0.c | 5 +-
arch/arm/mm/l2x0-sleep.S | 136 ++++++++++++++++++++++++++++
5 files changed, 174 insertions(+), 3 deletions(-)
create mode 100644 arch/arm/mm/l2x0-sleep.S
diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
index 54bf625..05312eb 100644
--- a/arch/arm/include/asm/hardware/cache-l2x0.h
+++ b/arch/arm/include/asm/hardware/cache-l2x0.h
@@ -97,6 +97,25 @@
extern void __init l2x0_init(void __iomem *base, void __iomem *pbase,
__u32 aux_val, __u32 aux_mask);
extern int l2x0_of_init(__u32 aux_val, __u32 aux_mask);
-#endif
+#ifndef CONFIG_PM_SLEEP
+static inline void l2x0_resume(void) {}
+static inline void l2x0_save_context(void __iomem *pbase, __u32 cache_id) {}
+#else
+struct l2x0_regs {
+ __u32 aux_ctrl;
+ __u32 tag_latency;
+ __u32 data_latency;
+ __u32 afilter_start;
+ __u32 afilter_end;
+ __u32 debug_ctrl;
+ __u32 prefetch_ctrl;
+ __u32 power_ctrl;
+} __packed;
+
+extern struct l2x0_regs l2x0_data;
+extern void l2x0_resume(void);
+extern void l2x0_save_context(void __iomem *pbase, __u32 cache_id);
+#endif /* CONFIG_PM_SLEEP */
+#endif /* __ASSEMBLY__ */
#endif
diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c
index 16baba2..91d7b7b 100644
--- a/arch/arm/kernel/asm-offsets.c
+++ b/arch/arm/kernel/asm-offsets.c
@@ -20,6 +20,7 @@
#include <asm/thread_info.h>
#include <asm/memory.h>
#include <asm/procinfo.h>
+#include <asm/hardware/cache-l2x0.h>
#include <linux/kbuild.h>
/*
@@ -128,6 +129,17 @@ int main(void)
#ifdef MULTI_CACHE
DEFINE(CACHE_FLUSH_KERN_ALL, offsetof(struct cpu_cache_fns, flush_kern_all));
#endif
+#ifdef CONFIG_CACHE_L2X0
+ DEFINE(L2X0_REGS_SZ, sizeof(struct l2x0_regs));
+ DEFINE(L2X0_R_AUX_CTRL, offsetof(struct l2x0_regs, aux_ctrl));
+ DEFINE(L2X0_R_TAG_LATENCY, offsetof(struct l2x0_regs, tag_latency));
+ DEFINE(L2X0_R_DATA_LATENCY, offsetof(struct l2x0_regs, data_latency));
+ DEFINE(L2X0_R_AFILTER_START, offsetof(struct l2x0_regs, afilter_start));
+ DEFINE(L2X0_R_AFILTER_END, offsetof(struct l2x0_regs, afilter_end));
+ DEFINE(L2X0_R_DEBUG_CTRL, offsetof(struct l2x0_regs, debug_ctrl));
+ DEFINE(L2X0_R_PREFETCH_CTRL, offsetof(struct l2x0_regs, prefetch_ctrl));
+ DEFINE(L2X0_R_POWER_CTRL, offsetof(struct l2x0_regs, power_ctrl));
+#endif
BLANK();
DEFINE(DMA_BIDIRECTIONAL, DMA_BIDIRECTIONAL);
DEFINE(DMA_TO_DEVICE, DMA_TO_DEVICE);
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
index bca7e61..5936d6b 100644
--- a/arch/arm/mm/Makefile
+++ b/arch/arm/mm/Makefile
@@ -98,5 +98,8 @@ AFLAGS_proc-v7.o :=-Wa,-march=armv7-a
obj-$(CONFIG_CACHE_FEROCEON_L2) += cache-feroceon-l2.o
obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o
+ifeq ($(CONFIG_PM_SLEEP),y)
+obj-$(CONFIG_CACHE_L2X0) += l2x0-sleep.o
+endif
obj-$(CONFIG_CACHE_XSC3L2) += cache-xsc3l2.o
obj-$(CONFIG_CACHE_TAUROS2) += cache-tauros2.o
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 46a507a..9b9d619 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -28,7 +28,7 @@
#define CACHE_LINE_SIZE 32
-static void __iomem *l2x0_base;
+void __iomem *l2x0_base;
static DEFINE_SPINLOCK(l2x0_lock);
static uint32_t l2x0_way_mask; /* Bitmask of active ways */
static uint32_t l2x0_size;
@@ -358,7 +358,7 @@ void __init l2x0_init(void __iomem *base, void __iomem *pbase,
writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL);
l2x0_inv_all();
-
+ l2x0_save_context(pbase, cache_id & L2X0_CACHE_ID_PART_MASK);
/* enable L2X0 */
writel_relaxed(1, l2x0_base + L2X0_CTRL);
}
@@ -371,6 +371,7 @@ void __init l2x0_init(void __iomem *base, void __iomem *pbase,
outer_cache.inv_all = l2x0_inv_all;
outer_cache.disable = l2x0_disable;
outer_cache.set_debug = l2x0_set_debug;
+ outer_cache.resume = l2x0_resume;
printk(KERN_INFO "%s cache controller enabled\n", type);
printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n",
diff --git a/arch/arm/mm/l2x0-sleep.S b/arch/arm/mm/l2x0-sleep.S
new file mode 100644
index 0000000..ac4998a
--- /dev/null
+++ b/arch/arm/mm/l2x0-sleep.S
@@ -0,0 +1,136 @@
+/*
+ * Copyright (C) 2011 ARM Ltd
+ * Author: Lorenzo Pieralisi
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/linkage.h>
+#include <asm/asm-offsets.h>
+#include <asm/hardware/cache-l2x0.h>
+
+ __INIT
+
+save_l210:
+ ldr r4, [r1, #L2X0_AUX_CTRL]
+ str r4, [r0], #4
+ ldmnefd sp!, {r4 - r11, pc} @ if l210 returns
+save_l310:
+ ldr r5, [r1, #L2X0_TAG_LATENCY_CTRL]
+ ldr r6, [r1, #L2X0_DATA_LATENCY_CTRL]
+ ldr r7, [r1, #L2X0_ADDR_FILTER_START]
+ ldr r8, [r1, #L2X0_ADDR_FILTER_END]
+ ldr r9, [r1, #L2X0_DEBUG_CTRL]
+ ldr r10, [r1, #L2X0_PREFETCH_CTRL]
+ ldr r11, [r1, #L2X0_POWER_CTRL]
+ stmia r0, {r5 - r11}
+ ldmfd sp!, {r4 - r11, pc}
+
+/*
+ * Save L2x0 registers depending on L2 HW configuration.
+ * A check on cache type is carried out and registers are saved
+ * accordingly, once for all at boot time. L2 is off so there is no
+ * need to clean L2 cache lines containing reg values to DRAM.
+ * r0 = L2 physical base address
+ * r1 = cache type
+ */
+
+ENTRY(l2x0_save_context)
+ stmfd sp!, {r4 - r11, lr}
+ ldr r2, =l2x0_phys_base
+ str r0, [r2] @ save physical address
+ ldr r0, =l2x0_base @ get L2 base address
+ mov r2, r1 @ stash cache type
+ ldr r1, [r0]
+ ldr r0, =l2x0_data @ get context pointer
+ ldr r3, =l2x0_type
+ str r2, [r3] @ save cache type
+ cmp r2, #L2X0_CACHE_ID_PART_L310 @ jump table
+ b save_l210
+ENDPROC(l2x0_save_context)
+
+ __FINIT
+/*
+ * Function entered with flags set by jump table in l2x0_resume
+ * If zero flag is set this is a pl310
+ * r0 = l2x0_data
+ * r1 = L2 address
+ */
+resume_l210:
+ ldr r2, [r0], #4 @ just use scratch regs
+ str r2, [r1, #L2X0_AUX_CTRL]
+ mov r3, #0
+ mov r12, #L2X0_LOCKDOWN_WAY_D_BASE
+ mov r2, r12
+ str r3, [r1, r2]
+ add r2, r2, #4
+ str r3, [r1, r2]
+ movne r0, #0x1 @ if l210 we are done
+ strne r0, [r1, #L2X0_CTRL] @ enable L2
+ movne pc, lr
+resume_l310:
+ add r12, r12, r1
+ add r12, r12, #L2X0_LOCKDOWN_STRIDE @ start D lock
+ mov r2, #0
+ mov r3, #7
+unlock:
+ str r2, [r12, #4] @ I lock
+ str r2, [r12], #L2X0_LOCKDOWN_STRIDE @ D lock and increment
+ subs r3, r3, #1
+ bne unlock
+ ldmia r0!, {r2, r3, r12}
+ str r2, [r1, #L2X0_TAG_LATENCY_CTRL]
+ str r3, [r1, #L2X0_DATA_LATENCY_CTRL]
+ str r12, [r1, #L2X0_ADDR_FILTER_START]
+ ldmia r0!, {r2, r3, r12}
+ str r2, [r1, #L2X0_ADDR_FILTER_END]
+ str r3, [r1, #L2X0_DEBUG_CTRL]
+ str r12, [r1, #L2X0_PREFETCH_CTRL]
+ ldr r2, [r0]
+ str r2, [r1, #L2X0_POWER_CTRL]
+ mov r0, #0x1
+ str r0, [r1, #L2X0_CTRL] @ enable L2
+ mov pc, lr
+
+/*
+ * Resume function does not use any stack since it might be called
+ * when C environment is not set up yet. It checks the MMU status, and
+ * loads the L2 base address accordingly. Only data accessed if MMU is off is
+ * through PC relative loads, to avoid fetching data from virtual addresses
+ * that would wreak havoc.
+ */
+
+ .data
+ .align
+ENTRY(l2x0_resume)
+ mrc p15, 0, r2, c1, c0, 0 @ check if MMU is on
+ tst r2, #0x1
+ ldrne r0, =l2x0_base
+ adr r1, l2x0_phys_base
+ ldreq r1, [r1] @ it is not r1 = L2 phys
+ ldrne r1, [r0] @ it is r1 = L2 virt
+ ldr r0, [r1, #L2X0_CTRL] @ L2 enabled ?
+ tst r0, #0x1
+ movne pc, lr @ yes, bug out
+ adr r0, l2x0_data
+ adr r2, l2x0_type @ check L2 type
+ ldr r2, [r2]
+ cmp r2, #L2X0_CACHE_ID_PART_L310 @ jump table
+ b resume_l210
+ENDPROC(l2x0_restore_context)
+
+l2x0_phys_base:
+ .long 0
+
+l2x0_type:
+ .long 0
+
+ .align
+ .globl l2x0_data
+ .type l2x0_data, %object
+l2x0_data:
+ .space L2X0_REGS_SZ
+ .size l2x0_data, . - l2x0_data
--
1.7.4.4
^ permalink raw reply related
* Pull request: removal of most instances of mach/memory.h
From: Nicolas Pitre @ 2011-09-26 14:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.LFD.2.00.1109260952490.2718@xanadu.home>
On Mon, 26 Sep 2011, Nicolas Pitre wrote:
> On Mon, 26 Sep 2011, Russell King - ARM Linux wrote:
>
> > On Tue, Sep 20, 2011 at 01:53:49PM -0400, Nicolas Pitre wrote:
> > > Re-ping.
> > >
> > > Please let me know if there is something wrong with this series as I
> > > would like to have sufficient time to fix it if needed.
> >
> > I think it's fairly obvious why I've not taken this (because of the
> > StrongARM changes which I've still not yet tested.) Once I've sorted
> > that out I can take it, but not before then. Especially so as my
> > firewall uses this CPU and I don't want it to break and force me
> > offline as a result.
>
> As I said in that same message:
>
> | I also merged the patch entitled "get rid of a few StrongARM
> | cache-related build time constants" as this is a prerequisite for the
> | removal of mach/memory.h in mach-ebsa110 and mach-shark (more if the
> | sparsemem stuff gets moved). If you don't feel comfortable having
> | this patch merged then I can remove it along with those commits that depend
> | on it.
>
> So let me remove that and ask you to pull again.
Here it is. Please pull:
git://git.linaro.org/people/nico/linux mach_memory_h
Same blurb as in the original pull request, except for the above quoted
paragraph as the StrongARM stuff has now been kept out. The new
shortlog and diffstat follow.
Nicolas Pitre (50):
Merge the enabling by default of ARM_PATCH_PHYS_VIRT
ARM: mach-prima2: move ARM_DMA_ZONE_SIZE to mdesc->dma_zone_size
musb_debugfs.c: remove unneeded includes on ARM
ARM: add an extra temp register to the low level debugging addruart macro
ARM: plat-omap: make OMAP_UART_INFO into a relative offset
ARM: mach-omap1: clean up debug-macro.S
ARM: mach-omap2: clean up debug-macro.S
ARM: mach-davinci: make DAVINCI_UART_INFO into a relative offset
ARM: mach-davinci: clean up debug-macro.S
ARM: prepare for removal of a bunch of <mach/memory.h> files
ARM: mach-dove: remove include/mach/memory.h
ARM: mach-kirkwood: remove mach/memory.h
ARM: mach-orion5x: remove mach/memory.h
ARM: OMAP: move OMAP1 memory config from plat/memory.h to its mach/memory.h
ARM: mach-omap2: remove mach/memory.h
ARM: mach-iop33x: remove mach/memory.h
ARM: mach-ep93xx: remove mach/memory.h and Kconfig selection of SDRAM bank
ARM: mach-s3c2410: remove memory.h
ARM: mach-mv78xx0: remove mach/memory.h
ARM: mach-vexpress: remove mach/memory.h
ARM: mach-w90x900: remove mach/memory.h
ARM: mach-pnx4008: remove mach/memory.h
ARM: mach-iop32x: remove mach/memory.h
ARM: mach-nomadik: remove mach/memory.h
ARM: mach-ux500: remove mach/memory.h
ARM: mach-versatile: remove mach/memory.h
ARM: mach-netx: remove mach/memory.h
ARM: mach-lpc32xx: remove mach/memory.h
ARM: mach-gemini: remove mach/memory.h
ARM: mach-msm: remove mach/memory.h
ARM: spear: remove mach/memory.h and plat/memory.h
ARM: mach-mxs: remove mach/memory.h
ARM: mach-nuc93x: remove mach/memory.h
ARM: mach-cns3xxx: remove mach/memory.h
ARM: mach-mmp: remove mach/memory.h
ARM: plat-tcc: remove mach/memory.h
ARM: mach-tegra: remove mach/memory.h
ARM: mach-s5pc100: remove mach/memory.h
ARM: mach-vt8500: remove mach/memory.h
ARM: mach-h720x: remove mach/memory.h
ARM: mach-ixp4xx: remove mach/memory.h
ARM: mach-pxa: remove mach/memory.h
ARM: mach-davinci: remove mach/memory.h
ARM: mach-bcmring: remove mach/memory.h
ARM: mach-zynq: remove mach/memory.h
ARM: mach-prima2: remove mach/memory.h
ARM: plat-mxc: remove mach/memory.h
ARM: mach-s3c64xx: remove mach/memory.h
ARM: mach-s5p64x0: remove mach/memory.h
ARM: switch from NO_MACH_MEMORY_H to NEED_MACH_MEMORY_H
arch/arm/Kconfig | 30 +++++
arch/arm/include/asm/memory.h | 9 ++-
arch/arm/kernel/debug.S | 4 +-
arch/arm/kernel/head.S | 4 +-
arch/arm/mach-at91/include/mach/debug-macro.S | 2 +-
arch/arm/mach-bcmring/include/mach/hardware.h | 3 +-
arch/arm/mach-bcmring/include/mach/memory.h | 28 ----
arch/arm/mach-clps711x/include/mach/debug-macro.S | 2 +-
arch/arm/mach-cns3xxx/include/mach/debug-macro.S | 2 +-
arch/arm/mach-cns3xxx/include/mach/memory.h | 26 ----
arch/arm/mach-davinci/cpuidle.c | 2 +-
arch/arm/mach-davinci/include/mach/ddr2.h | 4 +
arch/arm/mach-davinci/include/mach/debug-macro.S | 52 ++++-----
arch/arm/mach-davinci/include/mach/memory.h | 39 ------
arch/arm/mach-davinci/include/mach/serial.h | 3 +-
arch/arm/mach-davinci/include/mach/uncompress.h | 7 +-
arch/arm/mach-davinci/sleep.S | 2 +-
arch/arm/mach-dove/include/mach/debug-macro.S | 2 +-
arch/arm/mach-dove/include/mach/memory.h | 10 --
arch/arm/mach-ebsa110/include/mach/debug-macro.S | 2 +-
arch/arm/mach-ep93xx/Kconfig | 53 --------
arch/arm/mach-ep93xx/Makefile.boot | 14 --
arch/arm/mach-ep93xx/include/mach/debug-macro.S | 2 +-
arch/arm/mach-ep93xx/include/mach/memory.h | 22 ----
arch/arm/mach-exynos4/include/mach/debug-macro.S | 2 +-
.../arm/mach-footbridge/include/mach/debug-macro.S | 4 +-
arch/arm/mach-gemini/include/mach/debug-macro.S | 2 +-
arch/arm/mach-gemini/include/mach/memory.h | 19 ---
arch/arm/mach-h720x/include/mach/debug-macro.S | 2 +-
arch/arm/mach-h720x/include/mach/memory.h | 11 --
.../arm/mach-integrator/include/mach/debug-macro.S | 2 +-
arch/arm/mach-iop13xx/include/mach/debug-macro.S | 2 +-
arch/arm/mach-iop32x/include/mach/debug-macro.S | 2 +-
arch/arm/mach-iop32x/include/mach/memory.h | 13 --
arch/arm/mach-iop33x/include/mach/debug-macro.S | 2 +-
arch/arm/mach-iop33x/include/mach/memory.h | 13 --
arch/arm/mach-ixp2000/include/mach/debug-macro.S | 2 +-
arch/arm/mach-ixp23xx/include/mach/debug-macro.S | 2 +-
arch/arm/mach-ixp4xx/include/mach/debug-macro.S | 2 +-
arch/arm/mach-ixp4xx/include/mach/memory.h | 17 ---
arch/arm/mach-kirkwood/include/mach/debug-macro.S | 2 +-
arch/arm/mach-kirkwood/include/mach/memory.h | 10 --
arch/arm/mach-ks8695/include/mach/debug-macro.S | 2 +-
arch/arm/mach-l7200/include/mach/debug-macro.S | 2 +-
arch/arm/mach-lpc32xx/include/mach/debug-macro.S | 2 +-
arch/arm/mach-lpc32xx/include/mach/memory.h | 27 ----
arch/arm/mach-mmp/include/mach/debug-macro.S | 2 +-
arch/arm/mach-mmp/include/mach/memory.h | 14 --
arch/arm/mach-msm/include/mach/debug-macro.S | 4 +-
arch/arm/mach-msm/include/mach/memory.h | 35 ------
arch/arm/mach-mv78xx0/include/mach/debug-macro.S | 2 +-
arch/arm/mach-mv78xx0/include/mach/memory.h | 10 --
arch/arm/mach-mxs/include/mach/debug-macro.S | 2 +-
arch/arm/mach-mxs/include/mach/memory.h | 24 ----
arch/arm/mach-netx/include/mach/debug-macro.S | 2 +-
arch/arm/mach-netx/include/mach/memory.h | 26 ----
arch/arm/mach-nomadik/include/mach/debug-macro.S | 2 +-
arch/arm/mach-nomadik/include/mach/memory.h | 28 ----
arch/arm/mach-nuc93x/include/mach/memory.h | 21 ---
arch/arm/mach-omap1/include/mach/debug-macro.S | 48 +++----
arch/arm/mach-omap1/include/mach/memory.h | 53 ++++++++-
arch/arm/mach-omap2/include/mach/debug-macro.S | 81 ++++++-------
arch/arm/mach-omap2/include/mach/memory.h | 5 -
arch/arm/mach-orion5x/include/mach/debug-macro.S | 2 +-
arch/arm/mach-orion5x/include/mach/memory.h | 12 --
arch/arm/mach-pnx4008/include/mach/debug-macro.S | 2 +-
arch/arm/mach-pnx4008/include/mach/memory.h | 21 ---
arch/arm/mach-prima2/include/mach/debug-macro.S | 2 +-
arch/arm/mach-prima2/include/mach/memory.h | 21 ---
arch/arm/mach-prima2/l2x0.c | 5 +-
arch/arm/mach-prima2/prima2.c | 1 +
arch/arm/mach-pxa/include/mach/debug-macro.S | 2 +-
arch/arm/mach-pxa/include/mach/memory.h | 20 ---
arch/arm/mach-pxa/z2.c | 2 +-
arch/arm/mach-realview/include/mach/debug-macro.S | 2 +-
arch/arm/mach-rpc/include/mach/debug-macro.S | 2 +-
arch/arm/mach-s3c2400/include/mach/memory.h | 20 ---
arch/arm/mach-s3c2410/include/mach/debug-macro.S | 2 +-
arch/arm/mach-s3c2410/include/mach/memory.h | 16 ---
arch/arm/mach-s3c64xx/include/mach/debug-macro.S | 2 +-
arch/arm/mach-s3c64xx/include/mach/memory.h | 18 ---
arch/arm/mach-s5p64x0/include/mach/debug-macro.S | 2 +-
arch/arm/mach-s5p64x0/include/mach/memory.h | 18 ---
arch/arm/mach-s5pc100/include/mach/debug-macro.S | 2 +-
arch/arm/mach-s5pc100/include/mach/memory.h | 18 ---
arch/arm/mach-s5pv210/include/mach/debug-macro.S | 2 +-
arch/arm/mach-sa1100/include/mach/debug-macro.S | 2 +-
arch/arm/mach-shark/include/mach/debug-macro.S | 2 +-
arch/arm/mach-spear3xx/include/mach/memory.h | 19 ---
arch/arm/mach-spear6xx/include/mach/memory.h | 19 ---
arch/arm/mach-tegra/include/mach/debug-macro.S | 2 +-
arch/arm/mach-tegra/include/mach/memory.h | 28 ----
arch/arm/mach-u300/include/mach/debug-macro.S | 2 +-
arch/arm/mach-ux500/include/mach/debug-macro.S | 2 +-
arch/arm/mach-ux500/include/mach/memory.h | 18 ---
arch/arm/mach-versatile/include/mach/debug-macro.S | 2 +-
arch/arm/mach-versatile/include/mach/memory.h | 28 ----
arch/arm/mach-vexpress/include/mach/debug-macro.S | 2 +-
arch/arm/mach-vexpress/include/mach/memory.h | 25 ----
arch/arm/mach-vt8500/include/mach/debug-macro.S | 2 +-
arch/arm/mach-vt8500/include/mach/memory.h | 28 ----
arch/arm/mach-w90x900/include/mach/memory.h | 23 ----
arch/arm/mach-zynq/include/mach/debug-macro.S | 2 +-
arch/arm/mach-zynq/include/mach/memory.h | 22 ----
arch/arm/plat-mxc/include/mach/debug-macro.S | 2 +-
arch/arm/plat-mxc/include/mach/memory.h | 43 -------
arch/arm/plat-omap/Kconfig | 1 +
arch/arm/plat-omap/include/plat/memory.h | 89 --------------
arch/arm/plat-omap/include/plat/serial.h | 6 +-
arch/arm/plat-omap/include/plat/uncompress.h | 8 +-
arch/arm/plat-spear/include/plat/debug-macro.S | 2 +-
arch/arm/plat-spear/include/plat/memory.h | 20 ---
arch/arm/plat-tcc/include/mach/debug-macro.S | 2 +-
arch/arm/plat-tcc/include/mach/memory.h | 18 ---
drivers/usb/musb/musb_debugfs.c | 6 -
115 files changed, 256 insertions(+), 1188 deletions(-)
^ permalink raw reply
* [PATCHv2 0/3] Initial support for Picochip picoxcell
From: Arnd Bergmann @ 2011-09-26 14:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110926092008.GC3372@pulham.picochip.com>
On Monday 26 September 2011, Jamie Iles wrote:
> Hi Arnd,
>
> Is there likely to be any chance of getting support for picoxcell
> merged? This series can now be based on top of Nicolas' static IO
> mapping patches to remove some more code but I'm not sure what else I
> can do to make them easier to review!
>
Hi Jamie,
I think you did everything right, but I haven't gotten to do a proper
review, which is entirely my fault.
Please send out the current version to the mailing list again and put me
on Cc, so it shows up in my inbox. In my extremely brief review
I found no show stoppers, so I'm sure we can find a way to get it into 3.2.
Do you have a git tree that I can pull?
Arnd
^ permalink raw reply
* [PATCH 3/4] iommu/exynos: Add iommu driver for Exynos4 Platforms
From: KyongHo Cho @ 2011-09-26 14:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAK=WgbaOwe8Q19tpZMeHdvyCj8fcV194zA-oSD20tF7j7_MvpQ@mail.gmail.com>
On Mon, Sep 26, 2011 at 6:36 PM, Ohad Ben-Cohen <ohad@wizery.com> wrote:
> It seems your default behavior just prints an error message with the
> details of the fault (addresses, flags, etc..). We can probably have
> this unified.
>
> In case you want to print exonys-specific info when the fault is not
> handled by upper layers, we can change report_iommu_fault() to return
> an error whenever a handler is not installed. This way
> exynos_sysmmu_irq() can easily tell whether to proceed with the
> default behavior or not, without installing a fault handler in the
> driver:
>
> diff --git a/include/linux/iommu.h b/include/linux/iommu.h
> index 297893f..dc4b282 100644
> --- a/include/linux/iommu.h
> +++ b/include/linux/iommu.h
> @@ -103,7 +103,7 @@ extern void iommu_set_fault_handler(struct iommu_domain *dom
> ?static inline int report_iommu_fault(struct iommu_domain *domain,
> ? ? ? ? ? ? ? ?struct device *dev, unsigned long iova, int flags)
> ?{
> - ? ? ? int ret = 0;
> + ? ? ? int ret = -EFAULT;
>
That looks better for me :)
However, I think the irq handler need to identify if the return value
is an error
returned by a fault handler or a notice that no fault handler is installed.
I am sorry but I still think that
installing default fault handler is quite simple and straightforward.
Providing generic default behavior for all architectures is also good
if it is available for other architectures.
My intention with the default behavior for unrecoverable fault from IOMMU is
to show what the problem is, where the problem caused and
thus, providing a hint to solve or catch the problem
for the device drivers and the developers.
>> BTW,
>> I think we need more fault type than IOMMU_FAULT_READ and IOMMU_FAULT_WRITE.
>> We have page fault, access fault(read, write), security fault
>> and bus error (translated physical address is not available)
>
> Initially we had a argument for the type of the fault, but dropped it
> because it was not used. Feel free to add it back if you need it.
>
OK. thanks.
> Thanks,
> Ohad.
Thank you.
Cho KyongHo.
^ permalink raw reply
* [RFC PATCH 2/3] ARM: mm: add l2x0 physical address parameter to init
From: Russell King - ARM Linux @ 2011-09-26 14:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1317047561-11020-3-git-send-email-lorenzo.pieralisi@arm.com>
On Mon, Sep 26, 2011 at 03:32:40PM +0100, Lorenzo Pieralisi wrote:
> This patch redefines the l2x0_init function, and it adds a
> parameter defining the L2 physical base address in preparation
> for L2 resume support. The device tree init code retrieves the
> physical address from the "reg" array and converts it to a
> physical address pointer.
I've no idea why many people have a really dire time understanding the
following basic fact. I keep seeing the same things: virtual addresses
as integers and physical addresses as pointers.
Virtual addresses are pointers.
Physical addresses are NOT pointers but integers.
Why? You CAN'T dereference a physical address when running in the virtual
address space (which is the space which the kernel runs in.)
Stop doing it.
^ permalink raw reply
* [RFC PATCH 3/3] ARM: mm: add l2x0 suspend/resume support
From: Russell King - ARM Linux @ 2011-09-26 14:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1317047561-11020-4-git-send-email-lorenzo.pieralisi@arm.com>
On Mon, Sep 26, 2011 at 03:32:41PM +0100, Lorenzo Pieralisi wrote:
> + __FINIT
> +/*
> + * Function entered with flags set by jump table in l2x0_resume
> + * If zero flag is set this is a pl310
> + * r0 = l2x0_data
> + * r1 = L2 address
> + */
> +resume_l210:
...
> + .data
> + .align
> +ENTRY(l2x0_resume)
...
> + b resume_l210
> +ENDPROC(l2x0_restore_context)
This is not a good idea - jumping from the data segment into the text
segment. We place initrds and initramfs images between the text and
data segments which can push the branch relocation out of range.
^ permalink raw reply
* [RFC PATCH 3/3] ARM: mm: add l2x0 suspend/resume support
From: Russell King - ARM Linux @ 2011-09-26 15:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1317047561-11020-4-git-send-email-lorenzo.pieralisi@arm.com>
On Mon, Sep 26, 2011 at 03:32:41PM +0100, Lorenzo Pieralisi wrote:
> Context is saved once for all at boot time, along with the L2 physical address
> and cache type.
Why is this assembly code? As Barry's previous patch shows, it's
entirely possible to save all the state required at init time from
the existing C code without needing any additional functions.
> The resume hook avoids using the stack since it might be called
> before the C environment is up and running and fetches data using
> program counter relative addressing so that it can be run both
> with MMU on or off to simplify its adoption.
What about parts where the security gets in the way of reinitializing
the L2 cache?
> +resume_l210:
> + ldr r2, [r0], #4 @ just use scratch regs
> + str r2, [r1, #L2X0_AUX_CTRL]
> + mov r3, #0
> + mov r12, #L2X0_LOCKDOWN_WAY_D_BASE
> + mov r2, r12
> + str r3, [r1, r2]
> + add r2, r2, #4
> + str r3, [r1, r2]
> + movne r0, #0x1 @ if l210 we are done
> + strne r0, [r1, #L2X0_CTRL] @ enable L2
> + movne pc, lr
It's not very obvious where the compare is for this conditional (which is
at the end of l2x0_resume in the .data section. Also, wouldn't a branch
to the enable at the end of this function be better and a more obvious
flow?
> +resume_l310:
> + add r12, r12, r1
> + add r12, r12, #L2X0_LOCKDOWN_STRIDE @ start D lock
> + mov r2, #0
> + mov r3, #7
> +unlock:
> + str r2, [r12, #4] @ I lock
> + str r2, [r12], #L2X0_LOCKDOWN_STRIDE @ D lock and increment
> + subs r3, r3, #1
> + bne unlock
Why not reverse r2 and r3 here? r3 was already set to zero previously.
And given what you're doing, this code could become:
mov r3, #0
add r12, r1, #L2X0_LOCKDOWN_WAY_D_BASE
str r3, [r12, #4] @ I lock
str r3, [r12], #L2X0_LOCKDOWN_STRIDE @ D lock and increment
bne enable_l2
resume_l310:
mov r2, #7
unlock:
str r3, [r12, #4] @ I lock
str r3, [r12], #L2X0_LOCKDOWN_STRIDE @ D lock and increment
subs r2, r2, #1
bne unlock
> + ldmia r0!, {r2, r3, r12}
> + str r2, [r1, #L2X0_TAG_LATENCY_CTRL]
> + str r3, [r1, #L2X0_DATA_LATENCY_CTRL]
> + str r12, [r1, #L2X0_ADDR_FILTER_START]
> + ldmia r0!, {r2, r3, r12}
> + str r2, [r1, #L2X0_ADDR_FILTER_END]
> + str r3, [r1, #L2X0_DEBUG_CTRL]
> + str r12, [r1, #L2X0_PREFETCH_CTRL]
> + ldr r2, [r0]
> + str r2, [r1, #L2X0_POWER_CTRL]
enable_l2:
> + mov r0, #0x1
> + str r0, [r1, #L2X0_CTRL] @ enable L2
> + mov pc, lr
^ permalink raw reply
* [RFC PATCH v3] drivercore: Add driver probe deferral mechanism
From: Russell King - ARM Linux @ 2011-09-26 15:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110926141643.GK2946@opensource.wolfsonmicro.com>
On Mon, Sep 26, 2011 at 03:16:43PM +0100, Mark Brown wrote:
> On Thu, Sep 22, 2011 at 12:51:23PM -0600, Grant Likely wrote:
> > Allow drivers to report at probe time that they cannot get all the resources
> > required by the device, and should be retried at a later time.
>
> > This should completely solve the problem of getting devices
> > initialized in the right order. Right now this is mostly handled by
> > mucking about with initcall ordering which is a complete hack, and
> > doesn't even remotely handle the case where device drivers are in
> > modules. This approach completely sidesteps the issues by allowing
> > driver registration to occur in any order, and any driver can request
> > to be retried after a few more other drivers get probed.
>
> So, one issue I did think of the other day while putting some support in
> the regulator core for using this: what happens with devices which can
> optionally use a resource but don't rely on it? One example here is
> that a lot of the MMC drivers have an optional regulator to control some
> of the supplies for the cards. If the reglator isn't there it won't be
> used but it's not a blocker for anything. Devices doing this would need
> some way to figure out if they should -EBUSY or fail otherwise.
Just to avoid confusion - ITYM -EAGAIN there. -EBUSY is already used
by drivers to mean "someone else claimed a resource I need" be it the
IO region or an IRQ resource...
^ permalink raw reply
* [PATCHv3 0/4] Initial support for Picochip picoXcell
From: Jamie Iles @ 2011-09-26 15:24 UTC (permalink / raw)
To: linux-arm-kernel
This is largely a repost of v2, but with a couple of minor changes:
- Removed bootargs from board dts files
- Fix up the VIC binding documentation
I've also added a 4th patch which removes the picoxcell specific ioremap
functionality. This could either be applied/folded into the first patch
if Nicolas' vmalloc cleanups go in.
These patches can also be found in a git tree at:
git://github.com/jamieiles/linux-2.6-ji.git for-next
Jamie Iles (4):
picoxcell: support for Picochip picoxcell devices
picoxcell: add the DTS for pc3x2 and pc3x3 devices
picoxcell: add the DTS for the PC7302 board
picoxcell: remove custom ioremap implementation
.../devicetree/bindings/arm/picoxcell.txt | 24 ++
arch/arm/Kconfig | 18 +
arch/arm/Makefile | 1 +
arch/arm/boot/dts/picoxcell-pc3x2.dtsi | 249 +++++++++++++
arch/arm/boot/dts/picoxcell-pc3x3.dtsi | 365 ++++++++++++++++++++
arch/arm/boot/dts/picoxcell-pc7302-pc3x2.dts | 86 +++++
arch/arm/boot/dts/picoxcell-pc7302-pc3x3.dts | 92 +++++
arch/arm/mach-picoxcell/Makefile | 3 +
arch/arm/mach-picoxcell/Makefile.boot | 1 +
arch/arm/mach-picoxcell/common.c | 55 +++
arch/arm/mach-picoxcell/common.h | 18 +
arch/arm/mach-picoxcell/include/mach/debug-macro.S | 35 ++
arch/arm/mach-picoxcell/include/mach/entry-macro.S | 19 +
arch/arm/mach-picoxcell/include/mach/gpio.h | 1 +
arch/arm/mach-picoxcell/include/mach/hardware.h | 21 ++
arch/arm/mach-picoxcell/include/mach/io.h | 22 ++
arch/arm/mach-picoxcell/include/mach/irqs.h | 25 ++
arch/arm/mach-picoxcell/include/mach/map.h | 25 ++
arch/arm/mach-picoxcell/include/mach/memory.h | 1 +
.../mach-picoxcell/include/mach/picoxcell_soc.h | 25 ++
arch/arm/mach-picoxcell/include/mach/system.h | 31 ++
arch/arm/mach-picoxcell/include/mach/timex.h | 25 ++
arch/arm/mach-picoxcell/include/mach/uncompress.h | 21 ++
arch/arm/mach-picoxcell/io.c | 32 ++
arch/arm/mach-picoxcell/time.c | 132 +++++++
25 files changed, 1327 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/picoxcell.txt
create mode 100644 arch/arm/boot/dts/picoxcell-pc3x2.dtsi
create mode 100644 arch/arm/boot/dts/picoxcell-pc3x3.dtsi
create mode 100644 arch/arm/boot/dts/picoxcell-pc7302-pc3x2.dts
create mode 100644 arch/arm/boot/dts/picoxcell-pc7302-pc3x3.dts
create mode 100644 arch/arm/mach-picoxcell/Makefile
create mode 100644 arch/arm/mach-picoxcell/Makefile.boot
create mode 100644 arch/arm/mach-picoxcell/common.c
create mode 100644 arch/arm/mach-picoxcell/common.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/debug-macro.S
create mode 100644 arch/arm/mach-picoxcell/include/mach/entry-macro.S
create mode 100644 arch/arm/mach-picoxcell/include/mach/gpio.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/hardware.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/io.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/irqs.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/map.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/memory.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/picoxcell_soc.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/system.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/timex.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/uncompress.h
create mode 100644 arch/arm/mach-picoxcell/io.c
create mode 100644 arch/arm/mach-picoxcell/time.c
--
1.7.4.1
^ permalink raw reply
* [PATCHv3 1/4] picoxcell: support for Picochip picoxcell devices
From: Jamie Iles @ 2011-09-26 15:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1317050689-16417-1-git-send-email-jamie@jamieiles.com>
picoXcell is a family of femtocell devices with an ARM application
processor and picoArray DSP processor array.
This patch adds support for picoXcell boards to be booted using the
device tree registering the VIC's, UART's and timers.
v3: - fixup vic compatible string in binding
v2: - cleanup empty mach headers
- convert to of_platform_populate()
- simplify uncompress.h
- split vic node into 2 devices
- add missing __initconst attributes
Signed-off-by: Jamie Iles <jamie@jamieiles.com>
---
.../devicetree/bindings/arm/picoxcell.txt | 24 ++++
arch/arm/Kconfig | 18 +++
arch/arm/Makefile | 1 +
arch/arm/mach-picoxcell/Makefile | 3 +
arch/arm/mach-picoxcell/Makefile.boot | 1 +
arch/arm/mach-picoxcell/common.c | 55 ++++++++
arch/arm/mach-picoxcell/common.h | 18 +++
arch/arm/mach-picoxcell/include/mach/debug-macro.S | 35 +++++
arch/arm/mach-picoxcell/include/mach/entry-macro.S | 19 +++
arch/arm/mach-picoxcell/include/mach/gpio.h | 1 +
arch/arm/mach-picoxcell/include/mach/hardware.h | 21 +++
arch/arm/mach-picoxcell/include/mach/io.h | 29 +++++
arch/arm/mach-picoxcell/include/mach/irqs.h | 25 ++++
arch/arm/mach-picoxcell/include/mach/map.h | 25 ++++
arch/arm/mach-picoxcell/include/mach/memory.h | 1 +
.../mach-picoxcell/include/mach/picoxcell_soc.h | 25 ++++
arch/arm/mach-picoxcell/include/mach/system.h | 31 +++++
arch/arm/mach-picoxcell/include/mach/timex.h | 25 ++++
arch/arm/mach-picoxcell/include/mach/uncompress.h | 21 +++
arch/arm/mach-picoxcell/include/mach/vmalloc.h | 18 +++
arch/arm/mach-picoxcell/io.c | 56 ++++++++
arch/arm/mach-picoxcell/time.c | 132 ++++++++++++++++++++
22 files changed, 584 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/picoxcell.txt
create mode 100644 arch/arm/mach-picoxcell/Makefile
create mode 100644 arch/arm/mach-picoxcell/Makefile.boot
create mode 100644 arch/arm/mach-picoxcell/common.c
create mode 100644 arch/arm/mach-picoxcell/common.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/debug-macro.S
create mode 100644 arch/arm/mach-picoxcell/include/mach/entry-macro.S
create mode 100644 arch/arm/mach-picoxcell/include/mach/gpio.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/hardware.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/io.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/irqs.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/map.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/memory.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/picoxcell_soc.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/system.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/timex.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/uncompress.h
create mode 100644 arch/arm/mach-picoxcell/include/mach/vmalloc.h
create mode 100644 arch/arm/mach-picoxcell/io.c
create mode 100644 arch/arm/mach-picoxcell/time.c
diff --git a/Documentation/devicetree/bindings/arm/picoxcell.txt b/Documentation/devicetree/bindings/arm/picoxcell.txt
new file mode 100644
index 0000000..e75c0ef
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/picoxcell.txt
@@ -0,0 +1,24 @@
+Picochip picoXcell device tree bindings.
+========================================
+
+Required root node properties:
+ - compatible:
+ - "picochip,pc7302-pc3x3" : PC7302 development board with PC3X3 device.
+ - "picochip,pc7302-pc3x2" : PC7302 development board with PC3X2 device.
+ - "picochip,pc3x3" : picoXcell PC3X3 device based board.
+ - "picochip,pc3x2" : picoXcell PC3X2 device based board.
+
+Timers required properties:
+ - compatible = "picochip,pc3x2-timer"
+ - interrupts : The single IRQ line for the timer.
+ - clock-freq : The frequency in HZ of the timer.
+ - reg : The register bank for the timer.
+
+Note: two timers are required - one for the scheduler clock and one for the
+event tick/NOHZ.
+
+VIC required properties:
+ - compatible = "arm,pl192-vic".
+ - interrupt-controller.
+ - reg : The register bank for the device.
+ - #interrupt-cells : Must be 1.
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5ebc5d9..15fab78 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -608,6 +608,24 @@ config ARCH_TEGRA
This enables support for NVIDIA Tegra based systems (Tegra APX,
Tegra 6xx and Tegra 2 series).
+config ARCH_PICOXCELL
+ bool "Picochip picoXcell"
+ select ARCH_REQUIRE_GPIOLIB
+ select ARM_PATCH_PHYS_VIRT
+ select ARM_VIC
+ select CPU_V6K
+ select DW_APB_TIMER
+ select GENERIC_CLOCKEVENTS
+ select GENERIC_GPIO
+ select HAVE_SCHED_CLOCK
+ select HAVE_TCM
+ select NO_IOPORT
+ select USE_OF
+ help
+ This enables support for systems based on the Picochip picoXcell
+ family of Femtocell devices. The picoxcell support requires device tree
+ for all boards.
+
config ARCH_PNX4008
bool "Philips Nexperia PNX4008 Mobile"
select CPU_ARM926T
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 70c424e..c941399 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -167,6 +167,7 @@ machine-$(CONFIG_ARCH_OMAP2) := omap2
machine-$(CONFIG_ARCH_OMAP3) := omap2
machine-$(CONFIG_ARCH_OMAP4) := omap2
machine-$(CONFIG_ARCH_ORION5X) := orion5x
+machine-$(CONFIG_ARCH_PICOXCELL) := picoxcell
machine-$(CONFIG_ARCH_PNX4008) := pnx4008
machine-$(CONFIG_ARCH_PRIMA2) := prima2
machine-$(CONFIG_ARCH_PXA) := pxa
diff --git a/arch/arm/mach-picoxcell/Makefile b/arch/arm/mach-picoxcell/Makefile
new file mode 100644
index 0000000..c550b63
--- /dev/null
+++ b/arch/arm/mach-picoxcell/Makefile
@@ -0,0 +1,3 @@
+obj-y := common.o
+obj-y += time.o
+obj-y += io.o
diff --git a/arch/arm/mach-picoxcell/Makefile.boot b/arch/arm/mach-picoxcell/Makefile.boot
new file mode 100644
index 0000000..b327175
--- /dev/null
+++ b/arch/arm/mach-picoxcell/Makefile.boot
@@ -0,0 +1 @@
+zreladdr-y := 0x00008000
diff --git a/arch/arm/mach-picoxcell/common.c b/arch/arm/mach-picoxcell/common.c
new file mode 100644
index 0000000..34d0834
--- /dev/null
+++ b/arch/arm/mach-picoxcell/common.c
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2011 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * All enquiries to support at picochip.com
+ */
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+
+#include <asm/mach/arch.h>
+#include <asm/hardware/vic.h>
+
+#include <mach/map.h>
+#include <mach/picoxcell_soc.h>
+
+#include "common.h"
+
+static void __init picoxcell_init_machine(void)
+{
+ of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+static const char *picoxcell_dt_match[] = {
+ "picochip,pc3x2",
+ "picochip,pc3x3",
+ NULL
+};
+
+static const struct of_device_id vic_of_match[] __initconst = {
+ { .compatible = "arm,pl192-vic" },
+ { /* Sentinel */ }
+};
+
+static void __init picoxcell_init_irq(void)
+{
+ vic_init(IO_ADDRESS(PICOXCELL_VIC0_BASE), 0, ~0, 0);
+ vic_init(IO_ADDRESS(PICOXCELL_VIC1_BASE), 32, ~0, 0);
+ irq_domain_generate_simple(vic_of_match, PICOXCELL_VIC0_BASE, 0);
+ irq_domain_generate_simple(vic_of_match, PICOXCELL_VIC1_BASE, 32);
+}
+
+DT_MACHINE_START(PICOXCELL, "Picochip picoXcell")
+ .map_io = picoxcell_map_io,
+ .nr_irqs = ARCH_NR_IRQS,
+ .init_irq = picoxcell_init_irq,
+ .timer = &picoxcell_timer,
+ .init_machine = picoxcell_init_machine,
+ .dt_compat = picoxcell_dt_match,
+MACHINE_END
diff --git a/arch/arm/mach-picoxcell/common.h b/arch/arm/mach-picoxcell/common.h
new file mode 100644
index 0000000..5263f0f
--- /dev/null
+++ b/arch/arm/mach-picoxcell/common.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2011 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * All enquiries to support at picochip.com
+ */
+#ifndef __PICOXCELL_COMMON_H__
+#define __PICOXCELL_COMMON_H__
+
+#include <asm/mach/time.h>
+
+extern struct sys_timer picoxcell_timer;
+extern void picoxcell_map_io(void);
+
+#endif /* __PICOXCELL_COMMON_H__ */
diff --git a/arch/arm/mach-picoxcell/include/mach/debug-macro.S b/arch/arm/mach-picoxcell/include/mach/debug-macro.S
new file mode 100644
index 0000000..8f2c234
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/debug-macro.S
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2011 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Derived from arch/arm/mach-davinci/include/mach/debug-macro.S to use 32-bit
+ * accesses to the 8250.
+ */
+#include <linux/serial_reg.h>
+#include <mach/hardware.h>
+#include <mach/map.h>
+
+#define UART_SHIFT 2
+
+ .macro addruart, rp, rv
+ ldr \rv, =PHYS_TO_IO(PICOXCELL_UART1_BASE)
+ ldr \rp, =PICOXCELL_UART1_BASE
+ .endm
+
+ .macro senduart,rd,rx
+ str \rd, [\rx, #UART_TX << UART_SHIFT]
+ .endm
+
+ .macro busyuart,rd,rx
+1002: ldr \rd, [\rx, #UART_LSR << UART_SHIFT]
+ and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
+ teq \rd, #UART_LSR_TEMT | UART_LSR_THRE
+ bne 1002b
+ .endm
+
+ /* The UART's don't have any flow control IO's wired up. */
+ .macro waituart,rd,rx
+ .endm
diff --git a/arch/arm/mach-picoxcell/include/mach/entry-macro.S b/arch/arm/mach-picoxcell/include/mach/entry-macro.S
new file mode 100644
index 0000000..a6b09f7
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/entry-macro.S
@@ -0,0 +1,19 @@
+/*
+ * entry-macro.S
+ *
+ * Copyright (c) 2011 Picochip Ltd., Jamie Iles
+ *
+ * Low-level IRQ helper macros for picoXcell platforms
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <mach/hardware.h>
+#include <mach/irqs.h>
+#include <mach/map.h>
+
+#define VA_VIC0 IO_ADDRESS(PICOXCELL_VIC0_BASE)
+#define VA_VIC1 IO_ADDRESS(PICOXCELL_VIC1_BASE)
+
+#include <asm/entry-macro-vic2.S>
diff --git a/arch/arm/mach-picoxcell/include/mach/gpio.h b/arch/arm/mach-picoxcell/include/mach/gpio.h
new file mode 100644
index 0000000..40a8c17
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/gpio.h
@@ -0,0 +1 @@
+/* empty */
diff --git a/arch/arm/mach-picoxcell/include/mach/hardware.h b/arch/arm/mach-picoxcell/include/mach/hardware.h
new file mode 100644
index 0000000..70ff581
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/hardware.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2011 Picochip Ltd., Jamie Iles
+ *
+ * This file contains the hardware definitions of the picoXcell SoC devices.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <mach/picoxcell_soc.h>
+
+#endif
diff --git a/arch/arm/mach-picoxcell/include/mach/io.h b/arch/arm/mach-picoxcell/include/mach/io.h
new file mode 100644
index 0000000..a863b0f
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/io.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2011 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+/* No ioports, but needed for driver compatibility. */
+#define __io(a) __typesafe_io(a)
+/* No PCI possible on picoxcell. */
+#define __mem_pci(a) (a)
+
+#define __arch_ioremap picoxcell_ioremap
+#define __arch_iounmap picoxcell_iounmap
+
+extern void __iomem *picoxcell_ioremap(unsigned long phys, size_t size,
+ unsigned int type);
+extern void picoxcell_iounmap(volatile void __iomem *addr);
+
+#endif /* __ASM_ARM_ARCH_IO_H */
diff --git a/arch/arm/mach-picoxcell/include/mach/irqs.h b/arch/arm/mach-picoxcell/include/mach/irqs.h
new file mode 100644
index 0000000..4d13ed9
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/irqs.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2011 Picochip Ltd., Jamie Iles
+ *
+ * This file contains the hardware definitions of the picoXcell SoC devices.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef __MACH_IRQS_H
+#define __MACH_IRQS_H
+
+#define ARCH_NR_IRQS 64
+#define NR_IRQS (128 + ARCH_NR_IRQS)
+
+#define IRQ_VIC0_BASE 0
+#define IRQ_VIC1_BASE 32
+
+#endif /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-picoxcell/include/mach/map.h b/arch/arm/mach-picoxcell/include/mach/map.h
new file mode 100644
index 0000000..c06afad
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/map.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2011 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef __PICOXCELL_MAP_H__
+#define __PICOXCELL_MAP_H__
+
+#define PHYS_TO_IO(x) (((x) & 0x00ffffff) | 0xfe000000)
+
+#ifdef __ASSEMBLY__
+#define IO_ADDRESS(x) PHYS_TO_IO((x))
+#else
+#define IO_ADDRESS(x) (void __iomem __force *)(PHYS_TO_IO((x)))
+#endif
+
+#endif /* __PICOXCELL_MAP_H__ */
diff --git a/arch/arm/mach-picoxcell/include/mach/memory.h b/arch/arm/mach-picoxcell/include/mach/memory.h
new file mode 100644
index 0000000..40a8c17
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/memory.h
@@ -0,0 +1 @@
+/* empty */
diff --git a/arch/arm/mach-picoxcell/include/mach/picoxcell_soc.h b/arch/arm/mach-picoxcell/include/mach/picoxcell_soc.h
new file mode 100644
index 0000000..5566fc8
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/picoxcell_soc.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2011 Picochip Ltd., Jamie Iles
+ *
+ * This file contains the hardware definitions of the picoXcell SoC devices.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef __PICOXCELL_SOC_H__
+#define __PICOXCELL_SOC_H__
+
+#define PICOXCELL_UART1_BASE 0x80230000
+#define PICOXCELL_PERIPH_BASE 0x80000000
+#define PICOXCELL_PERIPH_LENGTH SZ_4M
+#define PICOXCELL_VIC0_BASE 0x80060000
+#define PICOXCELL_VIC1_BASE 0x80064000
+
+#endif /* __PICOXCELL_SOC_H__ */
diff --git a/arch/arm/mach-picoxcell/include/mach/system.h b/arch/arm/mach-picoxcell/include/mach/system.h
new file mode 100644
index 0000000..67c589b
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/system.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2011 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+static inline void arch_idle(void)
+{
+ /*
+ * This should do all the clock switching and wait for interrupt
+ * tricks.
+ */
+ cpu_do_idle();
+}
+
+static inline void arch_reset(int mode, const char *cmd)
+{
+ /* Watchdog reset to go here. */
+}
+
+#endif /* __ASM_ARCH_SYSTEM_H */
diff --git a/arch/arm/mach-picoxcell/include/mach/timex.h b/arch/arm/mach-picoxcell/include/mach/timex.h
new file mode 100644
index 0000000..6c540a6
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/timex.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2011 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __TIMEX_H__
+#define __TIMEX_H__
+
+/* Bogus value to allow the kernel to compile. */
+#define CLOCK_TICK_RATE 1000000
+
+#endif /* __TIMEX_H__ */
+
diff --git a/arch/arm/mach-picoxcell/include/mach/uncompress.h b/arch/arm/mach-picoxcell/include/mach/uncompress.h
new file mode 100644
index 0000000..b60b19d
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/uncompress.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2011 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#define putc(c)
+#define flush()
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/arch/arm/mach-picoxcell/include/mach/vmalloc.h b/arch/arm/mach-picoxcell/include/mach/vmalloc.h
new file mode 100644
index 0000000..62559e3
--- /dev/null
+++ b/arch/arm/mach-picoxcell/include/mach/vmalloc.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2011 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#define VMALLOC_END 0xFE000000UL
diff --git a/arch/arm/mach-picoxcell/io.c b/arch/arm/mach-picoxcell/io.c
new file mode 100644
index 0000000..935a2fa
--- /dev/null
+++ b/arch/arm/mach-picoxcell/io.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2011 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * All enquiries to support at picochip.com
+ */
+#include <linux/io.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/of.h>
+
+#include <asm/mach/map.h>
+
+#include <mach/map.h>
+#include <mach/picoxcell_soc.h>
+
+#include "common.h"
+
+void __init picoxcell_map_io(void)
+{
+ struct map_desc io_map = {
+ .virtual = PHYS_TO_IO(PICOXCELL_PERIPH_BASE),
+ .pfn = __phys_to_pfn(PICOXCELL_PERIPH_BASE),
+ .length = PICOXCELL_PERIPH_LENGTH,
+ .type = MT_DEVICE,
+ };
+
+ iotable_init(&io_map, 1);
+}
+
+void __iomem *picoxcell_ioremap(unsigned long p, size_t size,
+ unsigned int type)
+{
+ if (unlikely(size == 0))
+ return NULL;
+
+ if (p >= PICOXCELL_PERIPH_BASE &&
+ p < PICOXCELL_PERIPH_BASE + PICOXCELL_PERIPH_LENGTH)
+ return IO_ADDRESS(p);
+
+ return __arm_ioremap_caller(p, size, type,
+ __builtin_return_address(0));
+}
+EXPORT_SYMBOL_GPL(picoxcell_ioremap);
+
+void picoxcell_iounmap(volatile void __iomem *addr)
+{
+ unsigned long virt = (unsigned long)addr;
+
+ if (virt >= VMALLOC_START && virt < VMALLOC_END)
+ __iounmap(addr);
+}
+EXPORT_SYMBOL_GPL(picoxcell_iounmap);
diff --git a/arch/arm/mach-picoxcell/time.c b/arch/arm/mach-picoxcell/time.c
new file mode 100644
index 0000000..90a554f
--- /dev/null
+++ b/arch/arm/mach-picoxcell/time.c
@@ -0,0 +1,132 @@
+/*
+ * Copyright (c) 2011 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * All enquiries to support@picochip.com
+ */
+#include <linux/dw_apb_timer.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/sched.h>
+
+#include <asm/mach/time.h>
+#include <asm/sched_clock.h>
+
+#include "common.h"
+
+static void timer_get_base_and_rate(struct device_node *np,
+ void __iomem **base, u32 *rate)
+{
+ *base = of_iomap(np, 0);
+
+ if (!*base)
+ panic("Unable to map regs for %s", np->name);
+
+ if (of_property_read_u32(np, "clock-freq", rate))
+ panic("No clock-freq property for %s", np->name);
+}
+
+static void picoxcell_add_clockevent(struct device_node *event_timer)
+{
+ void __iomem *iobase;
+ struct dw_apb_clock_event_device *ced;
+ u32 irq, rate;
+
+ irq = irq_of_parse_and_map(event_timer, 0);
+ if (irq == NO_IRQ)
+ panic("No IRQ for clock event timer");
+
+ timer_get_base_and_rate(event_timer, &iobase, &rate);
+
+ ced = dw_apb_clockevent_init(0, event_timer->name, 300, iobase, irq,
+ rate);
+ if (!ced)
+ panic("Unable to initialise clockevent device");
+
+ dw_apb_clockevent_register(ced);
+}
+
+static void picoxcell_add_clocksource(struct device_node *source_timer)
+{
+ void __iomem *iobase;
+ struct dw_apb_clocksource *cs;
+ u32 rate;
+
+ timer_get_base_and_rate(source_timer, &iobase, &rate);
+
+ cs = dw_apb_clocksource_init(300, source_timer->name, iobase, rate);
+ if (!cs)
+ panic("Unable to initialise clocksource device");
+
+ dw_apb_clocksource_start(cs);
+ dw_apb_clocksource_register(cs);
+}
+
+static DEFINE_CLOCK_DATA(cd);
+static void __iomem *sched_io_base;
+
+unsigned long long notrace sched_clock(void)
+{
+ cycle_t cyc = sched_io_base ? __raw_readl(sched_io_base) : 0;
+
+ return cyc_to_sched_clock(&cd, cyc, (u32)~0);
+}
+
+static void notrace picoxcell_update_sched_clock(void)
+{
+ cycle_t cyc = sched_io_base ? __raw_readl(sched_io_base) : 0;
+
+ update_sched_clock(&cd, cyc, (u32)~0);
+}
+
+static const struct of_device_id picoxcell_rtc_ids[] __initconst = {
+ { .compatible = "picochip,pc3x2-rtc" },
+ { /* Sentinel */ },
+};
+
+static void picoxcell_init_sched_clock(void)
+{
+ struct device_node *sched_timer;
+ u32 rate;
+
+ sched_timer = of_find_matching_node(NULL, picoxcell_rtc_ids);
+ if (!sched_timer)
+ panic("No RTC for sched clock to use");
+
+ timer_get_base_and_rate(sched_timer, &sched_io_base, &rate);
+ of_node_put(sched_timer);
+
+ init_sched_clock(&cd, picoxcell_update_sched_clock, 32, rate);
+}
+
+static const struct of_device_id picoxcell_timer_ids[] __initconst = {
+ { .compatible = "picochip,pc3x2-timer" },
+ {},
+};
+
+static void __init picoxcell_timer_init(void)
+{
+ struct device_node *event_timer, *source_timer;
+
+ event_timer = of_find_matching_node(NULL, picoxcell_timer_ids);
+ if (!event_timer)
+ panic("No timer for clockevent");
+ picoxcell_add_clockevent(event_timer);
+
+ source_timer = of_find_matching_node(event_timer, picoxcell_timer_ids);
+ if (!source_timer)
+ panic("No timer for clocksource");
+ picoxcell_add_clocksource(source_timer);
+
+ of_node_put(source_timer);
+
+ picoxcell_init_sched_clock();
+}
+
+struct sys_timer picoxcell_timer = {
+ .init = picoxcell_timer_init,
+};
--
1.7.4.1
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