* [PATCHv2 02/10] ARM: vic: MULTI_IRQ_HANDLER handler
From: Linus Walleij @ 2011-09-29 6:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110928203905.GB2838@ponder.secretlab.ca>
On Wed, Sep 28, 2011 at 10:39 PM, Grant Likely
<grant.likely@secretlab.ca> wrote:
> Why isn't it simply written this way:
>
> ? ? ? ?stat = readl_relaxed(vic->base + VIC_IRQ_STATUS);
> ? ? ? ?while (stat) {
> ? ? ? ? ? ? ? ?irq = fls(stat) - 1;
> ? ? ? ? ? ? ? ?handle_IRQ(irq_domain_to_irq(&vic->domain, irq), regs);
> ? ? ? ? ? ? ? ?stat &= ~(1 << irq);
> ? ? ? ?}
That is indeed closer to the assembly loop most platforms have
implemented.
Jamie can you test this approach? And also use ffs() insteadof
fls()...
Thanks,
Linus Walleij
^ permalink raw reply
* [PATCH] ARM: OMAP2+: dmtimer: Fix warning
From: Afzal Mohammed @ 2011-09-29 6:44 UTC (permalink / raw)
To: linux-arm-kernel
Fix,
arch/arm/mach-omap2/timer.c: In function 'omap_timer_init':
arch/arm/mach-omap2/timer.c:482: warning: assignment from incompatible pointer type
Signed-off-by: Afzal Mohammed <afzal@ti.com>
---
Fix on tony/master
arch/arm/mach-omap2/timer.c | 6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 1140e98..e49fc7b 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -434,7 +434,7 @@ static int __init omap_timer_init(struct omap_hwmod *oh, void *unused)
int ret = 0;
char *name = "omap_timer";
struct dmtimer_platform_data *pdata;
- struct omap_device *od;
+ struct platform_device *pdev;
struct omap_timer_capability_dev_attr *timer_dev_attr;
struct powerdomain *pwrdm;
@@ -476,12 +476,12 @@ static int __init omap_timer_init(struct omap_hwmod *oh, void *unused)
#ifdef CONFIG_PM
pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
#endif
- od = omap_device_build(name, id, oh, pdata, sizeof(*pdata),
+ pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata),
omap2_dmtimer_latency,
ARRAY_SIZE(omap2_dmtimer_latency),
0);
- if (IS_ERR(od)) {
+ if (IS_ERR(pdev)) {
pr_err("%s: Can't build omap_device for %s: %s.\n",
__func__, name, oh->name);
ret = -EINVAL;
--
1.6.2.4
^ permalink raw reply related
* [PATCH v2] ARM: cache-l2x0: add resume entry for l2 in secure mode
From: Barry Song @ 2011-09-29 5:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110929054938.GD19318@S2100-06.ap.freescale.net>
2011/9/29 Shawn Guo <shawn.guo@freescale.com>:
> On Thu, Sep 29, 2011 at 11:05:58AM +0530, Santosh Shilimkar wrote:
>> Barry,
>>
>> On Monday 26 September 2011 08:56 AM, Barry Song wrote:
>> > we save the l2x0 registers at the first initialization, and platform codes
>> > can get them to restore l2x0 status after wakeup.
>> >
>> > Cc: Shawn Guo <shawn.guo@linaro.org>
>> > Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
>> > Signed-off-by: Barry Song <Baohua.Song@csr.com>
>> > ---
>> > ?-v2:
>> > ?define the structure l2x0_regs to hold all saved registers;
>> > ?make saved copy of registers non-static so that platform codes can access them;
>> > ?add asm_offset for l2x0 saved regs(l2x0_regs struct) so that asm codes can use
>> >
>> > ?arch/arm/include/asm/hardware/cache-l2x0.h | ? 13 +++++
>> > ?arch/arm/include/asm/outercache.h ? ? ? ? ?| ? ?7 +++
>> > ?arch/arm/kernel/asm-offsets.c ? ? ? ? ? ? ?| ? ?9 +++
>> > ?arch/arm/mm/cache-l2x0.c ? ? ? ? ? ? ? ? ? | ? 81 ++++++++++++++++++++++++---
>> > ?4 files changed, 101 insertions(+), 9 deletions(-)
>> >
>> > diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
>> > index c48cb1e..4f9e81d 100644
>> > --- a/arch/arm/include/asm/hardware/cache-l2x0.h
>> > +++ b/arch/arm/include/asm/hardware/cache-l2x0.h
>> > @@ -96,6 +96,19 @@
>> > ?#ifndef __ASSEMBLY__
>> > ?extern void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask);
>> > ?extern int l2x0_of_init(__u32 aux_val, __u32 aux_mask);
>> > +
>> > +struct l2x0_regs {
>> > + ? unsigned long aux_ctrl;
>> > + ? /*
>> > + ? ?* Whether the following registers need to be saved/restored
>> > + ? ?* depends on platform
>> > + ? ?*/
>> > + ? unsigned long tag_latency;
>> > + ? unsigned long data_latency;
>> > + ? unsigned long filter_start;
>> > + ? unsigned long filter_end;
>> > +};
>> > +
>> You are missing POR register here which is available on
>> PL310 versions. You should add that.
>>
>> [...]
>> > ?static inline void outer_inv_range(phys_addr_t start, phys_addr_t end)
>> > diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c
>> > index 16baba2..b8d72a8 100644
>> > --- a/arch/arm/kernel/asm-offsets.c
>> > +++ b/arch/arm/kernel/asm-offsets.c
>> > @@ -20,6 +20,7 @@
>> > ?#include <asm/thread_info.h>
>> > ?#include <asm/memory.h>
>> > ?#include <asm/procinfo.h>
>> > +#include <asm/hardware/cache-l2x0.h>
>> > ?#include <linux/kbuild.h>
>> >
>> > ?/*
>> > @@ -92,6 +93,14 @@ int main(void)
>> > ? ?DEFINE(S_OLD_R0, ? ? ? ? offsetof(struct pt_regs, ARM_ORIG_r0));
>> > ? ?DEFINE(S_FRAME_SIZE, ? ? ? ? ? ? sizeof(struct pt_regs));
>> > ? ?BLANK();
>> > +#ifdef CONFIG_CACHE_L2X0
>> > + ?DEFINE(L2X0_R_AUX_CTRL, ?offsetof(struct l2x0_regs, aux_ctrl));
>> > + ?DEFINE(L2X0_R_TAG_LATENCY, ? ? ? offsetof(struct l2x0_regs, tag_latency));
>> > + ?DEFINE(L2X0_R_DATA_LATENCY, ? ? ?offsetof(struct l2x0_regs, data_latency));
>> > + ?DEFINE(L2X0_R_FILTER_START, ? ? ?offsetof(struct l2x0_regs, filter_start));
>> > + ?DEFINE(L2X0_R_FILTER_END, ? ? ? ?offsetof(struct l2x0_regs, filter_end));
>> Add POR as commented earlier.
>>
>> Rest of the patch looks good to me. I have ignored DT related
>> changes since I don't understand them.
>>
>> Shawn,
>> Have you tried this patch on IMX and see if you are
>> able to use it from the asm code?
>>
> Will give it a test today
well, thanks. once after you test and think it is ok, i'll send v3
with fixing the lost POR.
>
> --
> Regards,
> Shawn
-barry
^ permalink raw reply
* [PATCH v3 1/3] genirq: add support for per-cpu dev_id interrupts
From: Abhijeet Dharmapurikar @ 2011-09-29 5:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1316793788-14500-2-git-send-email-marc.zyngier@arm.com>
On 09/23/2011 09:03 AM, Marc Zyngier wrote:
> The ARM GIC interrupt controller offers per CPU interrupts (PPIs),
> which are usually used to connect local timers to each core.
> Each CPU has its own private interface to the GIC,
> and only sees the PPIs that are directly connect to it.
>
> While these timers are separate devices and have a separate
> interrupt line to a core, they all use the same IRQ number.
>
> For these devices, request_irq() is not the right API as it
> assumes that an IRQ number is visible by a number of CPUs
> (through the affinity setting), but makes it very awkward to
> express that an IRQ number can be handled by all CPUs, and
> yet be a different interrupt line on each CPU, requiring a
> different dev_id cookie to be passed back to the handler.
>
> The *_percpu_irq() functions is designed to overcome these
> limitations, by providing a per-cpu dev_id vector:
>
> int request_percpu_irq(unsigned int irq, irq_handler_t handler,
> const char *devname, void __percpu *percpu_dev_id);
> void free_percpu_irq(unsigned int, void __percpu *);
> int setup_percpu_irq(unsigned int irq, struct irqaction *new);
> void remove_percpu_irq(unsigned int irq, struct irqaction *act);
> void enable_percpu_irq(unsigned int irq);
As mentioned here
https://lkml.org/lkml/2011/9/25/121
can we add irqflags to enable_percpu_irq? This will make msm's
usage cleaner and it wont have to rely on accessing the gic
registers outside the driver.
---
Sent by an employee of the Qualcomm Innovation Center, Inc. The Qualcomm
Innovation Center, Inc. is a member of the Code Aurora Forum.
^ permalink raw reply
* [PATCH v2] ARM: cache-l2x0: add resume entry for l2 in secure mode
From: Shawn Guo @ 2011-09-29 5:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4E8403BE.9050302@ti.com>
On Thu, Sep 29, 2011 at 11:05:58AM +0530, Santosh Shilimkar wrote:
> Barry,
>
> On Monday 26 September 2011 08:56 AM, Barry Song wrote:
> > we save the l2x0 registers at the first initialization, and platform codes
> > can get them to restore l2x0 status after wakeup.
> >
> > Cc: Shawn Guo <shawn.guo@linaro.org>
> > Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> > Signed-off-by: Barry Song <Baohua.Song@csr.com>
> > ---
> > -v2:
> > define the structure l2x0_regs to hold all saved registers;
> > make saved copy of registers non-static so that platform codes can access them;
> > add asm_offset for l2x0 saved regs(l2x0_regs struct) so that asm codes can use
> >
> > arch/arm/include/asm/hardware/cache-l2x0.h | 13 +++++
> > arch/arm/include/asm/outercache.h | 7 +++
> > arch/arm/kernel/asm-offsets.c | 9 +++
> > arch/arm/mm/cache-l2x0.c | 81 ++++++++++++++++++++++++---
> > 4 files changed, 101 insertions(+), 9 deletions(-)
> >
> > diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
> > index c48cb1e..4f9e81d 100644
> > --- a/arch/arm/include/asm/hardware/cache-l2x0.h
> > +++ b/arch/arm/include/asm/hardware/cache-l2x0.h
> > @@ -96,6 +96,19 @@
> > #ifndef __ASSEMBLY__
> > extern void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask);
> > extern int l2x0_of_init(__u32 aux_val, __u32 aux_mask);
> > +
> > +struct l2x0_regs {
> > + unsigned long aux_ctrl;
> > + /*
> > + * Whether the following registers need to be saved/restored
> > + * depends on platform
> > + */
> > + unsigned long tag_latency;
> > + unsigned long data_latency;
> > + unsigned long filter_start;
> > + unsigned long filter_end;
> > +};
> > +
> You are missing POR register here which is available on
> PL310 versions. You should add that.
>
> [...]
> > static inline void outer_inv_range(phys_addr_t start, phys_addr_t end)
> > diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c
> > index 16baba2..b8d72a8 100644
> > --- a/arch/arm/kernel/asm-offsets.c
> > +++ b/arch/arm/kernel/asm-offsets.c
> > @@ -20,6 +20,7 @@
> > #include <asm/thread_info.h>
> > #include <asm/memory.h>
> > #include <asm/procinfo.h>
> > +#include <asm/hardware/cache-l2x0.h>
> > #include <linux/kbuild.h>
> >
> > /*
> > @@ -92,6 +93,14 @@ int main(void)
> > DEFINE(S_OLD_R0, offsetof(struct pt_regs, ARM_ORIG_r0));
> > DEFINE(S_FRAME_SIZE, sizeof(struct pt_regs));
> > BLANK();
> > +#ifdef CONFIG_CACHE_L2X0
> > + DEFINE(L2X0_R_AUX_CTRL, offsetof(struct l2x0_regs, aux_ctrl));
> > + DEFINE(L2X0_R_TAG_LATENCY, offsetof(struct l2x0_regs, tag_latency));
> > + DEFINE(L2X0_R_DATA_LATENCY, offsetof(struct l2x0_regs, data_latency));
> > + DEFINE(L2X0_R_FILTER_START, offsetof(struct l2x0_regs, filter_start));
> > + DEFINE(L2X0_R_FILTER_END, offsetof(struct l2x0_regs, filter_end));
> Add POR as commented earlier.
>
> Rest of the patch looks good to me. I have ignored DT related
> changes since I don't understand them.
>
> Shawn,
> Have you tried this patch on IMX and see if you are
> able to use it from the asm code?
>
Will give it a test today.
--
Regards,
Shawn
^ permalink raw reply
* [PATCH 2/2] msm: Support DEBUG_LL on MSM8660 and MSM8960
From: Stephen Boyd @ 2011-09-29 5:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.LFD.2.02.1109290012400.9106@xanadu.home>
On 9/28/2011 9:21 PM, Nicolas Pitre wrote:
> On Wed, 28 Sep 2011, Stephen Boyd wrote:
>
>
>> .macro senduart,rd,rx
>> +#ifdef CONFIG_MSM_HAS_DEBUG_UART_HS
>> + @ Clear TX_READY by writing to the UARTDM_CR register
>> + mov r12, #0x300
>> + str r12, [\rx, #0x10]
>> + @ Write 0x1 to NCF register
>> + mov r12, #0x1
>> + str r12, [\rx, #0x40]
>> + @ UARTDM reg. Read to induce delay
>> + ldr r12, [\rx, #0x08]
>> + @ Write the 1 character to UARTDM_TF
>> + str \rd, [\rx, #0x70]
> This is a really bad idea to pick a register (r12) when the calling code
> is completely unaware of that. This _will_ break on you someday.
>
> Except for the last line, why didn't you simply fold this code into the
> waituart macro instead?
We need to configure the uart to be ready for a write and it didn't seem
appropriate to put that in the waituart macro because it isn't actually
waiting for anything. I suppose putting it after the waiting is fine
though and avoids future breakage. Thanks.
--
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
^ permalink raw reply
* [RFC PATCH 3/3] ARM: mm: add l2x0 suspend/resume support
From: Santosh Shilimkar @ 2011-09-29 5:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110928192443.GB23944@n2100.arm.linux.org.uk>
On Thursday 29 September 2011 12:54 AM, Russell King - ARM Linux wrote:
> On Tue, Sep 27, 2011 at 04:27:32PM +0530, Santosh Shilimkar wrote:
>> I agree. From various discussion so far, apart MX, nobody complained
>> about C-version of the code. Hence the comment. If there are more
>> platforms which needs it, then the asm version would be useful and
>> should be preferred over C-version.
>
> Santosh,
>
> Can you also look at Barry Song's version of this infrastructure as
> well? He posted it a couple of days ago:
>
> Subject: [PATCH v2] ARM: cache-l2x0: add resume entry for l2 in secure mode
> Message-ID: <1317007569-31213-1-git-send-email-Baohua.Song@csr.com>
>
> with this diffstat:
>
> 4 files changed, 101 insertions(+), 9 deletions(-)
Just finished reviewing it. Apart from missing POR register,
rest of the patch looks fine and should address the asm code
need. I have just requested Shawn to try that out on IMX.
Regards
Santosh
^ permalink raw reply
* [PATCH v2] ARM: cache-l2x0: add resume entry for l2 in secure mode
From: Santosh Shilimkar @ 2011-09-29 5:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1317007569-31213-1-git-send-email-Baohua.Song@csr.com>
Barry,
On Monday 26 September 2011 08:56 AM, Barry Song wrote:
> we save the l2x0 registers at the first initialization, and platform codes
> can get them to restore l2x0 status after wakeup.
>
> Cc: Shawn Guo <shawn.guo@linaro.org>
> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Signed-off-by: Barry Song <Baohua.Song@csr.com>
> ---
> -v2:
> define the structure l2x0_regs to hold all saved registers;
> make saved copy of registers non-static so that platform codes can access them;
> add asm_offset for l2x0 saved regs(l2x0_regs struct) so that asm codes can use
>
> arch/arm/include/asm/hardware/cache-l2x0.h | 13 +++++
> arch/arm/include/asm/outercache.h | 7 +++
> arch/arm/kernel/asm-offsets.c | 9 +++
> arch/arm/mm/cache-l2x0.c | 81 ++++++++++++++++++++++++---
> 4 files changed, 101 insertions(+), 9 deletions(-)
>
> diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
> index c48cb1e..4f9e81d 100644
> --- a/arch/arm/include/asm/hardware/cache-l2x0.h
> +++ b/arch/arm/include/asm/hardware/cache-l2x0.h
> @@ -96,6 +96,19 @@
> #ifndef __ASSEMBLY__
> extern void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask);
> extern int l2x0_of_init(__u32 aux_val, __u32 aux_mask);
> +
> +struct l2x0_regs {
> + unsigned long aux_ctrl;
> + /*
> + * Whether the following registers need to be saved/restored
> + * depends on platform
> + */
> + unsigned long tag_latency;
> + unsigned long data_latency;
> + unsigned long filter_start;
> + unsigned long filter_end;
> +};
> +
You are missing POR register here which is available on
PL310 versions. You should add that.
[...]
> static inline void outer_inv_range(phys_addr_t start, phys_addr_t end)
> diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c
> index 16baba2..b8d72a8 100644
> --- a/arch/arm/kernel/asm-offsets.c
> +++ b/arch/arm/kernel/asm-offsets.c
> @@ -20,6 +20,7 @@
> #include <asm/thread_info.h>
> #include <asm/memory.h>
> #include <asm/procinfo.h>
> +#include <asm/hardware/cache-l2x0.h>
> #include <linux/kbuild.h>
>
> /*
> @@ -92,6 +93,14 @@ int main(void)
> DEFINE(S_OLD_R0, offsetof(struct pt_regs, ARM_ORIG_r0));
> DEFINE(S_FRAME_SIZE, sizeof(struct pt_regs));
> BLANK();
> +#ifdef CONFIG_CACHE_L2X0
> + DEFINE(L2X0_R_AUX_CTRL, offsetof(struct l2x0_regs, aux_ctrl));
> + DEFINE(L2X0_R_TAG_LATENCY, offsetof(struct l2x0_regs, tag_latency));
> + DEFINE(L2X0_R_DATA_LATENCY, offsetof(struct l2x0_regs, data_latency));
> + DEFINE(L2X0_R_FILTER_START, offsetof(struct l2x0_regs, filter_start));
> + DEFINE(L2X0_R_FILTER_END, offsetof(struct l2x0_regs, filter_end));
Add POR as commented earlier.
Rest of the patch looks good to me. I have ignored DT related
changes since I don't understand them.
Shawn,
Have you tried this patch on IMX and see if you are
able to use it from the asm code?
Regards
Santosh
^ permalink raw reply
* [PATCH 0/6] Support single zImage for imx3 and imx6
From: Shawn Guo @ 2011-09-29 5:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110928122049.GZ31404@pengutronix.de>
On Wed, Sep 28, 2011 at 02:20:49PM +0200, Sascha Hauer wrote:
> Hi Shawn,
>
> On Wed, Sep 28, 2011 at 05:16:02PM +0800, Shawn Guo wrote:
> > This series supports the single zImage build for imx3 and imx6. It's
> > based on linux-next with imx6 series applied, and tested on imx35 and
> > imx6q.
>
> I'm fine with this series (and the i.MX6 series). I can merge this
> series without the last patch now.
Thanks.
> For the i.MX6 series I think we have
> to wait until the prerequisites are merged. Maybe we should merge this
> in a second pull request during the merge window.
>
Ok, will send you the pull request at a later time.
--
Regards,
Shawn
^ permalink raw reply
* [PATCH 6/6] arm/imx: merge i.MX3 and i.MX6
From: Shawn Guo @ 2011-09-29 5:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110928121808.GY31404@pengutronix.de>
On Wed, Sep 28, 2011 at 02:18:08PM +0200, Sascha Hauer wrote:
> On Wed, Sep 28, 2011 at 05:16:08PM +0800, Shawn Guo wrote:
> >
> >
> > -config ARCH_MX3
> > - bool "MX3-based"
> > +config ARCH_IMX_V6_V7
> > + bool "i.MX3, i.MX6"
> > + select AUTO_ZRELADDR
> > + select ARM_PATCH_PHYS_VIRT
>
> Russell pointed out that it's not a good idea to select this.
>
Yeah, I saw that. So you would support ZBOOT_ROM over single zImage
between these two? I'm not sure how many imx users are actually using
ZBOOT_ROM. If there are only very few, we still want to keep the
default configuration compatible with ZBOOT_ROM? I think we can move
the default build to single zImage, and let those limited users sort
out their own configuration to get ZBOOT_ROM back. After all, the
support is still there, and it's just about build configuration
adjustment.
Anyway, it's only my opinion, and the decision is on you plate.
--
Regards,
Shawn
^ permalink raw reply
* [PATCH V2 1/1] dmaengine/amba-pl08x: Add support for s3c64xx DMAC
From: Viresh Kumar @ 2011-09-29 4:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAGOxZ535KHUp6An2br0scU9HvCmg4OsnfCj7hWYq4iy+OEpO2Q@mail.gmail.com>
On 9/28/2011 5:24 PM, Alim Akhtar wrote:
> I did Modified pl08x_cctl_bits(), but for some reason i reverted it back.
> what i was doing something like returning just __retbits__ instead of
> retbits |= tsize << PL080_CONTROL_TRANSFER_SIZE_SHIFT;
> and doing the below for the __non-s3c__ controllers in the
> pl08x_fill_lli_for_desc().
> cctl |= 1 << PL080_CONTROL_TRANSFER_SIZE_SHIFT;
> pl08x_fill_lli_for_desc(&bd, num_llis++, 1, cctl);
>
One way out would be:
Don't do retbits |= tsize << PL080_CONTROL_TRANSFER_SIZE_SHIFT in
pl08x_cctl_bits() and do this conditionally in pl08x_fill_lli_for_desc().
This needs adding tsize argument in fill_lli_**() routine and removing it
from cctl_bits().
Probably this is what you were mentioning.
--
viresh
^ permalink raw reply
* [PATCH 2/2] msm: Support DEBUG_LL on MSM8660 and MSM8960
From: Nicolas Pitre @ 2011-09-29 4:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1317243959-26383-3-git-send-email-sboyd@codeaurora.org>
On Wed, 28 Sep 2011, Stephen Boyd wrote:
> Add support for DEBUG_LL on the 8660 and 8960 development boards.
> While we're here, cleanup the uncompress.h code a bit.
>
> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
> ---
[...]
> .macro senduart,rd,rx
> +#ifdef CONFIG_MSM_HAS_DEBUG_UART_HS
> + @ Clear TX_READY by writing to the UARTDM_CR register
> + mov r12, #0x300
> + str r12, [\rx, #0x10]
> + @ Write 0x1 to NCF register
> + mov r12, #0x1
> + str r12, [\rx, #0x40]
> + @ UARTDM reg. Read to induce delay
> + ldr r12, [\rx, #0x08]
> + @ Write the 1 character to UARTDM_TF
> + str \rd, [\rx, #0x70]
This is a really bad idea to pick a register (r12) when the calling code
is completely unaware of that. This _will_ break on you someday.
Except for the last line, why didn't you simply fold this code into the
waituart macro instead?
Nicolas
^ permalink raw reply
* [PATCHv2 01/10] ARM: vic: device tree binding
From: Rob Herring @ 2011-09-29 4:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1317206507-18867-2-git-send-email-jamie@jamieiles.com>
On 09/28/2011 05:41 AM, Jamie Iles wrote:
> This adds a device tree binding for the VIC based on the of_irq_init()
> support. This adds an irqdomain to the vic and always registers all
> vics in the static vic array rather than for pm only to keep track of
> the irq domain. struct irq_data::hwirq is used where appropriate rather
> than runtime masking.
>
> v2: - use irq_domain_simple_ops
> - remove stub implementation of vic_of_init for !CONFIG_OF
> - Make VIC select IRQ_DOMAIN
>
> Cc: Rob Herring <robherring2@gmail.com>
> Cc: Grant Likely <grant.likely@secretlab.ca>
> Signed-off-by: Jamie Iles <jamie@jamieiles.com>
Looks good. One minor comment below, but otherwise:
Reviewed-by: Rob Herring <rob.herring@calxeda.com>
> ---
> Documentation/devicetree/bindings/arm/vic.txt | 29 +++++++
> arch/arm/common/Kconfig | 1 +
> arch/arm/common/vic.c | 106 ++++++++++++++++++-------
> arch/arm/include/asm/hardware/vic.h | 10 ++-
> 4 files changed, 117 insertions(+), 29 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/arm/vic.txt
>
> diff --git a/Documentation/devicetree/bindings/arm/vic.txt b/Documentation/devicetree/bindings/arm/vic.txt
> new file mode 100644
> index 0000000..266716b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/vic.txt
> @@ -0,0 +1,29 @@
> +* ARM Vectored Interrupt Controller
> +
> +One or more Vectored Interrupt Controllers (VIC's) can be connected in an ARM
> +system for interrupt routing. For multiple controllers they can either be
> +nested or have the outputs wire-OR'd together.
> +
> +Required properties:
> +
> +- compatible : should be one of
> + "arm,pl190-vic"
> + "arm,pl192-vic"
> +- interrupt-controller : Identifies the node as an interrupt controller
> +- #interrupt-cells : The number of cells to define the interrupts. Must be 1 as
> + the VIC has no configuration options for interrupt sources. The cell is a u32
> + and defines the interrupt number.
> +- reg : The register bank for the VIC.
> +
> +Optional properties:
> +
> +- interrupts : Interrupt source for parent controllers if the VIC is nested.
> +
> +Example:
> +
> + vic0: interrupt-controller at 60000 {
> + compatible = "arm,pl192-vic";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + reg = <0x60000 0x1000>;
> + };
> diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig
> index 4b71766..43e9d1a 100644
> --- a/arch/arm/common/Kconfig
> +++ b/arch/arm/common/Kconfig
> @@ -2,6 +2,7 @@ config ARM_GIC
> bool
>
> config ARM_VIC
> + select IRQ_DOMAIN
> bool
>
> config ARM_VIC_NR
> diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c
> index 7aa4262..3f9c8f2 100644
> --- a/arch/arm/common/vic.c
> +++ b/arch/arm/common/vic.c
> @@ -22,6 +22,10 @@
> #include <linux/init.h>
> #include <linux/list.h>
> #include <linux/io.h>
> +#include <linux/irqdomain.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>
> #include <linux/syscore_ops.h>
> #include <linux/device.h>
> #include <linux/amba/bus.h>
> @@ -29,7 +33,6 @@
> #include <asm/mach/irq.h>
> #include <asm/hardware/vic.h>
>
> -#ifdef CONFIG_PM
> /**
> * struct vic_device - VIC PM device
> * @irq: The IRQ number for the base of the VIC.
> @@ -40,6 +43,7 @@
> * @int_enable: Save for VIC_INT_ENABLE.
> * @soft_int: Save for VIC_INT_SOFT.
> * @protect: Save for VIC_PROTECT.
> + * @domain: The IRQ domain for the VIC.
> */
> struct vic_device {
> void __iomem *base;
> @@ -50,13 +54,13 @@ struct vic_device {
> u32 int_enable;
> u32 soft_int;
> u32 protect;
> + struct irq_domain domain;
> };
>
> /* we cannot allocate memory when VICs are initially registered */
> static struct vic_device vic_devices[CONFIG_ARM_VIC_NR];
>
> static int vic_id;
> -#endif /* CONFIG_PM */
>
> /**
> * vic_init2 - common initialisation code
> @@ -156,39 +160,50 @@ static int __init vic_pm_init(void)
> return 0;
> }
> late_initcall(vic_pm_init);
> +#endif /* CONFIG_PM */
>
> /**
> - * vic_pm_register - Register a VIC for later power management control
> + * vic_register() - Register a VIC.
> * @base: The base address of the VIC.
> * @irq: The base IRQ for the VIC.
> * @resume_sources: bitmask of interrupts allowed for resume sources.
> + * @node: The device tree node associated with the VIC.
> *
> * Register the VIC with the system device tree so that it can be notified
> * of suspend and resume requests and ensure that the correct actions are
> * taken to re-instate the settings on resume.
> + *
> + * This also configures the IRQ domain for the VIC.
> */
> -static void __init vic_pm_register(void __iomem *base, unsigned int irq, u32 resume_sources)
> +static void __init vic_register(void __iomem *base, unsigned int irq,
> + u32 resume_sources, struct device_node *node)
> {
> struct vic_device *v;
>
> - if (vic_id >= ARRAY_SIZE(vic_devices))
> + if (vic_id >= ARRAY_SIZE(vic_devices)) {
> printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__);
> - else {
> - v = &vic_devices[vic_id];
> - v->base = base;
> - v->resume_sources = resume_sources;
> - v->irq = irq;
> - vic_id++;
> + return;
> }
> +
> + v = &vic_devices[vic_id];
> + v->base = base;
> + v->resume_sources = resume_sources;
> + v->irq = irq;
> + vic_id++;
> +
> + v->domain.irq_base = irq;
> + v->domain.nr_irq = 32;
> +#ifdef CONFIG_OF_IRQ
> + v->domain.of_node = of_node_get(node);
> + v->domain.ops = &irq_domain_simple_ops;
> +#endif /* CONFIG_OF */
> + irq_domain_add(&v->domain);
> }
> -#else
> -static inline void vic_pm_register(void __iomem *base, unsigned int irq, u32 arg1) { }
> -#endif /* CONFIG_PM */
>
> static void vic_ack_irq(struct irq_data *d)
> {
> void __iomem *base = irq_data_get_irq_chip_data(d);
> - unsigned int irq = d->irq & 31;
> + unsigned int irq = d->hwirq;
> writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
> /* moreover, clear the soft-triggered, in case it was the reason */
> writel(1 << irq, base + VIC_INT_SOFT_CLEAR);
> @@ -197,14 +212,14 @@ static void vic_ack_irq(struct irq_data *d)
> static void vic_mask_irq(struct irq_data *d)
> {
> void __iomem *base = irq_data_get_irq_chip_data(d);
> - unsigned int irq = d->irq & 31;
> + unsigned int irq = d->hwirq;
> writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
> }
>
> static void vic_unmask_irq(struct irq_data *d)
> {
> void __iomem *base = irq_data_get_irq_chip_data(d);
> - unsigned int irq = d->irq & 31;
> + unsigned int irq = d->hwirq;
> writel(1 << irq, base + VIC_INT_ENABLE);
> }
>
> @@ -226,7 +241,7 @@ static struct vic_device *vic_from_irq(unsigned int irq)
> static int vic_set_wake(struct irq_data *d, unsigned int on)
> {
> struct vic_device *v = vic_from_irq(d->irq);
> - unsigned int off = d->irq & 31;
> + unsigned int off = d->hwirq;
> u32 bit = 1 << off;
>
> if (!v)
> @@ -331,15 +346,9 @@ static void __init vic_init_st(void __iomem *base, unsigned int irq_start,
> vic_set_irq_sources(base, irq_start, vic_sources);
> }
>
> -/**
> - * vic_init - initialise a vectored interrupt controller
> - * @base: iomem base address
> - * @irq_start: starting interrupt number, must be muliple of 32
> - * @vic_sources: bitmask of interrupt sources to allow
> - * @resume_sources: bitmask of interrupt sources to allow for resume
> - */
> -void __init vic_init(void __iomem *base, unsigned int irq_start,
> - u32 vic_sources, u32 resume_sources)
> +static void __init __vic_init(void __iomem *base, unsigned int irq_start,
> + u32 vic_sources, u32 resume_sources,
> + struct device_node *node)
> {
> unsigned int i;
> u32 cellid = 0;
> @@ -375,5 +384,46 @@ void __init vic_init(void __iomem *base, unsigned int irq_start,
>
> vic_set_irq_sources(base, irq_start, vic_sources);
>
> - vic_pm_register(base, irq_start, resume_sources);
> + vic_register(base, irq_start, resume_sources, node);
> +}
> +
> +/**
> + * vic_init() - initialise a vectored interrupt controller
> + * @base: iomem base address
> + * @irq_start: starting interrupt number, must be muliple of 32
> + * @vic_sources: bitmask of interrupt sources to allow
> + * @resume_sources: bitmask of interrupt sources to allow for resume
> + */
> +void __init vic_init(void __iomem *base, unsigned int irq_start,
> + u32 vic_sources, u32 resume_sources)
> +{
> + __vic_init(base, irq_start, vic_sources, resume_sources, NULL);
> +}
> +
> +#ifdef CONFIG_OF
> +int __init vic_of_init(struct device_node *node, struct device_node *parent)
> +{
> + void __iomem *regs;
> + int irq_base;
> +
> + if (WARN(parent, "non-root VICs are not supported"))
> + return -EINVAL;
> +
> + regs = of_iomap(node, 0);
> + if (WARN_ON(!regs))
> + return -EIO;
> +
> + irq_base = irq_alloc_descs(-1, 0, 32, numa_node_id());
> + if (WARN_ON(irq_base < 0))
> + goto out_unmap;
> +
> + __vic_init(regs, irq_base, ~0, ~0, node);
> +
> + return 0;
> +
> + out_unmap:
> + iounmap(regs);
> +
> + return -EIO;
> }
> +#endif /* CONFIG OF */
> diff --git a/arch/arm/include/asm/hardware/vic.h b/arch/arm/include/asm/hardware/vic.h
> index 5d72550..0135215 100644
> --- a/arch/arm/include/asm/hardware/vic.h
> +++ b/arch/arm/include/asm/hardware/vic.h
> @@ -41,7 +41,15 @@
> #define VIC_PL192_VECT_ADDR 0xF00
>
> #ifndef __ASSEMBLY__
> +#include <linux/compiler.h>
> +#include <linux/types.h>
> +
> +struct device_node;
> void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources, u32 resume_sources);
> -#endif
>
> +#ifdef CONFIG_OF
> +int vic_of_init(struct device_node *node, struct device_node *parent);
> +#endif /* CONFIG_OF */
You don't need an ifdef around this.
Rob
^ permalink raw reply
* [PATCH 2/2] ARM: gic: add OF based initialization
From: Rob Herring @ 2011-09-29 3:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1317268436-1613-1-git-send-email-robherring2@gmail.com>
From: Rob Herring <rob.herring@calxeda.com>
This adds ARM gic interrupt controller initialization using device tree
data.
The initialization function is intended to be called by of_irq_init
function like this:
const static struct of_device_id irq_match[] = {
{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
{}
};
static void __init init_irqs(void)
{
of_irq_init(irq_match);
}
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
---
Documentation/devicetree/bindings/arm/gic.txt | 55 +++++++++++++++++++++
arch/arm/common/gic.c | 64 +++++++++++++++++++++++++
arch/arm/include/asm/hardware/gic.h | 1 +
3 files changed, 120 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/gic.txt
diff --git a/Documentation/devicetree/bindings/arm/gic.txt b/Documentation/devicetree/bindings/arm/gic.txt
new file mode 100644
index 0000000..52916b4
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/gic.txt
@@ -0,0 +1,55 @@
+* ARM Generic Interrupt Controller
+
+ARM SMP cores are often associated with a GIC, providing per processor
+interrupts (PPI), shared processor interrupts (SPI) and software
+generated interrupts (SGI).
+
+Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
+Secondary GICs are cascaded into the upward interrupt controller and do not
+have PPIs or SGIs.
+
+Main node required properties:
+
+- compatible : should be one of:
+ "arm,cortex-a9-gic"
+ "arm,arm11mp-gic"
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode an
+ interrupt source. The type shall be a <u32> and the value shall be 3.
+
+ The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
+ interrupts.
+
+ The 2nd cell contains the interrupt number for the interrupt type.
+ SPI interrupts are in the range [0-987]. PPI interrupts are in the
+ range [0-15].
+
+ The 3rd cell is the flags, encoded as follows:
+ bits[3:0] trigger type and level flags.
+ 1 = low-to-high edge triggered
+ 2 = high-to-low edge triggered
+ 4 = active high level-sensitive
+ 8 = active low level-sensitive
+ bits[15:8] PPI interrupt cpu mask. Each bit corresponds to each of
+ the 8 possible cpus attached to the GIC. A bit set to '1' indicated
+ the interrupt is wired to that CPU. Only valid for PPI interrupts.
+
+- reg : Specifies base physical address(s) and size of the GIC registers. The
+ first region is the GIC distributor register base and size. The 2nd region is
+ the GIC cpu interface register base and size.
+
+Optional
+- interrupts : Interrupt source of the parent interrupt controller. Only
+ present on secondary GICs.
+
+Example:
+
+ intc: interrupt-controller at fff11000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <1>;
+ interrupt-controller;
+ reg = <0xfff11000 0x1000>,
+ <0xfff10100 0x100>;
+ };
+
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index fa59c99..505ced7 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -29,6 +29,9 @@
#include <linux/cpu_pm.h>
#include <linux/cpumask.h>
#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
#include <linux/irqdomain.h>
#include <asm/irq.h>
@@ -519,7 +522,36 @@ static void __init gic_pm_init(struct gic_chip_data *gic)
}
#endif
+#ifdef CONFIG_OF
+static int gic_irq_domain_dt_translate(struct irq_domain *d,
+ struct device_node *controller,
+ const u32 *intspec, unsigned int intsize,
+ unsigned long *out_hwirq, unsigned int *out_type)
+{
+ struct gic_chip_data *gic_data = d->priv;
+
+ if (d->of_node != controller)
+ return -EINVAL;
+ if (intsize < 3)
+ return -EINVAL;
+
+ *out_hwirq = intspec[1];
+ /*
+ * We've already skipped over SGIs, so PPIs need no translation.
+ * For SPIs, we need to skip over 16 PPIs on primary GICs.
+ */
+ if (!intspec[0] && (gic_data->irq_offset == 16))
+ *out_hwirq += 16;
+
+ *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
+ return 0;
+}
+#endif
+
const struct irq_domain_ops gic_irq_domain_ops = {
+#ifdef CONFIG_OF
+ .dt_translate = gic_irq_domain_dt_translate,
+#endif
};
void __init gic_init(unsigned int gic_nr, unsigned int irq_start,
@@ -607,3 +639,35 @@ void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
writel_relaxed(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT);
}
#endif
+
+#ifdef CONFIG_OF
+static int gic_cnt __initdata = 0;
+
+int __init gic_of_init(struct device_node *node, struct device_node *parent)
+{
+ void __iomem *cpu_base;
+ void __iomem *dist_base;
+ int irq;
+ struct irq_domain *domain = &gic_data[gic_cnt].domain;
+
+ if (WARN_ON(!node))
+ return -ENODEV;
+
+ dist_base = of_iomap(node, 0);
+ WARN(!dist_base, "unable to map gic dist registers\n");
+
+ cpu_base = of_iomap(node, 1);
+ WARN(!cpu_base, "unable to map gic cpu registers\n");
+
+ domain->of_node = of_node_get(node);
+
+ gic_init(gic_cnt, 16, dist_base, cpu_base);
+
+ if (parent) {
+ irq = irq_of_parse_and_map(node, 0);
+ gic_cascade_irq(gic_cnt, irq);
+ }
+ gic_cnt++;
+ return 0;
+}
+#endif
diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h
index 4893b10..a343c96 100644
--- a/arch/arm/include/asm/hardware/gic.h
+++ b/arch/arm/include/asm/hardware/gic.h
@@ -39,6 +39,7 @@ extern void __iomem *gic_cpu_base_addr;
extern struct irq_chip gic_arch_extn;
void gic_init(unsigned int, unsigned int, void __iomem *, void __iomem *);
+int gic_of_init(struct device_node *node, struct device_node *parent);
void gic_secondary_init(unsigned int);
void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);
--
1.7.5.4
^ permalink raw reply related
* [PATCH 1/2] ARM: gic: add irq_domain support
From: Rob Herring @ 2011-09-29 3:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1317268436-1613-1-git-send-email-robherring2@gmail.com>
From: Rob Herring <rob.herring@calxeda.com>
Convert the gic interrupt controller to use irq domains in preparation
for device-tree binding and MULTI_IRQ. This allows for translation between
GIC interrupt IDs and Linux irq numbers.
The meaning of irq_offset has changed. It now is just the number of skipped
GIC interrupt IDs for the controller. It will be 16 for primary GIC and 32
for secondary GICs.
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
---
arch/arm/common/Kconfig | 1 +
arch/arm/common/gic.c | 80 ++++++++++++++++++++--------------
arch/arm/include/asm/hardware/gic.h | 3 +
3 files changed, 51 insertions(+), 33 deletions(-)
diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig
index 4b71766..74df9ca 100644
--- a/arch/arm/common/Kconfig
+++ b/arch/arm/common/Kconfig
@@ -1,4 +1,5 @@
config ARM_GIC
+ select IRQ_DOMAIN
bool
config ARM_VIC
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index 8b5be72..fa59c99 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -29,6 +29,7 @@
#include <linux/cpu_pm.h>
#include <linux/cpumask.h>
#include <linux/io.h>
+#include <linux/irqdomain.h>
#include <asm/irq.h>
#include <asm/mach/irq.h>
@@ -73,7 +74,7 @@ static inline void __iomem *gic_cpu_base(struct irq_data *d)
static inline unsigned int gic_irq(struct irq_data *d)
{
struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
- return d->irq - gic_data->irq_offset;
+ return d->hwirq + gic_data->irq_offset;
}
/*
@@ -81,7 +82,7 @@ static inline unsigned int gic_irq(struct irq_data *d)
*/
static void gic_mask_irq(struct irq_data *d)
{
- u32 mask = 1 << (d->irq % 32);
+ u32 mask = 1 << (gic_irq(d) % 32);
spin_lock(&irq_controller_lock);
writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4);
@@ -92,7 +93,7 @@ static void gic_mask_irq(struct irq_data *d)
static void gic_unmask_irq(struct irq_data *d)
{
- u32 mask = 1 << (d->irq % 32);
+ u32 mask = 1 << (gic_irq(d) % 32);
spin_lock(&irq_controller_lock);
if (gic_arch_extn.irq_unmask)
@@ -173,7 +174,7 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
bool force)
{
void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3);
- unsigned int shift = (d->irq % 4) * 8;
+ unsigned int shift = (gic_irq(d) % 4) * 8;
unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask);
u32 val, mask, bit;
@@ -224,7 +225,7 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
if (gic_irq == 1023)
goto out;
- cascade_irq = gic_irq + chip_data->irq_offset;
+ cascade_irq = irq_domain_to_irq(&chip_data->domain, gic_irq);
if (unlikely(gic_irq < 32 || gic_irq > 1020 || cascade_irq >= NR_IRQS))
do_bad_IRQ(cascade_irq, desc);
else
@@ -256,10 +257,10 @@ void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
irq_set_chained_handler(irq, gic_handle_cascade_irq);
}
-static void __init gic_dist_init(struct gic_chip_data *gic,
- unsigned int irq_start)
+static void __init gic_dist_init(struct gic_chip_data *gic)
{
- unsigned int gic_irqs, irq_limit, i;
+ unsigned int gic_irqs = gic->gic_irqs;
+ unsigned int i;
u32 cpumask;
void __iomem *base = gic->dist_base;
u32 cpu = 0;
@@ -275,17 +276,6 @@ static void __init gic_dist_init(struct gic_chip_data *gic,
writel_relaxed(0, base + GIC_DIST_CTRL);
/*
- * Find out how many interrupts are supported.
- * The GIC only supports up to 1020 interrupt sources.
- */
- gic_irqs = readl_relaxed(base + GIC_DIST_CTR) & 0x1f;
- gic_irqs = (gic_irqs + 1) * 32;
- if (gic_irqs > 1020)
- gic_irqs = 1020;
-
- gic->gic_irqs = gic_irqs;
-
- /*
* Set all global interrupts to be level triggered, active low.
*/
for (i = 32; i < gic_irqs; i += 16)
@@ -311,19 +301,13 @@ static void __init gic_dist_init(struct gic_chip_data *gic,
writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
/*
- * Limit number of interrupts registered to the platform maximum
- */
- irq_limit = gic->irq_offset + gic_irqs;
- if (WARN_ON(irq_limit > NR_IRQS))
- irq_limit = NR_IRQS;
-
- /*
* Setup the Linux IRQ subsystem.
*/
- for (i = irq_start; i < irq_limit; i++) {
- irq_set_chip_and_handler(i, &gic_chip, handle_fasteoi_irq);
- irq_set_chip_data(i, gic);
- set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
+ for (i = 0; i < gic->domain.nr_irq; i++) {
+ int irq = irq_domain_to_irq(&gic->domain, i);
+ irq_set_chip_and_handler(irq, &gic_chip, handle_fasteoi_irq);
+ irq_set_chip_data(irq, gic);
+ set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
writel_relaxed(1, base + GIC_DIST_CTRL);
@@ -535,23 +519,53 @@ static void __init gic_pm_init(struct gic_chip_data *gic)
}
#endif
+const struct irq_domain_ops gic_irq_domain_ops = {
+};
+
void __init gic_init(unsigned int gic_nr, unsigned int irq_start,
void __iomem *dist_base, void __iomem *cpu_base)
{
struct gic_chip_data *gic;
+ struct irq_domain *domain;
+ int gic_irqs;
BUG_ON(gic_nr >= MAX_GIC_NR);
gic = &gic_data[gic_nr];
+ domain = &gic->domain;
gic->dist_base = dist_base;
gic->cpu_base = cpu_base;
- gic->irq_offset = (irq_start - 1) & ~31;
- if (gic_nr == 0)
+ /*
+ * For primary GICs, skip over SGIs.
+ * For secondary GICs, skip over PPIs, too.
+ */
+ if (gic_nr == 0) {
gic_cpu_base_addr = cpu_base;
+ gic->irq_offset = 16;
+ irq_start = (irq_start & ~31) + 16;
+ } else
+ gic->irq_offset = 32;
+
+ /*
+ * Find out how many interrupts are supported.
+ * The GIC only supports up to 1020 interrupt sources.
+ */
+ gic_irqs = readl_relaxed(dist_base + GIC_DIST_CTR) & 0x1f;
+ gic_irqs = (gic_irqs + 1) * 32;
+ if (gic_irqs > 1020)
+ gic_irqs = 1020;
+ gic->gic_irqs = gic_irqs;
+
+ domain->nr_irq = gic_irqs - gic->irq_offset;
+ domain->irq_base = irq_alloc_descs(-1, irq_start, domain->nr_irq,
+ numa_node_id());
+ domain->priv = gic;
+ domain->ops = &gic_irq_domain_ops;
+ irq_domain_add(domain);
gic_chip.flags |= gic_arch_extn.flags;
- gic_dist_init(gic, irq_start);
+ gic_dist_init(gic);
gic_cpu_init(gic);
gic_pm_init(gic);
}
diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h
index c562705..4893b10 100644
--- a/arch/arm/include/asm/hardware/gic.h
+++ b/arch/arm/include/asm/hardware/gic.h
@@ -33,6 +33,8 @@
#define GIC_DIST_SOFTINT 0xf00
#ifndef __ASSEMBLY__
+#include <linux/irqdomain.h>
+
extern void __iomem *gic_cpu_base_addr;
extern struct irq_chip gic_arch_extn;
@@ -53,6 +55,7 @@ struct gic_chip_data {
u32 __percpu *saved_ppi_enable;
u32 __percpu *saved_ppi_conf;
#endif
+ struct irq_domain domain;
unsigned int gic_irqs;
};
#endif
--
1.7.5.4
^ permalink raw reply related
* [PATCH 0/2] GIC OF bindings
From: Rob Herring @ 2011-09-29 3:53 UTC (permalink / raw)
To: linux-arm-kernel
From: Rob Herring <rob.herring@calxeda.com>
With recent patches for VIC device tree support and GIC MULTI_IRQ support,
it is evident that the irq domain support should be moved into the core GIC
code and not be dependent on the DT initialization. So I've split things up
into 2 patches separating irq_domain and device-tree code.
This should only change the internals of the GIC code. The binding is
unchanged from the previous version. Yeah!
The full series is available here. This includes Russell's devel-stable and
for-next branches and Nico's vmalloc branch.
git://git.jdl.com/software/linux-3.0.git gic
Rob
Rob Herring (2):
ARM: gic: add irq_domain support
ARM: gic: add OF based initialization
Documentation/devicetree/bindings/arm/gic.txt | 55 ++++++++++
arch/arm/common/Kconfig | 1 +
arch/arm/common/gic.c | 144 +++++++++++++++++++------
arch/arm/include/asm/hardware/gic.h | 4 +
4 files changed, 171 insertions(+), 33 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/gic.txt
--
1.7.5.4
^ permalink raw reply
* [PATCH v2 1/6] OMAP4: Add missing clock divider for OCP_ABE_ICLK
From: Paul Walmsley @ 2011-09-29 2:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1316195249-14914-1-git-send-email-jon-hunter@ti.com>
On Fri, 16 Sep 2011, Jon Hunter wrote:
> From: Jon Hunter <jon-hunter@ti.com>
>
> The parent clock of the OCP_ABE_ICLK is the AESS_FCLK and the
> parent clock of the AESS_FCLK is the ABE_FCLK...
>
> ABE_FCLK --> AESS_FCLK --> OCP_ABE_ICLK
>
> The AESS_FCLK and OCP_ABE_ICLK clocks both have dividers which
> determine their operational frequency. However, the dividers for
> the AESS_FCLK and OCP_ABE_ICLK are controlled via a single bit,
> which is the CM1_ABE_AESS_CLKCTRL[24] bit. When this bit is set to
> 0, the AESS_FCLK divider is 1 and the OCP_ABE_ICLK divider is 2.
> Similarly, when this bit is set to 1, the AESS_FCLK divider is 2
> and the OCP_ABE_ICLK is 1.
>
> The above relationship between the AESS_FCLK and OCP_ABE_ICLK
> dividers ensure that the OCP_ABE_ICLK clock is always half the
> frequency of the ABE_CLK...
>
> OCP_ABE_ICLK = ABE_FCLK/2
>
> The divider for the OCP_ABE_ICLK is currently missing so add a
> divider that will ensure the OCP_ABE_ICLK frequency is always half
> the ABE_FCLK frequency.
>
> Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Thanks, queued for 3.2.
- Paul
^ permalink raw reply
* [PATCHv2 2/2] ARM: debug: Move DEBUG_ICEDCC into the DEBUG_LL choice
From: Stephen Boyd @ 2011-09-29 2:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1316568208-4518-2-git-send-email-sboyd@codeaurora.org>
On 09/20/11 18:23, Stephen Boyd wrote:
> DEBUG_ICEDCC support is just another DEBUG_LL choice and
> selecting it along with other DEBUG_LL options doesn't make
> much sense. Put it into the DEBUG_LL choice to avoid confusion.
>
> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
> Acked-by: Will Deacon <will.deacon@arm.com>
> ---
>
Chatting with David Brown made me realize that this patch now forces
ICEDCC for anybody who selects DEBUG_LL and hasn't moved to adding a
Kconfig in the choice menu. I'm not sure if that actually matters since
it may be incentive to put your machine of choice into this menu.
Otherwise, we may want to drop this until a later point, or just leave
it out of the choice menu altogether.
--
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
^ permalink raw reply
* [PATCH] leds-class: change back LEDS_CLASS to tristate instead of bool
From: Bryan Wu @ 2011-09-29 2:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1317113432-7299-1-git-send-email-bryan.wu@canonical.com>
Hiya,
Any comments and need I do anything to improve this patch?
Thanks,
-Bryan
On Tue, Sep 27, 2011 at 4:50 PM, Bryan Wu <bryan.wu@canonical.com> wrote:
> LEDS_CLASS is required by leds and trigger drivers, but we can build it as
> module. ?So change this option back as tristate and treak the help message
> as well.
>
> LEDS_TRIGGERS depends on LEDS_CLASSS, which should be tristate. ?So set it
> as tristate too and update header files as well.
>
> Change those ifdefs to take care of module configuration.
>
> Signed-off-by: Bryan Wu <bryan.wu@canonical.com>
> ---
> ?arch/arm/mach-omap1/board-ams-delta.c | ? ?4 ++--
> ?drivers/leds/Kconfig ? ? ? ? ? ? ? ? ?| ? ?9 ++++++---
> ?drivers/leds/led-class.c ? ? ? ? ? ? ?| ? ?8 ++++----
> ?drivers/leds/leds.h ? ? ? ? ? ? ? ? ? | ? ?2 +-
> ?drivers/mmc/host/au1xmmc.c ? ? ? ? ? ?| ? ?6 +++---
> ?drivers/power/power_supply.h ? ? ? ? ?| ? ?2 +-
> ?include/linux/leds.h ? ? ? ? ? ? ? ? ?| ? ?7 ++++---
> ?include/linux/mmc/host.h ? ? ? ? ? ? ?| ? ?2 +-
> ?include/linux/power_supply.h ? ? ? ? ?| ? ?2 +-
> ?9 files changed, 23 insertions(+), 19 deletions(-)
>
> diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
> index b2572f7..fd28696 100644
> --- a/arch/arm/mach-omap1/board-ams-delta.c
> +++ b/arch/arm/mach-omap1/board-ams-delta.c
> @@ -241,7 +241,7 @@ static struct i2c_board_info ams_delta_camera_board_info[] = {
> ? ? ? ?},
> ?};
>
> -#ifdef CONFIG_LEDS_TRIGGERS
> +#if defined(CONFIG_LEDS_TRIGGERS) || defined(CONFIG_LEDS_TRIGGERS_MODULE)
> ?DEFINE_LED_TRIGGER(ams_delta_camera_led_trigger);
>
> ?static int ams_delta_camera_power(struct device *dev, int power)
> @@ -320,7 +320,7 @@ static void __init ams_delta_init(void)
>
> ? ? ? ?omap1_usb_init(&ams_delta_usb_config);
> ? ? ? ?omap1_set_camera_info(&ams_delta_camera_platform_data);
> -#ifdef CONFIG_LEDS_TRIGGERS
> +#if defined(CONFIG_LEDS_TRIGGERS) || defined(CONFIG_LEDS_TRIGGERS_MODULE)
> ? ? ? ?led_trigger_register_simple("ams_delta_camera",
> ? ? ? ? ? ? ? ? ? ? ? ?&ams_delta_camera_led_trigger);
> ?#endif
> diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig
> index ff203a4..c30233e 100644
> --- a/drivers/leds/Kconfig
> +++ b/drivers/leds/Kconfig
> @@ -17,10 +17,13 @@ menuconfig NEW_LEDS
> ?if NEW_LEDS
>
> ?config LEDS_CLASS
> - ? ? ? bool "LED Class Support"
> + ? ? ? tristate "LED Class Support"
> ? ? ? ?help
> ? ? ? ? ?This option enables the led sysfs class in /sys/class/leds. ?You'll
> - ? ? ? ? need this to do anything useful with LEDs. ?If unsure, say N.
> + ? ? ? ? need this to do anything useful with LEDs. ?If unsure, say M.
> +
> + ? ? ? ? Note: don't disable it as N, because plenty of led and trigger drivers
> + ? ? ? ? are using this option.
>
> ?comment "LED drivers"
>
> @@ -388,7 +391,7 @@ config LEDS_RENESAS_TPU
> ? ? ? ? ?Brightness control is supported but hardware blinking is not.
>
> ?config LEDS_TRIGGERS
> - ? ? ? bool "LED Trigger support"
> + ? ? ? tristate "LED Trigger support"
> ? ? ? ?depends on LEDS_CLASS
> ? ? ? ?help
> ? ? ? ? ?This option enables trigger support for the leds class.
> diff --git a/drivers/leds/led-class.c b/drivers/leds/led-class.c
> index dc3d3d8..1f54cb0 100644
> --- a/drivers/leds/led-class.c
> +++ b/drivers/leds/led-class.c
> @@ -75,7 +75,7 @@ static ssize_t led_max_brightness_show(struct device *dev,
> ?static struct device_attribute led_class_attrs[] = {
> ? ? ? ?__ATTR(brightness, 0644, led_brightness_show, led_brightness_store),
> ? ? ? ?__ATTR(max_brightness, 0444, led_max_brightness_show, NULL),
> -#ifdef CONFIG_LEDS_TRIGGERS
> +#if defined(CONFIG_LEDS_TRIGGERS) || defined(CONFIG_LEDS_TRIGGERS_MODULE)
> ? ? ? ?__ATTR(trigger, 0644, led_trigger_show, led_trigger_store),
> ?#endif
> ? ? ? ?__ATTR_NULL,
> @@ -209,7 +209,7 @@ int led_classdev_register(struct device *parent, struct led_classdev *led_cdev)
> ? ? ? ?if (IS_ERR(led_cdev->dev))
> ? ? ? ? ? ? ? ?return PTR_ERR(led_cdev->dev);
>
> -#ifdef CONFIG_LEDS_TRIGGERS
> +#if defined(CONFIG_LEDS_TRIGGERS) || defined(CONFIG_LEDS_TRIGGERS_MODULE)
> ? ? ? ?init_rwsem(&led_cdev->trigger_lock);
> ?#endif
> ? ? ? ?/* add to the list of leds */
> @@ -226,7 +226,7 @@ int led_classdev_register(struct device *parent, struct led_classdev *led_cdev)
> ? ? ? ?led_cdev->blink_timer.function = led_timer_function;
> ? ? ? ?led_cdev->blink_timer.data = (unsigned long)led_cdev;
>
> -#ifdef CONFIG_LEDS_TRIGGERS
> +#if defined(CONFIG_LEDS_TRIGGERS) || defined(CONFIG_LEDS_TRIGGERS_MODULE)
> ? ? ? ?led_trigger_set_default(led_cdev);
> ?#endif
>
> @@ -245,7 +245,7 @@ EXPORT_SYMBOL_GPL(led_classdev_register);
> ?*/
> ?void led_classdev_unregister(struct led_classdev *led_cdev)
> ?{
> -#ifdef CONFIG_LEDS_TRIGGERS
> +#if defined(CONFIG_LEDS_TRIGGERS) || defined(CONFIG_LEDS_TRIGGERS_MODULE)
> ? ? ? ?down_write(&led_cdev->trigger_lock);
> ? ? ? ?if (led_cdev->trigger)
> ? ? ? ? ? ? ? ?led_trigger_set(led_cdev, NULL);
> diff --git a/drivers/leds/leds.h b/drivers/leds/leds.h
> index e77c7f8..53b59b7 100644
> --- a/drivers/leds/leds.h
> +++ b/drivers/leds/leds.h
> @@ -35,7 +35,7 @@ static inline int led_get_brightness(struct led_classdev *led_cdev)
> ?extern struct rw_semaphore leds_list_lock;
> ?extern struct list_head leds_list;
>
> -#ifdef CONFIG_LEDS_TRIGGERS
> +#if defined(CONFIG_LEDS_TRIGGERS) || defined(CONFIG_LEDS_TRIGGERS_MODULE)
> ?void led_trigger_set_default(struct led_classdev *led_cdev);
> ?void led_trigger_set(struct led_classdev *led_cdev,
> ? ? ? ? ? ? ? ? ? ? ? ?struct led_trigger *trigger);
> diff --git a/drivers/mmc/host/au1xmmc.c b/drivers/mmc/host/au1xmmc.c
> index 56e7834..83f4913 100644
> --- a/drivers/mmc/host/au1xmmc.c
> +++ b/drivers/mmc/host/au1xmmc.c
> @@ -1043,7 +1043,7 @@ static int __devinit au1xmmc_probe(struct platform_device *pdev)
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? "using PIO\n");
> ? ? ? ?}
>
> -#ifdef CONFIG_LEDS_CLASS
> +#if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE)
> ? ? ? ?if (host->platdata && host->platdata->led) {
> ? ? ? ? ? ? ? ?struct led_classdev *led = host->platdata->led;
> ? ? ? ? ? ? ? ?led->name = mmc_hostname(mmc);
> @@ -1072,7 +1072,7 @@ static int __devinit au1xmmc_probe(struct platform_device *pdev)
> ? ? ? ?return 0; ? ? ? /* all ok */
>
> ?out6:
> -#ifdef CONFIG_LEDS_CLASS
> +#if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE)
> ? ? ? ?if (host->platdata && host->platdata->led)
> ? ? ? ? ? ? ? ?led_classdev_unregister(host->platdata->led);
> ?out5:
> @@ -1111,7 +1111,7 @@ static int __devexit au1xmmc_remove(struct platform_device *pdev)
> ? ? ? ?if (host) {
> ? ? ? ? ? ? ? ?mmc_remove_host(host->mmc);
>
> -#ifdef CONFIG_LEDS_CLASS
> +#if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE)
> ? ? ? ? ? ? ? ?if (host->platdata && host->platdata->led)
> ? ? ? ? ? ? ? ? ? ? ? ?led_classdev_unregister(host->platdata->led);
> ?#endif
> diff --git a/drivers/power/power_supply.h b/drivers/power/power_supply.h
> index 018de2b..efa9544 100644
> --- a/drivers/power/power_supply.h
> +++ b/drivers/power/power_supply.h
> @@ -22,7 +22,7 @@ static inline void power_supply_init_attrs(struct device_type *dev_type) {}
>
> ?#endif /* CONFIG_SYSFS */
>
> -#ifdef CONFIG_LEDS_TRIGGERS
> +#if defined(CONFIG_LEDS_TRIGGERS) || defined(CONFIG_LEDS_TRIGGERS_MODULE)
>
> ?extern void power_supply_update_leds(struct power_supply *psy);
> ?extern int power_supply_create_triggers(struct power_supply *psy);
> diff --git a/include/linux/leds.h b/include/linux/leds.h
> index 5884def..051bc7e 100644
> --- a/include/linux/leds.h
> +++ b/include/linux/leds.h
> @@ -66,7 +66,7 @@ struct led_classdev {
> ? ? ? ?struct timer_list ? ? ? ?blink_timer;
> ? ? ? ?int ? ? ? ? ? ? ? ? ? ? ?blink_brightness;
>
> -#ifdef CONFIG_LEDS_TRIGGERS
> +#if defined(CONFIG_LEDS_TRIGGERS) || defined(CONFIG_LEDS_TRIGGERS_MODULE)
> ? ? ? ?/* Protects the trigger data below */
> ? ? ? ?struct rw_semaphore ? ? ?trigger_lock;
>
> @@ -115,7 +115,7 @@ extern void led_brightness_set(struct led_classdev *led_cdev,
> ?/*
> ?* LED Triggers
> ?*/
> -#ifdef CONFIG_LEDS_TRIGGERS
> +#if defined(CONFIG_LEDS_TRIGGERS) || defined(CONFIG_LEDS_TRIGGERS_MODULE)
>
> ?#define TRIG_NAME_MAX 50
>
> @@ -161,7 +161,8 @@ extern void led_trigger_blink(struct led_trigger *trigger,
> ?#endif
>
> ?/* Trigger specific functions */
> -#ifdef CONFIG_LEDS_TRIGGER_IDE_DISK
> +#if defined(CONFIG_LEDS_TRIGGER_IDE_DISK) || \
> + ? ? ? defined(CONFIG_LEDS_TRIGGER_IDE_DISK_MODULE)
> ?extern void ledtrig_ide_activity(void);
> ?#else
> ?#define ledtrig_ide_activity() do {} while(0)
> diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
> index aed5bc7..adac344 100644
> --- a/include/linux/mmc/host.h
> +++ b/include/linux/mmc/host.h
> @@ -300,7 +300,7 @@ struct mmc_host {
>
> ? ? ? ?mmc_pm_flag_t ? ? ? ? ? pm_flags; ? ? ? /* requested pm features */
>
> -#ifdef CONFIG_LEDS_TRIGGERS
> +#if defined(CONFIG_LEDS_TRIGGERS) || defined(CONFIG_LEDS_TRIGGERS_MODULE)
> ? ? ? ?struct led_trigger ? ? ?*led; ? ? ? ? ? /* activity led */
> ?#endif
>
> diff --git a/include/linux/power_supply.h b/include/linux/power_supply.h
> index 204c18d..cb09fa0 100644
> --- a/include/linux/power_supply.h
> +++ b/include/linux/power_supply.h
> @@ -164,7 +164,7 @@ struct power_supply {
> ? ? ? ?struct device *dev;
> ? ? ? ?struct work_struct changed_work;
>
> -#ifdef CONFIG_LEDS_TRIGGERS
> +#if defined(CONFIG_LEDS_TRIGGERS) || defined(CONFIG_LEDS_TRIGGERS_MODULE)
> ? ? ? ?struct led_trigger *charging_full_trig;
> ? ? ? ?char *charging_full_trig_name;
> ? ? ? ?struct led_trigger *charging_trig;
> --
> 1.7.5
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at ?http://vger.kernel.org/majordomo-info.html
>
--
Bryan Wu <bryan.wu@canonical.com>
Kernel Developer ? ?+86.138-1617-6545 Mobile
Ubuntu Kernel Team
Canonical Ltd. ? ? ?www.canonical.com
Ubuntu - Linux for human beings | www.ubuntu.com
^ permalink raw reply
* [PATCH v3 3/3] ARM: OMAP: TI814X: Create board support and enable build for TI8148 EVM
From: Hemant Pedanekar @ 2011-09-29 1:09 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds minimal support and build configuration for TI8148 EVM. Also
adds support for low level debugging on UART1 console on the EVM.
Note that existing TI8168 EVM file (board-ti8168evm.c) is updated with machine
info for TI8148 EVM and renamed as board-ti81xxevm.c.
Signed-off-by: Hemant Pedanekar <hemantp@ti.com>
---
arch/arm/mach-omap2/Kconfig | 5 ++++
arch/arm/mach-omap2/Makefile | 3 +-
.../{board-ti8168evm.c => board-ti81xxevm.c} | 22 ++++++++++++++-----
arch/arm/plat-omap/include/plat/uncompress.h | 3 ++
4 files changed, 26 insertions(+), 7 deletions(-)
rename arch/arm/mach-omap2/{board-ti8168evm.c => board-ti81xxevm.c} (66%)
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index a3b9227..cc4f213 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -316,6 +316,11 @@ config MACH_TI8168EVM
depends on SOC_OMAPTI81XX
default y
+config MACH_TI8148EVM
+ bool "TI8148 Evaluation Module"
+ depends on SOC_OMAPTI81XX
+ default y
+
config MACH_OMAP_4430SDP
bool "OMAP 4430 SDP board"
default y
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 5ee4cd6..1dc2c6b 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -239,7 +239,8 @@ obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o \
obj-$(CONFIG_MACH_CRANEBOARD) += board-am3517crane.o
obj-$(CONFIG_MACH_SBC3530) += board-omap3stalker.o
-obj-$(CONFIG_MACH_TI8168EVM) += board-ti8168evm.o
+obj-$(CONFIG_MACH_TI8168EVM) += board-ti81xxevm.o
+obj-$(CONFIG_MACH_TI8148EVM) += board-ti81xxevm.o
# Platform specific device init code
diff --git a/arch/arm/mach-omap2/board-ti8168evm.c b/arch/arm/mach-omap2/board-ti81xxevm.c
similarity index 66%
rename from arch/arm/mach-omap2/board-ti8168evm.c
rename to arch/arm/mach-omap2/board-ti81xxevm.c
index 7935fc9..b858921 100644
--- a/arch/arm/mach-omap2/board-ti8168evm.c
+++ b/arch/arm/mach-omap2/board-ti81xxevm.c
@@ -1,5 +1,5 @@
/*
- * Code for TI8168 EVM.
+ * Code for TI8168/TI8148 EVM.
*
* Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
*
@@ -24,15 +24,15 @@
#include <plat/board.h>
#include <plat/common.h>
-static struct omap_board_config_kernel ti8168_evm_config[] __initdata = {
+static struct omap_board_config_kernel ti81xx_evm_config[] __initdata = {
};
-static void __init ti8168_evm_init(void)
+static void __init ti81xx_evm_init(void)
{
omap_serial_init();
omap_sdrc_init(NULL, NULL);
- omap_board_config = ti8168_evm_config;
- omap_board_config_size = ARRAY_SIZE(ti8168_evm_config);
+ omap_board_config = ti81xx_evm_config;
+ omap_board_config_size = ARRAY_SIZE(ti81xx_evm_config);
}
MACHINE_START(TI8168EVM, "ti8168evm")
@@ -42,5 +42,15 @@ MACHINE_START(TI8168EVM, "ti8168evm")
.init_early = ti81xx_init_early,
.init_irq = ti81xx_init_irq,
.timer = &omap3_timer,
- .init_machine = ti8168_evm_init,
+ .init_machine = ti81xx_evm_init,
+MACHINE_END
+
+MACHINE_START(TI8148EVM, "ti8148evm")
+ /* Maintainer: Texas Instruments */
+ .atag_offset = 0x100,
+ .map_io = ti81xx_map_io,
+ .init_early = ti81xx_init_early,
+ .init_irq = ti81xx_init_irq,
+ .timer = &omap3_timer,
+ .init_machine = ti81xx_evm_init,
MACHINE_END
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
index 40336ad..8d052e7 100644
--- a/arch/arm/plat-omap/include/plat/uncompress.h
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -175,6 +175,9 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
/* TI8168 base boards using UART3 */
DEBUG_LL_TI81XX(3, ti8168evm);
+ /* TI8148 base boards using UART1 */
+ DEBUG_LL_TI81XX(1, ti8148evm);
+
} while (0);
}
--
1.7.3.5
^ permalink raw reply related
* [PATCH v3 2/3] ARM: OMAP: TI814X: Add cpu type macros and detection support
From: Hemant Pedanekar @ 2011-09-29 1:09 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds cpu type, macros for identification of TI814X device.
Note that following update to common OMAP data structures is made:
cpu_mask and RATE_IN_XXX flags have crossed 8 bit hence struct
clksel_rate.flags, struct prcm_config.flags and cpu_mask are changed to u16 from
u8.
Signed-off-by: Hemant Pedanekar <hemantp@ti.com>
---
arch/arm/mach-omap2/clock.c | 2 +-
arch/arm/mach-omap2/clock.h | 2 +-
arch/arm/mach-omap2/clock3xxx_data.c | 3 +++
arch/arm/mach-omap2/id.c | 22 ++++++++++++++++++++++
arch/arm/mach-omap2/opp2xxx.h | 2 +-
arch/arm/plat-omap/include/plat/clkdev_omap.h | 1 +
arch/arm/plat-omap/include/plat/clock.h | 3 ++-
arch/arm/plat-omap/include/plat/cpu.h | 9 +++++++++
8 files changed, 40 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 1f3481f..f57ed5b 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -35,7 +35,7 @@
#include "cm-regbits-24xx.h"
#include "cm-regbits-34xx.h"
-u8 cpu_mask;
+u16 cpu_mask;
/*
* clkdm_control: if true, then when a clock is enabled in the
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 48ac568..687d3d3 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -130,7 +130,7 @@ void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
const char *core_ck_name,
const char *mpu_ck_name);
-extern u8 cpu_mask;
+extern u16 cpu_mask;
extern const struct clkops clkops_omap2_dflt_wait;
extern const struct clkops clkops_dummy;
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 74cc7ce..230ff88 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -3529,6 +3529,9 @@ int __init omap3xxx_clk_init(void)
} else if (cpu_is_ti816x()) {
cpu_mask = RATE_IN_TI816X;
cpu_clkflg = CK_TI816X;
+ } else if (cpu_is_ti814x()) {
+ cpu_mask = RATE_IN_TI814X;
+ cpu_clkflg = CK_TI814X;
} else if (cpu_is_omap34xx()) {
if (omap_rev() == OMAP3430_REV_ES1_0) {
cpu_mask = RATE_IN_3430ES1;
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index ab2f417..f07faa9 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -337,6 +337,26 @@ static void __init omap3_check_revision(const char **cpu_rev)
break;
}
break;
+ case 0xb8f2:
+ switch (rev) {
+ case 0:
+ /* FALLTHROUGH */
+ case 1:
+ omap_revision = TI8148_REV_ES1_0;
+ *cpu_rev = "1.0";
+ break;
+ case 2:
+ omap_revision = TI8148_REV_ES2_0;
+ *cpu_rev = "2.0";
+ break;
+ case 3:
+ /* FALLTHROUGH */
+ default:
+ omap_revision = TI8148_REV_ES2_1;
+ *cpu_rev = "2.1";
+ break;
+ }
+ break;
default:
/* Unknown default to latest silicon rev as default */
omap_revision = OMAP3630_REV_ES1_2;
@@ -429,6 +449,8 @@ static void __init omap3_cpuinfo(const char *cpu_rev)
cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
} else if (cpu_is_ti816x()) {
cpu_name = "TI816X";
+ } else if (cpu_is_ti814x()) {
+ cpu_name = "TI814X";
} else if (omap3_has_iva() && omap3_has_sgx()) {
/* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
cpu_name = "OMAP3430/3530";
diff --git a/arch/arm/mach-omap2/opp2xxx.h b/arch/arm/mach-omap2/opp2xxx.h
index 8affc66..8fae534 100644
--- a/arch/arm/mach-omap2/opp2xxx.h
+++ b/arch/arm/mach-omap2/opp2xxx.h
@@ -51,7 +51,7 @@ struct prcm_config {
unsigned long cm_clksel2_pll; /* dpllx1 or x2 out */
unsigned long cm_clksel_mdm; /* modem dividers 2430 only */
unsigned long base_sdrc_rfr; /* base refresh timing for a set */
- unsigned char flags;
+ unsigned short flags;
};
diff --git a/arch/arm/plat-omap/include/plat/clkdev_omap.h b/arch/arm/plat-omap/include/plat/clkdev_omap.h
index 387a963..3c50ec8 100644
--- a/arch/arm/plat-omap/include/plat/clkdev_omap.h
+++ b/arch/arm/plat-omap/include/plat/clkdev_omap.h
@@ -40,6 +40,7 @@ struct omap_clk {
#define CK_443X (1 << 11)
#define CK_TI816X (1 << 12)
#define CK_446X (1 << 13)
+#define CK_TI814X (1 << 14)
#define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS)
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index 197ca03..3c6e6f8 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -59,6 +59,7 @@ struct clkops {
#define RATE_IN_4430 (1 << 5)
#define RATE_IN_TI816X (1 << 6)
#define RATE_IN_4460 (1 << 7)
+#define RATE_IN_TI814X (1 << 8)
#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
#define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
@@ -84,7 +85,7 @@ struct clkops {
struct clksel_rate {
u32 val;
u8 div;
- u8 flags;
+ u16 flags;
};
/**
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index 2c3fbce..35f9d43 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -117,6 +117,7 @@ IS_OMAP_SUBCLASS(443x, 0x443)
IS_OMAP_SUBCLASS(446x, 0x446)
IS_TI_SUBCLASS(816x, 0x816)
+IS_TI_SUBCLASS(814x, 0x814)
#define cpu_is_omap7xx() 0
#define cpu_is_omap15xx() 0
@@ -128,6 +129,7 @@ IS_TI_SUBCLASS(816x, 0x816)
#define cpu_is_omap343x() 0
#define cpu_is_ti81xx() 0
#define cpu_is_ti816x() 0
+#define cpu_is_ti814x() 0
#define cpu_is_omap44xx() 0
#define cpu_is_omap443x() 0
#define cpu_is_omap446x() 0
@@ -335,6 +337,7 @@ IS_OMAP_TYPE(3517, 0x3517)
# undef cpu_is_omap3517
# undef cpu_is_ti81xx
# undef cpu_is_ti816x
+# undef cpu_is_ti814x
# define cpu_is_omap3430() is_omap3430()
# define cpu_is_omap3503() (cpu_is_omap3430() && \
(!omap3_has_iva()) && \
@@ -353,6 +356,7 @@ IS_OMAP_TYPE(3517, 0x3517)
# define cpu_is_omap3630() is_omap363x()
# define cpu_is_ti81xx() is_ti81xx()
# define cpu_is_ti816x() is_ti816x()
+# define cpu_is_ti814x() is_ti814x()
#endif
# if defined(CONFIG_ARCH_OMAP4)
@@ -399,6 +403,11 @@ IS_OMAP_TYPE(3517, 0x3517)
#define TI8168_REV_ES1_0 TI816X_CLASS
#define TI8168_REV_ES1_1 (TI816X_CLASS | (0x1 << 8))
+#define TI814X_CLASS 0x81400034
+#define TI8148_REV_ES1_0 TI814X_CLASS
+#define TI8148_REV_ES2_0 (TI814X_CLASS | (0x1 << 8))
+#define TI8148_REV_ES2_1 (TI814X_CLASS | (0x2 << 8))
+
#define OMAP443X_CLASS 0x44300044
#define OMAP4430_REV_ES1_0 (OMAP443X_CLASS | (0x10 << 8))
#define OMAP4430_REV_ES2_0 (OMAP443X_CLASS | (0x20 << 8))
--
1.7.3.5
^ permalink raw reply related
* [PATCH v3 1/3] ARM: OMAP: TI81XX: Prepare for addition of TI814X support
From: Hemant Pedanekar @ 2011-09-29 1:09 UTC (permalink / raw)
To: linux-arm-kernel
This patch updates existing macros, functions used for TI816X, to enable
addition of other SoCs belonging to TI81XX family (e.g., TI814X).
The approach taken is to use TI81XX/ti81xx for code/data going to be common
across all TI81XX devices.
cpu_is_ti81xx() is introduced to handle code common across TI81XX devices.
In addition, ti8168_evm_map_io() is now replaced with ti81xx_map_io() and moved
in mach-omap2/common.c as same will be used for TI814X and is not board
specific.
Signed-off-by: Hemant Pedanekar <hemantp@ti.com>
---
arch/arm/mach-omap2/Kconfig | 6 ++--
arch/arm/mach-omap2/board-ti8168evm.c | 12 ++------
arch/arm/mach-omap2/clock3xxx_data.c | 2 +-
arch/arm/mach-omap2/common.c | 28 ++++++++++++--------
arch/arm/mach-omap2/control.h | 8 +++---
arch/arm/mach-omap2/id.c | 8 +++---
arch/arm/mach-omap2/include/mach/debug-macro.S | 12 ++++----
arch/arm/mach-omap2/include/mach/entry-macro.S | 4 +-
arch/arm/mach-omap2/io.c | 12 ++++----
arch/arm/mach-omap2/irq.c | 2 +-
arch/arm/mach-omap2/serial.c | 6 ++--
arch/arm/plat-omap/include/plat/common.h | 5 ++-
arch/arm/plat-omap/include/plat/cpu.h | 13 +++++++++
arch/arm/plat-omap/include/plat/hardware.h | 2 +-
arch/arm/plat-omap/include/plat/io.h | 6 ++--
arch/arm/plat-omap/include/plat/irqs.h | 2 +-
arch/arm/plat-omap/include/plat/serial.h | 14 +++++-----
.../plat-omap/include/plat/{ti816x.h => ti81xx.h} | 18 ++++++------
arch/arm/plat-omap/include/plat/uncompress.h | 8 +++---
arch/arm/plat-omap/io.c | 2 +-
20 files changed, 92 insertions(+), 78 deletions(-)
rename arch/arm/plat-omap/include/plat/{ti816x.h => ti81xx.h} (60%)
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 7edf802..a3b9227 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -73,8 +73,8 @@ config SOC_OMAP3430
default y
select ARCH_OMAP_OTG
-config SOC_OMAPTI816X
- bool "TI816X support"
+config SOC_OMAPTI81XX
+ bool "TI81XX support"
depends on ARCH_OMAP3
default y
@@ -313,7 +313,7 @@ config MACH_OMAP_3630SDP
config MACH_TI8168EVM
bool "TI8168 Evaluation Module"
- depends on SOC_OMAPTI816X
+ depends on SOC_OMAPTI81XX
default y
config MACH_OMAP_4430SDP
diff --git a/arch/arm/mach-omap2/board-ti8168evm.c b/arch/arm/mach-omap2/board-ti8168evm.c
index e26c79c..7935fc9 100644
--- a/arch/arm/mach-omap2/board-ti8168evm.c
+++ b/arch/arm/mach-omap2/board-ti8168evm.c
@@ -35,18 +35,12 @@ static void __init ti8168_evm_init(void)
omap_board_config_size = ARRAY_SIZE(ti8168_evm_config);
}
-static void __init ti8168_evm_map_io(void)
-{
- omap2_set_globals_ti816x();
- omapti816x_map_common_io();
-}
-
MACHINE_START(TI8168EVM, "ti8168evm")
/* Maintainer: Texas Instruments */
.atag_offset = 0x100,
- .map_io = ti8168_evm_map_io,
- .init_early = ti816x_init_early,
- .init_irq = ti816x_init_irq,
+ .map_io = ti81xx_map_io,
+ .init_early = ti81xx_init_early,
+ .init_irq = ti81xx_init_irq,
.timer = &omap3_timer,
.init_machine = ti8168_evm_init,
MACHINE_END
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 65dd363..74cc7ce 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -3612,7 +3612,7 @@ int __init omap3xxx_clk_init(void)
* Lock DPLL5 -- here only until other device init code can
* handle this
*/
- if (!cpu_is_ti816x() && (omap_rev() >= OMAP3430_REV_ES2_0))
+ if (!cpu_is_ti81xx() && (omap_rev() >= OMAP3430_REV_ES2_0))
omap3_clk_lock_dpll5();
/* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c
index 3f20cbb..2ce8e2b 100644
--- a/arch/arm/mach-omap2/common.c
+++ b/arch/arm/mach-omap2/common.c
@@ -101,23 +101,29 @@ void __init omap3_map_io(void)
/*
* Adjust TAP register base such that omap3_check_revision accesses the correct
- * TI816X register for checking device ID (it adds 0x204 to tap base while
- * TI816X DEVICE ID register is at offset 0x600 from control base).
+ * TI81XX register for checking device ID (it adds 0x204 to tap base while
+ * TI81XX DEVICE ID register is at offset 0x600 from control base).
*/
-#define TI816X_TAP_BASE (TI816X_CTRL_BASE + \
- TI816X_CONTROL_DEVICE_ID - 0x204)
+#define TI81XX_TAP_BASE (TI81XX_CTRL_BASE + \
+ TI81XX_CONTROL_DEVICE_ID - 0x204)
-static struct omap_globals ti816x_globals = {
+static struct omap_globals ti81xx_globals = {
.class = OMAP343X_CLASS,
- .tap = OMAP2_L4_IO_ADDRESS(TI816X_TAP_BASE),
- .ctrl = TI816X_CTRL_BASE,
- .prm = TI816X_PRCM_BASE,
- .cm = TI816X_PRCM_BASE,
+ .tap = OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE),
+ .ctrl = TI81XX_CTRL_BASE,
+ .prm = TI81XX_PRCM_BASE,
+ .cm = TI81XX_PRCM_BASE,
};
-void __init omap2_set_globals_ti816x(void)
+void __init omap2_set_globals_ti81xx(void)
{
- __omap2_set_globals(&ti816x_globals);
+ __omap2_set_globals(&ti81xx_globals);
+}
+
+void __init ti81xx_map_io(void)
+{
+ omap2_set_globals_ti81xx();
+ omapti81xx_map_common_io();
}
#endif
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index d4ef75d..0ba68d3 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -52,8 +52,8 @@
#define OMAP343X_CONTROL_PADCONFS_WKUP 0xa00
#define OMAP343X_CONTROL_GENERAL_WKUP 0xa60
-/* TI816X spefic control submodules */
-#define TI816X_CONTROL_DEVCONF 0x600
+/* TI81XX spefic control submodules */
+#define TI81XX_CONTROL_DEVCONF 0x600
/* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */
@@ -244,8 +244,8 @@
#define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250
#define OMAP3_PADCONF_SAD2D_IDLEACK 0x254
-/* TI816X CONTROL_DEVCONF register offsets */
-#define TI816X_CONTROL_DEVICE_ID (TI816X_CONTROL_DEVCONF + 0x000)
+/* TI81XX CONTROL_DEVCONF register offsets */
+#define TI81XX_CONTROL_DEVICE_ID (TI81XX_CONTROL_DEVCONF + 0x000)
/*
* REVISIT: This list of registers is not comprehensive - there are more
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index d27daf9..ab2f417 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -223,7 +223,7 @@ static void __init omap4_check_features(void)
}
}
-static void __init ti816x_check_features(void)
+static void __init ti81xx_check_features(void)
{
omap_features = OMAP3_HAS_NEON;
}
@@ -469,11 +469,11 @@ void __init omap2_check_revision(void)
} else if (cpu_is_omap34xx()) {
omap3_check_revision(&cpu_rev);
- /* TI816X doesn't have feature register */
- if (!cpu_is_ti816x())
+ /* TI81XX doesn't have feature register */
+ if (!cpu_is_ti81xx())
omap3_check_features();
else
- ti816x_check_features();
+ ti81xx_check_features();
omap3_cpuinfo(cpu_rev);
return;
diff --git a/arch/arm/mach-omap2/include/mach/debug-macro.S b/arch/arm/mach-omap2/include/mach/debug-macro.S
index 48adfe9..309e328 100644
--- a/arch/arm/mach-omap2/include/mach/debug-macro.S
+++ b/arch/arm/mach-omap2/include/mach/debug-macro.S
@@ -72,11 +72,11 @@ omap_uart_lsr: .word 0
beq 34f @ configure OMAP3UART4
cmp \rp, #OMAP4UART4 @ only on 44xx
beq 44f @ configure OMAP4UART4
- cmp \rp, #TI816XUART1 @ ti816x UART offsets different
+ cmp \rp, #TI81XXUART1 @ ti81Xx UART offsets different
beq 81f @ configure UART1
- cmp \rp, #TI816XUART2 @ ti816x UART offsets different
+ cmp \rp, #TI81XXUART2 @ ti81Xx UART offsets different
beq 82f @ configure UART2
- cmp \rp, #TI816XUART3 @ ti816x UART offsets different
+ cmp \rp, #TI81XXUART3 @ ti81Xx UART offsets different
beq 83f @ configure UART3
cmp \rp, #ZOOM_UART @ only on zoom2/3
beq 95f @ configure ZOOM_UART
@@ -100,11 +100,11 @@ omap_uart_lsr: .word 0
b 98f
44: mov \rp, #UART_OFFSET(OMAP4_UART4_BASE)
b 98f
-81: mov \rp, #UART_OFFSET(TI816X_UART1_BASE)
+81: mov \rp, #UART_OFFSET(TI81XX_UART1_BASE)
b 98f
-82: mov \rp, #UART_OFFSET(TI816X_UART2_BASE)
+82: mov \rp, #UART_OFFSET(TI81XX_UART2_BASE)
b 98f
-83: mov \rp, #UART_OFFSET(TI816X_UART3_BASE)
+83: mov \rp, #UART_OFFSET(TI81XX_UART3_BASE)
b 98f
95: ldr \rp, =ZOOM_UART_BASE
mrc p15, 0, \rv, c1, c0
diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S
index ceb8b7e..cb2fb98 100644
--- a/arch/arm/mach-omap2/include/mach/entry-macro.S
+++ b/arch/arm/mach-omap2/include/mach/entry-macro.S
@@ -64,7 +64,7 @@
bne 9998f
/*
- * ti816x has additional IRQ pending register. Checking this
+ * ti81xx has additional IRQ pending register. Checking this
* register on omap2 & omap3 has no effect (read as 0).
*/
ldr \irqnr, [\base, #0xf8] /* IRQ pending reg 4 */
@@ -141,7 +141,7 @@
bne 9999f
ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
cmp \irqnr, #0x0
-#ifdef CONFIG_SOC_OMAPTI816X
+#ifdef CONFIG_SOC_OMAPTI81XX
bne 9999f
ldr \irqnr, [\base, #0xf8] /* IRQ pending reg 4 */
cmp \irqnr, #0x0
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 15f91c4..f065edf 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -176,8 +176,8 @@ static struct map_desc omap34xx_io_desc[] __initdata = {
};
#endif
-#ifdef CONFIG_SOC_OMAPTI816X
-static struct map_desc omapti816x_io_desc[] __initdata = {
+#ifdef CONFIG_SOC_OMAPTI81XX
+static struct map_desc omapti81xx_io_desc[] __initdata = {
{
.virtual = L4_34XX_VIRT,
.pfn = __phys_to_pfn(L4_34XX_PHYS),
@@ -279,10 +279,10 @@ void __init omap34xx_map_common_io(void)
}
#endif
-#ifdef CONFIG_SOC_OMAPTI816X
-void __init omapti816x_map_common_io(void)
+#ifdef CONFIG_SOC_OMAPTI81XX
+void __init omapti81xx_map_common_io(void)
{
- iotable_init(omapti816x_io_desc, ARRAY_SIZE(omapti816x_io_desc));
+ iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
_omap2_map_common_io();
}
#endif
@@ -435,7 +435,7 @@ void __init am35xx_init_early(void)
omap2_init_common_infrastructure();
}
-void __init ti816x_init_early(void)
+void __init ti81xx_init_early(void)
{
omap2_init_common_infrastructure();
}
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 65f1be6..95dee1e 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -186,7 +186,7 @@ void __init omap3_init_irq(void)
omap_init_irq(OMAP34XX_IC_BASE, 96);
}
-void __init ti816x_init_irq(void)
+void __init ti81xx_init_irq(void)
{
omap_init_irq(OMAP34XX_IC_BASE, 128);
}
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 3d1c1d3..a1c10aa 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -486,7 +486,7 @@ static void omap_uart_idle_init(struct omap_uart_state *uart)
mod_timer(&uart->timer, jiffies + uart->timeout);
omap_uart_smart_idle_enable(uart, 0);
- if (cpu_is_omap34xx() && !cpu_is_ti816x()) {
+ if (cpu_is_omap34xx() && !cpu_is_ti81xx()) {
u32 mod = (uart->num > 1) ? OMAP3430_PER_MOD : CORE_MOD;
u32 wk_mask = 0;
u32 padconf = 0;
@@ -768,7 +768,7 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
*/
uart->regshift = p->regshift;
uart->membase = p->membase;
- if (cpu_is_omap44xx() || cpu_is_ti816x())
+ if (cpu_is_omap44xx() || cpu_is_ti81xx())
uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
else if ((serial_read_reg(uart, UART_OMAP_MVER) & 0xFF)
>= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV)
@@ -851,7 +851,7 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
}
/* Enable the MDR1 errata for OMAP3 */
- if (cpu_is_omap34xx() && !cpu_is_ti816x())
+ if (cpu_is_omap34xx() && !cpu_is_ti81xx())
uart->errata |= UART_ERRATA_i202_MDR1_ACCESS;
}
diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
index 5cac97e..0cc1940 100644
--- a/arch/arm/plat-omap/include/plat/common.h
+++ b/arch/arm/plat-omap/include/plat/common.h
@@ -51,7 +51,7 @@ void omap3430_init_early(void);
void omap35xx_init_early(void);
void omap3630_init_early(void);
void am35xx_init_early(void);
-void ti816x_init_early(void);
+void ti81xx_init_early(void);
void omap4430_init_early(void);
/*
@@ -75,7 +75,7 @@ void omap2_set_globals_242x(void);
void omap2_set_globals_243x(void);
void omap2_set_globals_3xxx(void);
void omap2_set_globals_443x(void);
-void omap2_set_globals_ti816x(void);
+void omap2_set_globals_ti81xx(void);
/* These get called from omap2_set_globals_xxxx(), do not call these */
void omap2_set_globals_tap(struct omap_globals *);
@@ -84,6 +84,7 @@ void omap2_set_globals_control(struct omap_globals *);
void omap2_set_globals_prcm(struct omap_globals *);
void omap3_map_io(void);
+void ti81xx_map_io(void);
/**
* omap_test_timeout - busy-loop, testing a condition
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index 2f90269..2c3fbce 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -78,6 +78,14 @@ static inline int is_omap ##class (void) \
return (GET_OMAP_CLASS == (id)) ? 1 : 0; \
}
+#define GET_TI_CLASS ((omap_rev() >> 24) & 0xff)
+
+#define IS_TI_CLASS(class, id) \
+static inline int is_ti ##class (void) \
+{ \
+ return (GET_TI_CLASS == (id)) ? 1 : 0; \
+}
+
#define GET_OMAP_SUBCLASS ((omap_rev() >> 20) & 0x0fff)
#define IS_OMAP_SUBCLASS(subclass, id) \
@@ -99,6 +107,8 @@ IS_OMAP_CLASS(24xx, 0x24)
IS_OMAP_CLASS(34xx, 0x34)
IS_OMAP_CLASS(44xx, 0x44)
+IS_TI_CLASS(81xx, 0x81)
+
IS_OMAP_SUBCLASS(242x, 0x242)
IS_OMAP_SUBCLASS(243x, 0x243)
IS_OMAP_SUBCLASS(343x, 0x343)
@@ -116,6 +126,7 @@ IS_TI_SUBCLASS(816x, 0x816)
#define cpu_is_omap243x() 0
#define cpu_is_omap34xx() 0
#define cpu_is_omap343x() 0
+#define cpu_is_ti81xx() 0
#define cpu_is_ti816x() 0
#define cpu_is_omap44xx() 0
#define cpu_is_omap443x() 0
@@ -322,6 +333,7 @@ IS_OMAP_TYPE(3517, 0x3517)
# undef cpu_is_omap3530
# undef cpu_is_omap3505
# undef cpu_is_omap3517
+# undef cpu_is_ti81xx
# undef cpu_is_ti816x
# define cpu_is_omap3430() is_omap3430()
# define cpu_is_omap3503() (cpu_is_omap3430() && \
@@ -339,6 +351,7 @@ IS_OMAP_TYPE(3517, 0x3517)
!omap3_has_sgx())
# undef cpu_is_omap3630
# define cpu_is_omap3630() is_omap363x()
+# define cpu_is_ti81xx() is_ti81xx()
# define cpu_is_ti816x() is_ti816x()
#endif
diff --git a/arch/arm/plat-omap/include/plat/hardware.h b/arch/arm/plat-omap/include/plat/hardware.h
index e87efe1..1a2f830 100644
--- a/arch/arm/plat-omap/include/plat/hardware.h
+++ b/arch/arm/plat-omap/include/plat/hardware.h
@@ -286,6 +286,6 @@
#include <plat/omap24xx.h>
#include <plat/omap34xx.h>
#include <plat/omap44xx.h>
-#include <plat/ti816x.h>
+#include <plat/ti81xx.h>
#endif /* __ASM_ARCH_OMAP_HARDWARE_H */
diff --git a/arch/arm/plat-omap/include/plat/io.h b/arch/arm/plat-omap/include/plat/io.h
index 6591875..3f9c0bd 100644
--- a/arch/arm/plat-omap/include/plat/io.h
+++ b/arch/arm/plat-omap/include/plat/io.h
@@ -283,10 +283,10 @@ static inline void omap34xx_map_common_io(void)
}
#endif
-#ifdef CONFIG_SOC_OMAPTI816X
-extern void omapti816x_map_common_io(void);
+#ifdef CONFIG_SOC_OMAPTI81XX
+extern void omapti81xx_map_common_io(void);
#else
-static inline void omapti816x_map_common_io(void)
+static inline void omapti81xx_map_common_io(void)
{
}
#endif
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
index 30e1071..0af9a22 100644
--- a/arch/arm/plat-omap/include/plat/irqs.h
+++ b/arch/arm/plat-omap/include/plat/irqs.h
@@ -441,7 +441,7 @@ extern void __iomem *omap_irq_base;
void omap1_init_irq(void);
void omap2_init_irq(void);
void omap3_init_irq(void);
-void ti816x_init_irq(void);
+void ti81xx_init_irq(void);
extern int omap_irq_pending(void);
void omap_intc_save_context(void);
void omap_intc_restore_context(void);
diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h
index de3b10c..865b13e 100644
--- a/arch/arm/plat-omap/include/plat/serial.h
+++ b/arch/arm/plat-omap/include/plat/serial.h
@@ -51,10 +51,10 @@
#define OMAP4_UART3_BASE 0x48020000
#define OMAP4_UART4_BASE 0x4806e000
-/* TI816X serial ports */
-#define TI816X_UART1_BASE 0x48020000
-#define TI816X_UART2_BASE 0x48022000
-#define TI816X_UART3_BASE 0x48024000
+/* TI81XX serial ports */
+#define TI81XX_UART1_BASE 0x48020000
+#define TI81XX_UART2_BASE 0x48022000
+#define TI81XX_UART3_BASE 0x48024000
/* AM3505/3517 UART4 */
#define AM35XX_UART4_BASE 0x4809E000 /* Only on AM3505/3517 */
@@ -89,9 +89,9 @@
#define OMAP4UART2 OMAP2UART2
#define OMAP4UART3 43
#define OMAP4UART4 44
-#define TI816XUART1 81
-#define TI816XUART2 82
-#define TI816XUART3 83
+#define TI81XXUART1 81
+#define TI81XXUART2 82
+#define TI81XXUART3 83
#define ZOOM_UART 95 /* Only on zoom2/3 */
/* This is only used by 8250.c for omap1510 */
diff --git a/arch/arm/plat-omap/include/plat/ti816x.h b/arch/arm/plat-omap/include/plat/ti81xx.h
similarity index 60%
rename from arch/arm/plat-omap/include/plat/ti816x.h
rename to arch/arm/plat-omap/include/plat/ti81xx.h
index 50510f5..8f9843f 100644
--- a/arch/arm/plat-omap/include/plat/ti816x.h
+++ b/arch/arm/plat-omap/include/plat/ti81xx.h
@@ -1,5 +1,5 @@
/*
- * This file contains the address data for various TI816X modules.
+ * This file contains the address data for various TI81XX modules.
*
* Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
*
@@ -13,15 +13,15 @@
* GNU General Public License for more details.
*/
-#ifndef __ASM_ARCH_TI816X_H
-#define __ASM_ARCH_TI816X_H
+#ifndef __ASM_ARCH_TI81XX_H
+#define __ASM_ARCH_TI81XX_H
-#define L4_SLOW_TI816X_BASE 0x48000000
+#define L4_SLOW_TI81XX_BASE 0x48000000
-#define TI816X_SCM_BASE 0x48140000
-#define TI816X_CTRL_BASE TI816X_SCM_BASE
-#define TI816X_PRCM_BASE 0x48180000
+#define TI81XX_SCM_BASE 0x48140000
+#define TI81XX_CTRL_BASE TI81XX_SCM_BASE
+#define TI81XX_PRCM_BASE 0x48180000
-#define TI816X_ARM_INTC_BASE 0x48200000
+#define TI81XX_ARM_INTC_BASE 0x48200000
-#endif /* __ASM_ARCH_TI816X_H */
+#endif /* __ASM_ARCH_TI81XX_H */
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
index cb4a6c2..40336ad 100644
--- a/arch/arm/plat-omap/include/plat/uncompress.h
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -93,9 +93,9 @@ static inline void flush(void)
#define DEBUG_LL_ZOOM(mach) \
_DEBUG_LL_ENTRY(mach, ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART)
-#define DEBUG_LL_TI816X(p, mach) \
- _DEBUG_LL_ENTRY(mach, TI816X_UART##p##_BASE, OMAP_PORT_SHIFT, \
- TI816XUART##p)
+#define DEBUG_LL_TI81XX(p, mach) \
+ _DEBUG_LL_ENTRY(mach, TI81XX_UART##p##_BASE, OMAP_PORT_SHIFT, \
+ TI81XXUART##p)
static inline void __arch_decomp_setup(unsigned long arch_id)
{
@@ -173,7 +173,7 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
DEBUG_LL_ZOOM(omap_zoom3);
/* TI8168 base boards using UART3 */
- DEBUG_LL_TI816X(3, ti8168evm);
+ DEBUG_LL_TI81XX(3, ti8168evm);
} while (0);
}
diff --git a/arch/arm/plat-omap/io.c b/arch/arm/plat-omap/io.c
index f1ecfa9..1443992 100644
--- a/arch/arm/plat-omap/io.c
+++ b/arch/arm/plat-omap/io.c
@@ -85,7 +85,7 @@ void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type)
}
#endif
#ifdef CONFIG_ARCH_OMAP3
- if (cpu_is_ti816x()) {
+ if (cpu_is_ti81xx()) {
if (BETWEEN(p, L4_34XX_PHYS, L4_34XX_SIZE))
return XLATE(p, L4_34XX_PHYS, L4_34XX_VIRT);
} else if (cpu_is_omap34xx()) {
--
1.7.3.5
^ permalink raw reply related
* [PATCH v3 0/3] Add support for TI814X processor series
From: Hemant Pedanekar @ 2011-09-29 1:08 UTC (permalink / raw)
To: linux-arm-kernel
This patch set adds support for DM814x/AM387x device series having Cortex-A8
MPU.
The technical documents are available from following link:
http://focus.ti.com/docs/prod/folders/print/tms320dm8148.html
This series is referred in code as TI814X.
Since these devices share similar architecture as TI816X devices, existing
TI816X code is updated to accomodate TI814X support. The code shared across
TI816X and TI814X devices is updated with TI81XX/ti81xx prefix as applicable,
while maintaining cpu_is_ti816x() and cpu_is_ti814x() to distinguish specific
execution differences.
Changes since v2:
1) Incorporate Tony's suggestion about moving ti8168_evm_map_io() to
arch/arm/mach-omap2/common.c to keep common across TI81XX.
2) Keeping single board file (board-ti81xxevm.c) for TI816X and TI814X EVMs
Changes since v1:
1) Rebased and updated after Paul's CHIP_IS removal changes
2) Removed call to omap2_init_common_devices() as per Kevin's comment
Hemant Pedanekar (3):
ARM: OMAP: TI81XX: Prepare for addition of TI814X support
ARM: OMAP: TI814X: Add cpu type macros and detection support
ARM: OMAP: TI814X: Create board support and enable build for TI8148
EVM
arch/arm/mach-omap2/Kconfig | 11 +++++--
arch/arm/mach-omap2/Makefile | 3 +-
.../{board-ti8168evm.c => board-ti81xxevm.c} | 34 +++++++++++---------
arch/arm/mach-omap2/clock.c | 2 +-
arch/arm/mach-omap2/clock.h | 2 +-
arch/arm/mach-omap2/clock3xxx_data.c | 5 ++-
arch/arm/mach-omap2/common.c | 28 ++++++++++------
arch/arm/mach-omap2/control.h | 8 ++--
arch/arm/mach-omap2/id.c | 30 +++++++++++++++--
arch/arm/mach-omap2/include/mach/debug-macro.S | 12 +++---
arch/arm/mach-omap2/include/mach/entry-macro.S | 4 +-
arch/arm/mach-omap2/io.c | 12 +++---
arch/arm/mach-omap2/irq.c | 2 +-
arch/arm/mach-omap2/opp2xxx.h | 2 +-
arch/arm/mach-omap2/serial.c | 6 ++--
arch/arm/plat-omap/include/plat/clkdev_omap.h | 1 +
arch/arm/plat-omap/include/plat/clock.h | 3 +-
arch/arm/plat-omap/include/plat/common.h | 5 ++-
arch/arm/plat-omap/include/plat/cpu.h | 22 +++++++++++++
arch/arm/plat-omap/include/plat/hardware.h | 2 +-
arch/arm/plat-omap/include/plat/io.h | 6 ++--
arch/arm/plat-omap/include/plat/irqs.h | 2 +-
arch/arm/plat-omap/include/plat/serial.h | 14 ++++----
.../plat-omap/include/plat/{ti816x.h => ti81xx.h} | 18 +++++-----
arch/arm/plat-omap/include/plat/uncompress.h | 11 ++++--
arch/arm/plat-omap/io.c | 2 +-
26 files changed, 158 insertions(+), 89 deletions(-)
rename arch/arm/mach-omap2/{board-ti8168evm.c => board-ti81xxevm.c} (60%)
rename arch/arm/plat-omap/include/plat/{ti816x.h => ti81xx.h} (60%)
--
1.7.3.5
^ permalink raw reply
* [PATCH 1/2] msm: Consolidate and move DEBUG_LL to generic ARM Kconfig
From: David Brown @ 2011-09-28 23:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1317243959-26383-2-git-send-email-sboyd@codeaurora.org>
On Wed, Sep 28, 2011 at 02:05:58PM -0700, Stephen Boyd wrote:
> Now that DEBUG_LL is a choice, we can move MSM's homegrown choice
> menu to DEBUG_LL.
>
> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This seems to make DEBUG_LL work again on MSM8250. So:
Tested-by: David Brown <davidb@codeaurora.org>
David
--
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
^ permalink raw reply
* [RFC PATCH v3] drivercore: Add driver probe deferral mechanism
From: Grant Likely @ 2011-09-28 23:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110927221308.GA2674@opensource.wolfsonmicro.com>
On Tue, Sep 27, 2011 at 11:13:10PM +0100, Mark Brown wrote:
> On Tue, Sep 27, 2011 at 03:08:49PM -0600, Grant Likely wrote:
>
> > Okay, will do. How does EPROBE_DEFER 518 sound?
>
> Note that I'm not sure this answers the issue I was raising - the issue
> isn't that the caller doesn't know what the error code means, the issue
> is that in some cases the driver needs to take a decision about what
> failure to get a resource means. Does it mean that the driver can work
> fine and be slightly less featureful or should it cause a deferral?
Right. That was answering a different question.
For your question, I still think it is the driver that gets to make
the decision. If it can proceed without a resource, then it should go
ahead and succeed on the probe, and then arrange to either be notified
of new gpio controller (or whatever) registrations, or poll for the
resource to be set up.
g.
^ permalink raw reply
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