* [PATCH v2] ARM: cache-l2x0: add resume entry for l2 in secure mode
From: Russell King - ARM Linux @ 2011-09-29 9:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110929092828.GE19318@S2100-06.ap.freescale.net>
On Thu, Sep 29, 2011 at 05:28:29PM +0800, Shawn Guo wrote:
> On Sun, Sep 25, 2011 at 08:26:09PM -0700, Barry Song wrote:
> > we save the l2x0 registers at the first initialization, and platform codes
> > can get them to restore l2x0 status after wakeup.
> >
> > Cc: Shawn Guo <shawn.guo@linaro.org>
> > Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> > Signed-off-by: Barry Song <Baohua.Song@csr.com>
> > ---
> > -v2:
> > define the structure l2x0_regs to hold all saved registers;
> > make saved copy of registers non-static so that platform codes can access them;
> > add asm_offset for l2x0 saved regs(l2x0_regs struct) so that asm codes can use
> >
>
> I'm trying to migrate imx6q to this infrastructure, but seeing some
> facts that might stop me from the effort. Please help me understand
> these facts are correct.
>
> It seems to me that the only benefit that imx6q gains from the
> infrastructure is the register saving, and I fail to see any benefit
> on the restoring.
That's correct - because I believe that's the only part which is worth
doing in common code. The restoring tends to be platform dependent so
I don't see the point of having a bunch of code in common files to do
that which almost no one uses.
> * I still have to save physical base of l2x0 for register restoring.
That could be added to the structure.
> * I do not have the physical address of l2x0_saved_regs, and I have
> to manage to get it somehow.
That's true no matter what - we could store the physical address of
the struct somewhere, but then in order for you to obtain that, you'd
somehow need to know the physical address of _that_ location too - so
there's no benefit there.
It can be obtained simply by: __pa(l2x0_saved_regs) in C code, and
saving that in a location known to the platform prior to suspend.
^ permalink raw reply
* [PATCH 0/2] GIC OF bindings
From: Jamie Iles @ 2011-09-29 9:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1317268436-1613-1-git-send-email-robherring2@gmail.com>
On Wed, Sep 28, 2011 at 10:53:54PM -0500, Rob Herring wrote:
> From: Rob Herring <rob.herring@calxeda.com>
>
> With recent patches for VIC device tree support and GIC MULTI_IRQ support,
> it is evident that the irq domain support should be moved into the core GIC
> code and not be dependent on the DT initialization. So I've split things up
> into 2 patches separating irq_domain and device-tree code.
>
> This should only change the internals of the GIC code. The binding is
> unchanged from the previous version. Yeah!
>
> The full series is available here. This includes Russell's devel-stable and
> for-next branches and Nico's vmalloc branch.
Looks good to me!
Reviewed-by: Jamie Iles <jamie@jamieiles.com>
^ permalink raw reply
* [PATCHv2 2/2] ARM: debug: Move DEBUG_ICEDCC into the DEBUG_LL choice
From: Will Deacon @ 2011-09-29 9:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4E83D25C.6020306@codeaurora.org>
On Thu, Sep 29, 2011 at 03:05:16AM +0100, Stephen Boyd wrote:
> On 09/20/11 18:23, Stephen Boyd wrote:
> > DEBUG_ICEDCC support is just another DEBUG_LL choice and
> > selecting it along with other DEBUG_LL options doesn't make
> > much sense. Put it into the DEBUG_LL choice to avoid confusion.
> >
> > Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
> > Acked-by: Will Deacon <will.deacon@arm.com>
> > ---
> >
>
> Chatting with David Brown made me realize that this patch now forces
> ICEDCC for anybody who selects DEBUG_LL and hasn't moved to adding a
> Kconfig in the choice menu. I'm not sure if that actually matters since
> it may be incentive to put your machine of choice into this menu.
>
> Otherwise, we may want to drop this until a later point, or just leave
> it out of the choice menu altogether.
Given that the ICEDCC stuff shouldn't cause any other problems by having it
enabled (that is, your kernel should still boot) then we should be alright
leaving this as-is while platforms move over to the new scheme.
However, if we get attacked by the United Army of Enraged Platform Maintainers
wanting to use earlyprintk, then I'm hiding behind you :)
Will
^ permalink raw reply
* [PATCH 4/6] arm/imx: remove cpu_is_xxx() from arch_idle()
From: Sascha Hauer @ 2011-09-29 8:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1317201368-6403-5-git-send-email-shawn.guo@linaro.org>
On Wed, Sep 28, 2011 at 05:16:06PM +0800, Shawn Guo wrote:
> This patch adds an idle hook imx_idle to be called in arch_idle().
> Any soc that needs a customized idle implementation other than
> cpu_do_idle() can set up this hook in soc specific call.
>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
> ---
> arch/arm/mach-imx/mm-imx3.c | 30 ++++++++++++++++++++++++++
> arch/arm/mach-mx5/mm.c | 6 +++++
> arch/arm/mach-mx5/pm-imx5.c | 3 +-
> arch/arm/plat-mxc/include/mach/common.h | 2 +
> arch/arm/plat-mxc/include/mach/system.h | 35 ++----------------------------
> arch/arm/plat-mxc/system.c | 2 +
> 6 files changed, 45 insertions(+), 33 deletions(-)
>
I had to fold the following into this commit, otherwise we end
up with:
In file included from arch/arm/mach-mx5/pm-imx5.c:17:0:arch/arm/plat-mxc/include/mach/common.h:77:33: warning: 'enum mxc_cpu_pwr_mode' declared inside parameter list
arch/arm/plat-mxc/include/mach/common.h:77:33: warning: its scope is only this definition or declaration, which is probably not what you want
Sascha
diff --git a/arch/arm/mach-mx5/system.c b/arch/arm/mach-mx5/system.c
index 76ae8dc..144ebeb 100644
--- a/arch/arm/mach-mx5/system.c
+++ b/arch/arm/mach-mx5/system.c
@@ -13,6 +13,7 @@
#include <linux/platform_device.h>
#include <linux/io.h>
#include <mach/hardware.h>
+#include <mach/common.h>
#include "crm_regs.h"
/* set cpu low power mode before WFI instruction. This function is called
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index 2b298d8..afaa967 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -72,6 +72,15 @@ extern void mxc_arch_reset_init(void __iomem *);
extern void mx51_efikamx_reset(void);
extern int mx53_revision(void);
extern int mx53_display_revision(void);
+
+enum mxc_cpu_pwr_mode {
+ WAIT_CLOCKED, /* wfi only */
+ WAIT_UNCLOCKED, /* WAIT */
+ WAIT_UNCLOCKED_POWER_OFF, /* WAIT + SRPG */
+ STOP_POWER_ON, /* just STOP */
+ STOP_POWER_OFF, /* STOP + SRPG */
+};
+
extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode);
extern void (*imx_idle)(void);
#endif
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index 0987923..00a7819 100644
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -183,13 +183,6 @@ struct cpu_op {
};
int tzic_enable_wake(int is_idle);
-enum mxc_cpu_pwr_mode {
- WAIT_CLOCKED, /* wfi only */
- WAIT_UNCLOCKED, /* WAIT */
- WAIT_UNCLOCKED_POWER_OFF, /* WAIT + SRPG */
- STOP_POWER_ON, /* just STOP */
- STOP_POWER_OFF, /* STOP + SRPG */
-};
extern struct cpu_op *(*get_cpu_op)(int *op);
#endif
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply related
* Perf support for OMAP4
From: Will Deacon @ 2011-09-29 8:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACVXFVPxVQmAGmbhCH6KSogeQC3EcCseoApNABfmqWmGePpoOA@mail.gmail.com>
On Thu, Sep 29, 2011 at 08:20:53AM +0100, Ming Lei wrote:
> Hi,
>
> On Wed, Sep 28, 2011 at 11:54 PM, Will Deacon <will.deacon@arm.com> wrote:
> > Hi Tom,
> >
> > I can't see your OMAP4 Perf/PMU patches from here:
> >
> > http://lists.infradead.org/pipermail/linux-arm-kernel/2011-March/045283.html
> >
> > in mainline or next.
> >
> > Are you still pushing these or did you get blocked awaiting feedback?
>
> OK, I will rebase the patch against -next tree and resend it later.
Ok. Note that there are some substantial changes to the ARM perf and PMU
code that are in Russell's devel-stable branch but don't appear in -next.
Will
^ permalink raw reply
* [PATCH v2 07/16] ARM: GIC: Add global gic_handle_irq_offset() function
From: Marc Zyngier @ 2011-09-29 8:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4E834248.3010908@gmail.com>
On 28/09/11 16:50, Rob Herring wrote:
> On 09/26/2011 06:02 AM, Marc Zyngier wrote:
>> Similar to gic_handle_irq(), gic_handle_irq_offset() is provided
>> for those platform who insist on having their GIC base interrupt
>> at something different from zero. At the moment, Exynos4 is the
>> only one...
>>
>> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
>> ---
>> arch/arm/common/gic.c | 24 ++++++++++++++++++++++++
>> arch/arm/include/asm/hardware/gic.h | 1 +
>> 2 files changed, 25 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
>> index 5a22896..ef803d2 100644
>> --- a/arch/arm/common/gic.c
>> +++ b/arch/arm/common/gic.c
>> @@ -232,6 +232,30 @@ asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
>> } while (1);
>> }
>>
>> +asmlinkage void __exception_irq_entry gic_handle_irq_offset(struct pt_regs *regs)
>> +{
>> + u32 irqstat, irqnr;
>> + u32 offset = gic_data[0].irq_offset;
>> +
>> + do {
>> + irqstat = readl_relaxed(gic_cpu_base_addr + GIC_CPU_INTACK);
>> + irqnr = irqstat & ~0x1c00;
>> +
>> + if (likely(irqnr > 15 && irqnr < 1021)) {
>> + handle_IRQ(irqnr + offset, regs);
>
> Can't this be combined with gic_handle_irq. irq_offset will be 0 in that
> case. Really, irq_domain should be used here.
I completely agree on the irq_domain thing. The reason I introduced two
functions is to keep things as similar as possible to the old
implementation, and also to save a memory reference + addition on the
hot path of all the other platforms.
If we all agree that keeping that piece of code as generic as possible
is the way forward, then I'll happily drop that patch and let Exynos4
use the same handler.
Cheers,
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply
* [PATCH v5 00/15] OMAP2+: Serial: Runtime adaptation + cleanup
From: Govindraj @ 2011-09-29 8:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1316607097-21564-1-git-send-email-govindraj.raja@ti.com>
On Wed, Sep 21, 2011 at 5:41 PM, Govindraj.R <govindraj.raja@ti.com> wrote:
> Converting uart driver to adapt to pm runtime API's.
> Code re-org + cleanup.
> Moving some functionality from serial.c to omap-serial.c
>
> Changes involves:
> ================
> 1.) Cleaning up certain uart calls from sram_idle func.
> 2.) Removed all types of uart clock handling code from serial.c
> 3.) Using hwmod_mux API enable wakeup capability for uart pad during
> ? hwmod_idle state i.e., when uart clocks are disabled we can enable
> ? io-pad wakeup capability for uart if mux_data is available for
> ? given uart. Also during during resume from idle call to uart we need
> ? to enable clocks back conditionally and this can be done only when io-pad
> ? wakeup event bit is set for uart_rx pad. So we need a hwmod API
> ? which can probe the uart pad and let us know whether a uart wakeup
> ? happened. So omap_hmwod_pad_wakeup_status API is added to meet this
> ? requirement.
> 3.) Adapted omap-serial driver to use runtime API's.
> 4.) Modify serial_init calls to accept uart parameters from board file.
> ? ?Like dma_usage, rx_timeout, dma_rx_pollrate, auto_suspend_timeout etc.
> 5.) Use the omap_prm driver with irq_chaining to wake up uart after clocks are
> ? ?cut.
>
> Patch series is based on 3.1.0-rc4 + omap_device fixes.
> From Kevin's tree.
> git://gitorious.org/khilman/linux-omap-pm.git for_3.2/omap_device
>
> Also the patch series depends on Tero's Irq_chaining patches.
> Dependent irq_chaining patches are as below.
>
> 3d5b543 omap3: pm: use prcm chain handler
> c00b340 OMAP2+: mux: add support for PAD wakeup interrupts
> db6397c power: omap-prm: added chain interrupt handler
> b3f8628 TEMP: OMAP4xxx: hwmod data: add PRM hwmod
> 61ec0fc TEMP: OMAP3xxx: hwmod data: add PRM hwmod
> a1ecf8c power: add omap prm driver skeleton
>
> Same combination is hosted at:
> git://gitorious.org/runtime_3-0/runtime_3-0.git v5_uart_irqchn
>
Update:
-----------
This patch series was tested against Tero's Irq chaining v9 [1]
tmp patches where dropped from tero's series and applied
on top v5 uart_runtime patches.
same combination is hosted here [2]
--
Thanks,
Govindraj.R
[1]:
43c5073 omap3+: add omap prm driver initialization
dad7fc5 OMAP3: pm: do not enable PRCM MPU interrupts manually
c205290 omap3: pm: use prcm chain handler
453656e OMAP2+: mux: add support for PAD wakeup interrupts
563bed3 mfd: omap-prm: added suspend prepare and complete callbacks
ff8770a mfd: omap-prm: added chain interrupt handler
46386a9 mfd: omap-prm: add driver skeleton
bdc8ddf TEMP: OMAP4xxx: hwmod data: add PRM hwmod
8cc0382 TEMP: OMAP3xxx: hwmod data: add PRM hwmod
[2]: git://gitorious.org/runtime_3-0/runtime_3-0.git v5_uart_runtime
> Ensure CONFIG_OMAP_PRM is set while testing irq_chaining with uart.
>
> Changes from v4:
> ---------------
>
> 1.) Fixing v4 comments from Kevin.
> ? ?Spilt into smaller logical patches.
> 2.) Using Irq_chaining OMAP_PRM driver for waking up uart.
>
> Testing updates:
> ----------------
> 3430SDP:
> retention, off_mode, system_wide suspend is tested.
> (earlyprintk & no_console_suspend checked)
>
> OMAP3630 - Zoom3:
> pm-retention checked with quart/omap-uart3
> [Also tested with uart3 as console uart and pm-ret checked]
>
> OMAP4430-SDP: Boot tested.
> OMAP2420/2430SDP: Boot tested.
>
> Deepak K (1):
> ?OMAP2+: UART: Allow UART parameters to be configured from board file.
>
> Govindraj.R (13):
> ?OMAP2+: hwmod: Add API to enable IO ring wakeup.
> ?OMAP2+: hwmod: Add API to check IO PAD wakeup status
> ?OMAP2+: UART: cleanup + remove uart pm specific API
> ?OMAP2+: UART: cleanup 8250 console driver support
> ?OMAP2+: UART: Cleanup part of clock gating mechanism for uart
> ?OMAP2+: UART: Remove certain feilds from omap_uart_state struct
> ?OMAP2+: UART: Add default mux for all uarts.
> ?OMAP2+: UART: Store certain reg values to port structure
> ?OMAP2+: UART: Add runtime pm support for omap-serial driver
> ?OMAP2+: UART: Move errata handling from serial.c to omap-serial
> ?OMAP2+: UART: Take console_lock in suspend path if not taken
> ?OMAP2+: UART: Enable back uart clocks with runtime API for early
> ? ?console
> ?OMAP2+: UART: Do not gate uart clocks if used for debug_prints
>
> Jon Hunter (1):
> ?OMAP2+: UART: Make the RX_TIMEOUT for DMA configurable for each UART
>
> ?arch/arm/mach-omap2/board-3430sdp.c ? ? ? ? ? | ?100 +---
> ?arch/arm/mach-omap2/board-4430sdp.c ? ? ? ? ? | ? ?8 +-
> ?arch/arm/mach-omap2/board-n8x0.c ? ? ? ? ? ? ?| ? ?6 +-
> ?arch/arm/mach-omap2/board-omap4panda.c ? ? ? ?| ? ?8 +-
> ?arch/arm/mach-omap2/mux.c ? ? ? ? ? ? ? ? ? ? | ? 30 +
> ?arch/arm/mach-omap2/mux.h ? ? ? ? ? ? ? ? ? ? | ? 13 +
> ?arch/arm/mach-omap2/omap_hwmod.c ? ? ? ? ? ? ?| ? 66 ++
> ?arch/arm/mach-omap2/pm24xx.c ? ? ? ? ? ? ? ? ?| ? 19 -
> ?arch/arm/mach-omap2/pm34xx.c ? ? ? ? ? ? ? ? ?| ? 24 -
> ?arch/arm/mach-omap2/serial.c ? ? ? ? ? ? ? ? ?| ?933 +++++++------------------
> ?arch/arm/plat-omap/include/plat/omap-serial.h | ? 30 +-
> ?arch/arm/plat-omap/include/plat/omap_hwmod.h ?| ? ?1 +
> ?arch/arm/plat-omap/include/plat/serial.h ? ? ?| ? 11 +-
> ?drivers/tty/serial/omap-serial.c ? ? ? ? ? ? ?| ?305 +++++++--
> ?14 files changed, 654 insertions(+), 900 deletions(-)
>
> --
> 1.7.4.1
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-serial" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at ?http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply
* [PATCH v2] ARM: mm: Align bank start to MAX_ORDER_NR_PAGES
From: Linus Walleij @ 2011-09-29 8:36 UTC (permalink / raw)
To: linux-arm-kernel
From: Johan Palsson <johan.palsson@stericsson.com>
The VM subsystem assumes that there are valid memmap entries from
the bank start aligned to MAX_ORDER_NR_PAGES.
On the Ux500 we have a lot of mem=N arguments on the commandline
triggering this bug several times over and causing kernel
oops messages.
Cc: stable at kernel.org
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Cc: Michael Bohan <mbohan@codeaurora.org>
Cc: Nicolas Pitre <nico@fluxnic.net>
Signed-off-by: Johan Palsson <johan.palsson@stericsson.com>
Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/mm/init.c | 7 +++++++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index cc7e2d8..f8037ba 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -496,6 +496,13 @@ static void __init free_unused_memmap(struct meminfo *mi)
*/
bank_start = min(bank_start,
ALIGN(prev_bank_end, PAGES_PER_SECTION));
+#else
+ /*
+ * Align down here since the VM subsystem insists that the
+ * memmap entries are valid from the bank start aligned to
+ * MAX_ORDER_NR_PAGES.
+ */
+ bank_start = round_down(bank_start, MAX_ORDER_NR_PAGES);
#endif
/*
* If we had a previous bank, and there is a space
--
1.7.6.2
^ permalink raw reply related
* [PATCH 6/6] arm/imx: merge i.MX3 and i.MX6
From: Sascha Hauer @ 2011-09-29 8:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110929051725.GA19318@S2100-06.ap.freescale.net>
On Thu, Sep 29, 2011 at 01:17:28PM +0800, Shawn Guo wrote:
> On Wed, Sep 28, 2011 at 02:18:08PM +0200, Sascha Hauer wrote:
> > On Wed, Sep 28, 2011 at 05:16:08PM +0800, Shawn Guo wrote:
> > >
> > >
> > > -config ARCH_MX3
> > > - bool "MX3-based"
> > > +config ARCH_IMX_V6_V7
> > > + bool "i.MX3, i.MX6"
> > > + select AUTO_ZRELADDR
> > > + select ARM_PATCH_PHYS_VIRT
> >
> > Russell pointed out that it's not a good idea to select this.
> >
> Yeah, I saw that. So you would support ZBOOT_ROM over single zImage
> between these two? I'm not sure how many imx users are actually using
> ZBOOT_ROM. If there are only very few, we still want to keep the
> default configuration compatible with ZBOOT_ROM? I think we can move
> the default build to single zImage, and let those limited users sort
> out their own configuration to get ZBOOT_ROM back. After all, the
> support is still there, and it's just about build configuration
> adjustment.
I'm not sure there are i.MX ZBOOT_ROM users at all. Anyway,
select AUTO_ZRELADDR if !ZBOOT_ROM
seems to work.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply
* [PATCH] ARM: mm: Align bank start to MAX_ORDER_NR_PAGES
From: Linus Walleij @ 2011-09-29 8:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1317198748-17705-1-git-send-email-johan.palsson@stericsson.com>
On Wed, Sep 28, 2011 at 10:32 AM, Johan Palsson
<johan.palsson@stericsson.com> wrote:
> The VM subsystem assumes that there are valid memmap entries from
> the bank start aligned to MAX_ORDER_NR_PAGES.
>
> Cc: stable at kernel.org
> Cc: Russell King <rmk+kernel@arm.linux.org.uk>
> Cc: Michael Bohan <mbohan@codeaurora.org>
> Cc: Nicolas Pitre <nico@fluxnic.net>
> Signed-off-by: Johan Palsson <johan.palsson@stericsson.com>
> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
I should mention that this is triggered a lot by our platform using
several disparate mem=n arguments on the command line,
chopping out pieces of memory here and there.
I will repost with a more descriptive message and then I'll
put it into the patch tracker, as it's a blocker already on 3.0
for us.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH 5/5] ARM: EXYNOS4: Add support SMDK4412 Board
From: Kukjin Kim @ 2011-09-29 8:13 UTC (permalink / raw)
To: linux-arm-kernel
From: Changhwan Youn <chaos.youn@samsung.com>
SMDK4412 board is same as a SMDK4212 board except that
it has EXYNOS4412 SoC, thus it can share machine code
with SMDK4212.
This patch renames mach-smdk4212.c to mach-smdk4x12.c
to support both SMDK4212 and SMDK4412 board with one
machine file.
Signed-off-by: Changhwan Youn <chaos.youn@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
arch/arm/mach-exynos4/Kconfig | 9 ++
arch/arm/mach-exynos4/Makefile | 3 +-
.../{mach-smdk4212.c => mach-smdk4x12.c} | 128 +++++++++++---------
3 files changed, 80 insertions(+), 60 deletions(-)
rename arch/arm/mach-exynos4/{mach-smdk4212.c => mach-smdk4x12.c} (61%)
diff --git a/arch/arm/mach-exynos4/Kconfig b/arch/arm/mach-exynos4/Kconfig
index bf3e21d..6dfde07 100644
--- a/arch/arm/mach-exynos4/Kconfig
+++ b/arch/arm/mach-exynos4/Kconfig
@@ -278,6 +278,15 @@ config MACH_SMDK4212
help
Machine support for Samsung SMDK4212
+comment "EXYNOS4412 Boards"
+
+config MACH_SMDK4412
+ bool "SMDK4412"
+ select SOC_EXYNOS4412
+ select MACH_SMDK4212
+ help
+ Machine support for Samsung SMDK4412
+
endmenu
comment "Configuration for HSMMC bus width"
diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile
index e19cd12..c9b2e1f 100644
--- a/arch/arm/mach-exynos4/Makefile
+++ b/arch/arm/mach-exynos4/Makefile
@@ -34,7 +34,8 @@ obj-$(CONFIG_MACH_UNIVERSAL_C210) += mach-universal_c210.o
obj-$(CONFIG_MACH_NURI) += mach-nuri.o
obj-$(CONFIG_MACH_ORIGEN) += mach-origen.o
-obj-$(CONFIG_MACH_SMDK4212) += mach-smdk4212.o
+obj-$(CONFIG_MACH_SMDK4212) += mach-smdk4x12.o
+obj-$(CONFIG_MACH_SMDK4412) += mach-smdk4x12.o
# device support
diff --git a/arch/arm/mach-exynos4/mach-smdk4212.c b/arch/arm/mach-exynos4/mach-smdk4x12.c
similarity index 61%
rename from arch/arm/mach-exynos4/mach-smdk4212.c
rename to arch/arm/mach-exynos4/mach-smdk4x12.c
index 3479a93..fcf2e0e 100644
--- a/arch/arm/mach-exynos4/mach-smdk4212.c
+++ b/arch/arm/mach-exynos4/mach-smdk4x12.c
@@ -1,5 +1,5 @@
/*
- * linux/arch/arm/mach-exynos4/mach-smdk4212.c
+ * linux/arch/arm/mach-exynos4/mach-smdk4x12.c
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
@@ -37,51 +37,51 @@
#include <mach/map.h>
/* Following are default values for UCON, ULCON and UFCON UART registers */
-#define SMDK4212_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
+#define SMDK4X12_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
S3C2410_UCON_RXILEVEL | \
S3C2410_UCON_TXIRQMODE | \
S3C2410_UCON_RXIRQMODE | \
S3C2410_UCON_RXFIFO_TOI | \
S3C2443_UCON_RXERR_IRQEN)
-#define SMDK4212_ULCON_DEFAULT S3C2410_LCON_CS8
+#define SMDK4X12_ULCON_DEFAULT S3C2410_LCON_CS8
-#define SMDK4212_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
+#define SMDK4X12_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
S5PV210_UFCON_TXTRIG4 | \
S5PV210_UFCON_RXTRIG4)
-static struct s3c2410_uartcfg smdk4212_uartcfgs[] __initdata = {
+static struct s3c2410_uartcfg smdk4x12_uartcfgs[] __initdata = {
[0] = {
.hwport = 0,
.flags = 0,
- .ucon = SMDK4212_UCON_DEFAULT,
- .ulcon = SMDK4212_ULCON_DEFAULT,
- .ufcon = SMDK4212_UFCON_DEFAULT,
+ .ucon = SMDK4X12_UCON_DEFAULT,
+ .ulcon = SMDK4X12_ULCON_DEFAULT,
+ .ufcon = SMDK4X12_UFCON_DEFAULT,
},
[1] = {
.hwport = 1,
.flags = 0,
- .ucon = SMDK4212_UCON_DEFAULT,
- .ulcon = SMDK4212_ULCON_DEFAULT,
- .ufcon = SMDK4212_UFCON_DEFAULT,
+ .ucon = SMDK4X12_UCON_DEFAULT,
+ .ulcon = SMDK4X12_ULCON_DEFAULT,
+ .ufcon = SMDK4X12_UFCON_DEFAULT,
},
[2] = {
.hwport = 2,
.flags = 0,
- .ucon = SMDK4212_UCON_DEFAULT,
- .ulcon = SMDK4212_ULCON_DEFAULT,
- .ufcon = SMDK4212_UFCON_DEFAULT,
+ .ucon = SMDK4X12_UCON_DEFAULT,
+ .ulcon = SMDK4X12_ULCON_DEFAULT,
+ .ufcon = SMDK4X12_UFCON_DEFAULT,
},
[3] = {
.hwport = 3,
.flags = 0,
- .ucon = SMDK4212_UCON_DEFAULT,
- .ulcon = SMDK4212_ULCON_DEFAULT,
- .ufcon = SMDK4212_UFCON_DEFAULT,
+ .ucon = SMDK4X12_UCON_DEFAULT,
+ .ulcon = SMDK4X12_ULCON_DEFAULT,
+ .ufcon = SMDK4X12_UFCON_DEFAULT,
},
};
-static struct s3c_sdhci_platdata smdk4212_hsmmc2_pdata __initdata = {
+static struct s3c_sdhci_platdata smdk4x12_hsmmc2_pdata __initdata = {
.cd_type = S3C_SDHCI_CD_INTERNAL,
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
@@ -90,7 +90,7 @@ static struct s3c_sdhci_platdata smdk4212_hsmmc2_pdata __initdata = {
#endif
};
-static struct s3c_sdhci_platdata smdk4212_hsmmc3_pdata __initdata = {
+static struct s3c_sdhci_platdata smdk4x12_hsmmc3_pdata __initdata = {
.cd_type = S3C_SDHCI_CD_INTERNAL,
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
};
@@ -106,7 +106,7 @@ static struct regulator_consumer_supply max8997_buck3 =
static struct regulator_init_data max8997_buck1_data = {
.constraints = {
- .name = "VDD_ARM_SMDK4212",
+ .name = "VDD_ARM_SMDK4X12",
.min_uV = 925000,
.max_uV = 1350000,
.always_on = 1,
@@ -121,7 +121,7 @@ static struct regulator_init_data max8997_buck1_data = {
static struct regulator_init_data max8997_buck2_data = {
.constraints = {
- .name = "VDD_INT_SMDK4212",
+ .name = "VDD_INT_SMDK4X12",
.min_uV = 950000,
.max_uV = 1150000,
.always_on = 1,
@@ -136,7 +136,7 @@ static struct regulator_init_data max8997_buck2_data = {
static struct regulator_init_data max8997_buck3_data = {
.constraints = {
- .name = "VDD_G3D_SMDK4212",
+ .name = "VDD_G3D_SMDK4X12",
.min_uV = 950000,
.max_uV = 1150000,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
@@ -149,15 +149,15 @@ static struct regulator_init_data max8997_buck3_data = {
.consumer_supplies = &max8997_buck3,
};
-static struct max8997_regulator_data smdk4212_max8997_regulators[] = {
+static struct max8997_regulator_data smdk4x12_max8997_regulators[] = {
{ MAX8997_BUCK1, &max8997_buck1_data },
{ MAX8997_BUCK2, &max8997_buck2_data },
{ MAX8997_BUCK3, &max8997_buck3_data },
};
-static struct max8997_platform_data smdk4212_max8997_pdata = {
- .num_regulators = ARRAY_SIZE(smdk4212_max8997_regulators),
- .regulators = smdk4212_max8997_regulators,
+static struct max8997_platform_data smdk4x12_max8997_pdata = {
+ .num_regulators = ARRAY_SIZE(smdk4x12_max8997_regulators),
+ .regulators = smdk4x12_max8997_regulators,
.buck1_voltage[0] = 1100000, /* 1.1V */
.buck1_voltage[1] = 1100000, /* 1.1V */
@@ -187,53 +187,53 @@ static struct max8997_platform_data smdk4212_max8997_pdata = {
.buck5_voltage[7] = 1100000, /* 1.1V */
};
-static struct i2c_board_info smdk4212_i2c_devs0[] __initdata = {
+static struct i2c_board_info smdk4x12_i2c_devs0[] __initdata = {
{
I2C_BOARD_INFO("max8997", 0x66),
- .platform_data = &smdk4212_max8997_pdata,
+ .platform_data = &smdk4x12_max8997_pdata,
}
};
-static struct i2c_board_info smdk4212_i2c_devs1[] __initdata = {
+static struct i2c_board_info smdk4x12_i2c_devs1[] __initdata = {
{ I2C_BOARD_INFO("wm8994", 0x1a), }
};
-static struct i2c_board_info smdk4212_i2c_devs3[] __initdata = {
+static struct i2c_board_info smdk4x12_i2c_devs3[] __initdata = {
/* nothing here yet */
};
-static struct i2c_board_info smdk4212_i2c_devs7[] __initdata = {
+static struct i2c_board_info smdk4x12_i2c_devs7[] __initdata = {
/* nothing here yet */
};
-static struct samsung_bl_gpio_info smdk4212_bl_gpio_info = {
+static struct samsung_bl_gpio_info smdk4x12_bl_gpio_info = {
.no = EXYNOS4_GPD0(1),
.func = S3C_GPIO_SFN(2),
};
-static struct platform_pwm_backlight_data smdk4212_bl_data = {
+static struct platform_pwm_backlight_data smdk4x12_bl_data = {
.pwm_id = 1,
.pwm_period_ns = 1000,
};
-static uint32_t smdk4212_keymap[] __initdata = {
+static uint32_t smdk4x12_keymap[] __initdata = {
/* KEY(row, col, keycode) */
KEY(1, 0, KEY_D), KEY(1, 1, KEY_A), KEY(1, 2, KEY_B),
KEY(1, 3, KEY_E), KEY(1, 4, KEY_C)
};
-static struct matrix_keymap_data smdk4212_keymap_data __initdata = {
- .keymap = smdk4212_keymap,
- .keymap_size = ARRAY_SIZE(smdk4212_keymap),
+static struct matrix_keymap_data smdk4x12_keymap_data __initdata = {
+ .keymap = smdk4x12_keymap,
+ .keymap_size = ARRAY_SIZE(smdk4x12_keymap),
};
-static struct samsung_keypad_platdata smdk4212_keypad_data __initdata = {
- .keymap_data = &smdk4212_keymap_data,
+static struct samsung_keypad_platdata smdk4x12_keypad_data __initdata = {
+ .keymap_data = &smdk4x12_keymap_data,
.rows = 2,
.cols = 5,
};
-static struct platform_device *smdk4212_devices[] __initdata = {
+static struct platform_device *smdk4x12_devices[] __initdata = {
&s3c_device_hsmmc2,
&s3c_device_hsmmc3,
&s3c_device_i2c0,
@@ -245,48 +245,58 @@ static struct platform_device *smdk4212_devices[] __initdata = {
&samsung_device_keypad,
};
-static void __init smdk4212_map_io(void)
+static void __init smdk4x12_map_io(void)
{
clk_xusbxti.rate = 24000000;
s5p_init_io(NULL, 0, S5P_VA_CHIPID);
s3c24xx_init_clocks(clk_xusbxti.rate);
- s3c24xx_init_uarts(smdk4212_uartcfgs, ARRAY_SIZE(smdk4212_uartcfgs));
+ s3c24xx_init_uarts(smdk4x12_uartcfgs, ARRAY_SIZE(smdk4x12_uartcfgs));
}
-static void __init smdk4212_machine_init(void)
+static void __init smdk4x12_machine_init(void)
{
s3c_i2c0_set_platdata(NULL);
- i2c_register_board_info(0, smdk4212_i2c_devs0,
- ARRAY_SIZE(smdk4212_i2c_devs0));
+ i2c_register_board_info(0, smdk4x12_i2c_devs0,
+ ARRAY_SIZE(smdk4x12_i2c_devs0));
s3c_i2c1_set_platdata(NULL);
- i2c_register_board_info(1, smdk4212_i2c_devs1,
- ARRAY_SIZE(smdk4212_i2c_devs1));
+ i2c_register_board_info(1, smdk4x12_i2c_devs1,
+ ARRAY_SIZE(smdk4x12_i2c_devs1));
s3c_i2c3_set_platdata(NULL);
- i2c_register_board_info(3, smdk4212_i2c_devs3,
- ARRAY_SIZE(smdk4212_i2c_devs3));
+ i2c_register_board_info(3, smdk4x12_i2c_devs3,
+ ARRAY_SIZE(smdk4x12_i2c_devs3));
s3c_i2c7_set_platdata(NULL);
- i2c_register_board_info(7, smdk4212_i2c_devs7,
- ARRAY_SIZE(smdk4212_i2c_devs7));
+ i2c_register_board_info(7, smdk4x12_i2c_devs7,
+ ARRAY_SIZE(smdk4x12_i2c_devs7));
- samsung_bl_set(&smdk4212_bl_gpio_info, &smdk4212_bl_data);
+ samsung_bl_set(&smdk4x12_bl_gpio_info, &smdk4x12_bl_data);
- samsung_keypad_set_platdata(&smdk4212_keypad_data);
+ samsung_keypad_set_platdata(&smdk4x12_keypad_data);
- s3c_sdhci2_set_platdata(&smdk4212_hsmmc2_pdata);
- s3c_sdhci3_set_platdata(&smdk4212_hsmmc3_pdata);
+ s3c_sdhci2_set_platdata(&smdk4x12_hsmmc2_pdata);
+ s3c_sdhci3_set_platdata(&smdk4x12_hsmmc3_pdata);
- platform_add_devices(smdk4212_devices, ARRAY_SIZE(smdk4212_devices));
+ platform_add_devices(smdk4x12_devices, ARRAY_SIZE(smdk4x12_devices));
}
MACHINE_START(SMDK4212, "SMDK4212")
/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
- .boot_params = S5P_PA_SDRAM + 0x100,
+ .atag_offset = 0x100,
.init_irq = exynos4_init_irq,
- .map_io = smdk4212_map_io,
- .init_machine = smdk4212_machine_init,
+ .map_io = smdk4x12_map_io,
+ .init_machine = smdk4x12_machine_init,
+ .timer = &exynos4_timer,
+MACHINE_END
+
+MACHINE_START(SMDK4412, "SMDK4412")
+ /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
+ /* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */
+ .atag_offset = 0x100,
+ .init_irq = exynos4_init_irq,
+ .map_io = smdk4x12_map_io,
+ .init_machine = smdk4x12_machine_init,
.timer = &exynos4_timer,
MACHINE_END
--
1.7.1
^ permalink raw reply related
* [PATCH 4/5] ARM: EXYNOS4: Add MCT support for EXYNOS4412
From: Kukjin Kim @ 2011-09-29 8:13 UTC (permalink / raw)
To: linux-arm-kernel
From: Changhwan Youn <chaos.youn@samsung.com>
Current MCT implementation only provide 2 event timers,
thus cannot support EXYNOS4412 which has 4 CPU cores.
This patch fixes MCT implementation to support SoCs
with 4 cores.
Signed-off-by: Changhwan Youn <chaos.youn@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
arch/arm/mach-exynos4/include/mach/regs-mct.h | 5 +-
arch/arm/mach-exynos4/mct.c | 113 ++++++++++++-------------
2 files changed, 56 insertions(+), 62 deletions(-)
diff --git a/arch/arm/mach-exynos4/include/mach/regs-mct.h b/arch/arm/mach-exynos4/include/mach/regs-mct.h
index ca9c843..80dd02a 100644
--- a/arch/arm/mach-exynos4/include/mach/regs-mct.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-mct.h
@@ -31,8 +31,9 @@
#define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248)
#define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C)
-#define EXYNOS4_MCT_L0_BASE EXYNOS4_MCTREG(0x300)
-#define EXYNOS4_MCT_L1_BASE EXYNOS4_MCTREG(0x400)
+#define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300)
+#define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x))
+#define EXYNOS4_MCT_L_MASK (0xffffff00)
#define MCT_L_TCNTB_OFFSET (0x00)
#define MCT_L_ICNTB_OFFSET (0x08)
diff --git a/arch/arm/mach-exynos4/mct.c b/arch/arm/mach-exynos4/mct.c
index f43f3fa..3fdcf7d 100644
--- a/arch/arm/mach-exynos4/mct.c
+++ b/arch/arm/mach-exynos4/mct.c
@@ -41,9 +41,10 @@ static unsigned int mct_int_type;
struct mct_clock_event_device {
struct clock_event_device *evt;
void __iomem *base;
+ char name[10];
};
-struct mct_clock_event_device mct_tick[2];
+struct mct_clock_event_device mct_tick[NR_CPUS];
static void exynos4_mct_write(unsigned int value, void *addr)
{
@@ -53,57 +54,53 @@ static void exynos4_mct_write(unsigned int value, void *addr)
__raw_writel(value, addr);
- switch ((u32) addr) {
- case (u32) EXYNOS4_MCT_G_TCON:
- stat_addr = EXYNOS4_MCT_G_WSTAT;
- mask = 1 << 16; /* G_TCON write status */
- break;
- case (u32) EXYNOS4_MCT_G_COMP0_L:
- stat_addr = EXYNOS4_MCT_G_WSTAT;
- mask = 1 << 0; /* G_COMP0_L write status */
- break;
- case (u32) EXYNOS4_MCT_G_COMP0_U:
- stat_addr = EXYNOS4_MCT_G_WSTAT;
- mask = 1 << 1; /* G_COMP0_U write status */
- break;
- case (u32) EXYNOS4_MCT_G_COMP0_ADD_INCR:
- stat_addr = EXYNOS4_MCT_G_WSTAT;
- mask = 1 << 2; /* G_COMP0_ADD_INCR write status */
- break;
- case (u32) EXYNOS4_MCT_G_CNT_L:
- stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
- mask = 1 << 0; /* G_CNT_L write status */
- break;
- case (u32) EXYNOS4_MCT_G_CNT_U:
- stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
- mask = 1 << 1; /* G_CNT_U write status */
- break;
- case (u32)(EXYNOS4_MCT_L0_BASE + MCT_L_TCON_OFFSET):
- stat_addr = EXYNOS4_MCT_L0_BASE + MCT_L_WSTAT_OFFSET;
- mask = 1 << 3; /* L0_TCON write status */
- break;
- case (u32)(EXYNOS4_MCT_L1_BASE + MCT_L_TCON_OFFSET):
- stat_addr = EXYNOS4_MCT_L1_BASE + MCT_L_WSTAT_OFFSET;
- mask = 1 << 3; /* L1_TCON write status */
- break;
- case (u32)(EXYNOS4_MCT_L0_BASE + MCT_L_TCNTB_OFFSET):
- stat_addr = EXYNOS4_MCT_L0_BASE + MCT_L_WSTAT_OFFSET;
- mask = 1 << 0; /* L0_TCNTB write status */
- break;
- case (u32)(EXYNOS4_MCT_L1_BASE + MCT_L_TCNTB_OFFSET):
- stat_addr = EXYNOS4_MCT_L1_BASE + MCT_L_WSTAT_OFFSET;
- mask = 1 << 0; /* L1_TCNTB write status */
- break;
- case (u32)(EXYNOS4_MCT_L0_BASE + MCT_L_ICNTB_OFFSET):
- stat_addr = EXYNOS4_MCT_L0_BASE + MCT_L_WSTAT_OFFSET;
- mask = 1 << 1; /* L0_ICNTB write status */
- break;
- case (u32)(EXYNOS4_MCT_L1_BASE + MCT_L_ICNTB_OFFSET):
- stat_addr = EXYNOS4_MCT_L1_BASE + MCT_L_WSTAT_OFFSET;
- mask = 1 << 1; /* L1_ICNTB write status */
- break;
- default:
- return;
+ if (likely(addr >= EXYNOS4_MCT_L_BASE(0))) {
+ u32 base = (u32) addr & EXYNOS4_MCT_L_MASK;
+ switch ((u32) addr & ~EXYNOS4_MCT_L_MASK) {
+ case (u32) MCT_L_TCON_OFFSET:
+ stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
+ mask = 1 << 3; /* L_TCON write status */
+ break;
+ case (u32) MCT_L_ICNTB_OFFSET:
+ stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
+ mask = 1 << 1; /* L_ICNTB write status */
+ break;
+ case (u32) MCT_L_TCNTB_OFFSET:
+ stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
+ mask = 1 << 0; /* L_TCNTB write status */
+ break;
+ default:
+ return;
+ }
+ } else {
+ switch ((u32) addr) {
+ case (u32) EXYNOS4_MCT_G_TCON:
+ stat_addr = EXYNOS4_MCT_G_WSTAT;
+ mask = 1 << 16; /* G_TCON write status */
+ break;
+ case (u32) EXYNOS4_MCT_G_COMP0_L:
+ stat_addr = EXYNOS4_MCT_G_WSTAT;
+ mask = 1 << 0; /* G_COMP0_L write status */
+ break;
+ case (u32) EXYNOS4_MCT_G_COMP0_U:
+ stat_addr = EXYNOS4_MCT_G_WSTAT;
+ mask = 1 << 1; /* G_COMP0_U write status */
+ break;
+ case (u32) EXYNOS4_MCT_G_COMP0_ADD_INCR:
+ stat_addr = EXYNOS4_MCT_G_WSTAT;
+ mask = 1 << 2; /* G_COMP0_ADD_INCR write status */
+ break;
+ case (u32) EXYNOS4_MCT_G_CNT_L:
+ stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
+ mask = 1 << 0; /* G_CNT_L write status */
+ break;
+ case (u32) EXYNOS4_MCT_G_CNT_U:
+ stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
+ mask = 1 << 1; /* G_CNT_U write status */
+ break;
+ default:
+ return;
+ }
}
/* Wait maximum 1 ms until written values are applied */
@@ -332,7 +329,7 @@ static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
}
}
-static inline int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
+static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
{
struct clock_event_device *evt = mevt->evt;
@@ -383,14 +380,10 @@ static void exynos4_mct_tick_init(struct clock_event_device *evt)
mct_tick[cpu].evt = evt;
- if (cpu == 0) {
- mct_tick[cpu].base = EXYNOS4_MCT_L0_BASE;
- evt->name = "mct_tick0";
- } else {
- mct_tick[cpu].base = EXYNOS4_MCT_L1_BASE;
- evt->name = "mct_tick1";
- }
+ mct_tick[cpu].base = EXYNOS4_MCT_L_BASE(cpu);
+ sprintf(mct_tick[cpu].name, "mct_tick%d", cpu);
+ evt->name = mct_tick[cpu].name;
evt->cpumask = cpumask_of(cpu);
evt->set_next_event = exynos4_tick_set_next_event;
evt->set_mode = exynos4_tick_set_mode;
--
1.7.1
^ permalink raw reply related
* [PATCH 3/5] ARM: EXYNOS4: Add functions for gic interrupt handling
From: Kukjin Kim @ 2011-09-29 8:12 UTC (permalink / raw)
To: linux-arm-kernel
From: Changhwan Youn <chaos.youn@samsung.com>
This patch adds two functions for gic interrupt handling.
1. Add interrupt handling of 4 cores.
2. Dynamically set gic bank offset according to the type of soc.
Gic bank offset of EXYNOS4412 is 0x4000 while the offset of
EXYNOS4210 and EXYNOS4212 is 0x8000.
This patch is necessary because EXYNOS4 socs cannot support
GIC register banking as described in commit aab74d3e75364.
Signed-off-by: Changhwan Youn <chaos.youn@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
arch/arm/mach-exynos4/cpu.c | 8 +++++-
arch/arm/mach-exynos4/include/mach/entry-macro.S | 23 +++++++++++++++++----
arch/arm/mach-exynos4/include/mach/map.h | 1 -
arch/arm/mach-exynos4/platsmp.c | 5 ++-
4 files changed, 27 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c
index 74d50d1..5b1765b 100644
--- a/arch/arm/mach-exynos4/cpu.c
+++ b/arch/arm/mach-exynos4/cpu.c
@@ -33,6 +33,8 @@
#include <mach/regs-irq.h>
#include <mach/regs-pmu.h>
+unsigned int gic_bank_offset __read_mostly;
+
extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
unsigned int irq_start);
extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
@@ -205,16 +207,18 @@ static void exynos4_gic_irq_fix_base(struct irq_data *d)
struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
gic_data->cpu_base = S5P_VA_GIC_CPU +
- (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
+ (gic_bank_offset * smp_processor_id());
gic_data->dist_base = S5P_VA_GIC_DIST +
- (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
+ (gic_bank_offset * smp_processor_id());
}
void __init exynos4_init_irq(void)
{
int irq;
+ gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
+
gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
gic_arch_extn.irq_eoi = exynos4_gic_irq_fix_base;
gic_arch_extn.irq_unmask = exynos4_gic_irq_fix_base;
diff --git a/arch/arm/mach-exynos4/include/mach/entry-macro.S b/arch/arm/mach-exynos4/include/mach/entry-macro.S
index 61393dc..4c9adbd 100644
--- a/arch/arm/mach-exynos4/include/mach/entry-macro.S
+++ b/arch/arm/mach-exynos4/include/mach/entry-macro.S
@@ -17,12 +17,25 @@
.endm
.macro get_irqnr_preamble, base, tmp
- ldr \base, =gic_cpu_base_addr
+ mov \tmp, #0
+
+ mrc p15, 0, \base, c0, c0, 5
+ and \base, \base, #3
+ cmp \base, #0
+ beq 1f
+
+ ldr \tmp, =gic_bank_offset
+ ldr \tmp, [\tmp]
+ cmp \base, #1
+ beq 1f
+
+ cmp \base, #2
+ addeq \tmp, \tmp, \tmp
+ addne \tmp, \tmp, \tmp, LSL #1
+
+1: ldr \base, =gic_cpu_base_addr
ldr \base, [\base]
- mrc p15, 0, \tmp, c0, c0, 5
- and \tmp, \tmp, #3
- cmp \tmp, #1
- addeq \base, \base, #EXYNOS4_GIC_BANK_OFFSET
+ add \base, \base, \tmp
.endm
.macro arch_ret_to_user, tmp1, tmp2
diff --git a/arch/arm/mach-exynos4/include/mach/map.h b/arch/arm/mach-exynos4/include/mach/map.h
index 1bea7d1..918a979 100644
--- a/arch/arm/mach-exynos4/include/mach/map.h
+++ b/arch/arm/mach-exynos4/include/mach/map.h
@@ -62,7 +62,6 @@
#define EXYNOS4_PA_GIC_CPU 0x10480000
#define EXYNOS4_PA_GIC_DIST 0x10490000
-#define EXYNOS4_GIC_BANK_OFFSET 0x8000
#define EXYNOS4_PA_COREPERI 0x10500000
#define EXYNOS4_PA_TWD 0x10500600
diff --git a/arch/arm/mach-exynos4/platsmp.c b/arch/arm/mach-exynos4/platsmp.c
index a3346e3..d5f0f29 100644
--- a/arch/arm/mach-exynos4/platsmp.c
+++ b/arch/arm/mach-exynos4/platsmp.c
@@ -32,6 +32,7 @@
#include <plat/cpu.h>
+extern unsigned int gic_bank_offset;
extern void exynos4_secondary_startup(void);
#define CPU1_BOOT_REG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
@@ -67,9 +68,9 @@ static DEFINE_SPINLOCK(boot_lock);
static void __cpuinit exynos4_gic_secondary_init(void)
{
void __iomem *dist_base = S5P_VA_GIC_DIST +
- (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
+ (gic_bank_offset * smp_processor_id());
void __iomem *cpu_base = S5P_VA_GIC_CPU +
- (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
+ (gic_bank_offset * smp_processor_id());
int i;
/*
--
1.7.1
^ permalink raw reply related
* [PATCH 2/5] ARM: EXYNOS4: Add support clock for EXYNOS4412
From: Kukjin Kim @ 2011-09-29 8:12 UTC (permalink / raw)
To: linux-arm-kernel
From: Changhwan Youn <chaos.youn@samsung.com>
This patch makes EXYNOS4412 use same clock code for
EXYNOS4212 because the clock hierarchy of both SoCs
are same.
Signed-off-by: Changhwan Youn <chaos.youn@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
arch/arm/mach-exynos4/clock.c | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c
index a25c818..db61691 100644
--- a/arch/arm/mach-exynos4/clock.c
+++ b/arch/arm/mach-exynos4/clock.c
@@ -1283,7 +1283,7 @@ static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
if (soc_is_exynos4210())
return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0),
pll_4508);
- else if (soc_is_exynos4212())
+ else if (soc_is_exynos4212() || soc_is_exynos4412())
return s5p_get_pll35xx(xtal_rate, __raw_readl(S5P_APLL_CON0));
else
return 0;
@@ -1399,7 +1399,7 @@ void __init_or_cpufreq exynos4_setup_clocks(void)
vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
__raw_readl(S5P_VPLL_CON1), pll_4650c);
- } else if (soc_is_exynos4212()) {
+ } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
apll = s5p_get_pll35xx(xtal, __raw_readl(S5P_APLL_CON0));
mpll = s5p_get_pll35xx(xtal, __raw_readl(S5P_MPLL_CON0));
epll = s5p_get_pll36xx(xtal, __raw_readl(S5P_EPLL_CON0),
--
1.7.1
^ permalink raw reply related
* [PATCH 1/5] ARM: EXYNOS4: Add support new EXYNOS4412 SoC
From: Kukjin Kim @ 2011-09-29 8:12 UTC (permalink / raw)
To: linux-arm-kernel
From: Changhwan Youn <chaos.youn@samsung.com>
This patch adds Samsung EXYNOS4412 SoC support.
The EXYNOS4412 integrates a ARM Cortex A9 quad-core.
Signed-off-by: Changhwan Youn <chaos.youn@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
arch/arm/mach-exynos4/Kconfig | 5 +++++
arch/arm/mach-exynos4/cpu.c | 4 ++--
arch/arm/plat-s5p/cpu.c | 9 +++++++++
arch/arm/plat-samsung/include/plat/cpu.h | 8 ++++++++
4 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-exynos4/Kconfig b/arch/arm/mach-exynos4/Kconfig
index d0491c2..bf3e21d 100644
--- a/arch/arm/mach-exynos4/Kconfig
+++ b/arch/arm/mach-exynos4/Kconfig
@@ -20,6 +20,11 @@ config SOC_EXYNOS4212
help
Enable EXYNOS4212 SoC support
+config SOC_EXYNOS4412
+ bool
+ help
+ Enable EXYNOS4412 SoC support
+
config EXYNOS4_MCT
bool
default y
diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c
index 9d5a171..74d50d1 100644
--- a/arch/arm/mach-exynos4/cpu.c
+++ b/arch/arm/mach-exynos4/cpu.c
@@ -193,7 +193,7 @@ void __init exynos4_init_clocks(int xtal)
if (soc_is_exynos4210())
exynos4210_register_clocks();
- else if (soc_is_exynos4212())
+ else if (soc_is_exynos4212() || soc_is_exynos4412())
exynos4212_register_clocks();
exynos4_register_clocks();
@@ -257,7 +257,7 @@ static int __init exynos4_l2x0_cache_init(void)
if (soc_is_exynos4210())
__raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
- else if (soc_is_exynos4212())
+ else if (soc_is_exynos4212() || soc_is_exynos4412())
__raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
/* L2X0 Prefetch Control */
diff --git a/arch/arm/plat-s5p/cpu.c b/arch/arm/plat-s5p/cpu.c
index 909507b..7b0a28f 100644
--- a/arch/arm/plat-s5p/cpu.c
+++ b/arch/arm/plat-s5p/cpu.c
@@ -34,6 +34,7 @@ static const char name_s5pc100[] = "S5PC100";
static const char name_s5pv210[] = "S5PV210/S5PC110";
static const char name_exynos4210[] = "EXYNOS4210";
static const char name_exynos4212[] = "EXYNOS4212";
+static const char name_exynos4412[] = "EXYNOS4412";
static struct cpu_table cpu_ids[] __initdata = {
{
@@ -84,6 +85,14 @@ static struct cpu_table cpu_ids[] __initdata = {
.init_uarts = exynos4_init_uarts,
.init = exynos4_init,
.name = name_exynos4212,
+ }, {
+ .idcode = EXYNOS4412_CPU_ID,
+ .idmask = EXYNOS4_CPU_MASK,
+ .map_io = exynos4_map_io,
+ .init_clocks = exynos4_init_clocks,
+ .init_uarts = exynos4_init_uarts,
+ .init = exynos4_init,
+ .name = name_exynos4412,
},
};
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 1bbbbb4..54f370f 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -40,6 +40,7 @@ extern unsigned long samsung_cpu_id;
#define EXYNOS4210_CPU_ID 0x43210000
#define EXYNOS4212_CPU_ID 0x43220000
+#define EXYNOS4412_CPU_ID 0xE4412200
#define EXYNOS4_CPU_MASK 0xFFFE0000
#define IS_SAMSUNG_CPU(name, id, mask) \
@@ -56,6 +57,7 @@ IS_SAMSUNG_CPU(s5pc100, S5PC100_CPU_ID, S5PC100_CPU_MASK)
IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK)
IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
+IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2440) || \
@@ -108,6 +110,12 @@ IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
# define soc_is_exynos4212() 0
#endif
+#if defined(CONFIG_SOC_EXYNOS4412)
+# define soc_is_exynos4412() is_samsung_exynos4412()
+#else
+# define soc_is_exynos4412() 0
+#endif
+
#define EXYNOS4210_REV_0 (0x0)
#define EXYNOS4210_REV_1_0 (0x10)
#define EXYNOS4210_REV_1_1 (0x11)
--
1.7.1
^ permalink raw reply related
* [PATCH 0/5] ARM: EXYNOS4: Add support for EXYNOS4412 SoC
From: Kukjin Kim @ 2011-09-29 8:12 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds support for EXYNOS4412 SoC which integrates a ARM Cortex A9 quad-core.
[PATCH 1/5] ARM: EXYNOS4: Add support new EXYNOS4412 SoC
[PATCH 2/5] ARM: EXYNOS4: Add support clock for EXYNOS4412
[PATCH 3/5] ARM: EXYNOS4: Add functions for gic interrupt handling
[PATCH 4/5] ARM: EXYNOS4: Add MCT support for EXYNOS4412
[PATCH 5/5] ARM: EXYNOS4: Add support SMDK4412 Board
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply
* [PATCH] leds-class: change back LEDS_CLASS to tristate instead of bool
From: Russell King - ARM Linux @ 2011-09-29 7:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAK5ve-KoanwFGFJcxGQGmAW0yR+MYR1uVGM5q+=8u_ofHrhwOQ@mail.gmail.com>
On Thu, Sep 29, 2011 at 10:00:58AM +0800, Bryan Wu wrote:
> Hiya,
>
> Any comments and need I do anything to improve this patch?
No idea, I don't remember the original errors which this stuff spat out
and how they were caused.
The only thing I care about is that the conversion of the existing ARM
LEDs support to the NEW_LEDS stuff doesn't cause any breakage.
^ permalink raw reply
* [PATCH] ARM: pxa/cm-x300: properly set bt_reset pin
From: Axel Lin @ 2011-09-29 7:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4E7B0E35.5010607@compulab.co.il>
2011/9/22 Igor Grinberg <grinberg@compulab.co.il>:
> Hi Axel,
>
> On 09/17/11 17:15, Axel Lin wrote:
>> Fix below build warning and properly set bt_reset pin.
>>
>> ? CC ? ? ?arch/arm/mach-pxa/cm-x300.o
>> arch/arm/mach-pxa/cm-x300.c: In function 'cm_x300_init_wi2wi':
>> arch/arm/mach-pxa/cm-x300.c:779: warning: unused variable 'wlan_en'
>> arch/arm/mach-pxa/cm-x300.c:795: warning: 'bt_reset' may be used uninitialized in this function
>
> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
>
> Also, this patch fixes a real regression since
> 5a009df1f200efa49658b0e9c7ad056d59fbefe4 (ARM: pxa/cm-x300: GPIO cleanup)
> - Wifi and Bluetooth do not work without it, so please:
>
> Cc: <stable@kernel.org> [3.0.x]
>
Hi, Eric,
Just to pin the status of this patch. I think it should go for 3.1.
Thanks,
Axel
^ permalink raw reply
* [patch] ARM: smpboot: Enable interrupts after marking CPU online/active
From: Kukjin Kim @ 2011-09-29 7:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110923084001.GP17169@n2100.arm.linux.org.uk>
Russell King - ARM Linux wrote:
>
> On Tue, Sep 13, 2011 at 06:53:12PM +0100, Russell King - ARM Linux wrote:
> > So, we must have the setting of CPU online _after_ we've setup the
> > scheduler domain information etc - so the following is a strict
> > ordering:
> >
> > 1. calibrate_delay()
> > 2. smp_store_cpu_info()
> > 3. set_cpu_online()
> >
> > Now, the question is do we need interrupts enabled to setup timers
> > via percpu_timer_setup() and calibrate delay. Can we move enabling
> > interrupts after smp_store_cpu_info(). IOW, instead of moving the
> > setting of cpu online before all this, can we move notify_cpu_starting()
> > and the enabling of _both_ interrupts after smp_store_cpu_info()...
> > No idea at the moment.
>
> And to make things worse... 4bd0fe1c78623062263cf5ae875fd484c5b8256d
> has appeared in mainline today.
>
> diff --git a/arch/arm/mach-exynos4/platsmp.c
b/arch/arm/mach-exynos4/platsmp.c
> index 7c2282c..df6ef1b 100644
> --- a/arch/arm/mach-exynos4/platsmp.c
> +++ b/arch/arm/mach-exynos4/platsmp.c
> @@ -106,6 +106,8 @@ void __cpuinit platform_secondary_init(unsigned int
cpu)
> */
> spin_lock(&boot_lock);
> spin_unlock(&boot_lock);
> +
> + set_cpu_online(cpu, true);
> }
>
> int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
>
> I think some work needs to be done to eliminate some of the dependencies
> in this code so that we can have a *sane* order for bringup of secondary
> CPUs.
>
Hi Russell,
Oops, as you said, it seems not proper place, platform_secondary_init() to
make secondary CPU online so I will submit its revert patch.
But as Amit said, current EXYNOS4 SoCs which are using SPI for local timers
has problem that the irq_set_affinity() method is called in
percpu_timer_setup() before CPU1 becomes online with the commit
5dfc54e087c15f823ee9b6541d2f0f314e69cbed ("ARM: GIC: avoid routing
interrupts to offline CPUs"). So I will check again.
If you have any ideas, please kindly let me know.
> I'm just going to sit on the fence and watch what platform people do
> during the next merge window when the support for the topological
> scheduler goes in.
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply
* [PATCH 2/2] ARM: EXYNOS4: Add support MCT PPI for EXYNOS4212
From: Kukjin Kim @ 2011-09-29 7:25 UTC (permalink / raw)
To: linux-arm-kernel
From: Changhwan Youn <chaos.youn@samsung.com>
This patch implements clock event timer using MCT PPI
and make EXYNOS4212 use MCT PPI instead of MCT SPI.
Signed-off-by: Changhwan Youn <chaos.youn@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
arch/arm/mach-exynos4/include/mach/entry-macro.S | 6 ++
arch/arm/mach-exynos4/include/mach/irqs.h | 2 +
arch/arm/mach-exynos4/mct.c | 55 ++++++++++++++++++----
3 files changed, 53 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-exynos4/include/mach/entry-macro.S b/arch/arm/mach-exynos4/include/mach/entry-macro.S
index d7a1e28..c09ab4c 100644
--- a/arch/arm/mach-exynos4/include/mach/entry-macro.S
+++ b/arch/arm/mach-exynos4/include/mach/entry-macro.S
@@ -80,4 +80,10 @@
/* As above, this assumes that irqstat and base are preserved.. */
.macro test_for_ltirq, irqnr, irqstat, base, tmp
+ bic \irqnr, \irqstat, #0x1c00
+ mov \tmp, #0
+ cmp \irqnr, #28
+ moveq \tmp, #1
+ streq \irqstat, [\base, #GIC_CPU_EOI]
+ cmp \tmp, #0
.endm
diff --git a/arch/arm/mach-exynos4/include/mach/irqs.h b/arch/arm/mach-exynos4/include/mach/irqs.h
index 62093b9..dfd4b7e 100644
--- a/arch/arm/mach-exynos4/include/mach/irqs.h
+++ b/arch/arm/mach-exynos4/include/mach/irqs.h
@@ -19,6 +19,8 @@
#define IRQ_PPI(x) S5P_IRQ(x+16)
+#define IRQ_MCT_LOCALTIMER IRQ_PPI(12)
+
/* SPI: Shared Peripheral Interrupt */
#define IRQ_SPI(x) S5P_IRQ(x+32)
diff --git a/arch/arm/mach-exynos4/mct.c b/arch/arm/mach-exynos4/mct.c
index ddd8686..f43f3fa 100644
--- a/arch/arm/mach-exynos4/mct.c
+++ b/arch/arm/mach-exynos4/mct.c
@@ -20,12 +20,23 @@
#include <linux/delay.h>
#include <linux/percpu.h>
+#include <asm/hardware/gic.h>
+
+#include <plat/cpu.h>
+
#include <mach/map.h>
+#include <mach/irqs.h>
#include <mach/regs-mct.h>
#include <asm/mach/time.h>
+enum {
+ MCT_INT_SPI,
+ MCT_INT_PPI
+};
+
static unsigned long clk_cnt_per_tick;
static unsigned long clk_rate;
+static unsigned int mct_int_type;
struct mct_clock_event_device {
struct clock_event_device *evt;
@@ -321,9 +332,8 @@ static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
}
}
-static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
+static inline int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
{
- struct mct_clock_event_device *mevt = dev_id;
struct clock_event_device *evt = mevt->evt;
/*
@@ -335,7 +345,20 @@ static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
exynos4_mct_tick_stop(mevt);
/* Clear the MCT tick interrupt */
- exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
+ if (__raw_readl(mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
+ exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
+static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
+{
+ struct mct_clock_event_device *mevt = dev_id;
+ struct clock_event_device *evt = mevt->evt;
+
+ exynos4_mct_tick_clear(mevt);
evt->event_handler(evt);
@@ -384,13 +407,17 @@ static void exynos4_mct_tick_init(struct clock_event_device *evt)
exynos4_mct_write(0x1, mct_tick[cpu].base + MCT_L_TCNTB_OFFSET);
- if (cpu == 0) {
- mct_tick0_event_irq.dev_id = &mct_tick[cpu];
- setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq);
+ if (mct_int_type == MCT_INT_SPI) {
+ if (cpu == 0) {
+ mct_tick0_event_irq.dev_id = &mct_tick[cpu];
+ setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq);
+ } else {
+ mct_tick1_event_irq.dev_id = &mct_tick[cpu];
+ setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq);
+ irq_set_affinity(IRQ_MCT_L1, cpumask_of(1));
+ }
} else {
- mct_tick1_event_irq.dev_id = &mct_tick[cpu];
- setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq);
- irq_set_affinity(IRQ_MCT_L1, cpumask_of(1));
+ gic_enable_ppi(IRQ_MCT_LOCALTIMER);
}
}
@@ -404,7 +431,10 @@ int __cpuinit local_timer_setup(struct clock_event_device *evt)
int local_timer_ack(void)
{
- return 0;
+ unsigned int cpu = smp_processor_id();
+ struct mct_clock_event_device *mevt = &mct_tick[cpu];
+
+ return exynos4_mct_tick_clear(mevt);
}
#endif /* CONFIG_LOCAL_TIMERS */
@@ -419,6 +449,11 @@ static void __init exynos4_timer_resources(void)
static void __init exynos4_timer_init(void)
{
+ if (soc_is_exynos4210())
+ mct_int_type = MCT_INT_SPI;
+ else
+ mct_int_type = MCT_INT_PPI;
+
exynos4_timer_resources();
exynos4_clocksource_init();
exynos4_clockevent_init();
--
1.7.1
^ permalink raw reply related
* [PATCH 1/2] ARM: EXYNOS4: Add support PPI in external GIC
From: Kukjin Kim @ 2011-09-29 7:24 UTC (permalink / raw)
To: linux-arm-kernel
From: Changhwan Youn <chaos.youn@samsung.com>
To support PPI in external GIC of EXYNOS4 SoCs,
gic_arch_extn.irq_eoi, irq_unmask and irq_mask are
fixed. This patch is necessary because external GIC of EXYNOS4
cannot support register banking.
Signed-off-by: Changhwan Youn <chaos.youn@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
arch/arm/mach-exynos4/cpu.c | 11 ++++++++---
1 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c
index 2aa3df0..9d5a171 100644
--- a/arch/arm/mach-exynos4/cpu.c
+++ b/arch/arm/mach-exynos4/cpu.c
@@ -200,20 +200,25 @@ void __init exynos4_init_clocks(int xtal)
exynos4_setup_clocks();
}
-static void exynos4_gic_irq_eoi(struct irq_data *d)
+static void exynos4_gic_irq_fix_base(struct irq_data *d)
{
struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
gic_data->cpu_base = S5P_VA_GIC_CPU +
(EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
+
+ gic_data->dist_base = S5P_VA_GIC_DIST +
+ (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
}
void __init exynos4_init_irq(void)
{
int irq;
- gic_init(0, IRQ_SPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
- gic_arch_extn.irq_eoi = exynos4_gic_irq_eoi;
+ gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
+ gic_arch_extn.irq_eoi = exynos4_gic_irq_fix_base;
+ gic_arch_extn.irq_unmask = exynos4_gic_irq_fix_base;
+ gic_arch_extn.irq_mask = exynos4_gic_irq_fix_base;
for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
--
1.7.1
^ permalink raw reply related
* [PATCH 0/2] ARM: EXYNOS4: Add support for MCT PPI
From: Kukjin Kim @ 2011-09-29 7:24 UTC (permalink / raw)
To: linux-arm-kernel
This patch is required to support upcoming Samsung SoCs.
Current MCT can support only SPI for local timers but upcoming EXYNOS SoCs
doesn't have SPI for local timers.
NOTE:
This patches will not work with Marc Zyngier's "ARM: gic: consolidate
PPI handling". It means if his patch is applied, this should be dropped
and re-worked.
[PATCH 1/2] ARM: EXYNOS4: Add support PPI in external GIC
[PATCH 2/2] ARM: EXYNOS4: Add support MCT PPI for EXYNOS4212
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply
* Perf support for OMAP4
From: Ming Lei @ 2011-09-29 7:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110928155437.GA18202@e102144-lin.cambridge.arm.com>
Hi,
On Wed, Sep 28, 2011 at 11:54 PM, Will Deacon <will.deacon@arm.com> wrote:
> Hi Tom,
>
> I can't see your OMAP4 Perf/PMU patches from here:
>
> http://lists.infradead.org/pipermail/linux-arm-kernel/2011-March/045283.html
>
> in mainline or next.
>
> Are you still pushing these or did you get blocked awaiting feedback?
OK, I will rebase the patch against -next tree and resend it later.
thanks,
--
Ming Lei
^ permalink raw reply
* [PATCH] usb: musb: OMAP4430: Remove a redundant omap4430_phy_init call in usb_musb_init
From: Felipe Balbi @ 2011-09-29 7:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1316508629.14514.2.camel@phoenix>
On Tue, Sep 20, 2011 at 04:50:29PM +0800, Axel Lin wrote:
> Current code calls omap4430_phy_init() twice in usb_musb_init().
> Calling omap4430_phy_init() once is enough.
> This patch removes the first omap4430_phy_init() call, which using an
> uninitialized pointer as parameter.
>
> This patch elimates below build warning:
> arch/arm/mach-omap2/usb-musb.c: In function 'usb_musb_init':
> arch/arm/mach-omap2/usb-musb.c:141: warning: 'dev' may be used uninitialized in this function
>
> Signed-off-by: Axel Lin <axel.lin@gmail.com>
Acked-by: Felipe Balbi <balbi@ti.com>
> ---
> arch/arm/mach-omap2/usb-musb.c | 3 ---
> 1 files changed, 0 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
> index a65145b..19e4dac 100644
> --- a/arch/arm/mach-omap2/usb-musb.c
> +++ b/arch/arm/mach-omap2/usb-musb.c
> @@ -137,9 +137,6 @@ void __init usb_musb_init(struct omap_musb_board_data *musb_board_data)
> musb_plat.mode = board_data->mode;
> musb_plat.extvbus = board_data->extvbus;
>
> - if (cpu_is_omap44xx())
> - omap4430_phy_init(dev);
> -
> if (cpu_is_omap3517() || cpu_is_omap3505()) {
> oh_name = "am35x_otg_hs";
> name = "musb-am35x";
> --
> 1.7.4.1
>
>
>
--
balbi
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^ permalink raw reply
* [PATCHv2 02/10] ARM: vic: MULTI_IRQ_HANDLER handler
From: Linus Walleij @ 2011-09-29 6:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110928203905.GB2838@ponder.secretlab.ca>
On Wed, Sep 28, 2011 at 10:39 PM, Grant Likely
<grant.likely@secretlab.ca> wrote:
> Why isn't it simply written this way:
>
> ? ? ? ?stat = readl_relaxed(vic->base + VIC_IRQ_STATUS);
> ? ? ? ?while (stat) {
> ? ? ? ? ? ? ? ?irq = fls(stat) - 1;
> ? ? ? ? ? ? ? ?handle_IRQ(irq_domain_to_irq(&vic->domain, irq), regs);
> ? ? ? ? ? ? ? ?stat &= ~(1 << irq);
> ? ? ? ?}
That is indeed closer to the assembly loop most platforms have
implemented.
Jamie can you test this approach? And also use ffs() insteadof
fls()...
Thanks,
Linus Walleij
^ permalink raw reply
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