* [PATCH 16/26] ARM: pxa: CPU_PJ4 requires IWMMXT
From: Eric Miao @ 2011-10-04 0:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20295619.jOfPxmug8T@wuerfel>
> 8<-----
> Subject: [PATCH] ARM: pxa: CPU_PJ4 requires IWMMXT
>
> The PJ4 based pxa95x cpus all have iwmmxt and there is no way to
> build that code conditionally, so better not ask the user
> in that configuration, in order to prevent broken builds.
I think this is true for other xscale CPUs as well, so either we make
them unconditionally all at once, or we still leave an option here.
It actually looks quite odd to me that CPU_PJ4 is made special here,
what're the real broken builds errors?
>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 5ebc5d9..8d66c32 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -1071,9 +1071,10 @@ config ARM_TIMER_SP804
> ?source arch/arm/mm/Kconfig
>
> ?config IWMMXT
> - ? ? ? bool "Enable iWMMXt support"
> + ? ? ? bool "Enable iWMMXt support" if !CPU_PJ4
> ? ? ? ?depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
> ? ? ? ?default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
> + ? ? ? default y if CPU_PJ4
> ? ? ? ?help
> ? ? ? ? ?Enable support for iWMMXt context switching at run time if
> ? ? ? ? ?running on a CPU that supports it.
>
^ permalink raw reply
* [RFC PATCH] tty/serial: atmel_serial: add device tree support
From: Rob Herring @ 2011-10-04 1:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1317635502-9430-1-git-send-email-nicolas.ferre@atmel.com>
On 10/03/2011 04:51 AM, Nicolas Ferre wrote:
> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
> ---
> Hi,
>
> Here is a first attempt to add device tree support to atmel_serial driver.
> RS485 data are not handled for the moment. My feeling is that they should be
> added as a generic DT biding set.
Feel free to propose something. :)
>
>
> .../devicetree/bindings/tty/serial/atmel-usart.txt | 27 +++++++++
> drivers/tty/serial/atmel_serial.c | 56 +++++++++++++++++---
> 2 files changed, 75 insertions(+), 8 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/tty/serial/atmel-usart.txt
>
> diff --git a/Documentation/devicetree/bindings/tty/serial/atmel-usart.txt b/Documentation/devicetree/bindings/tty/serial/atmel-usart.txt
> new file mode 100644
> index 0000000..a49d9a1
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/tty/serial/atmel-usart.txt
> @@ -0,0 +1,27 @@
> +* Atmel Universal Synchronous Asynchronous Receiver/Transmitter (USART)
> +
> +Required properties:
> +- compatible: Should be "atmel,<chip>-usart"
> + The compatible <chip> indicated will be the first SoC to support an
> + additional mode or an USART new feature.
> +- reg: Should contain registers location and length
> +- interrupts: Should contain interrupt
> +
> +Optional properties:
> +- atmel,use-dma-rx: use of PDC or DMA for receiving data
> +- atmel,use-dma-tx: use of PDC or DMA for transmitting data
Is this an internal DMA or separate DMA controller? If the latter, these
should be phandles to a DMA channel/request.
> +
> +<chip> compatible description:
> +- at91rm9200: legacy USART support
> +- at91sam9260: generic USART implementation for SAM9 SoCs
> +
> +Example:
> +
> + usart0: serial at fff8c000 {
> + compatible = "atmel,at91sam9260-usart";
> + reg = <0xfff8c000 0x4000>;
> + interrupts = <7>;
> + atmel,use-dma-rx;
> + atmel,use-dma-tx;
> + };
> +
> diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c
> index 453cdb5..65f56c3 100644
> --- a/drivers/tty/serial/atmel_serial.c
> +++ b/drivers/tty/serial/atmel_serial.c
> @@ -33,6 +33,8 @@
> #include <linux/sysrq.h>
> #include <linux/tty_flip.h>
> #include <linux/platform_device.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> #include <linux/dma-mapping.h>
> #include <linux/atmel_pdc.h>
> #include <linux/atmel_serial.h>
> @@ -162,6 +164,16 @@ static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
> static struct console atmel_console;
> #endif
>
> +#if defined(CONFIG_OF)
> +static const struct of_device_id atmel_serial_dt_ids[] = {
> + { .compatible = "atmel,at91rm9200-usart" },
> + { .compatible = "atmel,at91sam9260-usart" },
> + { /* sentinel */ }
> +};
> +
> +MODULE_DEVICE_TABLE(of, atmel_serial_dt_ids);
> +#endif
This ifdef isn't necessary, but it really depends if long term this
driver will be built without OF (and you care about the extra data).
> +
> static inline struct atmel_uart_port *
> to_atmel_uart_port(struct uart_port *uart)
> {
> @@ -1413,14 +1425,31 @@ static struct uart_ops atmel_pops = {
> static void __devinit atmel_init_port(struct atmel_uart_port *atmel_port,
> struct platform_device *pdev)
> {
> + struct device_node *np = pdev->dev.of_node;
> struct uart_port *port = &atmel_port->uart;
> struct atmel_uart_data *pdata = pdev->dev.platform_data;
> + int ret;
> +
> + if (np) {
> + ret = of_alias_get_id(np, "serial");
> + if (ret >= 0)
> + port->line = ret;
> + if (of_get_property(np, "atmel,use-dma-rx", NULL))
> + atmel_port->use_dma_rx = 1;
> + if (of_get_property(np, "atmel,use-dma-tx", NULL))
> + atmel_port->use_dma_tx = 1;
> + } else {
> + port->line = pdata->num;
> +
> + atmel_port->use_dma_rx = pdata->use_dma_rx;
> + atmel_port->use_dma_tx = pdata->use_dma_tx;
> + atmel_port->rs485 = pdata->rs485;
> + }
>
> port->iotype = UPIO_MEM;
> port->flags = UPF_BOOT_AUTOCONF;
> port->ops = &atmel_pops;
> port->fifosize = 1;
> - port->line = pdata->num;
> port->dev = &pdev->dev;
> port->mapbase = pdev->resource[0].start;
> port->irq = pdev->resource[1].start;
> @@ -1430,7 +1459,7 @@ static void __devinit atmel_init_port(struct atmel_uart_port *atmel_port,
>
> memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
>
> - if (pdata->regs) {
> + if (pdata && pdata->regs) {
> /* Already mapped by setup code */
> port->membase = pdata->regs;
> } else {
> @@ -1447,10 +1476,6 @@ static void __devinit atmel_init_port(struct atmel_uart_port *atmel_port,
> /* only enable clock when USART is in use */
> }
>
> - atmel_port->use_dma_rx = pdata->use_dma_rx;
> - atmel_port->use_dma_tx = pdata->use_dma_tx;
> - atmel_port->rs485 = pdata->rs485;
> -
> /* Use TXEMPTY for interrupt when rs485 else TXRDY or ENDTX|TXBUFE */
> if (atmel_port->rs485.flags & SER_RS485_ENABLED)
> atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
> @@ -1710,13 +1735,27 @@ static int atmel_serial_resume(struct platform_device *pdev)
> static int __devinit atmel_serial_probe(struct platform_device *pdev)
> {
> struct atmel_uart_port *port;
> + struct device_node *np = pdev->dev.of_node;
> struct atmel_uart_data *pdata = pdev->dev.platform_data;
> void *data;
> int ret;
>
> BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
>
> - port = &atmel_ports[pdata->num];
> + if (np) {
> + ret = of_alias_get_id(np, "serial");
I'll defer to Grant on this. There aren't any other drivers using this.
> + if (ret < 0)
> + goto err;
> + } else {
> + if (pdata) {
> + ret = pdata->num;
> + } else {
> + ret = -ENODEV;
> + goto err;
> + }
> + }
This would a bit more concise:
} else if (pdata) {
ret = pdata->num;
} else {
ret = -ENODEV;
goto err;
}
Rob
^ permalink raw reply
* [PATCH 1/2] ARM: CLKDEV: Add Common Macro for clk_lookup
From: padma venkat @ 2011-10-04 5:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20111001152938.GD11710@n2100.arm.linux.org.uk>
Thank you all for your comments.
Will resend the patches after removing "&" from the clk parameter and
trailing "," at the end of Macro.
Thanks and Regards,
Padmavathi Venna
On Sat, Oct 1, 2011 at 8:59 PM, Russell King - ARM Linux
<linux@arm.linux.org.uk> wrote:
> On Fri, Sep 30, 2011 at 04:41:36PM +0530, Padmavathi Venna wrote:
>> +#define CLKDEV_INIT(d, n, c) \
>> + ? ? { \
>> + ? ? ? ? ? ? .dev_id = d, \
>> + ? ? ? ? ? ? .con_id = n, \
>> + ? ? ? ? ? ? .clk = &c, \
>> + ? ? },
>> +
>
> As Heartley says, the trailing , and the end should not be there - it
> should be with each use of CLKDEV_INIT(). ?The reasoning is that it
> makes the use of macros much more conventional and consistent throughout
> the kernel:
>
> struct cl_lookup foo_lookups[] = {
> ? ? ? ?CLKDEV_INIT(...),
> ? ? ? ?CLKDEV_INIT(...),
> };
>
> struct cl_lookup bar_lookup = CLKDEV_INIT(...);
>
> Could you re-spin with that change please?
>
> Thanks.
>
^ permalink raw reply
* [PATCH 2/9] regulator: helper routine to extract regulator_init_data
From: Rajendra Nayak @ 2011-10-04 5:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110930121844.GI5366@opensource.wolfsonmicro.com>
On Friday 30 September 2011 05:48 PM, Mark Brown wrote:
> On Fri, Sep 30, 2011 at 04:39:02PM +0530, Rajendra Nayak wrote:
>
>> The "regulator-supplies" is used to specific the regulator *parent*.
>> Same as what was earlier passed by using the
>> "supply_regulator" field of regulator_init_data structure.
>> Grant wanted the bindings to support specifying multiple parents
>> and hence I was thinking of either a list of names *or*
>> a list of phandles to specify multiple parents to a regulator.
>
> So, as I'm fairly sure I said last time these are just standard
> supplies. It just happens to be that the consumer is a regulator. The
> fact that Linux chooses to have core framework handling for this is an
> implementation detail of Linux (and indeed many devices ignore this for
> their on board regulators).
Yes, the implementation details of linux is what is making me using
these bindings difficult, and maybe you can help me how I can work
around the framework. The binding themselves, I agree should not care
if the consumer is a device/IP or a regulator itself.
So here's my problem:
I use the <name-supply> = <®_phandle> binding to define
a device/IP using one/more regulators on one/more rails.
device mmc {
...
...
vmmc-supply = <&vmmc>;
vpll-supply = <&vpll>;
};
The parsing of the "vmmc-supply" or the "vpll-supply" property
happens only when a mmc drivers makes a call to
regulator_get() passing the supply-name as "vmmc" or "vpll".
For ex:
regulator_get(dev, "vmmc"); or regulator_get(dev, "vpll");
Its easy to just append the "-supply" to a "vmmc" or "vpll"
and derive a property name like "vmm-supply" or "vpll-supply".
Now lets take the case of a regulator as a consumer:
regulator vmmc {
...
...
vin-supply = <&vin>;
};
Now I need to parse the "vin-supply" property during a
regulator_register(), so I could do a set_supply() and
create the parent/child relationship between a vin and
vmmc.
The problem is I don't know if the property in the regulator dt
node is called "vin-supply" or "vxyz-supply" and hence I
can parse the property based on a substring alone, which is
"-supply" because all I know is the property name is expected
to end with a "-supply".
I can always add a new of_find_property_substr() which finds
me property based on a substring value passed rather than the
exact property-name string.
However I don;t know if this is the best way to handle it.
Any thoughts?
^ permalink raw reply
* Please help with the OMAP static mapping mess
From: Shilimkar, Santosh @ 2011-10-04 6:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20111003225908.GL6324@atomide.com>
On Tue, Oct 4, 2011 at 4:29 AM, Tony Lindgren <tony@atomide.com> wrote:
> * Nicolas Pitre <nico@fluxnic.net> [111003 15:05]:
>> On Mon, 3 Oct 2011, Nicolas Pitre wrote:
>>
>> > On Mon, 3 Oct 2011, Tony Lindgren wrote:
>> >
>> > > * Nicolas Pitre <nico@fluxnic.net> [111003 11:26]:
>> > > >
>> > > > Furthermore... there is also a static mapping for physical address
>> > > > 0x4e000000 using virtual address 0xff100000 which is already reserved
>> > > > for other purposes i.e. the consistent DMA area. ?It is not immediately
>> > > > obvious where this comes from without being intimate with the OMAP code.
>> > > > Can this be fixed as well i.e. moved elsewhere please?
>> > >
>> > > This sounds like a bug somewhere. Which omap are you seeing this on?
>> >
>> > OMAP4430 on a Panda board.
>> >
>> > Here are the static mappings I'm seeing:
>> >
>> > phys = 0x44000000 virt = 0xf8000000 size = 0x100000
>> > phys = 0x4a000000 virt = 0xfc000000 size = 0x400000
>> > phys = 0x50000000 virt = 0xf9000000 size = 0x100000
>> > phys = 0x4c000000 virt = 0xfd100000 size = 0x100000
>> > phys = 0x4d000000 virt = 0xfe100000 size = 0x100000
>> > phys = 0x4e000000 virt = 0xff100000 size = 0x100000 <---
>> > phys = 0x48000000 virt = 0xfa000000 size = 0x400000
>> > phys = 0x54000000 virt = 0xfe800000 size = 0x800000
>>
>> It looks like this comes from OMAP44XX_DMM_VIRT.
>>
>> #define OMAP44XX_DMM_PHYS ? ? ? OMAP44XX_DMM_BASE
>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? /* 0x4e000000 --> 0xfd300000 */
>> #define OMAP44XX_DMM_VIRT ? ? ? (OMAP44XX_DMM_PHYS + OMAP4_L3_PER_IO_OFFSET)
>> #define OMAP44XX_DMM_SIZE ? ? ? SZ_1M
>>
>> The comment suggesting a mapping correspondance is obviously wrong. We have:
>>
>> #define OMAP44XX_DMM_BASE ? ? ? 0x4e000000
>> #define OMAP4_L3_PER_IO_OFFSET ?0xb1100000
>>
>> Hence 0x4e000000 + 0xb1100000 = 0xff100000.
>
> Seem like it might cause some random patterns in tiler :)
> Santosh, can youp please check it?
>
This is already fixed Tony. You have pulled that patch.
http://www.mail-archive.com/linux-omap at vger.kernel.org/msg55258.html
Regards
Santosh
^ permalink raw reply
* [PATCH v4 04/10] ARM: SoC: convert OMAP4 to SoC descriptor
From: Shilimkar, Santosh @ 2011-10-04 6:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1317663356-5114-5-git-send-email-marc.zyngier@arm.com>
Marc,
On Mon, Oct 3, 2011 at 11:05 PM, Marc Zyngier <marc.zyngier@arm.com> wrote:
> Convert OMAP4 to use the SoC descriptor to provide its SMP
> and CPU hotplug operations.
>
> Tested on both Panda and IGEPv2 (MULTI_OMAP kernel)
>
> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
> ---
The changes very trivial and they look fine to me.
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Regards
Santosh
^ permalink raw reply
* Please help with the OMAP static mapping mess
From: Santosh Shilimkar @ 2011-10-04 7:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20111003223824.GK6324@atomide.com>
Nicolas,
On Tuesday 04 October 2011 04:08 AM, Tony Lindgren wrote:
> * Nicolas Pitre <nico@fluxnic.net> [111003 14:36]:
>> On Mon, 3 Oct 2011, Tony Lindgren wrote:
>>
>>> * Nicolas Pitre <nico@fluxnic.net> [111003 11:26]:
>>
>>>> OK, so let's modify omap4_panda_map_io() just to test this one board and
>>>> reverse the omap44xx_map_common_io() and omap2_set_globals_443x() call
>>>> order. Now the mappings will be there before ioremap() is called. But
>>>> that, too, doesn't work and the kernel now complains with:
>>>>
>>>> |OMAP revision unknown, please fix!
>>>> |Uninitialized omap_chip, please fix!
>>>> |Could not detect SRAM size
>>>>
>>>> But it looks like omap2_set_globals_tap() still has to be called first!
>>>> Isn't this wonderfully convoluted?
>>>
>>> We've already unravelled some of that with the init_early changes.
>>>
Sorry about that. We revamped io_map last time around to avoid
use of omap_readl()/omap_writel() and as Tony pointed out, as part
of early init code re-factoring, some more clean-up is happening.
>>> Earlier having the IO space moving around between 2420/2430/3430
>>> meant that we had to map some IO to detect the SoC. Now we have
>>> SoC specific initcalls where we assume the SoC category is initialized
>>> from board-*.c file (and from DT at some point).
>>
>> But the map_io method always has been tied to machine specific
>> descriptors. That always implied a fixed SoC category, no? Unless you
>> have a machine which can accommodate multiple different SOCs but that's
>> very uncommon.
>
> Hmm I think we initially tried to use board-generic.c with custom ATAGs
> to boot multiple SoCs and that's why we needed SoC detection for map_io.
>
> Now the only variable SoC headache left is that board-omap3beagle.c
> is using the same machine_id for 3430 and 3630 beagle which are somewhat
> different SoCs, but Luckily not from map_io point of view though. So that
> should be fixable with DT when the SoC type will be passed from DT.
>
>>> Having the SRAM base address move around with different sizes also
>>> requires the SoC detection.. Otherwise we can end up mapping wrong
>>> size and end up trying to access secure SRAM that will hang the system.
>>>
>>> The way to fix it is to move SRAM init happen much later so we don't
>>> have to map it early. I guess now we could use ioremap for SRAM,
>>> although we may not want device attributes for the executable code?
>>> Got any suggestions here on how we should map SRAM later on?
>>
>> You can use a variant of ioremap() such as __arm_ioremap() which let you
>> specify the memory attribute.
>
> OK, I'll take a look at that.
>
I have tried __arm_ioremap_pfn() for some DDR mapping and it didn't
work as expected. The mapping was not getting created. Needless to
say this can't be an IO memory. I later managed to get around with
it by using iotable_init() though downside is I have to pick a
static virtual address for the mapping.
But I agree that SRAM mapping can be moved further down. We
just need to ensure that it's ready before we initialise SDRC
and PM code. SDRC reconfigure of DDR needs to be executed from
SRAM and of-course the PM WFI routine. Today we do SDRC init early
and that's the reason SRAM is mapped before that. So both of them
needs to be moved down in the boot to make it work.
>>>> Furthermore... there is also a static mapping for physical address
>>>> 0x4e000000 using virtual address 0xff100000 which is already reserved
>>>> for other purposes i.e. the consistent DMA area. It is not immediately
>>>> obvious where this comes from without being intimate with the OMAP code.
>>>> Can this be fixed as well i.e. moved elsewhere please?
>>>
>>> This sounds like a bug somewhere. Which omap are you seeing this on?
>>
>> OMAP4430 on a Panda board.
>>
>> Here are the static mappings I'm seeing:
>>
>> phys = 0x44000000 virt = 0xf8000000 size = 0x100000
>> phys = 0x4a000000 virt = 0xfc000000 size = 0x400000
>> phys = 0x50000000 virt = 0xf9000000 size = 0x100000
>> phys = 0x4c000000 virt = 0xfd100000 size = 0x100000
>> phys = 0x4d000000 virt = 0xfe100000 size = 0x100000
>> phys = 0x4e000000 virt = 0xff100000 size = 0x100000 <---
>> phys = 0x48000000 virt = 0xfa000000 size = 0x400000
>> phys = 0x54000000 virt = 0xfe800000 size = 0x800000
>>
>> It is also possible that I might have screwed something up on my side.
>> What is located at 0x4e000000?
>
This was definitely a BUG which I noticed last merge window. The fix for
this is already getting into 3.2.
Regards
Santosh
^ permalink raw reply
* [PATCH 0/3] mmc: sdhci-s3c: Remove 'clk_type' member from platform data
From: Thomas Abraham @ 2011-10-04 7:28 UTC (permalink / raw)
To: linux-arm-kernel
This patchset removes all uses of 'clk_type' member from the platform data
of sdhci-s3c driver. The clk_type is a SoC specific information and not a board/
machine specific information. Hence, this information can be more aptly
represented using SoC specific driver data in the sdhci-s3c driver.
Hence all uses of 'clk_type' member in sdhci-s3c driver's platform data is
removed. In place of that, the sdhci host qurik 'SDHCI_QUIRK_NONSTANDARD_CLOCK'
is used to handle controllers that do not have a standard sdclk division
(like those in the exynos4 SoC's).
This is a pre-requisite patchset for adding device tree support for sdhci-s3c
driver. While migrating towards device tree support, retreving 'clk_type'
information does not seem correct and hence it has been added as SoC specific
driver data.
This patchset is based on the following tree
https://github.com/kgene/linux-samsung.git branch: for-next
and tested on smdkv310, smdkv210 and smdk2416.
Thomas Abraham (3):
mmc: sdhci-s3c: Remove usage of clk_type member in platform data
arm: exynos4: use 'exynos4-sdhci' as device name for sdhci controllers
arm: samsung: remove all uses of clk_type member in sdhci platform data
arch/arm/mach-exynos4/clock.c | 16 +++---
arch/arm/mach-exynos4/cpu.c | 5 ++
arch/arm/mach-exynos4/mach-armlex4210.c | 3 -
arch/arm/mach-exynos4/mach-nuri.c | 3 -
arch/arm/mach-exynos4/mach-origen.c | 2 -
arch/arm/mach-exynos4/mach-smdk4212.c | 2 -
arch/arm/mach-exynos4/mach-smdkv310.c | 4 --
arch/arm/mach-exynos4/mach-universal_c210.c | 2 -
arch/arm/plat-samsung/dev-hsmmc.c | 1 -
arch/arm/plat-samsung/dev-hsmmc1.c | 1 -
arch/arm/plat-samsung/dev-hsmmc2.c | 1 -
arch/arm/plat-samsung/dev-hsmmc3.c | 1 -
arch/arm/plat-samsung/include/plat/sdhci.h | 34 ++++++++++---
arch/arm/plat-samsung/platformdata.c | 2 -
drivers/mmc/host/sdhci-s3c.c | 74 +++++++++++++++++++++++++--
15 files changed, 110 insertions(+), 41 deletions(-)
^ permalink raw reply
* [PATCH 1/3] mmc: sdhci-s3c: Remove usage of clk_type member in platform data
From: Thomas Abraham @ 2011-10-04 7:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1317713315-5830-1-git-send-email-thomas.abraham@linaro.org>
SDHCI controllers on Exynos4 do not include the sdclk divider as per the
sdhci controller specification. This case can be represented using the
sdhci quirk SDHCI_QUIRK_NONSTANDARD_CLOCK instead of using an additional
enum type definition 'clk_types'.
Hence, usage of clk_type member in platform data is removed and the sdhci
quirk is used. In addition to that, since this qurik is SoC specific,
driver data is introduced to represent controllers on SoC's that require
this quirk.
Cc: Ben Dooks <ben-linux@fluff.org>
Cc: Jeongbae Seo <jeongbae.seo@samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
In the function 'sdhci_cmu_set_clock', the code that waits for a stable
sdclk clock is replicated from 'sdhci_set_clock' function. This portion
of code is replicated in sdhci-cns3xxx driver as well. This duplication
could have been avoid by adding a new function in sdhci host controller
driver that waits for stable sdclk and sdhci-s3c/sdhci-cns3xxx can be
the users of the new function. If adding a new function in sdhci host
controller driver is acceptable, an additional patch in this series
can be added that creates the new function that waits for stable sdclk.
drivers/mmc/host/sdhci-s3c.c | 74 +++++++++++++++++++++++++++++++++++++++--
1 files changed, 70 insertions(+), 4 deletions(-)
diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
index 82709b6..b29e734 100644
--- a/drivers/mmc/host/sdhci-s3c.c
+++ b/drivers/mmc/host/sdhci-s3c.c
@@ -53,6 +53,18 @@ struct sdhci_s3c {
struct clk *clk_bus[MAX_BUS_CLK];
};
+/**
+ * struct sdhci_s3c_driver_data - S3C SDHCI platform specific driver data
+ * @sdhci_quirks: sdhci host specific quirks.
+ *
+ * Specifies platform specific configuration of sdhci controller.
+ * Note: A structure for driver specific platform data is used for future
+ * expansion of its usage.
+ */
+struct sdhci_s3c_drv_data {
+ unsigned int sdhci_quirks;
+};
+
static inline struct sdhci_s3c *to_s3c(struct sdhci_host *host)
{
return sdhci_priv(host);
@@ -132,10 +144,10 @@ static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c *ourhost,
return UINT_MAX;
/*
- * Clock divider's step is different as 1 from that of host controller
- * when 'clk_type' is S3C_SDHCI_CLK_DIV_EXTERNAL.
+ * If controller uses a non-standard clock division, find the best clock
+ * speed possible with selected clock source and skip the division.
*/
- if (ourhost->pdata->clk_type) {
+ if (ourhost->host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) {
rate = clk_round_rate(clksrc, wanted);
return wanted - rate;
}
@@ -272,6 +284,8 @@ static unsigned int sdhci_cmu_get_min_clock(struct sdhci_host *host)
static void sdhci_cmu_set_clock(struct sdhci_host *host, unsigned int clock)
{
struct sdhci_s3c *ourhost = to_s3c(host);
+ unsigned long timeout;
+ u16 clk = 0;
/* don't bother if the clock is going off */
if (clock == 0)
@@ -282,6 +296,25 @@ static void sdhci_cmu_set_clock(struct sdhci_host *host, unsigned int clock)
clk_set_rate(ourhost->clk_bus[ourhost->cur_clk], clock);
host->clock = clock;
+
+ clk = SDHCI_CLOCK_INT_EN;
+ sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+
+ /* Wait max 20 ms */
+ timeout = 20;
+ while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
+ & SDHCI_CLOCK_INT_STABLE)) {
+ if (timeout == 0) {
+ printk(KERN_ERR "%s: Internal clock never "
+ "stabilised.\n", mmc_hostname(host->mmc));
+ return;
+ }
+ timeout--;
+ mdelay(1);
+ }
+
+ clk |= SDHCI_CLOCK_CARD_EN;
+ sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
}
/**
@@ -382,9 +415,17 @@ static void sdhci_s3c_setup_card_detect_gpio(struct sdhci_s3c *sc)
}
}
+static inline struct sdhci_s3c_drv_data *sdhci_s3c_get_driver_data(
+ struct platform_device *pdev)
+{
+ return (struct sdhci_s3c_drv_data *)
+ platform_get_device_id(pdev)->driver_data;
+}
+
static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
{
struct s3c_sdhci_platdata *pdata = pdev->dev.platform_data;
+ struct sdhci_s3c_drv_data *drv_data;
struct device *dev = &pdev->dev;
struct sdhci_host *host;
struct sdhci_s3c *sc;
@@ -414,6 +455,7 @@ static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
return PTR_ERR(host);
}
+ drv_data = sdhci_s3c_get_driver_data(pdev);
sc = sdhci_priv(host);
sc->host = host;
@@ -494,6 +536,8 @@ static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
/* Setup quirks for the controller */
host->quirks |= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC;
host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
+ if (drv_data)
+ host->quirks |= drv_data->sdhci_quirks;
#ifndef CONFIG_MMC_SDHCI_S3C_DMA
@@ -534,7 +578,7 @@ static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
* If controller does not have internal clock divider,
* we can use overriding functions instead of default.
*/
- if (pdata->clk_type) {
+ if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) {
sdhci_s3c_ops.set_clock = sdhci_cmu_set_clock;
sdhci_s3c_ops.get_min_clock = sdhci_cmu_get_min_clock;
sdhci_s3c_ops.get_max_clock = sdhci_cmu_get_max_clock;
@@ -639,9 +683,31 @@ static int sdhci_s3c_resume(struct platform_device *dev)
#define sdhci_s3c_resume NULL
#endif
+#if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212)
+static struct sdhci_s3c_drv_data exynos4_sdhci_drv_data = {
+ .sdhci_quirks = SDHCI_QUIRK_NONSTANDARD_CLOCK,
+};
+#define EXYNOS4_SDHCI_DRV_DATA ((kernel_ulong_t)&exynos4_sdhci_drv_data)
+#else
+#define EXYNOS4_SDHCI_DRV_DATA (kernel_ulong_t)NULL
+#endif
+
+static struct platform_device_id sdhci_s3c_driver_ids[] = {
+ {
+ .name = "s3c-sdhci",
+ .driver_data = (kernel_ulong_t)NULL,
+ },
+ {
+ .name = "exynos4-sdhci",
+ .driver_data = EXYNOS4_SDHCI_DRV_DATA,
+ },
+};
+MODULE_DEVICE_TABLE(platform, sdhci_s3c_driver_ids);
+
static struct platform_driver sdhci_s3c_driver = {
.probe = sdhci_s3c_probe,
.remove = __devexit_p(sdhci_s3c_remove),
+ .id_table = sdhci_s3c_driver_ids,
.suspend = sdhci_s3c_suspend,
.resume = sdhci_s3c_resume,
.driver = {
--
1.6.6.rc2
^ permalink raw reply related
* [PATCH 2/3] arm: exynos4: use 'exynos4-sdhci' as device name for sdhci controllers
From: Thomas Abraham @ 2011-10-04 7:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1317713315-5830-1-git-send-email-thomas.abraham@linaro.org>
With the addition of platform specific driver data in the sdhci driver
for exynos4, the device name of sdhci controllers on exynos4 is changed
accordingly.
Cc: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
arch/arm/mach-exynos4/clock.c | 16 ++++++++--------
arch/arm/mach-exynos4/cpu.c | 5 +++++
arch/arm/plat-samsung/include/plat/sdhci.h | 27 +++++++++++++++++++++++++++
3 files changed, 40 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c
index a25c818..d89b45e 100644
--- a/arch/arm/mach-exynos4/clock.c
+++ b/arch/arm/mach-exynos4/clock.c
@@ -495,25 +495,25 @@ static struct clk init_clocks_off[] = {
.ctrlbit = (1 << 0),
}, {
.name = "hsmmc",
- .devname = "s3c-sdhci.0",
+ .devname = "exynos4-sdhci.0",
.parent = &clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 5),
}, {
.name = "hsmmc",
- .devname = "s3c-sdhci.1",
+ .devname = "exynos4-sdhci.1",
.parent = &clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 6),
}, {
.name = "hsmmc",
- .devname = "s3c-sdhci.2",
+ .devname = "exynos4-sdhci.2",
.parent = &clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "hsmmc",
- .devname = "s3c-sdhci.3",
+ .devname = "exynos4-sdhci.3",
.parent = &clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 8),
@@ -1198,7 +1198,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
- .devname = "s3c-sdhci.0",
+ .devname = "exynos4-sdhci.0",
.parent = &clk_dout_mmc0.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 0),
@@ -1207,7 +1207,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
- .devname = "s3c-sdhci.1",
+ .devname = "exynos4-sdhci.1",
.parent = &clk_dout_mmc1.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 4),
@@ -1216,7 +1216,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
- .devname = "s3c-sdhci.2",
+ .devname = "exynos4-sdhci.2",
.parent = &clk_dout_mmc2.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 8),
@@ -1225,7 +1225,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
- .devname = "s3c-sdhci.3",
+ .devname = "exynos4-sdhci.3",
.parent = &clk_dout_mmc3.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 12),
diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c
index 2aa3df0..8f0f897 100644
--- a/arch/arm/mach-exynos4/cpu.c
+++ b/arch/arm/mach-exynos4/cpu.c
@@ -175,6 +175,11 @@ void __init exynos4_map_io(void)
s3c_fimc_setname(2, "exynos4-fimc");
s3c_fimc_setname(3, "exynos4-fimc");
+ s3c_sdhci_setname(0, "exynos4-sdhci");
+ s3c_sdhci_setname(1, "exynos4-sdhci");
+ s3c_sdhci_setname(2, "exynos4-sdhci");
+ s3c_sdhci_setname(3, "exynos4-sdhci");
+
/* The I2C bus controllers are directly compatible with s3c2440 */
s3c_i2c0_setname("s3c2440-i2c");
s3c_i2c1_setname("s3c2440-i2c");
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
index e7b3c75..8f9a7d7 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -18,6 +18,8 @@
#ifndef __PLAT_S3C_SDHCI_H
#define __PLAT_S3C_SDHCI_H __FILE__
+#include <plat/devs.h>
+
struct platform_device;
struct mmc_host;
struct mmc_card;
@@ -340,4 +342,29 @@ static inline void exynos4_default_sdhci3(void) { }
#endif /* CONFIG_EXYNOS4_SETUP_SDHCI */
+static inline void s3c_sdhci_setname(int id, char *name)
+{
+ switch (id) {
+#ifdef CONFIG_S3C_DEV_HSMMC
+ case 0:
+ s3c_device_hsmmc0.name = name;
+ break;
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC1
+ case 1:
+ s3c_device_hsmmc1.name = name;
+ break;
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC2
+ case 2:
+ s3c_device_hsmmc2.name = name;
+ break;
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC3
+ case 3:
+ s3c_device_hsmmc3.name = name;
+ break;
+#endif
+ }
+}
#endif /* __PLAT_S3C_SDHCI_H */
--
1.6.6.rc2
^ permalink raw reply related
* [PATCH 3/3] arm: samsung: remove all uses of clk_type member in sdhci platform data
From: Thomas Abraham @ 2011-10-04 7:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1317713315-5830-1-git-send-email-thomas.abraham@linaro.org>
The sdhci driver is modified to be independent of clk_type member in the sdhci
platform data. Hence, all usage of clk_type in platform code is removed.
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: JeongHyeon Kim <jhkim@insignal.co.kr>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Changhwan Youn <chaos.youn@samsung.com>
Cc: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
arch/arm/mach-exynos4/mach-armlex4210.c | 3 ---
arch/arm/mach-exynos4/mach-nuri.c | 3 ---
arch/arm/mach-exynos4/mach-origen.c | 2 --
arch/arm/mach-exynos4/mach-smdk4212.c | 2 --
arch/arm/mach-exynos4/mach-smdkv310.c | 4 ----
arch/arm/mach-exynos4/mach-universal_c210.c | 2 --
arch/arm/plat-samsung/dev-hsmmc.c | 1 -
arch/arm/plat-samsung/dev-hsmmc1.c | 1 -
arch/arm/plat-samsung/dev-hsmmc2.c | 1 -
arch/arm/plat-samsung/dev-hsmmc3.c | 1 -
arch/arm/plat-samsung/include/plat/sdhci.h | 7 -------
arch/arm/plat-samsung/platformdata.c | 2 --
12 files changed, 0 insertions(+), 29 deletions(-)
diff --git a/arch/arm/mach-exynos4/mach-armlex4210.c b/arch/arm/mach-exynos4/mach-armlex4210.c
index b482c62..8bb2c48 100644
--- a/arch/arm/mach-exynos4/mach-armlex4210.c
+++ b/arch/arm/mach-exynos4/mach-armlex4210.c
@@ -75,7 +75,6 @@ static struct s3c2410_uartcfg armlex4210_uartcfgs[] __initdata = {
static struct s3c_sdhci_platdata armlex4210_hsmmc0_pdata __initdata = {
.cd_type = S3C_SDHCI_CD_PERMANENT,
- .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
.max_width = 8,
.host_caps = MMC_CAP_8_BIT_DATA,
@@ -86,13 +85,11 @@ static struct s3c_sdhci_platdata armlex4210_hsmmc2_pdata __initdata = {
.cd_type = S3C_SDHCI_CD_GPIO,
.ext_cd_gpio = EXYNOS4_GPX2(5),
.ext_cd_gpio_invert = 1,
- .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
.max_width = 4,
};
static struct s3c_sdhci_platdata armlex4210_hsmmc3_pdata __initdata = {
.cd_type = S3C_SDHCI_CD_PERMANENT,
- .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
.max_width = 4,
};
diff --git a/arch/arm/mach-exynos4/mach-nuri.c b/arch/arm/mach-exynos4/mach-nuri.c
index bbd13f4..00b4b6f 100644
--- a/arch/arm/mach-exynos4/mach-nuri.c
+++ b/arch/arm/mach-exynos4/mach-nuri.c
@@ -101,7 +101,6 @@ static struct s3c_sdhci_platdata nuri_hsmmc0_data __initdata = {
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
MMC_CAP_DISABLE | MMC_CAP_ERASE),
.cd_type = S3C_SDHCI_CD_PERMANENT,
- .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
};
static struct regulator_consumer_supply emmc_supplies[] = {
@@ -143,7 +142,6 @@ static struct s3c_sdhci_platdata nuri_hsmmc2_data __initdata = {
.ext_cd_gpio = EXYNOS4_GPX3(3), /* XEINT_27 */
.ext_cd_gpio_invert = 1,
.cd_type = S3C_SDHCI_CD_GPIO,
- .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
};
/* WLAN */
@@ -152,7 +150,6 @@ static struct s3c_sdhci_platdata nuri_hsmmc3_data __initdata = {
.host_caps = MMC_CAP_4_BIT_DATA |
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
.cd_type = S3C_SDHCI_CD_EXTERNAL,
- .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
};
static void __init nuri_sdhci_init(void)
diff --git a/arch/arm/mach-exynos4/mach-origen.c b/arch/arm/mach-exynos4/mach-origen.c
index 421294b..82dfdc3 100644
--- a/arch/arm/mach-exynos4/mach-origen.c
+++ b/arch/arm/mach-exynos4/mach-origen.c
@@ -80,12 +80,10 @@ static struct s3c2410_uartcfg origen_uartcfgs[] __initdata = {
static struct s3c_sdhci_platdata origen_hsmmc0_pdata __initdata = {
.cd_type = S3C_SDHCI_CD_INTERNAL,
- .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
};
static struct s3c_sdhci_platdata origen_hsmmc2_pdata __initdata = {
.cd_type = S3C_SDHCI_CD_INTERNAL,
- .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
};
/* USB EHCI */
diff --git a/arch/arm/mach-exynos4/mach-smdk4212.c b/arch/arm/mach-exynos4/mach-smdk4212.c
index 8c41ae1..b460652 100644
--- a/arch/arm/mach-exynos4/mach-smdk4212.c
+++ b/arch/arm/mach-exynos4/mach-smdk4212.c
@@ -83,7 +83,6 @@ static struct s3c2410_uartcfg smdk4212_uartcfgs[] __initdata = {
static struct s3c_sdhci_platdata smdk4212_hsmmc2_pdata __initdata = {
.cd_type = S3C_SDHCI_CD_INTERNAL,
- .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
.max_width = 8,
.host_caps = MMC_CAP_8_BIT_DATA,
@@ -92,7 +91,6 @@ static struct s3c_sdhci_platdata smdk4212_hsmmc2_pdata __initdata = {
static struct s3c_sdhci_platdata smdk4212_hsmmc3_pdata __initdata = {
.cd_type = S3C_SDHCI_CD_INTERNAL,
- .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
};
static struct regulator_consumer_supply max8997_buck1 =
diff --git a/arch/arm/mach-exynos4/mach-smdkv310.c b/arch/arm/mach-exynos4/mach-smdkv310.c
index c74b2db..31a64d8 100644
--- a/arch/arm/mach-exynos4/mach-smdkv310.c
+++ b/arch/arm/mach-exynos4/mach-smdkv310.c
@@ -90,7 +90,6 @@ static struct s3c2410_uartcfg smdkv310_uartcfgs[] __initdata = {
static struct s3c_sdhci_platdata smdkv310_hsmmc0_pdata __initdata = {
.cd_type = S3C_SDHCI_CD_INTERNAL,
- .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
.max_width = 8,
.host_caps = MMC_CAP_8_BIT_DATA,
@@ -101,12 +100,10 @@ static struct s3c_sdhci_platdata smdkv310_hsmmc1_pdata __initdata = {
.cd_type = S3C_SDHCI_CD_GPIO,
.ext_cd_gpio = EXYNOS4_GPK0(2),
.ext_cd_gpio_invert = 1,
- .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
};
static struct s3c_sdhci_platdata smdkv310_hsmmc2_pdata __initdata = {
.cd_type = S3C_SDHCI_CD_INTERNAL,
- .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
.max_width = 8,
.host_caps = MMC_CAP_8_BIT_DATA,
@@ -117,7 +114,6 @@ static struct s3c_sdhci_platdata smdkv310_hsmmc3_pdata __initdata = {
.cd_type = S3C_SDHCI_CD_GPIO,
.ext_cd_gpio = EXYNOS4_GPK2(2),
.ext_cd_gpio_invert = 1,
- .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
};
static void lcd_lte480wv_set_power(struct plat_lcd_data *pd,
diff --git a/arch/arm/mach-exynos4/mach-universal_c210.c b/arch/arm/mach-exynos4/mach-universal_c210.c
index 18cf5c7..0556feb 100644
--- a/arch/arm/mach-exynos4/mach-universal_c210.c
+++ b/arch/arm/mach-exynos4/mach-universal_c210.c
@@ -737,7 +737,6 @@ static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = {
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
MMC_CAP_DISABLE),
.cd_type = S3C_SDHCI_CD_PERMANENT,
- .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
};
static struct regulator_consumer_supply mmc0_supplies[] = {
@@ -778,7 +777,6 @@ static struct s3c_sdhci_platdata universal_hsmmc2_data __initdata = {
.ext_cd_gpio = EXYNOS4_GPX3(4), /* XEINT_28 */
.ext_cd_gpio_invert = 1,
.cd_type = S3C_SDHCI_CD_GPIO,
- .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
};
/* WiFi */
diff --git a/arch/arm/plat-samsung/dev-hsmmc.c b/arch/arm/plat-samsung/dev-hsmmc.c
index 06825c4..ea0291f 100644
--- a/arch/arm/plat-samsung/dev-hsmmc.c
+++ b/arch/arm/plat-samsung/dev-hsmmc.c
@@ -41,7 +41,6 @@ struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata = {
.max_width = 4,
.host_caps = (MMC_CAP_4_BIT_DATA |
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
- .clk_type = S3C_SDHCI_CLK_DIV_INTERNAL,
};
struct platform_device s3c_device_hsmmc0 = {
diff --git a/arch/arm/plat-samsung/dev-hsmmc1.c b/arch/arm/plat-samsung/dev-hsmmc1.c
index 4524ef4..56dbe7a 100644
--- a/arch/arm/plat-samsung/dev-hsmmc1.c
+++ b/arch/arm/plat-samsung/dev-hsmmc1.c
@@ -41,7 +41,6 @@ struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata = {
.max_width = 4,
.host_caps = (MMC_CAP_4_BIT_DATA |
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
- .clk_type = S3C_SDHCI_CLK_DIV_INTERNAL,
};
struct platform_device s3c_device_hsmmc1 = {
diff --git a/arch/arm/plat-samsung/dev-hsmmc2.c b/arch/arm/plat-samsung/dev-hsmmc2.c
index 9cede96..916e11b 100644
--- a/arch/arm/plat-samsung/dev-hsmmc2.c
+++ b/arch/arm/plat-samsung/dev-hsmmc2.c
@@ -42,7 +42,6 @@ struct s3c_sdhci_platdata s3c_hsmmc2_def_platdata = {
.max_width = 4,
.host_caps = (MMC_CAP_4_BIT_DATA |
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
- .clk_type = S3C_SDHCI_CLK_DIV_INTERNAL,
};
struct platform_device s3c_device_hsmmc2 = {
diff --git a/arch/arm/plat-samsung/dev-hsmmc3.c b/arch/arm/plat-samsung/dev-hsmmc3.c
index 0358ef4..8f06670 100644
--- a/arch/arm/plat-samsung/dev-hsmmc3.c
+++ b/arch/arm/plat-samsung/dev-hsmmc3.c
@@ -45,7 +45,6 @@ struct s3c_sdhci_platdata s3c_hsmmc3_def_platdata = {
.max_width = 4,
.host_caps = (MMC_CAP_4_BIT_DATA |
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
- .clk_type = S3C_SDHCI_CLK_DIV_INTERNAL,
};
struct platform_device s3c_device_hsmmc3 = {
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
index 8f9a7d7..39a70ec 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -33,17 +33,11 @@ enum cd_types {
S3C_SDHCI_CD_PERMANENT, /* no CD line, card permanently wired to host */
};
-enum clk_types {
- S3C_SDHCI_CLK_DIV_INTERNAL, /* use mmc internal clock divider */
- S3C_SDHCI_CLK_DIV_EXTERNAL, /* use external clock divider */
-};
-
/**
* struct s3c_sdhci_platdata() - Platform device data for Samsung SDHCI
* @max_width: The maximum number of data bits supported.
* @host_caps: Standard MMC host capabilities bit field.
* @cd_type: Type of Card Detection method (see cd_types enum above)
- * @clk_type: Type of clock divider method (see clk_types enum above)
* @ext_cd_init: Initialize external card detect subsystem. Called on
* sdhci-s3c driver probe when cd_type == S3C_SDHCI_CD_EXTERNAL.
* notify_func argument is a callback to the sdhci-s3c driver
@@ -66,7 +60,6 @@ struct s3c_sdhci_platdata {
unsigned int max_width;
unsigned int host_caps;
enum cd_types cd_type;
- enum clk_types clk_type;
char **clocks; /* set of clock sources */
diff --git a/arch/arm/plat-samsung/platformdata.c b/arch/arm/plat-samsung/platformdata.c
index 4c9a207..88c5e7c 100644
--- a/arch/arm/plat-samsung/platformdata.c
+++ b/arch/arm/plat-samsung/platformdata.c
@@ -52,6 +52,4 @@ void s3c_sdhci_set_platdata(struct s3c_sdhci_platdata *pd,
set->cfg_gpio = pd->cfg_gpio;
if (pd->host_caps)
set->host_caps |= pd->host_caps;
- if (pd->clk_type)
- set->clk_type = pd->clk_type;
}
--
1.6.6.rc2
^ permalink raw reply related
* [PATCH 16/26] ARM: pxa: CPU_PJ4 requires IWMMXT
From: Arnd Bergmann @ 2011-10-04 7:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAMPhdO96WwmPVqVpM2Vpef3wSgfHEf-0tK5VewXn-EGMns2ubA@mail.gmail.com>
On Tuesday 04 October 2011, Eric Miao wrote:
> I think this is true for other xscale CPUs as well, so either we make
> them unconditionally all at once, or we still leave an option here.
Do all xscale have iwmmxt?
> It actually looks quite odd to me that CPU_PJ4 is made special here,
> what're the real broken builds errors?
Yes.
I should probably have provided a longer description of the problem.
The build error is in arch/arm/kernel/pj4-cp0.c, which calls
iwmmxt_task_release unconditionally. The code is obviously
copy-pasted from arch/arm/kernel/xscale-cp0.c, which does much
of the same, but uses both run-time and compile-time conditionals
for iwmmxt.
Arnd
^ permalink raw reply
* [PATCH] ARM: remove bashism in check for multiple zreladdrs
From: Sascha Hauer @ 2011-10-04 7:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1317660736-19081-1-git-send-email-rabin@rab.in>
On Mon, Oct 03, 2011 at 10:22:16PM +0530, Rabin Vincent wrote:
> Get rid of this complaint from dash:
>
> AS arch/arm/boot/compressed/lib1funcs.o
> /bin/sh: 1: [: y: unexpected operator
> LD arch/arm/boot/compressed/vmlinux
>
> Cc: Sascha Hauer <s.hauer@pengutronix.de>
> Signed-off-by: Rabin Vincent <rabin@rab.in>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
I guess using '=' for a comparison is hard to type for a C programmer ;)
Sascha
> ---
> arch/arm/boot/compressed/Makefile | 2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
> index a53a333..a6b30b3 100644
> --- a/arch/arm/boot/compressed/Makefile
> +++ b/arch/arm/boot/compressed/Makefile
> @@ -140,7 +140,7 @@ bad_syms=$$($(CROSS_COMPILE)nm $@ | sed -n 's/^.\{8\} [bc] \(.*\)/\1/p') && \
> echo "$$bad_syms" >&2; rm -f $@; false )
>
> check_for_multiple_zreladdr = \
> -if [ $(words $(ZRELADDR)) -gt 1 -a "$(CONFIG_AUTO_ZRELADDR)" == "" ]; then \
> +if [ $(words $(ZRELADDR)) -gt 1 -a "$(CONFIG_AUTO_ZRELADDR)" = "" ]; then \
> echo 'multiple zreladdrs: $(ZRELADDR)'; \
> echo 'This needs CONFIG_AUTO_ZRELADDR to be set'; \
> false; \
> --
> 1.7.5.4
>
>
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply
* [PATCH] mx5: modify pm and idle
From: Sascha Hauer @ 2011-10-04 7:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1317364642-22956-1-git-send-email-jason77.wang@gmail.com>
On Fri, Sep 30, 2011 at 02:37:22PM +0800, Hui Wang wrote:
> Two problems exist in the current i.MX5 pm suspend/resume and idle
> functions. The first is the current i.MX5 suspend routine will call
> tzic_enable_wake(1) to set wake source, this will set all enabled
> irq as wake source rather than those wake capable. The second
> is i.MX5 idle will call mx5_cpu_lp_set() to prepare enter low power
> mode, but it forgets to call wfi instruction to enter this mode.
>
> To fix these two problems, using generic irq chip pm interface and
> adding a new function mx5_arch_idle().
>
> Signed-off-by: Hui Wang <jason77.wang@gmail.com>
As shawn already pointed out this conflicts with the imx-cleanup
branch. Can you rework this onto it? Shawn has reworked the SoC
specific idle stuff, so this is different now.
Also, please find a better subject for this patch. 'modify pm and idle'
is not enough.
Sascha
> ---
>
> This patch is basing on the latest imx-features branch.
>
> This patch is validated on the i.MX51 PDK board (CPU revision 2.0).
>
> Since both pm suspend/resume and idle has close relation with
> mx5_cpu_lp_set() and tzic_enable_wake(), i choose to use one patch
> instead of independent two to address existing problems.
>
> arch/arm/mach-mx5/system.c | 24 +++++++++++++++--
> arch/arm/plat-mxc/include/mach/mxc.h | 2 +-
> arch/arm/plat-mxc/include/mach/system.h | 3 +-
> arch/arm/plat-mxc/tzic.c | 42 ++++++++++++++++++++++---------
> 4 files changed, 54 insertions(+), 17 deletions(-)
>
> diff --git a/arch/arm/mach-mx5/system.c b/arch/arm/mach-mx5/system.c
> index 76ae8dc..92bf341 100644
> --- a/arch/arm/mach-mx5/system.c
> +++ b/arch/arm/mach-mx5/system.c
> @@ -10,11 +10,17 @@
> * http://www.opensource.org/licenses/gpl-license.html
> * http://www.gnu.org/copyleft/gpl.html
> */
> +#include <linux/suspend.h>
> +#include <linux/clk.h>
> #include <linux/platform_device.h>
> #include <linux/io.h>
> #include <mach/hardware.h>
> +#include <mach/common.h>
> +
> #include "crm_regs.h"
>
> +static struct clk *gpc_dvfs_clk;
> +
> /* set cpu low power mode before WFI instruction. This function is called
> * mx5 because it can be used for mx50, mx51, and mx53.*/
> void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
> @@ -54,9 +60,6 @@ void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
> stop_mode = 1;
> }
> arm_srpgcr |= MXC_SRPGCR_PCR;
> -
> - if (tzic_enable_wake(1) != 0)
> - return;
> break;
> case STOP_POWER_ON:
> ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET;
> @@ -82,3 +85,18 @@ void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
> __raw_writel(empgc1, MXC_SRPG_EMPGC1_SRPGCR);
> }
> }
> +
> +void mx5_arch_idle(void)
> +{
> + if (gpc_dvfs_clk == NULL)
> + gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs");
> +
> + /* gpc clock is needed for SRPG */
> + clk_enable(gpc_dvfs_clk);
> + mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
> + if (tzic_enable_wake() != 0)
> + goto exit;
> + cpu_do_idle();
> +exit:
> + clk_disable(gpc_dvfs_clk);
> +}
> diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
> index 0987923..c4d324a 100644
> --- a/arch/arm/plat-mxc/include/mach/mxc.h
> +++ b/arch/arm/plat-mxc/include/mach/mxc.h
> @@ -182,7 +182,7 @@ struct cpu_op {
> u32 cpu_rate;
> };
>
> -int tzic_enable_wake(int is_idle);
> +int tzic_enable_wake(void);
> enum mxc_cpu_pwr_mode {
> WAIT_CLOCKED, /* wfi only */
> WAIT_UNCLOCKED, /* WAIT */
> diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h
> index 51f02a9..5b6f991 100644
> --- a/arch/arm/plat-mxc/include/mach/system.h
> +++ b/arch/arm/plat-mxc/include/mach/system.h
> @@ -21,6 +21,7 @@
> #include <mach/common.h>
>
> extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode);
> +extern void mx5_arch_idle(void);
>
> static inline void arch_idle(void)
> {
> @@ -51,7 +52,7 @@ static inline void arch_idle(void)
> "mcr p15, 0, %0, c1, c0, 0\n"
> : "=r" (reg));
> } else if (cpu_is_mx51())
> - mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
> + mx5_arch_idle();
> else
> cpu_do_idle();
> }
> diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c
> index e993a18..bd73910 100644
> --- a/arch/arm/plat-mxc/tzic.c
> +++ b/arch/arm/plat-mxc/tzic.c
> @@ -72,14 +72,35 @@ static int tzic_set_irq_fiq(unsigned int irq, unsigned int type)
> #define tzic_set_irq_fiq NULL
> #endif
>
> -static unsigned int *wakeup_intr[4];
> -
> static struct mxc_extra_irq tzic_extra_irq = {
> #ifdef CONFIG_FIQ
> .set_irq_fiq = tzic_set_irq_fiq,
> #endif
> };
>
> +#ifdef CONFIG_PM
> +static void tzic_irq_suspend(struct irq_data *d)
> +{
> + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
> + int idx = gc->irq_base >> 5;
> +
> + __raw_writel(gc->wake_active, tzic_base + TZIC_WAKEUP0(idx));
> +}
> +
> +static void tzic_irq_resume(struct irq_data *d)
> +{
> + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
> + int idx = gc->irq_base >> 5;
> +
> + __raw_writel(__raw_readl(tzic_base + TZIC_ENSET0(idx)),
> + tzic_base + TZIC_WAKEUP0(idx));
> +}
> +
> +#else
> +#define tzic_irq_suspend NULL
> +#define tzic_irq_resume NULL
> +#endif
> +
> static __init void tzic_init_gc(unsigned int irq_start)
> {
> struct irq_chip_generic *gc;
> @@ -90,12 +111,13 @@ static __init void tzic_init_gc(unsigned int irq_start)
> handle_level_irq);
> gc->private = &tzic_extra_irq;
> gc->wake_enabled = IRQ_MSK(32);
> - wakeup_intr[idx] = &gc->wake_active;
>
> ct = gc->chip_types;
> ct->chip.irq_mask = irq_gc_mask_disable_reg;
> ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
> ct->chip.irq_set_wake = irq_gc_set_wake;
> + ct->chip.irq_suspend = tzic_irq_suspend;
> + ct->chip.irq_resume = tzic_irq_resume;
> ct->regs.disable = TZIC_ENCLEAR0(idx);
> ct->regs.enable = TZIC_ENSET0(idx);
>
> @@ -166,23 +188,19 @@ void __init tzic_init_irq(void __iomem *irqbase)
> /**
> * tzic_enable_wake() - enable wakeup interrupt
> *
> - * @param is_idle 1 if called in idle loop (ENSET0 register);
> - * 0 to be used when called from low power entry
> * @return 0 if successful; non-zero otherwise
> */
> -int tzic_enable_wake(int is_idle)
> +int tzic_enable_wake(void)
> {
> - unsigned int i, v;
> + unsigned int i;
>
> __raw_writel(1, tzic_base + TZIC_DSMINT);
> if (unlikely(__raw_readl(tzic_base + TZIC_DSMINT) == 0))
> return -EAGAIN;
>
> - for (i = 0; i < 4; i++) {
> - v = is_idle ? __raw_readl(tzic_base + TZIC_ENSET0(i)) :
> - *wakeup_intr[i];
> - __raw_writel(v, tzic_base + TZIC_WAKEUP0(i));
> - }
> + for (i = 0; i < 4; i++)
> + __raw_writel(__raw_readl(tzic_base + TZIC_ENSET0(i)),
> + tzic_base + TZIC_WAKEUP0(i));
>
> return 0;
> }
> --
> 1.7.6
>
>
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply
* [PATCH 26/30] ARM: omap: add board autoselection
From: Arnd Bergmann @ 2011-10-04 7:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20111003182649.GC6324@atomide.com>
On Monday 03 October 2011, Tony Lindgren wrote:
> * Arnd Bergmann <arnd@arndb.de> [111003 02:20]:
> > On Monday 03 October 2011 11:27:44 Cousson, Benoit wrote:
> > > >
> > > > In the long run, I'd hope we can just get rid of these for subarchitectures
> > > > that support device tree probing and make the device tree based machine
> > > > description unconditional.
> > >
> > > This is really our goal, we will have soon the board-generic.c for that,
> > > someone will just have to migrate these ~30 board files to device tree
> > > DTS files
> >
> > For the purpose of build-time validation using randconfig, there is no
> > problem in keeping some board files forever, as long as the generic board
> > file is always built-in.
>
> Yes please leave out the list so we don't need to constantly update it.
> Let's just always build in MACH_OMAP_GENERIC.
That's what I had initially, but now that board file has become
omap2-specific and no longer works on omap3-only or omap4-only
configurations.
Arnd
^ permalink raw reply
* [PATCH 1/3] mmc: sdhci-s3c: Remove usage of clk_type member in platform data
From: Kyungmin Park @ 2011-10-04 7:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1317713315-5830-2-git-send-email-thomas.abraham@linaro.org>
Hi,
On Tue, Oct 4, 2011 at 4:28 PM, Thomas Abraham
<thomas.abraham@linaro.org> wrote:
> SDHCI controllers on Exynos4 do not include the sdclk divider as per the
> sdhci controller specification. This case can be represented using the
> sdhci quirk SDHCI_QUIRK_NONSTANDARD_CLOCK instead of using an additional
> enum type definition 'clk_types'.
>
> Hence, usage of clk_type member in platform data is removed and the sdhci
> quirk is used. In addition to that, since this qurik is SoC specific,
> driver data is introduced to represent controllers on SoC's that require
> this quirk.
Right.
>
> Cc: Ben Dooks <ben-linux@fluff.org>
> Cc: Jeongbae Seo <jeongbae.seo@samsung.com>
> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
> ---
> In the function 'sdhci_cmu_set_clock', the code that waits for a stable
> sdclk clock is replicated from 'sdhci_set_clock' function. This portion
> of code is replicated in sdhci-cns3xxx driver as well. This duplication
> could have been avoid by adding a new function in sdhci host controller
> driver that waits for stable sdclk and sdhci-s3c/sdhci-cns3xxx can be
> the users of the new function. If adding a new function in sdhci host
> controller driver is acceptable, an additional patch in this series
> can be added that creates the new function that waits for stable sdclk.
>
> ?drivers/mmc/host/sdhci-s3c.c | ? 74 +++++++++++++++++++++++++++++++++++++++--
> ?1 files changed, 70 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
> index 82709b6..b29e734 100644
> --- a/drivers/mmc/host/sdhci-s3c.c
> +++ b/drivers/mmc/host/sdhci-s3c.c
> @@ -53,6 +53,18 @@ struct sdhci_s3c {
> ? ? ? ?struct clk ? ? ? ? ? ? ?*clk_bus[MAX_BUS_CLK];
> ?};
>
> +/**
> + * struct sdhci_s3c_driver_data - S3C SDHCI platform specific driver data
> + * @sdhci_quirks: sdhci host specific quirks.
> + *
> + * Specifies platform specific configuration of sdhci controller.
> + * Note: A structure for driver specific platform data is used for future
> + * expansion of its usage.
> + */
> +struct sdhci_s3c_drv_data {
> + ? ? ? unsigned int ? ?sdhci_quirks;
> +};
> +
> ?static inline struct sdhci_s3c *to_s3c(struct sdhci_host *host)
> ?{
> ? ? ? ?return sdhci_priv(host);
> @@ -132,10 +144,10 @@ static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c *ourhost,
> ? ? ? ? ? ? ? ?return UINT_MAX;
>
> ? ? ? ?/*
> - ? ? ? ?* Clock divider's step is different as 1 from that of host controller
> - ? ? ? ?* when 'clk_type' is S3C_SDHCI_CLK_DIV_EXTERNAL.
> + ? ? ? ?* If controller uses a non-standard clock division, find the best clock
> + ? ? ? ?* speed possible with selected clock source and skip the division.
> ? ? ? ? */
> - ? ? ? if (ourhost->pdata->clk_type) {
> + ? ? ? if (ourhost->host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) {
> ? ? ? ? ? ? ? ?rate = clk_round_rate(clksrc, wanted);
> ? ? ? ? ? ? ? ?return wanted - rate;
> ? ? ? ?}
> @@ -272,6 +284,8 @@ static unsigned int sdhci_cmu_get_min_clock(struct sdhci_host *host)
> ?static void sdhci_cmu_set_clock(struct sdhci_host *host, unsigned int clock)
> ?{
> ? ? ? ?struct sdhci_s3c *ourhost = to_s3c(host);
> + ? ? ? unsigned long timeout;
> + ? ? ? u16 clk = 0;
>
> ? ? ? ?/* don't bother if the clock is going off */
> ? ? ? ?if (clock == 0)
> @@ -282,6 +296,25 @@ static void sdhci_cmu_set_clock(struct sdhci_host *host, unsigned int clock)
> ? ? ? ?clk_set_rate(ourhost->clk_bus[ourhost->cur_clk], clock);
>
> ? ? ? ?host->clock = clock;
> +
> + ? ? ? clk = SDHCI_CLOCK_INT_EN;
> + ? ? ? sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
> +
> + ? ? ? /* Wait max 20 ms */
> + ? ? ? timeout = 20;
> + ? ? ? while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
> + ? ? ? ? ? ? ? & SDHCI_CLOCK_INT_STABLE)) {
> + ? ? ? ? ? ? ? if (timeout == 0) {
> + ? ? ? ? ? ? ? ? ? ? ? printk(KERN_ERR "%s: Internal clock never "
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? "stabilised.\n", mmc_hostname(host->mmc));
> + ? ? ? ? ? ? ? ? ? ? ? return;
> + ? ? ? ? ? ? ? }
> + ? ? ? ? ? ? ? timeout--;
> + ? ? ? ? ? ? ? mdelay(1);
> + ? ? ? }
> +
> + ? ? ? clk |= SDHCI_CLOCK_CARD_EN;
> + ? ? ? sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
> ?}
>
> ?/**
> @@ -382,9 +415,17 @@ static void sdhci_s3c_setup_card_detect_gpio(struct sdhci_s3c *sc)
> ? ? ? ?}
> ?}
>
> +static inline struct sdhci_s3c_drv_data *sdhci_s3c_get_driver_data(
> + ? ? ? ? ? ? ? ? ? ? ? struct platform_device *pdev)
> +{
> + ? ? ? return (struct sdhci_s3c_drv_data *)
> + ? ? ? ? ? ? ? ? ? ? ? platform_get_device_id(pdev)->driver_data;
> +}
> +
> ?static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
> ?{
> ? ? ? ?struct s3c_sdhci_platdata *pdata = pdev->dev.platform_data;
> + ? ? ? struct sdhci_s3c_drv_data *drv_data;
> ? ? ? ?struct device *dev = &pdev->dev;
> ? ? ? ?struct sdhci_host *host;
> ? ? ? ?struct sdhci_s3c *sc;
> @@ -414,6 +455,7 @@ static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
> ? ? ? ? ? ? ? ?return PTR_ERR(host);
> ? ? ? ?}
>
> + ? ? ? drv_data = sdhci_s3c_get_driver_data(pdev);
> ? ? ? ?sc = sdhci_priv(host);
>
> ? ? ? ?sc->host = host;
> @@ -494,6 +536,8 @@ static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
> ? ? ? ?/* Setup quirks for the controller */
> ? ? ? ?host->quirks |= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC;
> ? ? ? ?host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
> + ? ? ? if (drv_data)
> + ? ? ? ? ? ? ? host->quirks |= drv_data->sdhci_quirks;
>
> ?#ifndef CONFIG_MMC_SDHCI_S3C_DMA
>
> @@ -534,7 +578,7 @@ static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
> ? ? ? ? * If controller does not have internal clock divider,
> ? ? ? ? * we can use overriding functions instead of default.
> ? ? ? ? */
> - ? ? ? if (pdata->clk_type) {
> + ? ? ? if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) {
> ? ? ? ? ? ? ? ?sdhci_s3c_ops.set_clock = sdhci_cmu_set_clock;
> ? ? ? ? ? ? ? ?sdhci_s3c_ops.get_min_clock = sdhci_cmu_get_min_clock;
> ? ? ? ? ? ? ? ?sdhci_s3c_ops.get_max_clock = sdhci_cmu_get_max_clock;
> @@ -639,9 +683,31 @@ static int sdhci_s3c_resume(struct platform_device *dev)
> ?#define sdhci_s3c_resume NULL
> ?#endif
>
> +#if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212)
> +static struct sdhci_s3c_drv_data exynos4_sdhci_drv_data = {
> + ? ? ? .sdhci_quirks = SDHCI_QUIRK_NONSTANDARD_CLOCK,
> +};
> +#define EXYNOS4_SDHCI_DRV_DATA ((kernel_ulong_t)&exynos4_sdhci_drv_data)
> +#else
> +#define EXYNOS4_SDHCI_DRV_DATA (kernel_ulong_t)NULL
> +#endif
It's too small to save the memory. I think no need to guard the exynos
driver data with ifdef/endif.
> +
> +static struct platform_device_id sdhci_s3c_driver_ids[] = {
> + ? ? ? {
> + ? ? ? ? ? ? ? .name ? ? ? ? ? = "s3c-sdhci",
> + ? ? ? ? ? ? ? .driver_data ? ?= (kernel_ulong_t)NULL,
> + ? ? ? },
> + ? ? ? {
> + ? ? ? ? ? ? ? .name ? ? ? ? ? = "exynos4-sdhci",
> + ? ? ? ? ? ? ? .driver_data ? ?= EXYNOS4_SDHCI_DRV_DATA,
> + ? ? ? },
> +};
> +MODULE_DEVICE_TABLE(platform, sdhci_s3c_driver_ids);
Do you have a plan to use the sdhci-pltfm.c as other drivers did?
some drivers are already use it and support OF features.
Thank you,
Kyungmin Park
> +
> ?static struct platform_driver sdhci_s3c_driver = {
> ? ? ? ?.probe ? ? ? ? ?= sdhci_s3c_probe,
> ? ? ? ?.remove ? ? ? ? = __devexit_p(sdhci_s3c_remove),
> + ? ? ? .id_table ? ? ? = sdhci_s3c_driver_ids,
> ? ? ? ?.suspend ? ? ? ?= sdhci_s3c_suspend,
> ? ? ? ?.resume ? ? ? ? = sdhci_s3c_resume,
> ? ? ? ?.driver ? ? ? ? = {
> --
> 1.6.6.rc2
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at ?http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply
* [PATCH 1/3] mmc: sdhci-s3c: Remove usage of clk_type member in platform data
From: Thomas Abraham @ 2011-10-04 8:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAH9JG2VKeRujhEUA=y7UuncwUFrMqtdnkpiVqz0VHCF1nPK4_Q@mail.gmail.com>
Hi Mr. Park,
On 4 October 2011 13:23, Kyungmin Park <kmpark@infradead.org> wrote:
> Hi,
>
> On Tue, Oct 4, 2011 at 4:28 PM, Thomas Abraham
> <thomas.abraham@linaro.org> wrote:
>> SDHCI controllers on Exynos4 do not include the sdclk divider as per the
>> sdhci controller specification. This case can be represented using the
>> sdhci quirk SDHCI_QUIRK_NONSTANDARD_CLOCK instead of using an additional
>> enum type definition 'clk_types'.
>>
>> Hence, usage of clk_type member in platform data is removed and the sdhci
>> quirk is used. In addition to that, since this qurik is SoC specific,
>> driver data is introduced to represent controllers on SoC's that require
>> this quirk.
> Right.
>>
>> Cc: Ben Dooks <ben-linux@fluff.org>
>> Cc: Jeongbae Seo <jeongbae.seo@samsung.com>
>> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
>> ---
>> In the function 'sdhci_cmu_set_clock', the code that waits for a stable
>> sdclk clock is replicated from 'sdhci_set_clock' function. This portion
>> of code is replicated in sdhci-cns3xxx driver as well. This duplication
>> could have been avoid by adding a new function in sdhci host controller
>> driver that waits for stable sdclk and sdhci-s3c/sdhci-cns3xxx can be
>> the users of the new function. If adding a new function in sdhci host
>> controller driver is acceptable, an additional patch in this series
>> can be added that creates the new function that waits for stable sdclk.
>>
>> ?drivers/mmc/host/sdhci-s3c.c | ? 74 +++++++++++++++++++++++++++++++++++++++--
>> ?1 files changed, 70 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
>> index 82709b6..b29e734 100644
>> --- a/drivers/mmc/host/sdhci-s3c.c
>> +++ b/drivers/mmc/host/sdhci-s3c.c
>> @@ -53,6 +53,18 @@ struct sdhci_s3c {
>> ? ? ? ?struct clk ? ? ? ? ? ? ?*clk_bus[MAX_BUS_CLK];
>> ?};
>>
>> +/**
>> + * struct sdhci_s3c_driver_data - S3C SDHCI platform specific driver data
>> + * @sdhci_quirks: sdhci host specific quirks.
>> + *
>> + * Specifies platform specific configuration of sdhci controller.
>> + * Note: A structure for driver specific platform data is used for future
>> + * expansion of its usage.
>> + */
>> +struct sdhci_s3c_drv_data {
>> + ? ? ? unsigned int ? ?sdhci_quirks;
>> +};
>> +
>> ?static inline struct sdhci_s3c *to_s3c(struct sdhci_host *host)
>> ?{
>> ? ? ? ?return sdhci_priv(host);
>> @@ -132,10 +144,10 @@ static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c *ourhost,
>> ? ? ? ? ? ? ? ?return UINT_MAX;
>>
>> ? ? ? ?/*
>> - ? ? ? ?* Clock divider's step is different as 1 from that of host controller
>> - ? ? ? ?* when 'clk_type' is S3C_SDHCI_CLK_DIV_EXTERNAL.
>> + ? ? ? ?* If controller uses a non-standard clock division, find the best clock
>> + ? ? ? ?* speed possible with selected clock source and skip the division.
>> ? ? ? ? */
>> - ? ? ? if (ourhost->pdata->clk_type) {
>> + ? ? ? if (ourhost->host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) {
>> ? ? ? ? ? ? ? ?rate = clk_round_rate(clksrc, wanted);
>> ? ? ? ? ? ? ? ?return wanted - rate;
>> ? ? ? ?}
>> @@ -272,6 +284,8 @@ static unsigned int sdhci_cmu_get_min_clock(struct sdhci_host *host)
>> ?static void sdhci_cmu_set_clock(struct sdhci_host *host, unsigned int clock)
>> ?{
>> ? ? ? ?struct sdhci_s3c *ourhost = to_s3c(host);
>> + ? ? ? unsigned long timeout;
>> + ? ? ? u16 clk = 0;
>>
>> ? ? ? ?/* don't bother if the clock is going off */
>> ? ? ? ?if (clock == 0)
>> @@ -282,6 +296,25 @@ static void sdhci_cmu_set_clock(struct sdhci_host *host, unsigned int clock)
>> ? ? ? ?clk_set_rate(ourhost->clk_bus[ourhost->cur_clk], clock);
>>
>> ? ? ? ?host->clock = clock;
>> +
>> + ? ? ? clk = SDHCI_CLOCK_INT_EN;
>> + ? ? ? sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
>> +
>> + ? ? ? /* Wait max 20 ms */
>> + ? ? ? timeout = 20;
>> + ? ? ? while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
>> + ? ? ? ? ? ? ? & SDHCI_CLOCK_INT_STABLE)) {
>> + ? ? ? ? ? ? ? if (timeout == 0) {
>> + ? ? ? ? ? ? ? ? ? ? ? printk(KERN_ERR "%s: Internal clock never "
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? "stabilised.\n", mmc_hostname(host->mmc));
>> + ? ? ? ? ? ? ? ? ? ? ? return;
>> + ? ? ? ? ? ? ? }
>> + ? ? ? ? ? ? ? timeout--;
>> + ? ? ? ? ? ? ? mdelay(1);
>> + ? ? ? }
>> +
>> + ? ? ? clk |= SDHCI_CLOCK_CARD_EN;
>> + ? ? ? sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
>> ?}
>>
>> ?/**
>> @@ -382,9 +415,17 @@ static void sdhci_s3c_setup_card_detect_gpio(struct sdhci_s3c *sc)
>> ? ? ? ?}
>> ?}
>>
>> +static inline struct sdhci_s3c_drv_data *sdhci_s3c_get_driver_data(
>> + ? ? ? ? ? ? ? ? ? ? ? struct platform_device *pdev)
>> +{
>> + ? ? ? return (struct sdhci_s3c_drv_data *)
>> + ? ? ? ? ? ? ? ? ? ? ? platform_get_device_id(pdev)->driver_data;
>> +}
>> +
>> ?static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
>> ?{
>> ? ? ? ?struct s3c_sdhci_platdata *pdata = pdev->dev.platform_data;
>> + ? ? ? struct sdhci_s3c_drv_data *drv_data;
>> ? ? ? ?struct device *dev = &pdev->dev;
>> ? ? ? ?struct sdhci_host *host;
>> ? ? ? ?struct sdhci_s3c *sc;
>> @@ -414,6 +455,7 @@ static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
>> ? ? ? ? ? ? ? ?return PTR_ERR(host);
>> ? ? ? ?}
>>
>> + ? ? ? drv_data = sdhci_s3c_get_driver_data(pdev);
>> ? ? ? ?sc = sdhci_priv(host);
>>
>> ? ? ? ?sc->host = host;
>> @@ -494,6 +536,8 @@ static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
>> ? ? ? ?/* Setup quirks for the controller */
>> ? ? ? ?host->quirks |= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC;
>> ? ? ? ?host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
>> + ? ? ? if (drv_data)
>> + ? ? ? ? ? ? ? host->quirks |= drv_data->sdhci_quirks;
>>
>> ?#ifndef CONFIG_MMC_SDHCI_S3C_DMA
>>
>> @@ -534,7 +578,7 @@ static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
>> ? ? ? ? * If controller does not have internal clock divider,
>> ? ? ? ? * we can use overriding functions instead of default.
>> ? ? ? ? */
>> - ? ? ? if (pdata->clk_type) {
>> + ? ? ? if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) {
>> ? ? ? ? ? ? ? ?sdhci_s3c_ops.set_clock = sdhci_cmu_set_clock;
>> ? ? ? ? ? ? ? ?sdhci_s3c_ops.get_min_clock = sdhci_cmu_get_min_clock;
>> ? ? ? ? ? ? ? ?sdhci_s3c_ops.get_max_clock = sdhci_cmu_get_max_clock;
>> @@ -639,9 +683,31 @@ static int sdhci_s3c_resume(struct platform_device *dev)
>> ?#define sdhci_s3c_resume NULL
>> ?#endif
>>
>> +#if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212)
>> +static struct sdhci_s3c_drv_data exynos4_sdhci_drv_data = {
>> + ? ? ? .sdhci_quirks = SDHCI_QUIRK_NONSTANDARD_CLOCK,
>> +};
>> +#define EXYNOS4_SDHCI_DRV_DATA ((kernel_ulong_t)&exynos4_sdhci_drv_data)
>> +#else
>> +#define EXYNOS4_SDHCI_DRV_DATA (kernel_ulong_t)NULL
>> +#endif
> It's too small to save the memory. I think no need to guard the exynos
> driver data with ifdef/endif.
There could be other elements added to the 'sdhci_s3c_drv_data'
structure as new variants of sdhci-s3c controller would appear in
future SoC. I am not aware of any such variations in the upcoming
SoC's but this was done taking into consideration that there could be
slight variations which the driver would have to support.
>> +
>> +static struct platform_device_id sdhci_s3c_driver_ids[] = {
>> + ? ? ? {
>> + ? ? ? ? ? ? ? .name ? ? ? ? ? = "s3c-sdhci",
>> + ? ? ? ? ? ? ? .driver_data ? ?= (kernel_ulong_t)NULL,
>> + ? ? ? },
>> + ? ? ? {
>> + ? ? ? ? ? ? ? .name ? ? ? ? ? = "exynos4-sdhci",
>> + ? ? ? ? ? ? ? .driver_data ? ?= EXYNOS4_SDHCI_DRV_DATA,
>> + ? ? ? },
>> +};
>> +MODULE_DEVICE_TABLE(platform, sdhci_s3c_driver_ids);
>
> Do you have a plan to use the sdhci-pltfm.c as other drivers did?
> some drivers are already use it and support OF features.
I did check few months back if sdhci-pltfm.c can be used for sdhci-s3c
drivers but due to slightly complex operations which sdhci-s3c
handles, I did not try to base samsung sdhci driver support on
sdhci-pltfm.c. So, at present, I do not have a plan to move to
sdhci-pltfm.c.
>
> Thank you,
> Kyungmin Park
Thanks for your review and comments.
Regards,
Thomas.
>> +
>> ?static struct platform_driver sdhci_s3c_driver = {
>> ? ? ? ?.probe ? ? ? ? ?= sdhci_s3c_probe,
>> ? ? ? ?.remove ? ? ? ? = __devexit_p(sdhci_s3c_remove),
>> + ? ? ? .id_table ? ? ? = sdhci_s3c_driver_ids,
>> ? ? ? ?.suspend ? ? ? ?= sdhci_s3c_suspend,
>> ? ? ? ?.resume ? ? ? ? = sdhci_s3c_resume,
>> ? ? ? ?.driver ? ? ? ? = {
>> --
>> 1.6.6.rc2
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
>> the body of a message to majordomo at vger.kernel.org
>> More majordomo info at ?http://vger.kernel.org/majordomo-info.html
>>
>
^ permalink raw reply
* [RFC PATCH] tty/serial: atmel_serial: add device tree support
From: Nicolas Ferre @ 2011-10-04 8:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4E8A6858.6020700@gmail.com>
On 10/04/2011 03:58 AM, Rob Herring :
> On 10/03/2011 04:51 AM, Nicolas Ferre wrote:
>> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
>> ---
>> Hi,
>>
>> Here is a first attempt to add device tree support to atmel_serial driver.
>> RS485 data are not handled for the moment. My feeling is that they should be
>> added as a generic DT biding set.
>
> Feel free to propose something. :)
Yes, I will have a look and practice my DT understanding on this...
>> .../devicetree/bindings/tty/serial/atmel-usart.txt | 27 +++++++++
>> drivers/tty/serial/atmel_serial.c | 56 +++++++++++++++++---
>> 2 files changed, 75 insertions(+), 8 deletions(-)
>> create mode 100644 Documentation/devicetree/bindings/tty/serial/atmel-usart.txt
>>
>> diff --git a/Documentation/devicetree/bindings/tty/serial/atmel-usart.txt b/Documentation/devicetree/bindings/tty/serial/atmel-usart.txt
>> new file mode 100644
>> index 0000000..a49d9a1
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/tty/serial/atmel-usart.txt
>> @@ -0,0 +1,27 @@
>> +* Atmel Universal Synchronous Asynchronous Receiver/Transmitter (USART)
>> +
>> +Required properties:
>> +- compatible: Should be "atmel,<chip>-usart"
>> + The compatible <chip> indicated will be the first SoC to support an
>> + additional mode or an USART new feature.
>> +- reg: Should contain registers location and length
>> +- interrupts: Should contain interrupt
>> +
>> +Optional properties:
>> +- atmel,use-dma-rx: use of PDC or DMA for receiving data
>> +- atmel,use-dma-tx: use of PDC or DMA for transmitting data
>
> Is this an internal DMA or separate DMA controller? If the latter, these
> should be phandles to a DMA channel/request.
Well, for now it relies on PDC (looks like an internal DMA). There is no
notion of channel/request so I think it is appropriate to keep it like this.
>> +<chip> compatible description:
>> +- at91rm9200: legacy USART support
>> +- at91sam9260: generic USART implementation for SAM9 SoCs
>> +
>> +Example:
>> +
>> + usart0: serial at fff8c000 {
>> + compatible = "atmel,at91sam9260-usart";
>> + reg = <0xfff8c000 0x4000>;
>> + interrupts = <7>;
>> + atmel,use-dma-rx;
>> + atmel,use-dma-tx;
>> + };
>> +
>> diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c
>> index 453cdb5..65f56c3 100644
>> --- a/drivers/tty/serial/atmel_serial.c
>> +++ b/drivers/tty/serial/atmel_serial.c
>> @@ -33,6 +33,8 @@
>> #include <linux/sysrq.h>
>> #include <linux/tty_flip.h>
>> #include <linux/platform_device.h>
>> +#include <linux/of.h>
>> +#include <linux/of_device.h>
>> #include <linux/dma-mapping.h>
>> #include <linux/atmel_pdc.h>
>> #include <linux/atmel_serial.h>
>> @@ -162,6 +164,16 @@ static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
>> static struct console atmel_console;
>> #endif
>>
>> +#if defined(CONFIG_OF)
>> +static const struct of_device_id atmel_serial_dt_ids[] = {
>> + { .compatible = "atmel,at91rm9200-usart" },
>> + { .compatible = "atmel,at91sam9260-usart" },
>> + { /* sentinel */ }
>> +};
>> +
>> +MODULE_DEVICE_TABLE(of, atmel_serial_dt_ids);
>> +#endif
>
> This ifdef isn't necessary, but it really depends if long term this
> driver will be built without OF (and you care about the extra data).
Yes, even in long term, this driver will be built without OF support. It
is true though that the extra data is not very big...
>> static inline struct atmel_uart_port *
>> to_atmel_uart_port(struct uart_port *uart)
>> {
>> @@ -1413,14 +1425,31 @@ static struct uart_ops atmel_pops = {
>> static void __devinit atmel_init_port(struct atmel_uart_port *atmel_port,
>> struct platform_device *pdev)
>> {
>> + struct device_node *np = pdev->dev.of_node;
>> struct uart_port *port = &atmel_port->uart;
>> struct atmel_uart_data *pdata = pdev->dev.platform_data;
>> + int ret;
>> +
>> + if (np) {
>> + ret = of_alias_get_id(np, "serial");
>> + if (ret >= 0)
>> + port->line = ret;
>> + if (of_get_property(np, "atmel,use-dma-rx", NULL))
>> + atmel_port->use_dma_rx = 1;
>> + if (of_get_property(np, "atmel,use-dma-tx", NULL))
>> + atmel_port->use_dma_tx = 1;
>> + } else {
>> + port->line = pdata->num;
>> +
>> + atmel_port->use_dma_rx = pdata->use_dma_rx;
>> + atmel_port->use_dma_tx = pdata->use_dma_tx;
>> + atmel_port->rs485 = pdata->rs485;
>> + }
>>
>> port->iotype = UPIO_MEM;
>> port->flags = UPF_BOOT_AUTOCONF;
>> port->ops = &atmel_pops;
>> port->fifosize = 1;
>> - port->line = pdata->num;
>> port->dev = &pdev->dev;
>> port->mapbase = pdev->resource[0].start;
>> port->irq = pdev->resource[1].start;
>> @@ -1430,7 +1459,7 @@ static void __devinit atmel_init_port(struct atmel_uart_port *atmel_port,
>>
>> memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
>>
>> - if (pdata->regs) {
>> + if (pdata && pdata->regs) {
>> /* Already mapped by setup code */
>> port->membase = pdata->regs;
>> } else {
>> @@ -1447,10 +1476,6 @@ static void __devinit atmel_init_port(struct atmel_uart_port *atmel_port,
>> /* only enable clock when USART is in use */
>> }
>>
>> - atmel_port->use_dma_rx = pdata->use_dma_rx;
>> - atmel_port->use_dma_tx = pdata->use_dma_tx;
>> - atmel_port->rs485 = pdata->rs485;
>> -
>> /* Use TXEMPTY for interrupt when rs485 else TXRDY or ENDTX|TXBUFE */
>> if (atmel_port->rs485.flags & SER_RS485_ENABLED)
>> atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
>> @@ -1710,13 +1735,27 @@ static int atmel_serial_resume(struct platform_device *pdev)
>> static int __devinit atmel_serial_probe(struct platform_device *pdev)
>> {
>> struct atmel_uart_port *port;
>> + struct device_node *np = pdev->dev.of_node;
>> struct atmel_uart_data *pdata = pdev->dev.platform_data;
>> void *data;
>> int ret;
>>
>> BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
>>
>> - port = &atmel_ports[pdata->num];
>> + if (np) {
>> + ret = of_alias_get_id(np, "serial");
>
> I'll defer to Grant on this. There aren't any other drivers using this.
I took the IMX serial driver as an example which is in devicetree/next
branch (tty/serial/imx.c).
Is it the proper way to use this?
>> + if (ret < 0)
>> + goto err;
>> + } else {
>> + if (pdata) {
>> + ret = pdata->num;
>> + } else {
>> + ret = -ENODEV;
>> + goto err;
>> + }
>> + }
>
> This would a bit more concise:
>
> } else if (pdata) {
> ret = pdata->num;
> } else {
> ret = -ENODEV;
> goto err;
> }
Ok.
Thanks for your review Rob.
Best regards,
--
Nicolas Ferre
^ permalink raw reply
* [PATCH] arm/tegra: select AUTO_ZRELADDR by default
From: Peter De Schrijver @ 2011-10-04 8:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <74CDBE0F657A3D45AFBB94109FB122FF173A2C6CAA@HQMAIL01.nvidia.com>
On Mon, Oct 03, 2011 at 06:22:47PM +0200, Stephen Warren wrote:
> Peter De Schrijver wrote at Monday, October 03, 2011 7:14 AM:
> > Ignore this one.
>
> I assume only ignore this copy of the patch because it's a duplicate;
> the patch itself is still needed, right?
Yes.
Cheers,
Peter.
^ permalink raw reply
* [PATCH] Add missing include of linux/ftrace.h
From: Jamie Iles @ 2011-10-04 8:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAH+eYFBESAp8Hz6fBAqjWSgAkzPuAub4JqU4r3SDU+TQTRagBA@mail.gmail.com>
On Sun, Oct 02, 2011 at 12:34:45AM +0530, Rabin Vincent wrote:
> On Sat, Oct 1, 2011 at 22:42, Jamie Iles <jamie@jamieiles.com> wrote:
> > diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
> > index de3dcab..61c1468 100644
> > --- a/arch/arm/kernel/irq.c
> > +++ b/arch/arm/kernel/irq.c
> > @@ -37,6 +37,7 @@
> > ?#include <linux/proc_fs.h>
> > ?#include <linux/ftrace.h>
>
> You can probably git rid of this inclusion of ftrace.h from
> here and from smp.c, because they were added only for
> __exception_irq_entry.
OK, I've updated the patch in Russell's tracker removing these includes.
Jamie
^ permalink raw reply
* [PATCH v3 3/3] ARM: OMAP: TI814X: Create board support and enable build for TI8148 EVM
From: Igor Grinberg @ 2011-10-04 9:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <2A3DCF3DA181AD40BDE86A3150B27B6B03B4EC5D52@dbde02.ent.ti.com>
On 10/03/11 18:45, Pedanekar, Hemant wrote:
> Hi Igor,
>
> Igor Grinberg wrote on Sunday, October 02, 2011 5:38 PM:
>
>> Hi Hemant,
>>
>> On 09/29/11 04:09, Hemant Pedanekar wrote:
>>> This patch adds minimal support and build configuration for TI8148 EVM.
>>> Also adds support for low level debugging on UART1 console on the EVM.
>>>
>>> Note that existing TI8168 EVM file (board-ti8168evm.c) is updated with
>>> machine info for TI8148 EVM and renamed as board-ti81xxevm.c.
>>
>> Should we really rename the existing file?
>> Shouldn't we just stick to the name of the file submitted first?
>> (e.g. board-ti8168evm.c) and just add the support for the new
>> TI8148 EVM in to the existing file?
>
> But won't this be misleading?
Misleading? For whom?
Actually, I don't really care how you call that file.
What I care (and I think not just me) is uniformity, so
if we decide to rename all those files that have multiple
boards supported in them, I'm fine with it.
So pros for my proposed approach would be:
1) Currently, there are already board files with multiple boards
supported in them that follow the approach and renaming them is
really unnecessary.
2) git log will not break.
3) boards that cannot be named after the convention like 81xx
but can be added to the same file will not require further renaming
(like 82x8 - I don't really know if that will exist, just wondering).
4) This renaming is really what Linus likes ;)
cons:
1) Misleading?
Currently, I don't think this renaming is good for anything,
especially that majority of the board stuff should be transformed
to the DT descriptors.
--
Regards,
Igor.
^ permalink raw reply
* [PULL] i.MX
From: Sascha Hauer @ 2011-10-04 9:20 UTC (permalink / raw)
To: linux-arm-kernel
Hi Arnd,
Please pull the following for next. There are merge conflicts between
the cleanup and the features branch, so I decided to merge them together
so you don't have to handle the conflicts yourself. Please let me know
if this is ok for you or if we have to find another solution.
Sascha
The following changes since commit dfa690cd787c72468f8d633c0be81330e4466c08:
Merge branch 'next/dmtimer' into for-next (2011-10-01 18:51:54 +0200)
are available in the git repository at:
git://git.pengutronix.de/git/imx/linux-2.6.git for-arnd
Arnaud Patard (2):
Fix pata imx resource
efika: Configure esdhc cd/wp on efika mx/sb
Fabio Estevam (3):
ARM: mach-qong: Add watchdog support
ARM: mach-mxs/mx28evk: Only register devices if their GPIO requests succeeded
ARM: mxs: Consolidate mm-mx23.c and mm-mx28.c into a single file
Hui Wang (1):
ARM i.MX avic: convert to use generic irq chip
Jason Liu (4):
ARM: mx5/mm: move i.MX50 mm stuff into mm.c
ARM: mx5/mm: Remove MX51_DEBUG related mapping
ARM: mx5/mm: consolidate TZIC map code
ARM: mx25: Add the missing IIM base definition
Philippe R?tornaz (1):
mx31moboard: Add poweroff support
Sascha Hauer (8):
Merge branches 'cleanups/assorted' and 'cleanups/mm-tzic' into imx-cleanup
ARM i.MX avic: add handle_irq function
ARM i.MX tzic: add handle_irq function
ARM i.MX boards: use CONFIG_MULTI_IRQ_HANDLER
ARM i.MX entry-macro.S: remove now unused code
Merge branches 'features/assorted', 'features/imx-pata' and 'features/imx-multi-irq-v2' into imx-features
Merge branches 'cleanups/mx3-mm-v2' and 'cleanups/mxs' into imx-cleanup
Merge branch 'imx-features' into for-arnd
Shawn Guo (5):
arm/imx: merge mm-imx35.c into mm-imx31.c
arm/imx: rename mm-imx31.c to mm-imx3.c
arm/imx: change mxc_init_l2x0() to an imx31/35 specific call
arm/imx: remove cpu_is_xxx() from arch_idle()
arm/imx: remove cpu_is_xxx() check from __imx_ioremap()
arch/arm/Kconfig | 1 +
arch/arm/mach-imx/Kconfig | 1 +
arch/arm/mach-imx/Makefile | 15 +-
arch/arm/mach-imx/cache-l2x0.c | 56 -
arch/arm/mach-imx/mach-apf9328.c | 1 +
arch/arm/mach-imx/mach-armadillo5x0.c | 19 +-
arch/arm/mach-imx/mach-bug.c | 1 +
arch/arm/mach-imx/mach-cpuimx27.c | 1 +
arch/arm/mach-imx/mach-cpuimx35.c | 3 +-
arch/arm/mach-imx/mach-eukrea_cpuimx25.c | 1 +
arch/arm/mach-imx/mach-imx27_visstrim_m10.c | 1 +
arch/arm/mach-imx/mach-imx27ipcam.c | 1 +
arch/arm/mach-imx/mach-imx27lite.c | 1 +
arch/arm/mach-imx/mach-kzm_arm11_01.c | 1 +
arch/arm/mach-imx/mach-mx1ads.c | 17 +-
arch/arm/mach-imx/mach-mx21ads.c | 1 +
arch/arm/mach-imx/mach-mx25_3ds.c | 1 +
arch/arm/mach-imx/mach-mx27_3ds.c | 3 +-
arch/arm/mach-imx/mach-mx27ads.c | 1 +
arch/arm/mach-imx/mach-mx31_3ds.c | 1 +
arch/arm/mach-imx/mach-mx31ads.c | 1 +
arch/arm/mach-imx/mach-mx31lilly.c | 1 +
arch/arm/mach-imx/mach-mx31lite.c | 1 +
arch/arm/mach-imx/mach-mx31moboard.c | 18 +
arch/arm/mach-imx/mach-mx35_3ds.c | 1 +
arch/arm/mach-imx/mach-mxt_td60.c | 1 +
arch/arm/mach-imx/mach-pca100.c | 1 +
arch/arm/mach-imx/mach-pcm037.c | 1 +
arch/arm/mach-imx/mach-pcm038.c | 1 +
arch/arm/mach-imx/mach-pcm043.c | 1 +
arch/arm/mach-imx/mach-qong.c | 2 +
arch/arm/mach-imx/mach-scb9328.c | 1 +
arch/arm/mach-imx/mach-vpr200.c | 3 +-
arch/arm/mach-imx/mm-imx3.c | 256 ++
arch/arm/mach-imx/mm-imx31.c | 91 -
arch/arm/mach-imx/mm-imx35.c | 109 -
arch/arm/mach-imx/pm-imx27.c | 2 +-
arch/arm/mach-mx5/Kconfig | 10 +-
arch/arm/mach-mx5/Makefile | 3 +-
arch/arm/mach-mx5/board-cpuimx51.c | 28 +-
arch/arm/mach-mx5/board-cpuimx51sd.c | 26 +-
arch/arm/mach-mx5/board-mx50_rdp.c | 1 +
arch/arm/mach-mx5/board-mx51_3ds.c | 2 +-
arch/arm/mach-mx5/board-mx51_babbage.c | 27 +-
arch/arm/mach-mx5/board-mx51_efikamx.c | 14 +-
arch/arm/mach-mx5/board-mx51_efikasb.c | 25 +-
arch/arm/mach-mx5/board-mx53_ard.c | 5 +-
arch/arm/mach-mx5/board-mx53_evk.c | 1 +
arch/arm/mach-mx5/board-mx53_loco.c | 1 +
arch/arm/mach-mx5/board-mx53_smd.c | 1 +
arch/arm/mach-mx5/clock-mx51-mx53.c | 2 +-
arch/arm/mach-mx5/devices-imx51.h | 13 +
arch/arm/mach-mx5/devices.c | 120 -
arch/arm/mach-mx5/devices.h | 5 -
arch/arm/mach-mx5/ehci.c | 2 +-
arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c | 3 +-
arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c | 6 +-
arch/arm/mach-mx5/mm-mx50.c | 72 -
arch/arm/mach-mx5/mm.c | 90 +-
arch/arm/mach-mx5/mx51_efika.c | 18 +-
arch/arm/mach-mx5/pm-imx5.c | 3 +-
arch/arm/mach-mx5/system.c | 1 +
arch/arm/mach-mxs/Makefile | 6 +-
arch/arm/mach-mxs/include/mach/gpio.h | 4 -
arch/arm/mach-mxs/include/mach/mxs.h | 2 +
arch/arm/mach-mxs/mach-mx23evk.c | 1 -
arch/arm/mach-mxs/mach-mx28evk.c | 24 +-
arch/arm/mach-mxs/mach-stmp378x_devb.c | 1 -
arch/arm/mach-mxs/mm-mx28.c | 44 -
arch/arm/mach-mxs/{mm-mx23.c => mm.c} | 19 +
arch/arm/plat-mxc/audmux-v2.c | 18 +-
arch/arm/plat-mxc/avic.c | 91 +-
arch/arm/plat-mxc/devices.c | 14 -
arch/arm/plat-mxc/devices/Kconfig | 2 +-
arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c | 5 +
arch/arm/plat-mxc/devices/platform-imx-i2c.c | 6 +
arch/arm/plat-mxc/devices/platform-mxc-ehci.c | 9 +
arch/arm/plat-mxc/devices/platform-pata_imx.c | 2 +-
arch/arm/plat-mxc/include/mach/common.h | 26 +-
arch/arm/plat-mxc/include/mach/entry-macro.S | 58 +-
arch/arm/plat-mxc/include/mach/gpio.h | 9 +-
arch/arm/plat-mxc/include/mach/hardware.h | 13 +-
arch/arm/plat-mxc/include/mach/io.h | 22 +-
arch/arm/plat-mxc/include/mach/iomux-mx3.h | 1 +
arch/arm/plat-mxc/include/mach/iomux-mx51.h | 2270 +++++---------
arch/arm/plat-mxc/include/mach/iomux-mx53.h | 3530 +++++++--------------
arch/arm/plat-mxc/include/mach/iomux-v3.h | 1 +
arch/arm/plat-mxc/include/mach/mx25.h | 1 +
arch/arm/plat-mxc/include/mach/mx51.h | 183 +-
arch/arm/plat-mxc/include/mach/mx53.h | 1 +
arch/arm/plat-mxc/include/mach/mxc.h | 7 -
arch/arm/plat-mxc/include/mach/system.h | 35 +-
arch/arm/plat-mxc/irq-common.c | 21 +-
arch/arm/plat-mxc/irq-common.h | 3 +-
arch/arm/plat-mxc/system.c | 3 +
arch/arm/plat-mxc/tzic.c | 32 +-
drivers/gpio/gpio-mxc.c | 12 +
drivers/gpio/gpio-mxs.c | 2 +
98 files changed, 2768 insertions(+), 4807 deletions(-)
delete mode 100644 arch/arm/mach-imx/cache-l2x0.c
create mode 100644 arch/arm/mach-imx/mm-imx3.c
delete mode 100644 arch/arm/mach-imx/mm-imx31.c
delete mode 100644 arch/arm/mach-imx/mm-imx35.c
delete mode 100644 arch/arm/mach-mx5/devices.c
delete mode 100644 arch/arm/mach-mx5/devices.h
delete mode 100644 arch/arm/mach-mx5/mm-mx50.c
delete mode 100644 arch/arm/mach-mxs/mm-mx28.c
rename arch/arm/mach-mxs/{mm-mx23.c => mm.c} (75%)
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply
* [RFC PATCH v2 0/6] TI81XX: Add clock and hwmod data
From: Paul Walmsley @ 2011-10-04 9:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1314119594-22647-1-git-send-email-hemantp@ti.com>
Hi,
On Tue, 23 Aug 2011, Hemant Pedanekar wrote:
> This patch set is the v2 of TI816X clock and hwmods patches sent earlier.
>
> The clock data is currently added only for TI816X, while minimal hwmod data
> common for TI816X and TI814X is added.
>
> This patch set depends on following patches:
> TI81XX: Prepare for addition of TI814X support
> TI814X: Add cpu type macros and detection support
> TI814X: Create board support and enable build for TI8148 EVM
>
> Please note that CHIP_IS_TI816X/CHIP_IS_TI814X are still being used and I will
> send update once SoC list usage is available.
I've been spending some time with these patches. A few aspects don't make
much sense to me. For example, looking at the TRMs, the 816x doesn't seem
to have powerdomains for HDVICP0, 1, or 2, although they are listed in the
patch. Also, the clockdomain layout is quite different between 814x and
816x, according to the TRMs. Are the patches more accurate than the TRMs,
or vice versa?
Will send over the current reworked patches for TI81XX PRCM accessors,
powerdomain code & data, and clockdomain code & data. They are intended
to apply over the TI814x patches that you sent recently. I'd like to get
your opinion(s) on these reworked patches. Please note, so far they have
only been compile-tested.
- Paul
^ permalink raw reply
* [RFC PATCH 0/5] Rework of the TI81xx PRCM support
From: Paul Walmsley @ 2011-10-04 9:31 UTC (permalink / raw)
To: linux-arm-kernel
This is a rework of the TI81xx PRCM, powerdomain, and clockdomain code and
data. Compile-tested only.
- Paul
---
Hemant Pedanekar (3):
ARM: OMAP: TI81XX: prcm: Add module and register offsets
ARM: OMAP: TI81xx: add powerdomain data
ARM: OMAP: TI81xx: add clockdomain data
Paul Walmsley (2):
ARM: OMAP: TI81xx: add powerdomain code
ARM: OMAP: TI81xx: add clockdomain control code
arch/arm/mach-omap2/Makefile | 7 +
arch/arm/mach-omap2/clockdomain.h | 3
arch/arm/mach-omap2/clockdomain81xx.c | 77 +++++++++
arch/arm/mach-omap2/clockdomains81xx_data.c | 223 +++++++++++++++++++++++++++
arch/arm/mach-omap2/io.c | 2
arch/arm/mach-omap2/powerdomain.h | 2
arch/arm/mach-omap2/powerdomain81xx.c | 81 ++++++++++
arch/arm/mach-omap2/powerdomain81xx_data.c | 91 +++++++++++
arch/arm/mach-omap2/prcm-regbits-81xx.h | 23 +++
arch/arm/mach-omap2/prcm814x.h | 62 ++++++++
arch/arm/mach-omap2/prcm816x.h | 186 +++++++++++++++++++++++
arch/arm/mach-omap2/prcm81xx.c | 184 ++++++++++++++++++++++
arch/arm/mach-omap2/prcm81xx.h | 212 ++++++++++++++++++++++++++
13 files changed, 1153 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-omap2/clockdomain81xx.c
create mode 100644 arch/arm/mach-omap2/clockdomains81xx_data.c
create mode 100644 arch/arm/mach-omap2/powerdomain81xx.c
create mode 100644 arch/arm/mach-omap2/powerdomain81xx_data.c
create mode 100644 arch/arm/mach-omap2/prcm-regbits-81xx.h
create mode 100644 arch/arm/mach-omap2/prcm814x.h
create mode 100644 arch/arm/mach-omap2/prcm816x.h
create mode 100644 arch/arm/mach-omap2/prcm81xx.c
create mode 100644 arch/arm/mach-omap2/prcm81xx.h
--
Signature
^ permalink raw reply
* [RFC PATCH 1/5] ARM: OMAP: TI81XX: prcm: Add module and register offsets
From: Paul Walmsley @ 2011-10-04 9:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20111004092947.9657.16166.stgit@dusk>
From: Hemant Pedanekar <hemantp@ti.com>
This patch adds some of the PRCM register offsets for the TI814X and
TI816X devices as required for the clockdomain, powerdomain, clock, and
hwmod data.
This patch is a collaboration between Hemant Pedanekar <hemantp@ti.com>
and Paul Walmsley <paul@pwsan.com>.
---
arch/arm/mach-omap2/Makefile | 1
arch/arm/mach-omap2/prcm814x.h | 62 +++++++++++++
arch/arm/mach-omap2/prcm816x.h | 186 +++++++++++++++++++++++++++++++++++++++
arch/arm/mach-omap2/prcm81xx.c | 32 +++++++
arch/arm/mach-omap2/prcm81xx.h | 193 ++++++++++++++++++++++++++++++++++++++++
5 files changed, 474 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-omap2/prcm814x.h
create mode 100644 arch/arm/mach-omap2/prcm816x.h
create mode 100644 arch/arm/mach-omap2/prcm81xx.c
create mode 100644 arch/arm/mach-omap2/prcm81xx.h
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index d4918ca..9c6b185 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -87,6 +87,7 @@ obj-$(CONFIG_ARCH_OMAP4) += prcm.o cm2xxx_3xxx.o cminst44xx.o \
cm44xx.o prcm_mpu44xx.o \
prminst44xx.o vc44xx_data.o \
vp44xx_data.o
+obj-$(CONFIG_SOC_OMAPTI81XX) += prcm81xx.o
# OMAP voltage domains
ifeq ($(CONFIG_PM),y)
diff --git a/arch/arm/mach-omap2/prcm814x.h b/arch/arm/mach-omap2/prcm814x.h
new file mode 100644
index 0000000..82ea300
--- /dev/null
+++ b/arch/arm/mach-omap2/prcm814x.h
@@ -0,0 +1,62 @@
+/*
+ * TI814X-specific PRCM register access macros
+ *
+ * Copyright (C) 2010-2011 Texas Instruments, Inc. - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRCM814X_H
+#define __ARCH_ARM_MACH_OMAP2_PRCM814X_H
+
+#include "prcm81xx.h"
+
+/* TI814X-specific PRCM instances */
+#define TI814X_CM_HDVICP_INST 0x0600 /* 256B */
+#define TI814X_CM_ISP_INST 0x0700 /* 256B */
+#define TI814X_CM_DSS_INST 0x0800 /* 256B */
+#define TI814X_PRM_HDVICP_INST 0x0c00 /* 256B */
+#define TI814X_PRM_ISP_INST 0x0d00 /* 256B */
+#define TI814X_PRM_DSS_INST 0x0e00 /* 256B */
+#define TI814X_PRM_ALWON_INST 0x1800 /* 1KiB */
+
+
+/*
+ * TI814x-specific PRCM registers offsets. The offsets below are
+ * relative to the PRCM instance base.
+ */
+
+/* CM_ALWON */
+#define TI814X_CM_ALWON_L3_SLOW_CLKSTCTRL_OFFSET 0x0000
+#define TI814X_CM_ALWON_L3_SLOW_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0000)
+#define TI814X_CM_ALWON_L3_MED_CLKSTCTRL_OFFSET 0x0008
+#define TI814X_CM_ALWON_L3_MED_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0008)
+
+/* CM_HDVICP */
+#define TI814X_CM_HDVICP_CLKSTCTRL_OFFSET 0x0000
+#define TI814X_CM_HDVICP_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_HDVICP_INST, 0x0000)
+
+/* CM_ISP */
+#define TI814X_CM_ISP_CLKSTCTRL_OFFSET 0x0000
+#define TI814X_CM_ISP_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ISP_INST, 0x0000)
+
+/* CM_DSS */
+#define TI814X_CM_DSS_CLKSTCTRL_OFFSET 0x0000
+#define TI814X_CM_DSS_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ISP_INST, 0x0000)
+
+/* CM_DEFAULT */
+#define TI814X_CM_DEFAULT_TPPSS_CLKSTCTRL_OFFSET 0x0000
+#define TI814X_CM_DEFAULT_TPPSS_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0000)
+#define TI814X_CM_DEFAULT_PCI_CLKSTCTRL_OFFSET 0x0004
+#define TI814X_CM_DEFAULT_PCI_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0004)
+#define TI814X_CM_DEFAULT_DUCATI_CLKSTCTRL_OFFSET 0x000c
+#define TI814X_CM_DEFAULT_DUCATI_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x000c)
+
+#endif
diff --git a/arch/arm/mach-omap2/prcm816x.h b/arch/arm/mach-omap2/prcm816x.h
new file mode 100644
index 0000000..74491d9
--- /dev/null
+++ b/arch/arm/mach-omap2/prcm816x.h
@@ -0,0 +1,186 @@
+/*
+ * TI816X-specific PRCM register access macros
+ *
+ * Copyright (C) 2010-2011 Texas Instruments, Inc. - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRCM816X_H
+#define __ARCH_ARM_MACH_OMAP2_PRCM816X_H
+
+#include "prcm81xx.h"
+
+/*
+ * TI816x-specific PRCM registers offsets. The offsets below are
+ * relative to the PRCM instance base.
+ */
+
+/* CM_DPLL */
+#define TI816X_CM_DPLL_SYSCLK1_CLKSEL_OFFSET 0x0000
+#define TI816X_CM_DPLL_SYSCLK1_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0000)
+#define TI816X_CM_DPLL_SYSCLK2_CLKSEL_OFFSET 0x0004
+#define TI816X_CM_DPLL_SYSCLK2_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0004)
+#define TI816X_CM_DPLL_SYSCLK3_CLKSEL_OFFSET 0x0008
+#define TI816X_CM_DPLL_SYSCLK3_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0008)
+#define TI816X_CM_DPLL_SYSCLK4_CLKSEL_OFFSET 0x000C
+#define TI816X_CM_DPLL_SYSCLK4_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x000C)
+#define TI816X_CM_DPLL_SYSCLK5_CLKSEL_OFFSET 0x0010
+#define TI816X_CM_DPLL_SYSCLK5_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0010)
+#define TI816X_CM_DPLL_SYSCLK6_CLKSEL_OFFSET 0x0014
+#define TI816X_CM_DPLL_SYSCLK6_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0014)
+#define TI816X_CM_DPLL_SYSCLK7_CLKSEL_OFFSET 0x0018
+#define TI816X_CM_DPLL_SYSCLK7_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0018)
+#define TI816X_CM_DPLL_SYSCLK10_CLKSEL_OFFSET 0x0024
+#define TI816X_CM_DPLL_SYSCLK10_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0024)
+#define TI816X_CM_DPLL_SYSCLK11_CLKSEL_OFFSET 0x002C
+#define TI816X_CM_DPLL_SYSCLK11_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x002C)
+#define TI816X_CM_DPLL_SYSCLK12_CLKSEL_OFFSET 0x0030
+#define TI816X_CM_DPLL_SYSCLK12_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0030)
+#define TI816X_CM_DPLL_SYSCLK13_CLKSEL_OFFSET 0x0034
+#define TI816X_CM_DPLL_SYSCLK13_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0034)
+#define TI816X_CM_DPLL_SYSCLK15_CLKSEL_OFFSET 0x0038
+#define TI816X_CM_DPLL_SYSCLK15_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0038)
+#define TI816X_CM_DPLL_VPB3_CLKSEL_OFFSET 0x0040
+#define TI816X_CM_DPLL_VPB3_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0040)
+#define TI816X_CM_DPLL_VPC1_CLKSEL_OFFSET 0x0044
+#define TI816X_CM_DPLL_VPC1_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0044)
+#define TI816X_CM_DPLL_VPD1_CLKSEL_OFFSET 0x0048
+#define TI816X_CM_DPLL_VPD1_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0048)
+#define TI816X_CM_DPLL_SYSCLK19_CLKSEL_OFFSET 0x004C
+#define TI816X_CM_DPLL_SYSCLK19_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x004C)
+#define TI816X_CM_DPLL_SYSCLK20_CLKSEL_OFFSET 0x0050
+#define TI816X_CM_DPLL_SYSCLK20_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0050)
+#define TI816X_CM_DPLL_SYSCLK21_CLKSEL_OFFSET 0x0054
+#define TI816X_CM_DPLL_SYSCLK21_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0054)
+#define TI816X_CM_DPLL_SYSCLK22_CLKSEL_OFFSET 0x0058
+#define TI816X_CM_DPLL_SYSCLK22_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0058)
+#define TI816X_CM_DPLL_APA_CLKSEL_OFFSET 0x005C
+#define TI816X_CM_DPLL_APA_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x005C)
+#define TI816X_CM_DPLL_SYSCLK14_CLKSEL_OFFSET 0x0070
+#define TI816X_CM_DPLL_SYSCLK14_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0070)
+#define TI816X_CM_DPLL_SYSCLK16_CLKSEL_OFFSET 0x0074
+#define TI816X_CM_DPLL_SYSCLK16_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0074)
+#define TI816X_CM_DPLL_SYSCLK18_CLKSEL_OFFSET 0x0078
+#define TI816X_CM_DPLL_SYSCLK18_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0078)
+#define TI816X_CM_DPLL_AUDIOCLK_MCASP0_CLKSEL_OFFSET 0x007C
+#define TI816X_CM_DPLL_AUDIOCLK_MCASP0_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x007C)
+#define TI816X_CM_DPLL_AUDIOCLK_MCASP1_CLKSEL_OFFSET 0x0080
+#define TI816X_CM_DPLL_AUDIOCLK_MCASP1_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0080)
+#define TI816X_CM_DPLL_AUDIOCLK_MCASP2_CLKSEL_OFFSET 0x0084
+#define TI816X_CM_DPLL_AUDIOCLK_MCASP2_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0084)
+#define TI816X_CM_DPLL_AUDIOCLK_MCBSP_CLKSEL_OFFSET 0x0088
+#define TI816X_CM_DPLL_AUDIOCLK_MCBSP_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0088)
+#define TI816X_CM_DPLL_TIMER1_CLKSEL_OFFSET 0x0090
+#define TI816X_CM_DPLL_TIMER1_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0090)
+#define TI816X_CM_DPLL_TIMER2_CLKSEL_OFFSET 0x0094
+#define TI816X_CM_DPLL_TIMER2_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0094)
+#define TI816X_CM_DPLL_TIMER3_CLKSEL_OFFSET 0x0098
+#define TI816X_CM_DPLL_TIMER3_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x0098)
+#define TI816X_CM_DPLL_TIMER4_CLKSEL_OFFSET 0x009C
+#define TI816X_CM_DPLL_TIMER4_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x009C)
+#define TI816X_CM_DPLL_TIMER5_CLKSEL_OFFSET 0x00A0
+#define TI816X_CM_DPLL_TIMER5_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x00A0)
+#define TI816X_CM_DPLL_TIMER6_CLKSEL_OFFSET 0x00A4
+#define TI816X_CM_DPLL_TIMER6_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x00A4)
+#define TI816X_CM_DPLL_TIMER7_CLKSEL_OFFSET 0x00A8
+#define TI816X_CM_DPLL_TIMER7_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x00A8)
+#define TI816X_CM_DPLL_HDMI_CLKSEL_OFFSET 0x00AC
+#define TI816X_CM_DPLL_HDMI_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x00AC)
+#define TI816X_CM_DPLL_SYSCLK23_CLKSEL_OFFSET 0x00B0
+#define TI816X_CM_DPLL_SYSCLK23_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x00B0)
+#define TI816X_CM_DPLL_SYSCLK24_CLKSEL_OFFSET 0x00B4
+#define TI816X_CM_DPLL_SYSCLK24_CLKSEL TI81XX_CM_REGADDR(TI81XX_CM_DPLL_INST, 0x00B4)
+
+/* CM_DEFAULT */
+#define TI816X_CM_DEFAULT_L3_MED_CLKSTCTRL_OFFSET 0x0004
+#define TI816X_CM_DEFAULT_L3_MED_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0004)
+#define TI816X_CM_DEFAULT_L3_FAST_CLKSTCTRL_OFFSET 0x0008
+#define TI816X_CM_DEFAULT_L3_FAST_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0008)
+#define TI816X_CM_DEFAULT_TPPSS_CLKSTCTRL_OFFSET 0x000C
+#define TI816X_CM_DEFAULT_TPPSS_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x000C)
+#define TI816X_CM_DEFAULT_PCI_CLKSTCTRL_OFFSET 0x0010
+#define TI816X_CM_DEFAULT_PCI_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0010)
+#define TI816X_CM_DEFAULT_L3_SLOW_CLKSTCTRL_OFFSET 0x0014
+#define TI816X_CM_DEFAULT_L3_SLOW_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0014)
+#define TI816X_CM_DEFAULT_DUCATI_CLKSTCTRL_OFFSET 0x0018
+#define TI816X_CM_DEFAULT_DUCATI_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0018)
+#define TI816X_CM_DEFAULT_EMIF_0_CLKCTRL_OFFSET 0x0020
+#define TI816X_CM_DEFAULT_EMIF_0_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0020)
+#define TI816X_CM_DEFAULT_EMIF_1_CLKCTRL_OFFSET 0x0024
+#define TI816X_CM_DEFAULT_EMIF_1_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0024)
+#define TI816X_CM_DEFAULT_DMM_CLKCTRL_OFFSET 0x0028
+#define TI816X_CM_DEFAULT_DMM_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0028)
+#define TI816X_CM_DEFAULT_FW_CLKCTRL_OFFSET 0x002C
+#define TI816X_CM_DEFAULT_FW_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x002C)
+#define TI816X_CM_DEFAULT_TPPSS_CLKCTRL_OFFSET 0x0054
+#define TI816X_CM_DEFAULT_TPPSS_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0054)
+#define TI816X_CM_DEFAULT_USB_CLKCTRL_OFFSET 0x0058
+#define TI816X_CM_DEFAULT_USB_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0058)
+#define TI816X_CM_DEFAULT_SATA_CLKCTRL_OFFSET 0x0060
+#define TI816X_CM_DEFAULT_SATA_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0060)
+#define TI816X_CM_DEFAULT_DUCATI_CLKCTRL_OFFSET 0x0074
+#define TI816X_CM_DEFAULT_DUCATI_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0074)
+#define TI816X_CM_DEFAULT_PCI_CLKCTRL_OFFSET 0x0078
+#define TI816X_CM_DEFAULT_PCI_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_DEFAULT_INST, 0x0078)
+
+/* CM_ALWON */
+#define TI816X_CM_ALWON_OCMC_1_CLKSTCTRL_OFFSET 0x0018
+#define TI816X_CM_ALWON_OCMC_1_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0018)
+#define TI816X_CM_ALWON_MPU_CLKSTCTRL_OFFSET 0x001C
+#define TI816X_CM_ALWON_MPU_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x001C)
+#define TI816X_CM_ALWON_TIMER_0_CLKCTRL_OFFSET 0x016C
+#define TI816X_CM_ALWON_TIMER_0_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x016C)
+#define TI816X_CM_ALWON_TIMER_1_CLKCTRL_OFFSET 0x0170
+#define TI816X_CM_ALWON_TIMER_1_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0170)
+#define TI816X_CM_ALWON_TIMER_2_CLKCTRL_OFFSET 0x0174
+#define TI816X_CM_ALWON_TIMER_2_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0174)
+#define TI816X_CM_ALWON_TIMER_3_CLKCTRL_OFFSET 0x0178
+#define TI816X_CM_ALWON_TIMER_3_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0178)
+#define TI816X_CM_ALWON_TIMER_5_CLKCTRL_OFFSET 0x0180
+#define TI816X_CM_ALWON_TIMER_5_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0180)
+#define TI816X_CM_ALWON_TIMER_6_CLKCTRL_OFFSET 0x0184
+#define TI816X_CM_ALWON_TIMER_6_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0184)
+#define TI816X_CM_ALWON_TIMER_7_CLKCTRL_OFFSET 0x0188
+#define TI816X_CM_ALWON_TIMER_7_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0188)
+#define TI816X_CM_ALWON_OCMC_1_CLKCTRL_OFFSET 0x01B8
+#define TI816X_CM_ALWON_OCMC_1_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01B8)
+#define TI816X_CM_ALWON_SMARTCARD_0_CLKCTR_OFFSET 0x01BC
+#define TI816X_CM_ALWON_SMARTCARD_0_CLKCTR TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01BC)
+#define TI816X_CM_ALWON_SMARTCARD_1_CLKCTR_OFFSET 0x01C0
+#define TI816X_CM_ALWON_SMARTCARD_1_CLKCTR TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01C0)
+#define TI816X_CM_ALWON_SECSS_CLKCTRL_OFFSET 0x01C8
+#define TI816X_CM_ALWON_SECSS_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01C8)
+#define TI816X_CM_ALWON_SR_2_CLKCTRL_OFFSET 0x0210
+#define TI816X_CM_ALWON_SR_2_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0210)
+#define TI816X_CM_ALWON_SR_3_CLKCTRL_OFFSET 0x0214
+#define TI816X_CM_ALWON_SR_3_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0214)
+#define TI816X_CM_ALWON_SR_4_CLKCTRL_OFFSET 0x0218
+#define TI816X_CM_ALWON_SR_4_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0218)
+#define TI816X_CM_ALWON_SR_5_CLKCTRL_OFFSET 0x021C
+#define TI816X_CM_ALWON_SR_5_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x021C)
+#define TI816X_CM_ALWON_SR_6_CLKCTRL_OFFSET 0x0220
+#define TI816X_CM_ALWON_SR_6_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0220)
+#define TI816X_CM_ALWON_SR_7_CLKCTRL_OFFSET 0x0224
+#define TI816X_CM_ALWON_SR_7_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0224)
+#define TI816X_CM_ALWON_CUST_EFUSE_CLKCTRL_OFFSET 0x0228
+#define TI816X_CM_ALWON_CUST_EFUSE_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0228)
+
+/* CM_ACTIVE */
+#define TI816X_CM_ACTIVE_HDDSS_CLKSTCTRL_OFFSET 0x0004
+#define TI816X_CM_ACTIVE_HDDSS_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ACTIVE_INST, 0x0004)
+#define TI816X_CM_ACTIVE_HDMI_CLKSTCTRL_OFFSET 0x0008
+#define TI816X_CM_ACTIVE_HDMI_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ACTIVE_INST, 0x0008)
+#define TI816X_CM_ACTIVE_HDDSS_CLKCTRL_OFFSET 0x0024
+#define TI816X_CM_ACTIVE_HDDSS_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ACTIVE_INST, 0x0024)
+#define TI816X_CM_ACTIVE_HDMI_CLKCTRL_OFFSET 0x0028
+#define TI816X_CM_ACTIVE_HDMI_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ACTIVE_INST, 0x0028)
+
+#endif
diff --git a/arch/arm/mach-omap2/prcm81xx.c b/arch/arm/mach-omap2/prcm81xx.c
new file mode 100644
index 0000000..d48e5fc
--- /dev/null
+++ b/arch/arm/mach-omap2/prcm81xx.c
@@ -0,0 +1,32 @@
+/*
+ * TI81XX PRCM register access functions
+ *
+ * Copyright (C) 2010-2011 Texas Instruments, Inc. - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+
+#include "prcm81xx.h"
+
+static u32 ti81xx_prcm_inst_read(u16 inst, u16 offs)
+{
+ return __raw_readl(prm_base + inst + offs);
+}
+
+static void ti81xx_prcm_inst_write(u32 v, u16 inst, u16 offs)
+{
+ __raw_writel(v, prm_base + inst + offs);
+}
+
+
diff --git a/arch/arm/mach-omap2/prcm81xx.h b/arch/arm/mach-omap2/prcm81xx.h
new file mode 100644
index 0000000..fd0a174
--- /dev/null
+++ b/arch/arm/mach-omap2/prcm81xx.h
@@ -0,0 +1,193 @@
+/*
+ * TI81XX PRCM register access macros and module offsets
+ *
+ * Copyright (C) 2010-2011 Texas Instruments, Inc. - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRCM81XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRCM81XX_H
+
+#include "prcm-common.h"
+
+#define TI81XX_PRCM_REGADDR(instance, reg) \
+ OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE + (instance) + (reg))
+
+/*
+ * TI81XX-common PRM/CM instance offsets
+ */
+#define TI81XX_PRM_DEVICE_INST 0x0000 /* 256B */
+#define TI81XX_CM_DEVICE_INST 0x0100 /* 256B */
+#define TI81XX_PRM_OCP_SOCKET_INST 0x0200 /* 256B */
+#define TI81XX_CM_DPLL_INST 0x0300 /* 256B */
+#define TI81XX_CM_ACTIVE_INST 0x0400 /* 256B */
+#define TI81XX_CM_DEFAULT_INST 0x0500 /* 256B */
+#define TI81XX_CM_SGX_INST 0x0900 /* 256B */
+#define TI81XX_PRM_ACTIVE_INST 0x0a00 /* 256B */
+#define TI81XX_PRM_DEFAULT_INST 0x0b00 /* 256B */
+#define TI81XX_PRM_SGX_INST 0x0f00 /* 256B */
+#define TI81XX_CM_ALWON_INST 0x1400 /* 1KB */
+
+/*
+ * TI81xx-common register offsets
+ */
+
+/* PRM_DEVICE */
+#define TI81XX_PRM_DEVICE_RSTCTRL_OFFSET 0x0000
+#define TI81XX_PRM_DEVICE_RSTCTRL TI81XX_PRCM_REGADDR(TI81XX_PRM_DEVICE_INST, 0x0000)
+#define TI81XX_PRM_DEVICE_RSTTIME_OFFSET 0x0004
+#define TI81XX_PRM_DEVICE_RSTTIME TI81XX_PRCM_REGADDR(TI81XX_PRM_DEVICE_INST, 0x0004)
+#define TI81XX_PRM_DEVICE_RSTST_OFFSET 0x0008
+#define TI81XX_PRM_DEVICE_RSTST TI81XX_PRCM_REGADDR(TI81XX_PRM_DEVICE_INST, 0x0008)
+
+/* CM_DEVICE */
+#define TI81XX_CM_DEVICE_CLKOUT_CTRL_OFFSET 0x0000
+#define TI81XX_CM_DEVICE_CLKOUT_CTRL TI81XX_PRCM_REGADDR(TI81XX_CM_DEVICE_INST, 0x0000)
+
+/* OCP_SOCKET_PRM */
+#define TI81XX_PRM_OCP_SOCKET_REVISION_OFFSET 0x0000
+#define TI81XX_PRM_OCP_SOCKET_REVISION TI81XX_PRCM_REGADDR(TI81XX_PRM_OCP_SOCKET_INST, 0x0000)
+
+/* CM_ACTIVE */
+#define TI81XX_CM_ACTIVE_GEM_CLKSTCTRL_OFFSET 0x0000
+#define TI81XX_CM_ACTIVE_GEM_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ACTIVE_INST, 0x0000)
+#define TI81XX_CM_ACTIVE_GEM_CLKCTRL_OFFSET 0x0020
+#define TI81XX_CM_ACTIVE_GEM_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ACTIVE_INST, 0x0020)
+
+/* CM_SGX */
+#define TI81XX_CM_SGX_SGX_CLKSTCTRL_OFFSET 0x0000
+#define TI81XX_CM_SGX_SGX_CLKSTCTRL TI81XX_PRCM_REGADDR(TI81XX_CM_SGX_INST, 0x0000)
+#define TI81XX_CM_SGX_SGX_SGX_CLKCTRL_OFFSET 0x0020
+#define TI81XX_CM_SGX_SGX_SGX_CLKCTRL TI81XX_PRCM_REGADDR(TI81XX_CM_SGX_INST, 0x0020)
+
+/* PRM_ACTIVE */
+#define TI81XX_PRM_ACTIVE_PM_PWRSTCTRL_OFFSET 0x0000
+#define TI81XX_PRM_ACTIVE_PM_PWRSTCTRL TI81XX_PRCM_REGADDR(TI81XX_PRM_ACTIVE_INST, 0x0000)
+#define TI81XX_PRM_ACTIVE_PM_PWRSTST_OFFSET 0x0004
+#define TI81XX_PRM_ACTIVE_PM_PWRSTST TI81XX_PRCM_REGADDR(TI81XX_PRM_ACTIVE_INST, 0x0004)
+#define TI81XX_PRM_ACTIVE_RM_RSTCTRL_OFFSET 0x0010
+#define TI81XX_PRM_ACTIVE_RM_RSTCTRL TI81XX_PRCM_REGADDR(TI81XX_PRM_ACTIVE_INST, 0x0010)
+#define TI81XX_PRM_ACTIVE_RM_RSTST_OFFSET 0x0014
+#define TI81XX_PRM_ACTIVE_RM_RSTST TI81XX_PRCM_REGADDR(TI81XX_PRM_ACTIVE_INST, 0x0014)
+
+/* PRM_SGX */
+#define TI81XX_PRM_SGX_PM_PWRSTCTRL_OFFSET 0x0000
+#define TI81XX_PRM_SGX_PM_PWRSTCTRL TI81XX_PRCM_REGADDR(TI81XX_PRM_SGX_INST, 0x0000)
+#define TI81XX_PRM_SGX_PM_PWRSTST_OFFSET 0x0004
+#define TI81XX_PRM_SGX_PM_PWRSTST TI81XX_PRCM_REGADDR(TI81XX_PRM_SGX_INST, 0x0004)
+#define TI81XX_PRM_SGX_RM_RSTCTRL_OFFSET 0x0010
+#define TI81XX_PRM_SGX_RM_RSTCTRL TI81XX_PRCM_REGADDR(TI81XX_PRM_SGX_INST, 0x0010)
+#define TI81XX_PRM_SGX_RM_RSTST_OFFSET 0x0014
+#define TI81XX_PRM_SGX_RM_RSTST TI81XX_PRCM_REGADDR(TI81XX_PRM_SGX_INST, 0x0014)
+
+/* CM_ALWON */
+#define TI81XX_CM_ALWON_L3_SLOW_CLKSTCTRL_OFFSET 0x0000
+#define TI81XX_CM_ALWON_L3_SLOW_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0000)
+#define TI81XX_CM_ETHERNET_CLKSTCTRL_OFFSET 0x0004
+#define TI81XX_CM_ETHERNET_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0004)
+#define TI81XX_CM_ALWON_L3_MED_CLKSTCTRL_OFFSET 0x0008
+#define TI81XX_CM_ALWON_L3_MED_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0008)
+#define TI81XX_CM_MMU_CLKSTCTRL_OFFSET 0x000C
+#define TI81XX_CM_MMU_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x000C)
+#define TI81XX_CM_MMUCFG_CLKSTCTRL_OFFSET 0x0010
+#define TI81XX_CM_MMUCFG_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0010)
+#define TI81XX_CM_ALWON_OCMC_0_CLKSTCTRL_OFFSET 0x0014
+#define TI81XX_CM_ALWON_OCMC_0_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0014)
+#define TI81XX_CM_ALWON_SYSCLK4_CLKSTCTRL_OFFSET 0x0020
+#define TI81XX_CM_ALWON_SYSCLK4_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0020)
+#define TI81XX_CM_ALWON_SYSCLK5_CLKSTCTRL_OFFSET 0x0024
+#define TI81XX_CM_ALWON_SYSCLK5_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0024)
+#define TI81XX_CM_ALWON_SYSCLK6_CLKSTCTRL_OFFSET 0x0028
+#define TI81XX_CM_ALWON_SYSCLK6_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0028)
+#define TI81XX_CM_ALWON_RTC_CLKSTCTRL_OFFSET 0x002C
+#define TI81XX_CM_ALWON_RTC_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x002C)
+#define TI81XX_CM_ALWON_L3_FAST_CLKSTCTRL_OFFSET 0x0030
+#define TI81XX_CM_ALWON_L3_FAST_CLKSTCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0030)
+#define TI81XX_CM_ALWON_MCASP0_CLKCTRL_OFFSET 0x0140
+#define TI81XX_CM_ALWON_MCASP0_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0140)
+#define TI81XX_CM_ALWON_MCASP1_CLKCTRL_OFFSET 0x0144
+#define TI81XX_CM_ALWON_MCASP1_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0144)
+#define TI81XX_CM_ALWON_MCASP2_CLKCTRL_OFFSET 0x0148
+#define TI81XX_CM_ALWON_MCASP2_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0148)
+#define TI81XX_CM_ALWON_MCBSP_CLKCTRL_OFFSET 0x014C
+#define TI81XX_CM_ALWON_MCBSP_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x014C)
+#define TI81XX_CM_ALWON_UART_0_CLKCTRL_OFFSET 0x0150
+#define TI81XX_CM_ALWON_UART_0_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0150)
+#define TI81XX_CM_ALWON_UART_1_CLKCTRL_OFFSET 0x0154
+#define TI81XX_CM_ALWON_UART_1_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0154)
+#define TI81XX_CM_ALWON_UART_2_CLKCTRL_OFFSET 0x0158
+#define TI81XX_CM_ALWON_UART_2_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0158)
+#define TI81XX_CM_ALWON_GPIO_0_CLKCTRL_OFFSET 0x015C
+#define TI81XX_CM_ALWON_GPIO_0_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x015C)
+#define TI81XX_CM_ALWON_GPIO_1_CLKCTRL_OFFSET 0x0160
+#define TI81XX_CM_ALWON_GPIO_1_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0160)
+#define TI81XX_CM_ALWON_I2C_0_CLKCTRL_OFFSET 0x0164
+#define TI81XX_CM_ALWON_I2C_0_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0164)
+#define TI81XX_CM_ALWON_I2C_1_CLKCTRL_OFFSET 0x0168
+#define TI81XX_CM_ALWON_I2C_1_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0168)
+#define TI81XX_CM_ALWON_TIMER_4_CLKCTRL_OFFSET 0x017C
+#define TI81XX_CM_ALWON_TIMER_4_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x017C)
+#define TI81XX_CM_ALWON_WDTIMER_CLKCTRL_OFFSET 0x018C
+#define TI81XX_CM_ALWON_WDTIMER_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x018C)
+#define TI81XX_CM_ALWON_SPI_CLKCTRL_OFFSET 0x0190
+#define TI81XX_CM_ALWON_SPI_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0190)
+#define TI81XX_CM_ALWON_MAILBOX_CLKCTRL_OFFSET 0x0194
+#define TI81XX_CM_ALWON_MAILBOX_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0194)
+#define TI81XX_CM_ALWON_SPINBOX_CLKCTRL_OFFSET 0x0198
+#define TI81XX_CM_ALWON_SPINBOX_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0198)
+#define TI81XX_CM_ALWON_MMUDATA_CLKCTRL_OFFSET 0x019C
+#define TI81XX_CM_ALWON_MMUDATA_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x019C)
+#define TI81XX_CM_ALWON_VLYNQ_CLKCTRL_OFFSET 0x01A0
+#define TI81XX_CM_ALWON_VLYNQ_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01A0)
+#define TI81XX_CM_ALWON_MMUCFG_CLKCTRL_OFFSET 0x01A8
+#define TI81XX_CM_ALWON_MMUCFG_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01A8)
+#define TI81XX_CM_ALWON_SDIO_CLKCTRL_OFFSET 0x01B0
+#define TI81XX_CM_ALWON_SDIO_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01B0)
+#define TI81XX_CM_ALWON_OCMC_0_CLKCTRL_OFFSET 0x01B4
+#define TI81XX_CM_ALWON_OCMC_0_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01B4)
+#define TI81XX_CM_ALWON_CONTROL_CLKCTRL_OFFSET 0x01C4
+#define TI81XX_CM_ALWON_CONTROL_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01C4)
+#define TI81XX_CM_ALWON_GPMC_CLKCTRL_OFFSET 0x01D0
+#define TI81XX_CM_ALWON_GPMC_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01D0)
+#define TI81XX_CM_ALWON_ETHERNET_0_CLKCTRL_OFFSET 0x01D4
+#define TI81XX_CM_ALWON_ETHERNET_0_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01D4)
+#define TI81XX_CM_ALWON_ETHERNET_1_CLKCTRL_OFFSET 0x01D8
+#define TI81XX_CM_ALWON_ETHERNET_1_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01D8)
+#define TI81XX_CM_ALWON_MPU_CLKCTRL_OFFSET 0x01DC
+#define TI81XX_CM_ALWON_MPU_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01DC)
+#define TI81XX_CM_ALWON_DEBUGSS_CLKCTRL_OFFSET 0x01E0
+#define TI81XX_CM_ALWON_DEBUGSS_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01E0)
+#define TI81XX_CM_ALWON_L3_CLKCTRL_OFFSET 0x01E4
+#define TI81XX_CM_ALWON_L3_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01E4)
+#define TI81XX_CM_ALWON_L4HS_CLKCTRL_OFFSET 0x01E8
+#define TI81XX_CM_ALWON_L4HS_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01E8)
+#define TI81XX_CM_ALWON_L4LS_CLKCTRL_OFFSET 0x01EC
+#define TI81XX_CM_ALWON_L4LS_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01EC)
+#define TI81XX_CM_ALWON_RTC_CLKCTRL_OFFSET 0x01F0
+#define TI81XX_CM_ALWON_RTC_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01F0)
+#define TI81XX_CM_ALWON_TPCC_CLKCTRL_OFFSET 0x01F4
+#define TI81XX_CM_ALWON_TPCC_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01F4)
+#define TI81XX_CM_ALWON_TPTC0_CLKCTRL_OFFSET 0x01F8
+#define TI81XX_CM_ALWON_TPTC0_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01F8)
+#define TI81XX_CM_ALWON_TPTC1_CLKCTRL_OFFSET 0x01FC
+#define TI81XX_CM_ALWON_TPTC1_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x01FC)
+#define TI81XX_CM_ALWON_TPTC2_CLKCTRL_OFFSET 0x0200
+#define TI81XX_CM_ALWON_TPTC2_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0200)
+#define TI81XX_CM_ALWON_TPTC3_CLKCTRL_OFFSET 0x0204
+#define TI81XX_CM_ALWON_TPTC3_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0204)
+#define TI81XX_CM_ALWON_SR_0_CLKCTRL_OFFSET 0x0208
+#define TI81XX_CM_ALWON_SR_0_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x0208)
+#define TI81XX_CM_ALWON_SR_1_CLKCTRL_OFFSET 0x020C
+#define TI81XX_CM_ALWON_SR_1_CLKCTRL TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x020C)
+
+/* Function prototypes */
+
+#endif
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