* [PATCH v8 06/24] gpio/omap: avoid cpu checks during module ena/disable
From: Tarun Kanti DebBarma @ 2011-10-05 8:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1317803593-12259-1-git-send-email-tarun.kanti@ti.com>
From: Charulatha V <charu@ti.com>
Remove cpu-is checks while enabling/disabling OMAP GPIO module during a gpio
request/free.
Signed-off-by: Charulatha V <charu@ti.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/mach-omap2/gpio.c | 2 +
arch/arm/plat-omap/include/plat/gpio.h | 1 +
drivers/gpio/gpio-omap.c | 53 ++++++++++++++------------------
3 files changed, 26 insertions(+), 30 deletions(-)
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index 02dd90d..fe28d91 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -96,6 +96,7 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
pdata->regs->clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1;
pdata->regs->debounce = OMAP24XX_GPIO_DEBOUNCE_VAL;
pdata->regs->debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN;
+ pdata->regs->ctrl = OMAP24XX_GPIO_CTRL;
break;
case 2:
pdata->bank_type = METHOD_GPIO_44XX;
@@ -112,6 +113,7 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
pdata->regs->clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0;
pdata->regs->debounce = OMAP4_GPIO_DEBOUNCINGTIME;
pdata->regs->debounce_en = OMAP4_GPIO_DEBOUNCENABLE;
+ pdata->regs->ctrl = OMAP4_GPIO_CTRL;
break;
default:
WARN(1, "Invalid gpio bank_type\n");
diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
index a93adeb..eaa6de3 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -188,6 +188,7 @@ struct omap_gpio_reg_offs {
u16 clr_irqenable;
u16 debounce;
u16 debounce_en;
+ u16 ctrl;
bool irqenable_inv;
};
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 090feb8..84cd934 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -83,6 +83,7 @@ struct gpio_bank {
#define GPIO_INDEX(bank, gpio) (gpio % bank->width)
#define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
+#define GPIO_MOD_CTRL_BIT BIT(0)
static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
{
@@ -577,22 +578,18 @@ static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
__raw_writel(__raw_readl(reg) | (1 << offset), reg);
}
#endif
- if (!cpu_class_is_omap1()) {
- if (!bank->mod_usage) {
- void __iomem *reg = bank->base;
- u32 ctrl;
-
- if (cpu_is_omap24xx() || cpu_is_omap34xx())
- reg += OMAP24XX_GPIO_CTRL;
- else if (cpu_is_omap44xx())
- reg += OMAP4_GPIO_CTRL;
- ctrl = __raw_readl(reg);
- /* Module is enabled, clocks are not gated */
- ctrl &= 0xFFFFFFFE;
- __raw_writel(ctrl, reg);
- }
- bank->mod_usage |= 1 << offset;
+ if (bank->regs->ctrl && !bank->mod_usage) {
+ void __iomem *reg = bank->base + bank->regs->ctrl;
+ u32 ctrl;
+
+ ctrl = __raw_readl(reg);
+ /* Module is enabled, clocks are not gated */
+ ctrl &= ~GPIO_MOD_CTRL_BIT;
+ __raw_writel(ctrl, reg);
}
+
+ bank->mod_usage |= 1 << offset;
+
spin_unlock_irqrestore(&bank->lock, flags);
return 0;
@@ -625,22 +622,18 @@ static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
__raw_writel(1 << offset, reg);
}
#endif
- if (!cpu_class_is_omap1()) {
- bank->mod_usage &= ~(1 << offset);
- if (!bank->mod_usage) {
- void __iomem *reg = bank->base;
- u32 ctrl;
-
- if (cpu_is_omap24xx() || cpu_is_omap34xx())
- reg += OMAP24XX_GPIO_CTRL;
- else if (cpu_is_omap44xx())
- reg += OMAP4_GPIO_CTRL;
- ctrl = __raw_readl(reg);
- /* Module is disabled, clocks are gated */
- ctrl |= 1;
- __raw_writel(ctrl, reg);
- }
+ bank->mod_usage &= ~(1 << offset);
+
+ if (bank->regs->ctrl && !bank->mod_usage) {
+ void __iomem *reg = bank->base + bank->regs->ctrl;
+ u32 ctrl;
+
+ ctrl = __raw_readl(reg);
+ /* Module is disabled, clocks are gated */
+ ctrl |= GPIO_MOD_CTRL_BIT;
+ __raw_writel(ctrl, reg);
}
+
_reset_gpio(bank, bank->chip.base + offset);
spin_unlock_irqrestore(&bank->lock, flags);
}
--
1.7.0.4
^ permalink raw reply related
* [PATCH v8 05/24] gpio/omap: make non-wakeup GPIO part of pdata
From: Tarun Kanti DebBarma @ 2011-10-05 8:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1317803593-12259-1-git-send-email-tarun.kanti@ti.com>
From: Charulatha V <charu@ti.com>
Non-wakeup GPIOs are available only in OMAP2. Avoid cpu_is checks by making
non_wakeup_gpios as part of pdata.
Signed-off-by: Charulatha V <charu@ti.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/mach-omap2/gpio.c | 8 ++++++++
arch/arm/plat-omap/include/plat/gpio.h | 1 +
drivers/gpio/gpio-omap.c | 8 +-------
3 files changed, 10 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index 9ff8366..02dd90d 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -73,6 +73,14 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
switch (oh->class->rev) {
case 0:
+ if (id == 1)
+ /* non-wakeup GPIO pins for OMAP2 Bank1 */
+ pdata->non_wakeup_gpios = 0xe203ffc0;
+ else if (id == 2)
+ /* non-wakeup GPIO pins for OMAP2 Bank2 */
+ pdata->non_wakeup_gpios = 0x08700040;
+ /* fall through */
+
case 1:
pdata->bank_type = METHOD_GPIO_24XX;
pdata->regs->revision = OMAP24XX_GPIO_REVISION;
diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
index 2c06e43..a93adeb 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -199,6 +199,7 @@ struct omap_gpio_platform_data {
int bank_stride; /* Only needed for omap1 MPUIO */
bool dbck_flag; /* dbck required or not - True for OMAP3&4 */
bool loses_context; /* whether the bank would ever lose context */
+ u32 non_wakeup_gpios;
struct omap_gpio_reg_offs *regs;
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index c3cf01f..090feb8 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -1021,13 +1021,6 @@ static void omap_gpio_mod_init(struct gpio_bank *bank)
/* Initialize interface clk ungated, module enabled */
__raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
- } else if (cpu_is_omap24xx()) {
- static const u32 non_wakeup_gpios[] = {
- 0xe203ffc0, 0x08700040
- };
- if (bank->id < ARRAY_SIZE(non_wakeup_gpios))
- bank->non_wakeup_gpios =
- non_wakeup_gpios[bank->id];
}
} else if (cpu_class_is_omap1()) {
if (bank_is_mpuio(bank)) {
@@ -1180,6 +1173,7 @@ static int __devinit omap_gpio_probe(struct platform_device *pdev)
bank->dbck_flag = pdata->dbck_flag;
bank->stride = pdata->bank_stride;
bank->width = pdata->bank_width;
+ bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
bank->loses_context = pdata->loses_context;
bank->get_context_loss_count = pdata->get_context_loss_count;
bank->regs = pdata->regs;
--
1.7.0.4
^ permalink raw reply related
* [PATCH v8 04/24] gpio/omap: handle save/restore context in GPIO driver
From: Tarun Kanti DebBarma @ 2011-10-05 8:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1317803593-12259-1-git-send-email-tarun.kanti@ti.com>
Modify omap_gpio_prepare_for_idle() & omap_gpio_resume_after_idle() functions
to handle save context & restore context respectively in the OMAP GPIO driver
itself instead of calling these functions from pm specific files.
For this, in gpio_prepare_for_idle(), call *_get_context_loss_count() and in
gpio_resume_after_idle() call it again. If the count is different, do restore
context. The workaround_enabled flag is no more required and is removed.
Signed-off-by: Charulatha V <charu@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/mach-omap2/gpio.c | 3 +-
arch/arm/mach-omap2/pm34xx.c | 14 ----
arch/arm/plat-omap/include/plat/gpio.h | 5 +-
drivers/gpio/gpio-omap.c | 131 ++++++++++++++------------------
4 files changed, 63 insertions(+), 90 deletions(-)
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index 9f3a007..9ff8366 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -23,6 +23,7 @@
#include <plat/omap_hwmod.h>
#include <plat/omap_device.h>
+#include <plat/omap-pm.h>
#include "powerdomain.h"
@@ -63,7 +64,7 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
pdata->bank_width = dev_attr->bank_width;
pdata->dbck_flag = dev_attr->dbck_flag;
pdata->virtual_irq_start = IH_GPIO_BASE + 32 * (id - 1);
-
+ pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
pdata->regs = kzalloc(sizeof(struct omap_gpio_reg_offs), GFP_KERNEL);
if (!pdata) {
pr_err("gpio%d: Memory allocation failed\n", id);
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 7255d9b..d5bb50e 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -85,16 +85,6 @@ static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
static struct powerdomain *core_pwrdm, *per_pwrdm;
static struct powerdomain *cam_pwrdm;
-static inline void omap3_per_save_context(void)
-{
- omap_gpio_save_context();
-}
-
-static inline void omap3_per_restore_context(void)
-{
- omap_gpio_restore_context();
-}
-
static void omap3_enable_io_chain(void)
{
int timeout = 0;
@@ -392,8 +382,6 @@ void omap_sram_idle(void)
omap_uart_prepare_idle(2);
omap_uart_prepare_idle(3);
omap2_gpio_prepare_for_idle(per_going_off);
- if (per_next_state == PWRDM_POWER_OFF)
- omap3_per_save_context();
}
/* CORE */
@@ -459,8 +447,6 @@ void omap_sram_idle(void)
if (per_next_state < PWRDM_POWER_ON) {
per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
omap2_gpio_resume_after_idle();
- if (per_prev_state == PWRDM_POWER_OFF)
- omap3_per_restore_context();
omap_uart_resume_idle(2);
omap_uart_resume_idle(3);
}
diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
index 58d0bf2..2c06e43 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -201,14 +201,15 @@ struct omap_gpio_platform_data {
bool loses_context; /* whether the bank would ever lose context */
struct omap_gpio_reg_offs *regs;
+
+ /* Return context loss count due to PM states changing */
+ u32 (*get_context_loss_count)(struct device *dev);
};
extern void omap2_gpio_prepare_for_idle(int off_mode);
extern void omap2_gpio_resume_after_idle(void);
extern void omap_set_gpio_debounce(int gpio, int enable);
extern void omap_set_gpio_debounce_time(int gpio, int enable);
-extern void omap_gpio_save_context(void);
-extern void omap_gpio_restore_context(void);
/*-------------------------------------------------------------------------*/
/* Wrappers for "new style" GPIO calls, using the new infrastructure
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 62d2213..c3cf01f 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -72,9 +72,11 @@ struct gpio_bank {
bool loses_context;
int stride;
u32 width;
+ u32 context_loss_count;
u16 id;
void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable);
+ u32 (*get_context_loss_count)(struct device *dev);
struct omap_gpio_reg_offs *regs;
};
@@ -1179,6 +1181,7 @@ static int __devinit omap_gpio_probe(struct platform_device *pdev)
bank->stride = pdata->bank_stride;
bank->width = pdata->bank_width;
bank->loses_context = pdata->loses_context;
+ bank->get_context_loss_count = pdata->get_context_loss_count;
bank->regs = pdata->regs;
if (bank->regs->set_dataout && bank->regs->clr_dataout)
@@ -1323,11 +1326,11 @@ static struct syscore_ops omap_gpio_syscore_ops = {
#ifdef CONFIG_ARCH_OMAP2PLUS
-static int workaround_enabled;
+static void omap_gpio_save_context(struct gpio_bank *bank);
+static void omap_gpio_restore_context(struct gpio_bank *bank);
void omap2_gpio_prepare_for_idle(int off_mode)
{
- int c = 0;
struct gpio_bank *bank;
list_for_each_entry(bank, &omap_gpio_list, node) {
@@ -1347,7 +1350,7 @@ void omap2_gpio_prepare_for_idle(int off_mode)
* non-wakeup GPIOs. Otherwise spurious IRQs will be
* generated. See OMAP2420 Errata item 1.101. */
if (!(bank->enabled_non_wakeup_gpios))
- continue;
+ goto save_gpio_context;
if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
bank->saved_datain = __raw_readl(bank->base +
@@ -1384,13 +1387,13 @@ void omap2_gpio_prepare_for_idle(int off_mode)
__raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
}
- c++;
- }
- if (!c) {
- workaround_enabled = 0;
- return;
+save_gpio_context:
+ if (bank->get_context_loss_count)
+ bank->context_loss_count =
+ bank->get_context_loss_count(bank->dev);
+
+ omap_gpio_save_context(bank);
}
- workaround_enabled = 1;
}
void omap2_gpio_resume_after_idle(void)
@@ -1398,6 +1401,7 @@ void omap2_gpio_resume_after_idle(void)
struct gpio_bank *bank;
list_for_each_entry(bank, &omap_gpio_list, node) {
+ u32 context_lost_cnt_after;
u32 l = 0, gen, gen0, gen1;
int j;
@@ -1407,8 +1411,13 @@ void omap2_gpio_resume_after_idle(void)
for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
clk_enable(bank->dbck);
- if (!workaround_enabled)
- continue;
+ if (bank->get_context_loss_count) {
+ context_lost_cnt_after =
+ bank->get_context_loss_count(bank->dev);
+ if (context_lost_cnt_after != bank->context_loss_count
+ || !context_lost_cnt_after)
+ omap_gpio_restore_context(bank);
+ }
if (!(bank->enabled_non_wakeup_gpios))
continue;
@@ -1486,74 +1495,50 @@ void omap2_gpio_resume_after_idle(void)
}
}
}
-
}
-#endif
-
-#ifdef CONFIG_ARCH_OMAP3
-void omap_gpio_save_context(void)
+static void omap_gpio_save_context(struct gpio_bank *bank)
{
- struct gpio_bank *bank;
-
- list_for_each_entry(bank, &omap_gpio_list, node) {
-
- if (!bank->loses_context)
- continue;
-
- bank->context.irqenable1 =
- __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
- bank->context.irqenable2 =
- __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
- bank->context.wake_en =
- __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
- bank->context.ctrl =
- __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
- bank->context.oe =
- __raw_readl(bank->base + OMAP24XX_GPIO_OE);
- bank->context.leveldetect0 =
- __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
- bank->context.leveldetect1 =
- __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
- bank->context.risingdetect =
- __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
- bank->context.fallingdetect =
- __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
- bank->context.dataout =
- __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
- }
+ bank->context.irqenable1 =
+ __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
+ bank->context.irqenable2 =
+ __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
+ bank->context.wake_en =
+ __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
+ bank->context.ctrl = __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
+ bank->context.oe = __raw_readl(bank->base + OMAP24XX_GPIO_OE);
+ bank->context.leveldetect0 =
+ __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
+ bank->context.leveldetect1 =
+ __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
+ bank->context.risingdetect =
+ __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
+ bank->context.fallingdetect =
+ __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
+ bank->context.dataout =
+ __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
}
-void omap_gpio_restore_context(void)
+static void omap_gpio_restore_context(struct gpio_bank *bank)
{
- struct gpio_bank *bank;
-
- list_for_each_entry(bank, &omap_gpio_list, node) {
-
- if (!bank->loses_context)
- continue;
-
- __raw_writel(bank->context.irqenable1,
- bank->base + OMAP24XX_GPIO_IRQENABLE1);
- __raw_writel(bank->context.irqenable2,
- bank->base + OMAP24XX_GPIO_IRQENABLE2);
- __raw_writel(bank->context.wake_en,
- bank->base + OMAP24XX_GPIO_WAKE_EN);
- __raw_writel(bank->context.ctrl,
- bank->base + OMAP24XX_GPIO_CTRL);
- __raw_writel(bank->context.oe,
- bank->base + OMAP24XX_GPIO_OE);
- __raw_writel(bank->context.leveldetect0,
- bank->base + OMAP24XX_GPIO_LEVELDETECT0);
- __raw_writel(bank->context.leveldetect1,
- bank->base + OMAP24XX_GPIO_LEVELDETECT1);
- __raw_writel(bank->context.risingdetect,
- bank->base + OMAP24XX_GPIO_RISINGDETECT);
- __raw_writel(bank->context.fallingdetect,
- bank->base + OMAP24XX_GPIO_FALLINGDETECT);
- __raw_writel(bank->context.dataout,
- bank->base + OMAP24XX_GPIO_DATAOUT);
- }
+ __raw_writel(bank->context.irqenable1,
+ bank->base + OMAP24XX_GPIO_IRQENABLE1);
+ __raw_writel(bank->context.irqenable2,
+ bank->base + OMAP24XX_GPIO_IRQENABLE2);
+ __raw_writel(bank->context.wake_en,
+ bank->base + OMAP24XX_GPIO_WAKE_EN);
+ __raw_writel(bank->context.ctrl, bank->base + OMAP24XX_GPIO_CTRL);
+ __raw_writel(bank->context.oe, bank->base + OMAP24XX_GPIO_OE);
+ __raw_writel(bank->context.leveldetect0,
+ bank->base + OMAP24XX_GPIO_LEVELDETECT0);
+ __raw_writel(bank->context.leveldetect1,
+ bank->base + OMAP24XX_GPIO_LEVELDETECT1);
+ __raw_writel(bank->context.risingdetect,
+ bank->base + OMAP24XX_GPIO_RISINGDETECT);
+ __raw_writel(bank->context.fallingdetect,
+ bank->base + OMAP24XX_GPIO_FALLINGDETECT);
+ __raw_writel(bank->context.dataout,
+ bank->base + OMAP24XX_GPIO_DATAOUT);
}
#endif
--
1.7.0.4
^ permalink raw reply related
* [PATCH v8 03/24] gpio/omap: make gpio_context part of gpio_bank structure
From: Tarun Kanti DebBarma @ 2011-10-05 8:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1317803593-12259-1-git-send-email-tarun.kanti@ti.com>
From: Charulatha V <charu@ti.com>
Currently gpio_context array used to save gpio bank's context, is used only for
OMAP3 architecture. Move gpio_context as part of gpio_bank structure so that it
can be specific to each gpio bank and can be used for any OMAP architecture
Signed-off-by: Charulatha V <charu@ti.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
drivers/gpio/gpio-omap.c | 76 ++++++++++++++++++++-------------------------
1 files changed, 34 insertions(+), 42 deletions(-)
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 65fed50..62d2213 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -30,6 +30,19 @@
static LIST_HEAD(omap_gpio_list);
+struct gpio_regs {
+ u32 irqenable1;
+ u32 irqenable2;
+ u32 wake_en;
+ u32 ctrl;
+ u32 oe;
+ u32 leveldetect0;
+ u32 leveldetect1;
+ u32 risingdetect;
+ u32 fallingdetect;
+ u32 dataout;
+};
+
struct gpio_bank {
struct list_head node;
unsigned long pbase;
@@ -43,7 +56,7 @@ struct gpio_bank {
#endif
u32 non_wakeup_gpios;
u32 enabled_non_wakeup_gpios;
-
+ struct gpio_regs context;
u32 saved_datain;
u32 saved_fallingdetect;
u32 saved_risingdetect;
@@ -66,23 +79,6 @@ struct gpio_bank {
struct omap_gpio_reg_offs *regs;
};
-#ifdef CONFIG_ARCH_OMAP3
-struct omap3_gpio_regs {
- u32 irqenable1;
- u32 irqenable2;
- u32 wake_en;
- u32 ctrl;
- u32 oe;
- u32 leveldetect0;
- u32 leveldetect1;
- u32 risingdetect;
- u32 fallingdetect;
- u32 dataout;
-};
-
-static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
-#endif
-
#define GPIO_INDEX(bank, gpio) (gpio % bank->width)
#define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
@@ -1499,33 +1495,31 @@ void omap2_gpio_resume_after_idle(void)
void omap_gpio_save_context(void)
{
struct gpio_bank *bank;
- int i = 0;
list_for_each_entry(bank, &omap_gpio_list, node) {
- i++;
if (!bank->loses_context)
continue;
- gpio_context[i].irqenable1 =
+ bank->context.irqenable1 =
__raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
- gpio_context[i].irqenable2 =
+ bank->context.irqenable2 =
__raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
- gpio_context[i].wake_en =
+ bank->context.wake_en =
__raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
- gpio_context[i].ctrl =
+ bank->context.ctrl =
__raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
- gpio_context[i].oe =
+ bank->context.oe =
__raw_readl(bank->base + OMAP24XX_GPIO_OE);
- gpio_context[i].leveldetect0 =
+ bank->context.leveldetect0 =
__raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
- gpio_context[i].leveldetect1 =
+ bank->context.leveldetect1 =
__raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
- gpio_context[i].risingdetect =
+ bank->context.risingdetect =
__raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
- gpio_context[i].fallingdetect =
+ bank->context.fallingdetect =
__raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
- gpio_context[i].dataout =
+ bank->context.dataout =
__raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
}
}
@@ -1533,33 +1527,31 @@ void omap_gpio_save_context(void)
void omap_gpio_restore_context(void)
{
struct gpio_bank *bank;
- int i = 0;
list_for_each_entry(bank, &omap_gpio_list, node) {
- i++;
if (!bank->loses_context)
continue;
- __raw_writel(gpio_context[i].irqenable1,
+ __raw_writel(bank->context.irqenable1,
bank->base + OMAP24XX_GPIO_IRQENABLE1);
- __raw_writel(gpio_context[i].irqenable2,
+ __raw_writel(bank->context.irqenable2,
bank->base + OMAP24XX_GPIO_IRQENABLE2);
- __raw_writel(gpio_context[i].wake_en,
+ __raw_writel(bank->context.wake_en,
bank->base + OMAP24XX_GPIO_WAKE_EN);
- __raw_writel(gpio_context[i].ctrl,
+ __raw_writel(bank->context.ctrl,
bank->base + OMAP24XX_GPIO_CTRL);
- __raw_writel(gpio_context[i].oe,
+ __raw_writel(bank->context.oe,
bank->base + OMAP24XX_GPIO_OE);
- __raw_writel(gpio_context[i].leveldetect0,
+ __raw_writel(bank->context.leveldetect0,
bank->base + OMAP24XX_GPIO_LEVELDETECT0);
- __raw_writel(gpio_context[i].leveldetect1,
+ __raw_writel(bank->context.leveldetect1,
bank->base + OMAP24XX_GPIO_LEVELDETECT1);
- __raw_writel(gpio_context[i].risingdetect,
+ __raw_writel(bank->context.risingdetect,
bank->base + OMAP24XX_GPIO_RISINGDETECT);
- __raw_writel(gpio_context[i].fallingdetect,
+ __raw_writel(bank->context.fallingdetect,
bank->base + OMAP24XX_GPIO_FALLINGDETECT);
- __raw_writel(gpio_context[i].dataout,
+ __raw_writel(bank->context.dataout,
bank->base + OMAP24XX_GPIO_DATAOUT);
}
}
--
1.7.0.4
^ permalink raw reply related
* [PATCH v8 02/24] gpio/omap: use flag to identify wakeup domain
From: Tarun Kanti DebBarma @ 2011-10-05 8:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1317803593-12259-1-git-send-email-tarun.kanti@ti.com>
From: Charulatha V <charu@ti.com>
In omap3, save/restore context is implemented for GPIO banks 2-6 as GPIO bank1
is in wakeup domain. Instead of identifying bank's power domain by bank id,
use 'loses_context' flag which is filled by pwrdm_can_ever_lose_context()
during dev_init.
For getting the powerdomain pointer, omap_hwmod_get_pwrdm() is used.
omap_device_get_pwrdm() could not be used as the pwrdm information needs to be
filled in pdata, whereas omap_device_get_pwrdm() could be used only after
omap_device_build() call.
Signed-off-by: Charulatha V <charu@ti.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
arch/arm/mach-omap2/gpio.c | 6 ++++++
arch/arm/plat-omap/include/plat/gpio.h | 1 +
drivers/gpio/gpio-omap.c | 13 ++++++-------
3 files changed, 13 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index fb162fd..9f3a007 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -24,6 +24,8 @@
#include <plat/omap_hwmod.h>
#include <plat/omap_device.h>
+#include "powerdomain.h"
+
static struct omap_device_pm_latency omap_gpio_latency[] = {
[0] = {
.deactivate_func = omap_device_idle_hwmods,
@@ -39,6 +41,7 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
struct omap_gpio_dev_attr *dev_attr;
char *name = "omap_gpio";
int id;
+ struct powerdomain *pwrdm;
/*
* extract the device id from name field available in the
@@ -107,6 +110,9 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
return -EINVAL;
}
+ pwrdm = omap_hwmod_get_pwrdm(oh);
+ pdata->loses_context = pwrdm_can_ever_lose_context(pwrdm);
+
od = omap_device_build(name, id - 1, oh, pdata,
sizeof(*pdata), omap_gpio_latency,
ARRAY_SIZE(omap_gpio_latency),
diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
index dd330ed..58d0bf2 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -198,6 +198,7 @@ struct omap_gpio_platform_data {
int bank_width; /* GPIO bank width */
int bank_stride; /* Only needed for omap1 MPUIO */
bool dbck_flag; /* dbck required or not - True for OMAP3&4 */
+ bool loses_context; /* whether the bank would ever lose context */
struct omap_gpio_reg_offs *regs;
};
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index fabe2c0..65fed50 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -56,6 +56,7 @@ struct gpio_bank {
u32 dbck_enable_mask;
struct device *dev;
bool dbck_flag;
+ bool loses_context;
int stride;
u32 width;
u16 id;
@@ -1181,7 +1182,7 @@ static int __devinit omap_gpio_probe(struct platform_device *pdev)
bank->dbck_flag = pdata->dbck_flag;
bank->stride = pdata->bank_stride;
bank->width = pdata->bank_width;
-
+ bank->loses_context = pdata->loses_context;
bank->regs = pdata->regs;
if (bank->regs->set_dataout && bank->regs->clr_dataout)
@@ -1337,8 +1338,7 @@ void omap2_gpio_prepare_for_idle(int off_mode)
u32 l1 = 0, l2 = 0;
int j;
- /* TODO: Do not use cpu_is_omap34xx */
- if ((cpu_is_omap34xx()) && (bank->id == 0))
+ if (!bank->loses_context)
continue;
for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
@@ -1405,8 +1405,7 @@ void omap2_gpio_resume_after_idle(void)
u32 l = 0, gen, gen0, gen1;
int j;
- /* TODO: Do not use cpu_is_omap34xx */
- if ((cpu_is_omap34xx()) && (bank->id == 0))
+ if (!bank->loses_context)
continue;
for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
@@ -1505,7 +1504,7 @@ void omap_gpio_save_context(void)
list_for_each_entry(bank, &omap_gpio_list, node) {
i++;
- if (bank->id == 0)
+ if (!bank->loses_context)
continue;
gpio_context[i].irqenable1 =
@@ -1539,7 +1538,7 @@ void omap_gpio_restore_context(void)
list_for_each_entry(bank, &omap_gpio_list, node) {
i++;
- if (bank->id == 0)
+ if (!bank->loses_context)
continue;
__raw_writel(gpio_context[i].irqenable1,
--
1.7.0.4
^ permalink raw reply related
* [PATCH v8 01/24] gpio/omap: remove dependency on gpio_bank_count
From: Tarun Kanti DebBarma @ 2011-10-05 8:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1317803593-12259-1-git-send-email-tarun.kanti@ti.com>
From: Charulatha V <charu@ti.com>
The gpio_bank_count is the count of number of GPIO devices in a SoC. Remove this
dependency from the driver by using list. Also remove the dependency on array of
pointers to gpio_bank struct of all GPIO devices.
Signed-off-by: Charulatha V <charu@ti.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/mach-omap1/gpio15xx.c | 1 -
arch/arm/mach-omap1/gpio16xx.c | 2 -
arch/arm/mach-omap1/gpio7xx.c | 2 -
arch/arm/mach-omap2/gpio.c | 1 -
arch/arm/plat-omap/include/plat/gpio.h | 3 -
drivers/gpio/gpio-omap.c | 163 ++++++++++++++++----------------
6 files changed, 80 insertions(+), 92 deletions(-)
diff --git a/arch/arm/mach-omap1/gpio15xx.c b/arch/arm/mach-omap1/gpio15xx.c
index 399da4c..f8c15ea 100644
--- a/arch/arm/mach-omap1/gpio15xx.c
+++ b/arch/arm/mach-omap1/gpio15xx.c
@@ -115,7 +115,6 @@ static int __init omap15xx_gpio_init(void)
platform_device_register(&omap15xx_mpu_gpio);
platform_device_register(&omap15xx_gpio);
- gpio_bank_count = 2;
return 0;
}
postcore_initcall(omap15xx_gpio_init);
diff --git a/arch/arm/mach-omap1/gpio16xx.c b/arch/arm/mach-omap1/gpio16xx.c
index 0f399bd..df4bb44 100644
--- a/arch/arm/mach-omap1/gpio16xx.c
+++ b/arch/arm/mach-omap1/gpio16xx.c
@@ -221,8 +221,6 @@ static int __init omap16xx_gpio_init(void)
for (i = 0; i < ARRAY_SIZE(omap16xx_gpio_dev); i++)
platform_device_register(omap16xx_gpio_dev[i]);
- gpio_bank_count = ARRAY_SIZE(omap16xx_gpio_dev);
-
return 0;
}
postcore_initcall(omap16xx_gpio_init);
diff --git a/arch/arm/mach-omap1/gpio7xx.c b/arch/arm/mach-omap1/gpio7xx.c
index 5ab63ea..923eaa1 100644
--- a/arch/arm/mach-omap1/gpio7xx.c
+++ b/arch/arm/mach-omap1/gpio7xx.c
@@ -282,8 +282,6 @@ static int __init omap7xx_gpio_init(void)
for (i = 0; i < ARRAY_SIZE(omap7xx_gpio_dev); i++)
platform_device_register(omap7xx_gpio_dev[i]);
- gpio_bank_count = ARRAY_SIZE(omap7xx_gpio_dev);
-
return 0;
}
postcore_initcall(omap7xx_gpio_init);
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index 2765cdc..fb162fd 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -121,7 +121,6 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
omap_device_disable_idle_on_suspend(od);
- gpio_bank_count++;
return 0;
}
diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
index 91e8de3..dd330ed 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -202,9 +202,6 @@ struct omap_gpio_platform_data {
struct omap_gpio_reg_offs *regs;
};
-/* TODO: Analyze removing gpio_bank_count usage from driver code */
-extern int gpio_bank_count;
-
extern void omap2_gpio_prepare_for_idle(int off_mode);
extern void omap2_gpio_resume_after_idle(void);
extern void omap_set_gpio_debounce(int gpio, int enable);
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index f0208a9..fabe2c0 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -28,7 +28,10 @@
#include <mach/gpio.h>
#include <asm/mach/irq.h>
+static LIST_HEAD(omap_gpio_list);
+
struct gpio_bank {
+ struct list_head node;
unsigned long pbase;
void __iomem *base;
u16 irq;
@@ -55,6 +58,7 @@ struct gpio_bank {
bool dbck_flag;
int stride;
u32 width;
+ u16 id;
void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable);
@@ -78,15 +82,6 @@ struct omap3_gpio_regs {
static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
#endif
-/*
- * TODO: Cleanup gpio_bank usage as it is having information
- * related to all instances of the device
- */
-static struct gpio_bank *gpio_bank;
-
-/* TODO: Analyze removing gpio_bank_count usage from driver code */
-int gpio_bank_count;
-
#define GPIO_INDEX(bank, gpio) (gpio % bank->width)
#define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
@@ -869,9 +864,8 @@ static struct platform_device omap_mpuio_device = {
/* could list the /proc/iomem resources */
};
-static inline void mpuio_init(void)
+static inline void mpuio_init(struct gpio_bank *bank)
{
- struct gpio_bank *bank = &gpio_bank[0];
platform_set_drvdata(&omap_mpuio_device, bank);
if (platform_driver_register(&omap_mpuio_driver) == 0)
@@ -879,13 +873,13 @@ static inline void mpuio_init(void)
}
#else
-static inline void mpuio_init(void) {}
+static inline void mpuio_init(struct gpio_bank *bank) {}
#endif /* 16xx */
#else
#define bank_is_mpuio(bank) 0
-static inline void mpuio_init(void) {}
+static inline void mpuio_init(struct gpio_bank *bank) {}
#endif
@@ -1007,20 +1001,8 @@ static void __init omap_gpio_show_rev(struct gpio_bank *bank)
*/
static struct lock_class_key gpio_lock_class;
-static inline int init_gpio_info(struct platform_device *pdev)
-{
- /* TODO: Analyze removing gpio_bank_count usage from driver code */
- gpio_bank = kzalloc(gpio_bank_count * sizeof(struct gpio_bank),
- GFP_KERNEL);
- if (!gpio_bank) {
- dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n");
- return -ENOMEM;
- }
- return 0;
-}
-
/* TODO: Cleanup cpu_is_* checks */
-static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
+static void omap_gpio_mod_init(struct gpio_bank *bank)
{
if (cpu_class_is_omap2()) {
if (cpu_is_omap44xx()) {
@@ -1044,13 +1026,16 @@ static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
static const u32 non_wakeup_gpios[] = {
0xe203ffc0, 0x08700040
};
- if (id < ARRAY_SIZE(non_wakeup_gpios))
- bank->non_wakeup_gpios = non_wakeup_gpios[id];
+ if (bank->id < ARRAY_SIZE(non_wakeup_gpios))
+ bank->non_wakeup_gpios =
+ non_wakeup_gpios[bank->id];
}
} else if (cpu_class_is_omap1()) {
- if (bank_is_mpuio(bank))
+ if (bank_is_mpuio(bank)) {
__raw_writew(0xffff, bank->base +
OMAP_MPUIO_GPIO_MASKIT / bank->stride);
+ mpuio_init(bank);
+ }
if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
__raw_writew(0xffff, bank->base
+ OMAP1510_GPIO_INT_MASK);
@@ -1161,35 +1146,35 @@ static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
static int __devinit omap_gpio_probe(struct platform_device *pdev)
{
- static int gpio_init_done;
struct omap_gpio_platform_data *pdata;
struct resource *res;
- int id;
struct gpio_bank *bank;
+ int ret = 0;
- if (!pdev->dev.platform_data)
- return -EINVAL;
-
- pdata = pdev->dev.platform_data;
-
- if (!gpio_init_done) {
- int ret;
-
- ret = init_gpio_info(pdev);
- if (ret)
- return ret;
+ if (!pdev->dev.platform_data) {
+ ret = -EINVAL;
+ goto err_exit;
}
- id = pdev->id;
- bank = &gpio_bank[id];
+ bank = kzalloc(sizeof(struct gpio_bank), GFP_KERNEL);
+ if (!bank) {
+ dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n");
+ ret = -ENOMEM;
+ goto err_exit;
+ }
res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
if (unlikely(!res)) {
- dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", id);
- return -ENODEV;
+ dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n",
+ pdev->id);
+ ret = -ENODEV;
+ goto err_free;
}
bank->irq = res->start;
+ bank->id = pdev->id;
+
+ pdata = pdev->dev.platform_data;
bank->virtual_irq_start = pdata->virtual_irq_start;
bank->method = pdata->bank_type;
bank->dev = &pdev->dev;
@@ -1209,39 +1194,46 @@ static int __devinit omap_gpio_probe(struct platform_device *pdev)
/* Static mapping, never released */
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (unlikely(!res)) {
- dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", id);
- return -ENODEV;
+ dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n",
+ pdev->id);
+ ret = -ENODEV;
+ goto err_free;
}
bank->base = ioremap(res->start, resource_size(res));
if (!bank->base) {
- dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", id);
- return -ENOMEM;
+ dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n",
+ pdev->id);
+ ret = -ENOMEM;
+ goto err_free;
}
pm_runtime_enable(bank->dev);
pm_runtime_get_sync(bank->dev);
- omap_gpio_mod_init(bank, id);
+ omap_gpio_mod_init(bank);
omap_gpio_chip_init(bank);
omap_gpio_show_rev(bank);
- if (!gpio_init_done)
- gpio_init_done = 1;
+ list_add_tail(&bank->node, &omap_gpio_list);
- return 0;
+ return ret;
+
+err_free:
+ kfree(bank);
+err_exit:
+ return ret;
}
#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
static int omap_gpio_suspend(void)
{
- int i;
+ struct gpio_bank *bank;
if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
return 0;
- for (i = 0; i < gpio_bank_count; i++) {
- struct gpio_bank *bank = &gpio_bank[i];
+ list_for_each_entry(bank, &omap_gpio_list, node) {
void __iomem *wake_status;
void __iomem *wake_clear;
void __iomem *wake_set;
@@ -1285,13 +1277,12 @@ static int omap_gpio_suspend(void)
static void omap_gpio_resume(void)
{
- int i;
+ struct gpio_bank *bank;
if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
return;
- for (i = 0; i < gpio_bank_count; i++) {
- struct gpio_bank *bank = &gpio_bank[i];
+ list_for_each_entry(bank, &omap_gpio_list, node) {
void __iomem *wake_clear;
void __iomem *wake_set;
unsigned long flags;
@@ -1339,17 +1330,17 @@ static int workaround_enabled;
void omap2_gpio_prepare_for_idle(int off_mode)
{
- int i, c = 0;
- int min = 0;
-
- if (cpu_is_omap34xx())
- min = 1;
+ int c = 0;
+ struct gpio_bank *bank;
- for (i = min; i < gpio_bank_count; i++) {
- struct gpio_bank *bank = &gpio_bank[i];
+ list_for_each_entry(bank, &omap_gpio_list, node) {
u32 l1 = 0, l2 = 0;
int j;
+ /* TODO: Do not use cpu_is_omap34xx */
+ if ((cpu_is_omap34xx()) && (bank->id == 0))
+ continue;
+
for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
clk_disable(bank->dbck);
@@ -1408,16 +1399,16 @@ void omap2_gpio_prepare_for_idle(int off_mode)
void omap2_gpio_resume_after_idle(void)
{
- int i;
- int min = 0;
+ struct gpio_bank *bank;
- if (cpu_is_omap34xx())
- min = 1;
- for (i = min; i < gpio_bank_count; i++) {
- struct gpio_bank *bank = &gpio_bank[i];
+ list_for_each_entry(bank, &omap_gpio_list, node) {
u32 l = 0, gen, gen0, gen1;
int j;
+ /* TODO: Do not use cpu_is_omap34xx */
+ if ((cpu_is_omap34xx()) && (bank->id == 0))
+ continue;
+
for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
clk_enable(bank->dbck);
@@ -1506,14 +1497,17 @@ void omap2_gpio_resume_after_idle(void)
#endif
#ifdef CONFIG_ARCH_OMAP3
-/* save the registers of bank 2-6 */
void omap_gpio_save_context(void)
{
- int i;
+ struct gpio_bank *bank;
+ int i = 0;
+
+ list_for_each_entry(bank, &omap_gpio_list, node) {
+ i++;
+
+ if (bank->id == 0)
+ continue;
- /* saving banks from 2-6 only since GPIO1 is in WKUP */
- for (i = 1; i < gpio_bank_count; i++) {
- struct gpio_bank *bank = &gpio_bank[i];
gpio_context[i].irqenable1 =
__raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
gpio_context[i].irqenable2 =
@@ -1537,13 +1531,17 @@ void omap_gpio_save_context(void)
}
}
-/* restore the required registers of bank 2-6 */
void omap_gpio_restore_context(void)
{
- int i;
+ struct gpio_bank *bank;
+ int i = 0;
+
+ list_for_each_entry(bank, &omap_gpio_list, node) {
+ i++;
+
+ if (bank->id == 0)
+ continue;
- for (i = 1; i < gpio_bank_count; i++) {
- struct gpio_bank *bank = &gpio_bank[i];
__raw_writel(gpio_context[i].irqenable1,
bank->base + OMAP24XX_GPIO_IRQENABLE1);
__raw_writel(gpio_context[i].irqenable2,
@@ -1588,7 +1586,6 @@ postcore_initcall(omap_gpio_drv_reg);
static int __init omap_gpio_sysinit(void)
{
- mpuio_init();
#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
if (cpu_is_omap16xx() || cpu_class_is_omap2())
--
1.7.0.4
^ permalink raw reply related
* [PATCH v8 00/24] gpio/omap: driver cleanup and fixes
From: Tarun Kanti DebBarma @ 2011-10-05 8:32 UTC (permalink / raw)
To: linux-arm-kernel
This series is continuation of cleanup of OMAP GPIO driver and fixes.
The cleanup include getting rid of cpu_is_* checks wherever possible,
use of gpio_bank list instead of static array, use of unique platform
specific value associated data member to OMAP platforms to avoid
cpu_is_* checks. The series also include PM runtime support.*
Baseline: git://gitorious.org/khilman/linux-omap-pm.git
Test info:
OMAP3430SDP
- Retention along Suspend and Idle paths
- Off-mode
OMAP4430SDP - functional
OMAP2430SDP - functional
OMAP1710SDP - Bootup
v8:
- Remove PM_CONFIG macro around following assignment.
pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
- Once pm_runtime is enabled there is no more need for calling the
omap_device_disable_idle_on_suspend(od).
- With pm_runtime, handling of clocks in Suspend is taken care of by
powerdomain hooks. So remove usage of *_runtime_put/get* from
suspend/resume hooks and Idle path.
- Add handling of debounce clocks along the Suspend and Idle paths.
- Remove [PATCH 04/24] gpio/omap: fix pwrdm_post_transition call sequence
from this series. This will be merged as part of power cleanup series.
- Remove [PATCH v7 20/26] gpio/omap: skip operations in runtime callbacks
The bank->mod_usage check in this patch is not needed any more because
they are now already being taken care in suspend/resume and Idle paths.
- Remove [PATCH v7 26/26] gpio/omap: add dbclk aliases for all gpio modules
This is already taken care in hwmod.
- Remove redundant blank line in
[PATCH v7 14/26] gpio/omap: remove unnecessary bit-masking for read access
- if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
- isr &= 0x0000ffff;
if (bank->level_mask)
level_mask = bank->level_mask & enabled;
v7:
- Use pm_runtime_put() instead of pm_runtime_put_sync_suspend()
- Keep *_runtime_get/put*() outside spinlock
- Remove additional checking of conditions in _restore_context()
From:
if (bank->regs->set_dataout && bank->regs->clear_dataout)
...
To:
if (bank->regs->set_dataout)
...
- Use SET_RUNTIME_PM_OPS and SET_SYSTEM_SLEEP_PM_OPS macros
- In [PATCH 19/25] gpio/omap: cleanup prepare_for_idle and resume_after_idle,
protect the bank data elements and register access using spinlock in
runtime_suspend/resume() callbacks.
This is because these callbacks run with interrupts enabled.
- Add dbclk aliases for all GPIO modules. Without this, GPIO modules were not
getting the correct clock handle to enable/disable debounec clock.
- Fix log comments on the following patches:
[PATCH 19/25] gpio/omap: cleanup prepare_for_idle and resume_after_idle
[PATCH 20/25] gpio/omap: skip operations in runtime callbacks
[PATCH 24/25] gpio/omap: restore OE only after setting the output level
v6:
- Save and restore debounce registers for proper driver operation.
- Restore interrupt enable after all configuration to avoid spurious interrupts.
- Restore dataout register before oe register.
- Restore dataout into dataout_set or dataout based upon the OMAP version.
- Change register name from wkup_status to wkup_en.
- Remove wrapper around omap_pm_get_dev_context_loss_count(). Use it directly.
Also, changed the signature of get_context_loss_count in pdata and bank structure
from int to u32.
- Use 'context' instead of 'ctx' for clarity wherever it is used.
- Merged two patches into one which are related to bank_is_mpuio() modification.
- Use shift operator instead of following:
+ .irqctrl = OMAP_MPUIO_GPIO_INT_EDGE / 2,
- Remove redundant check from the following
+ if (bank_is_mpuio(bank)) {
+ if (bank->regs->wkup_status) <--- redundant check
+ mpuio_init(bank);
- Change subject of following patch
[PATCH v5 15/22] gpio/omap: use readl in irq_handler for all access
into
[PATCH 14/25] gpio/omap: remove unnecessary bit-masking for read access
- Fix multi-line comments in
[PATCH v5 20/22] gpio/omap: cleanup prepare_for_idle and resume_after_idle
v5:
- Reduce runtime callback overhead when *_get/put_sync() called from probe()
and *_gpio_request/free().
- Dynamic context save within functions where context is modified instead of
saving all context within a common function.
- Removed call to mpuio_init() from omap_gpio_mod_init(). Both the functions are
called once during initialization in *_gpio_probe().
Call to omap_gpio_mod_init() has been removed from omap_gpio_request() on the
first access to gpio bank. One time initialization looks sufficient.
- In *_gpio_irq_handler() use *_put_sync_suspend() instead of *_put_sync().
- Removed hardcoding of OMAP16xx sysconfig register value and instead defined an
associated constant.
- Removed *_get_sync() call from *_gpio_suspend() and *_put_sync() call from
*_gpio_resume(). They got wrongly slipped into the code.
- Removed following redundant zero allocated initialization from mach-omap2/gpio.c
+ pdata->regs->irqctrl = 0;
+ pdata->regs->edgectrl1 = 0;
+ pdata->regs->edgectrl2 = 0;
- Removed following redundant code in gpio-omap.c
-#define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
v4:
- since all accesses to registers are 4-byte aligned, removing special
checks and handling of 16 and 32-bit wide bank registers and instead
use 32-bit read/write access consistently.
- redundant usage of MOD_REG_BIT has been corrected and replaced with
_gpio_rmw().
- omap_gpio_mod_init() function has been simplified further using _gpio_rmw().
- sysconfig register offset specific to omap16xx has been removed along
with its usage.
- additional logic to skip from suspend/resume:
if (!bank->regs->wkup_status || !bank->suspend_wakeup)
return 0;
if (!bank->regs->wkup_status || !bank->saved_wakeup)
return 0;
- separated mpuio related changes into a different patch from the patch where
wakeup status register related changes are done.
- Incorrect replacement of !cpu_class_is_omap2() in gpio_irq_type()
corrected:
+ if (!bank->regs->leveldetect0 &&
+ (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
return -EINVAL;
v3:
- Avoid use of wkup_set and wkup_clear registers. Instead use wkup_status
register for all platforms. This is because on OMAP4 it is recommended
not to use them.
- Remove duplicate code in omap_gpio_mod_init() for handling the same for
32-bit and 16-bit GPIO bank widths. This is accomplished by having two
functions to handle each case while assiging a common function pointer
during initialization.
- Remove OMAP16xx specific one time initialization from omap_gpio_mod_init().
Move it inside omap16xx_gpio_init().
- Avoid usage of USHRT_MAX to indicate undefined values. Use 0 instead.
- In omap_gpio_suspend()/resume() functions remove code that checks
if the feature is supported. Instead, assign these functions to
struct platform_driver's suspend & resume function pointers for those
OMAP platforms whcih support this feature.
- Remove 'suspend_support' flag because it is redundant. Instead use
wkup_* registers to decode the same information.
- Restore context also when we don't know if the context is lost.
- Make omap_gpio_save_context() and omap_gpio_restore_context()
static.
v2:
- Do special handling of non-wakeup GPIOs only on OMAP2420. Avoid this
handling on OMAP3430.
- Isolate cleanups and fixes into separate set of patches. Keep the cleanup
first followed by the fixes.
- Avoid calling omap_gpio_get_context_loss() directly and instead call it
through function pointer in pdata initialized during init.
- workaround_enabled flag is not longer needed and is removed.
- Call pwrdm_post_transition() before calling omap_gpio_resume_after_idle().
- In omap2_gpio_resume_after_idle() do context restore before handling
workaround.
- Use PM runtime framework.
- Modify register offset names to : wkup_status, wkup_clear, wkup_set.
Also use 'base + offset' for readibility in all relevant places.
- Remove unwanted messages from commit section like TODO, etc.
Charulatha V (8):
gpio/omap: remove dependency on gpio_bank_count
gpio/omap: use flag to identify wakeup domain
gpio/omap: make gpio_context part of gpio_bank structure
gpio/omap: make non-wakeup GPIO part of pdata
gpio/omap: avoid cpu checks during module ena/disable
gpio/omap: use pinctrl offset instead of macro
gpio/omap: remove bank->method & METHOD_* macros
gpio/omap: fix bankwidth for OMAP7xx MPUIO
Nishanth Menon (4):
gpio/omap: save and restore debounce registers
gpio/omap: enable irq at the end of all configuration in restore
gpio/omap: restore OE only after setting the output level
gpio/omap: handle set_dataout reg capable IP on restore
Tarun Kanti DebBarma (12):
gpio/omap: handle save/restore context in GPIO driver
gpio/omap: further cleanup using wkup_en register
gpio/omap: use level/edge detect reg offsets
gpio/omap: remove hardcoded offsets in context save/restore
gpio/omap: cleanup set_gpio_triggering function
gpio/omap: cleanup omap_gpio_mod_init function
gpio/omap: remove unnecessary bit-masking for read access
gpio/omap: use pm-runtime framework
gpio/omap: fix debounce clock handling
gpio/omap: optimize suspend and resume functions
gpio/omap: cleanup prepare_for_idle and resume_after_idle
gpio/omap: remove omap_gpio_save_context overhead
arch/arm/mach-omap1/gpio15xx.c | 7 +-
arch/arm/mach-omap1/gpio16xx.c | 47 ++-
arch/arm/mach-omap1/gpio7xx.c | 14 +-
arch/arm/mach-omap2/gpio.c | 36 +-
arch/arm/mach-omap2/pm34xx.c | 14 -
arch/arm/plat-omap/include/plat/gpio.h | 29 +-
drivers/gpio/gpio-omap.c | 1073 +++++++++++++-------------------
7 files changed, 532 insertions(+), 688 deletions(-)
^ permalink raw reply
* [PATCH 2/2] atmel_lcdfb: Use proper blanking on negative contrast polarity
From: Alexander Stein @ 2011-10-05 7:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1317801598-23757-1-git-send-email-alexander.stein@systec-electronic.com>
If used with negative polarity the PWM unit cannot be disabled. This would
result in a full contrast screen.
Instead let the PWM unit enabled using 0x0 as compare value which darkens
the display.
In result no power saving is possible if inverted contrast polarity
is used.
Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com>
---
drivers/video/atmel_lcdfb.c | 5 ++++-
1 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
index 816d528..2bd75b5 100644
--- a/drivers/video/atmel_lcdfb.c
+++ b/drivers/video/atmel_lcdfb.c
@@ -96,8 +96,11 @@ static int atmel_bl_update_status(struct backlight_device *bl)
brightness = 0;
lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_VAL, brightness);
- lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR,
+ if (contrast_ctr & ATMEL_LCDC_POL_POSITIVE)
+ lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR,
brightness ? contrast_ctr : 0);
+ else
+ lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, contrast_ctr);
bl->props.fb_blank = bl->props.power = sinfo->bl_power = power;
--
1.7.3.4
^ permalink raw reply related
* [PATCH 1/2] atmel_lcdfb: Adjust HFP calculation so it matches the manual.
From: Alexander Stein @ 2011-10-05 7:59 UTC (permalink / raw)
To: linux-arm-kernel
In the AT91SAM9263 Manual the HFP part in LCDTIM2 is described as follows:
* HFP: Horizontal Front Porch
Number of idle LCDDOTCK cycles at the end of the line.
Idle period is (HFP+2) LCDDOTCK cycles.
It is only a minor issue. I also changed all boards using atmel_lcdfb
I found to respect the new calculation.
Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com>
---
arch/arm/mach-at91/board-cap9adk.c | 2 +-
arch/arm/mach-at91/board-neocore926.c | 2 +-
arch/arm/mach-at91/board-sam9261ek.c | 4 ++--
arch/arm/mach-at91/board-sam9263ek.c | 2 +-
arch/arm/mach-at91/board-sam9m10g45ek.c | 2 +-
arch/arm/mach-at91/board-sam9rlek.c | 2 +-
drivers/video/atmel_lcdfb.c | 4 ++--
7 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-at91/board-cap9adk.c b/arch/arm/mach-at91/board-cap9adk.c
index 679b0b7..ae962bf 100644
--- a/arch/arm/mach-at91/board-cap9adk.c
+++ b/arch/arm/mach-at91/board-cap9adk.c
@@ -304,7 +304,7 @@ static struct fb_videomode at91_tft_vga_modes[] = {
.xres = 240, .yres = 320,
.pixclock = KHZ2PICOS(4965),
- .left_margin = 1, .right_margin = 33,
+ .left_margin = 1, .right_margin = 34,
.upper_margin = 1, .lower_margin = 0,
.hsync_len = 5, .vsync_len = 1,
diff --git a/arch/arm/mach-at91/board-neocore926.c b/arch/arm/mach-at91/board-neocore926.c
index 9bc6ab3..583878e 100644
--- a/arch/arm/mach-at91/board-neocore926.c
+++ b/arch/arm/mach-at91/board-neocore926.c
@@ -235,7 +235,7 @@ static struct fb_videomode at91_tft_vga_modes[] = {
.xres = 240, .yres = 320,
.pixclock = KHZ2PICOS(5000),
- .left_margin = 1, .right_margin = 33,
+ .left_margin = 1, .right_margin = 34,
.upper_margin = 1, .lower_margin = 0,
.hsync_len = 5, .vsync_len = 1,
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
index 5096a0e..8dda83b 100644
--- a/arch/arm/mach-at91/board-sam9261ek.c
+++ b/arch/arm/mach-at91/board-sam9261ek.c
@@ -370,7 +370,7 @@ static struct fb_videomode at91_stn_modes[] = {
.xres = 320, .yres = 240,
.pixclock = KHZ2PICOS(1440),
- .left_margin = 1, .right_margin = 1,
+ .left_margin = 1, .right_margin = 2,
.upper_margin = 0, .lower_margin = 0,
.hsync_len = 1, .vsync_len = 1,
@@ -431,7 +431,7 @@ static struct fb_videomode at91_tft_vga_modes[] = {
.xres = 240, .yres = 320,
.pixclock = KHZ2PICOS(4965),
- .left_margin = 1, .right_margin = 33,
+ .left_margin = 1, .right_margin = 34,
.upper_margin = 1, .lower_margin = 0,
.hsync_len = 5, .vsync_len = 1,
diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c
index ea8f185..e260070 100644
--- a/arch/arm/mach-at91/board-sam9263ek.c
+++ b/arch/arm/mach-at91/board-sam9263ek.c
@@ -258,7 +258,7 @@ static struct fb_videomode at91_tft_vga_modes[] = {
.xres = 240, .yres = 320,
.pixclock = KHZ2PICOS(4965),
- .left_margin = 1, .right_margin = 33,
+ .left_margin = 1, .right_margin = 34,
.upper_margin = 1, .lower_margin = 0,
.hsync_len = 5, .vsync_len = 1,
diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c
index ad234cc..5e9a5ca 100644
--- a/arch/arm/mach-at91/board-sam9m10g45ek.c
+++ b/arch/arm/mach-at91/board-sam9m10g45ek.c
@@ -197,7 +197,7 @@ static struct fb_videomode at91_tft_vga_modes[] = {
.xres = 480, .yres = 272,
.pixclock = KHZ2PICOS(9000),
- .left_margin = 1, .right_margin = 1,
+ .left_margin = 1, .right_margin = 2,
.upper_margin = 40, .lower_margin = 1,
.hsync_len = 45, .vsync_len = 1,
diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c
index 4f14b54..ad9e5c9 100644
--- a/arch/arm/mach-at91/board-sam9rlek.c
+++ b/arch/arm/mach-at91/board-sam9rlek.c
@@ -154,7 +154,7 @@ static struct fb_videomode at91_tft_vga_modes[] = {
.xres = 240, .yres = 320,
.pixclock = KHZ2PICOS(4965),
- .left_margin = 1, .right_margin = 33,
+ .left_margin = 1, .right_margin = 34,
.upper_margin = 1, .lower_margin = 0,
.hsync_len = 5, .vsync_len = 1,
diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
index 817ab60..816d528 100644
--- a/drivers/video/atmel_lcdfb.c
+++ b/drivers/video/atmel_lcdfb.c
@@ -393,7 +393,7 @@ static int atmel_lcdfb_check_var(struct fb_var_screeninfo *var,
var->lower_margin = min_t(u32, var->lower_margin,
ATMEL_LCDC_VFP);
var->right_margin = min_t(u32, var->right_margin,
- (ATMEL_LCDC_HFP >> ATMEL_LCDC_HFP_OFFSET) + 1);
+ (ATMEL_LCDC_HFP >> ATMEL_LCDC_HFP_OFFSET) + 2);
var->hsync_len = min_t(u32, var->hsync_len,
(ATMEL_LCDC_HPW >> ATMEL_LCDC_HPW_OFFSET) + 1);
var->left_margin = min_t(u32, var->left_margin,
@@ -578,7 +578,7 @@ static int atmel_lcdfb_set_par(struct fb_info *info)
lcdc_writel(sinfo, ATMEL_LCDC_TIM1, value);
/* Horizontal timing */
- value = (info->var.right_margin - 1) << ATMEL_LCDC_HFP_OFFSET;
+ value = (info->var.right_margin - 2) << ATMEL_LCDC_HFP_OFFSET;
value |= (info->var.hsync_len - 1) << ATMEL_LCDC_HPW_OFFSET;
value |= (info->var.left_margin - 1);
dev_dbg(info->device, " * LCDTIM2 = %08lx\n", value);
--
1.7.3.4
^ permalink raw reply related
* [PATCH 00/24 V2] OMAP4: PM: suspend, CPU-hotplug and CPUilde support
From: Santosh Shilimkar @ 2011-10-05 7:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <87zkhgk7pl.fsf@ti.com>
On Tuesday 04 October 2011 10:35 PM, Kevin Hilman wrote:
> Hi Santosh,
>
> Santosh Shilimkar <santosh.shilimkar@ti.com> writes:
>
>> The series adds OMAP4 MPUSS (MPU SubSystem) power management support for
>> suspend (S2R), CPU hotplug and CPUidle.
>
> No need to repost, but can you update the versions in your branch to
> have an ARM: prefix in the subject per Arnd's recent request?
>
Done. Branch for_3_2/omap4-mpuss-pm is updated with ARM on all patches.
Regards
Santosh
^ permalink raw reply
* [PATCH 3/3] ARM: SAMSUNG: Add lookup of sdhci-s3c clocks using generic names
From: Heiko Stübner @ 2011-10-05 7:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1317792669-19925-4-git-send-email-rajeshwari.s@samsung.com>
Am Mittwoch, 5. Oktober 2011, 07:31:09 schrieb Rajeshwari Shinde:
> Add support for lookup of sdhci-s3c controller clocks using generic names
> for s3c2416, s3c64xx, s5pc100, s5pv210 and exynos4 SoC's.
>
> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
> ---
[...]
> diff --git a/arch/arm/mach-s3c2416/clock.c b/arch/arm/mach-s3c2416/clock.c
> index 72b7c62..cebaf3f 100644
> --- a/arch/arm/mach-s3c2416/clock.c
> +++ b/arch/arm/mach-s3c2416/clock.c
[...]
> @@ -143,8 +142,14 @@ static struct clksrc_clk *clksrcs[] __initdata = {
> &hsspi_mux,
> &hsmmc_div[0],
> &hsmmc_div[1],
> - &hsmmc_mux[0],
> - &hsmmc_mux[1],
> + &hsmmc_mux0,
> + &hsmmc_mux1,
> +};
> +
> +static struct clk_lookup s3c2416_clk_lookup[] = {
> + CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &hsmmc0_clk),
This is missing the s3c-sdhci.1 mmc_busclk.0 as 4th entry which is defined in
s3c2443-clock.c. The pclk for hsmmc1 is common to S3C2416/2450 and S3C2443 and
is therefore defined in plat-s3c24xx [S3C2443 only has a hsmmc1 to be exact].
Also it would be nice to include the hsmmc-clock in mach-s3c2443/clock.c too.
The sdhci support there seems to be incomplete but it would be nice to have
the clocks similar to everything else if anyone wants to start on this arch.
> + CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &hsmmc_mux0.clk),
> + CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &hsmmc_mux1.clk),
> };
>
> void __init s3c2416_init_clocks(int xtal)
> @@ -164,6 +169,7 @@ void __init s3c2416_init_clocks(int xtal)
> s3c_register_clksrc(clksrcs[ptr], 1);
>
> s3c24xx_register_clock(&hsmmc0_clk);
> + clkdev_add_table(s3c2416_clk_lookup, ARRAY_SIZE(s3c2416_clk_lookup));
>
> s3c_pwmclk_init();
>
Heiko
^ permalink raw reply
* [PATCH 0/4] initialize omap SRAM later on with __arm_ioremap_exec()
From: Santosh Shilimkar @ 2011-10-05 7:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20111005004339.26980.31149.stgit@kaulin.local>
Tony,
On Wednesday 05 October 2011 06:15 AM, Tony Lindgren wrote:
> Hi all,
>
> Related to the omap static mapping, here's a first take on moving the
> SRAM init to happen later so we can do generic map_io.
>
> Still working on a similar patch for omap1, will send it a bit later.
>
> Regards,
>
> Tony
>
> ---
>
> Tony Lindgren (4):
> ARM: Add __arm_ioremap_exec for mapping external memory as MT_MEMORY
> ARM: OMAP: Avoid cpu_is_omapxxxx usage until map_io is done
> ARM: OMAP: Remove calls to SRAM allocations for framebuffer
> ARM: OMAP: Map SRAM later on with ioremap_exec()
>
>
Nice work.
With quick scan, looks like the series will work since
you have already taken care of SRAM is being ready before
SDRC has been initialised which was the only corner case
I was worried.
Will look at this series in next couple of days and do some testing.
Looks like you wanted to inlcude below patch also part of this
series though [PATCH 5/4] numbering is bit confusing.
[PATCH 5/4] ARM: OMAP: Move set_globals initialization to happen in
init_early
Regards
Santosh
^ permalink raw reply
* [RFC 2/5] ARM: OMAP: omap_device: add a method to set iommu private archdata
From: Ohad Ben-Cohen @ 2011-10-05 7:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <87mxdga4c0.fsf@ti.com>
On Tue, Oct 4, 2011 at 10:29 PM, Kevin Hilman <khilman@ti.com> wrote:
> tag. ?you're it.
Consider it done :)
> OK, as long as I have some confidence that this is going in the right
> direction (and having you on the job is a good sign!) ?I'm willing to
> merge something like this as an interim solution.
Thanks a lot!
Ohad.
^ permalink raw reply
* [PATCH v6 04/16] OMAP2+: UART: cleanup 8250 console driver support
From: Govindraj @ 2011-10-05 6:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <87lit077ry.fsf@ti.com>
Hi Kevin,
Thanks for the review,
On Wed, Oct 5, 2011 at 3:12 AM, Kevin Hilman <khilman@ti.com> wrote:
> "Govindraj.R" <govindraj.raja@ti.com> writes:
>
>> We had been using traditional 8250 driver as uart console driver
>> prior to omap-serial driver. Since we have omap-serial driver
>> in mainline kernel for some time now it has been used as default
>> uart console driver on omap2+ platforms. Remove 8250 support for
>> omap-uarts.
>
> Nice to see the this disappearing.
>
>> Serial_in and serial_out override for 8250 serial driver is also
>> removed.
>> Empty fifo read fix is already taken care with omap-serial
>> driver with data ready bit check from LSR reg before reading RX fifo.
>
> As stated in the previous review. ?Patches that move code/features
> should have the removal and the add-back in the same patch. ?Doing so
> makes it easy for reviewers to see whether it was simply moved, or if it
> was modified when it was moved, etc.
>
Empty fifo read is already taken care in omap-serial.c and is part of
mainline code.
Nothing to add to omap-serial.c
>> Also waiting for THRE(transmit hold reg empty) is done with wait_for_xmitr
>> in omap-serial driver.
>
> Again, remove it here in the patch that adds that support (the errata
> patch I guess.)
>
The errata patch ( [PATCH v6 11/16] ) moves only mdr_errata and force_idle
from serial.c to omap-serial.c.
Already handled stuffs and things that already exists with omap-serial.c
are removed here.
>> Remove headers that were necessary to support 8250 support
>> and remove all config bindings done to keep 8250 backward compatibility
>> while adding omap-serial driver. Remove omap_uart_reset needed for
>> 8250 autoconf.
>>
>> Signed-off-by: Govindraj.R <govindraj.raja@ti.com>
>
> So basically, this patch should only remove the legacy 8250 support (as
> the subject says) and everything else should be done in the other
> relevant patches.
>
Yes removes only the 8250 code. serial_in/serial_out were read/write overrides
part of 8250 code.
serial_in/serial_out had these checks for empty fifo read and wait for tx
which is already handled with omap-serial.c.
--
Thanks,
Govindraj.R
> Kevin
> --
> To unsubscribe from this list: send the line "unsubscribe linux-serial" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at ?http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply
* [PATCH 3/4] ARM: OMAP: Remove calls to SRAM allocations for framebuffer
From: Tomi Valkeinen @ 2011-10-05 6:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20111005004544.26980.35612.stgit@kaulin.local>
On Tue, 2011-10-04 at 17:45 -0700, Tony Lindgren wrote:
> This assumes fixed mappings which will not work once we move
> to use ioremap_exec(). It seems that these are currently
> not in use, or in use for some out of tree corner cases.
>
> If SRAM support for framebuffer is wanted, it should be done
> with ioremap in the driver.
>
> Note that further removal of the code can now be done,
> but that can be done seprately by the driver maintainers.
>
> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
> Signed-off-by: Tony Lindgren <tony@atomide.com>
Looks good to me. I have similar changes in my working branch for omapfb
cleanup.
Acked-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Tomi
^ permalink raw reply
* Please help with the OMAP static mapping mess
From: Santosh Shilimkar @ 2011-10-05 6:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.LFD.2.02.1110042232380.9106@xanadu.home>
On Wednesday 05 October 2011 08:09 AM, Nicolas Pitre wrote:
> On Tue, 4 Oct 2011, Rob Herring wrote:
>
>> On 10/04/2011 04:21 PM, Nicolas Pitre wrote:
>>> On Tue, 4 Oct 2011, Santosh Shilimkar wrote:
>>>
>>>> On Tuesday 04 October 2011 04:08 AM, Tony Lindgren wrote:
>>>>> * Nicolas Pitre <nico@fluxnic.net> [111003 14:36]:
>>>>>> On Mon, 3 Oct 2011, Tony Lindgren wrote:
>>>>>>
>>>>>>> Having the SRAM base address move around with different sizes also
>>>>>>> requires the SoC detection.. Otherwise we can end up mapping wrong
>>>>>>> size and end up trying to access secure SRAM that will hang the system.
>>>>>>>
>>>>>>> The way to fix it is to move SRAM init happen much later so we don't
>>>>>>> have to map it early. I guess now we could use ioremap for SRAM,
>>>>>>> although we may not want device attributes for the executable code?
>>>>>>> Got any suggestions here on how we should map SRAM later on?
>>>>>>
>>>>>> You can use a variant of ioremap() such as __arm_ioremap() which let you
>>>>>> specify the memory attribute.
>>>>>
>>>>> OK, I'll take a look at that.
>>>>>
>>>> I have tried __arm_ioremap_pfn() for some DDR mapping and it didn't
>>>> work as expected. The mapping was not getting created.
>>>
>>> Did you investigate why it wasn't created? Must have been a trivial
>>> issue surely? But you have to wait until memory management is fully
>>> initialized to call the real ioremap() though, which happens later
>>> during the boot.
>>>
I didn't investigate further on it but may be it was because of the
ordering as you pointed out. The new __arm_ioremap_exe() seems to me
a good idea and should solve the problem.
Regards
Santosh
^ permalink raw reply
* [PATCH 3/3] ARM: SAMSUNG: Add lookup of sdhci-s3c clocks using generic names
From: Rajeshwari Shinde @ 2011-10-05 5:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1317792669-19925-1-git-send-email-rajeshwari.s@samsung.com>
Add support for lookup of sdhci-s3c controller clocks using generic names
for s3c2416, s3c64xx, s5pc100, s5pv210 and exynos4 SoC's.
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
---
arch/arm/mach-exynos4/clock.c | 99 ++++++++++++++---------
arch/arm/mach-s3c2416/clock.c | 68 +++++++++-------
arch/arm/mach-s3c64xx/clock.c | 138 +++++++++++++++++++++-----------
arch/arm/mach-s5pc100/clock.c | 141 +++++++++++++++++++++------------
arch/arm/mach-s5pv210/clock.c | 177 ++++++++++++++++++++++++++---------------
5 files changed, 391 insertions(+), 232 deletions(-)
diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c
index d89b45e..3a7b206 100644
--- a/arch/arm/mach-exynos4/clock.c
+++ b/arch/arm/mach-exynos4/clock.c
@@ -1197,42 +1197,6 @@ static struct clksrc_clk clksrcs[] = {
.reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 },
}, {
.clk = {
- .name = "sclk_mmc",
- .devname = "exynos4-sdhci.0",
- .parent = &clk_dout_mmc0.clk,
- .enable = exynos4_clksrc_mask_fsys_ctrl,
- .ctrlbit = (1 << 0),
- },
- .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
- }, {
- .clk = {
- .name = "sclk_mmc",
- .devname = "exynos4-sdhci.1",
- .parent = &clk_dout_mmc1.clk,
- .enable = exynos4_clksrc_mask_fsys_ctrl,
- .ctrlbit = (1 << 4),
- },
- .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
- }, {
- .clk = {
- .name = "sclk_mmc",
- .devname = "exynos4-sdhci.2",
- .parent = &clk_dout_mmc2.clk,
- .enable = exynos4_clksrc_mask_fsys_ctrl,
- .ctrlbit = (1 << 8),
- },
- .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
- }, {
- .clk = {
- .name = "sclk_mmc",
- .devname = "exynos4-sdhci.3",
- .parent = &clk_dout_mmc3.clk,
- .enable = exynos4_clksrc_mask_fsys_ctrl,
- .ctrlbit = (1 << 12),
- },
- .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
- }, {
- .clk = {
.name = "sclk_dwmmc",
.parent = &clk_dout_mmc4.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl,
@@ -1242,6 +1206,57 @@ static struct clksrc_clk clksrcs[] = {
}
};
+static struct clksrc_clk clk_sclk_mmc0 = {
+ .clk = {
+ .name = "sclk_mmc",
+ .devname = "exynos4-sdhci.0",
+ .parent = &clk_dout_mmc0.clk,
+ .enable = exynos4_clksrc_mask_fsys_ctrl,
+ .ctrlbit = (1 << 0),
+ },
+ .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
+};
+
+static struct clksrc_clk clk_sclk_mmc1 = {
+ .clk = {
+ .name = "sclk_mmc",
+ .devname = "exynos4-sdhci.1",
+ .parent = &clk_dout_mmc1.clk,
+ .enable = exynos4_clksrc_mask_fsys_ctrl,
+ .ctrlbit = (1 << 4),
+ },
+ .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
+};
+
+static struct clksrc_clk clk_sclk_mmc2 = {
+ .clk = {
+ .name = "sclk_mmc",
+ .devname = "exynos4-sdhci.2",
+ .parent = &clk_dout_mmc2.clk,
+ .enable = exynos4_clksrc_mask_fsys_ctrl,
+ .ctrlbit = (1 << 8),
+ },
+ .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
+};
+
+static struct clksrc_clk clk_sclk_mmc3 = {
+ .clk = {
+ .name = "sclk_mmc",
+ .devname = "exynos4-sdhci.3",
+ .parent = &clk_dout_mmc3.clk,
+ .enable = exynos4_clksrc_mask_fsys_ctrl,
+ .ctrlbit = (1 << 12),
+ },
+ .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
+};
+
+static struct clksrc_clk *clksrc_cdev[] = {
+ &clk_sclk_mmc0,
+ &clk_sclk_mmc1,
+ &clk_sclk_mmc2,
+ &clk_sclk_mmc3,
+};
+
/* Clock initialization code */
static struct clksrc_clk *sysclks[] = {
&clk_mout_apll,
@@ -1276,6 +1291,13 @@ static struct clksrc_clk *sysclks[] = {
&clk_mout_mfc1,
};
+static struct clk_lookup exynos4_clk_lookup[] = {
+ CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
+ CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
+ CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
+ CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),
+};
+
static int xtal_rate;
static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
@@ -1484,13 +1506,16 @@ void __init exynos4_register_clocks(void)
s3c_register_clksrc(sclk_tv[ptr], 1);
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
- s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
+ for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
+ s3c_register_clksrc(clksrc_cdev[ptr], 1);
+ s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
register_syscore_ops(&exynos4_clock_syscore_ops);
s3c24xx_register_clock(&dummy_apb_pclk);
+ clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup));
s3c_pwmclk_init();
}
diff --git a/arch/arm/mach-s3c2416/clock.c b/arch/arm/mach-s3c2416/clock.c
index 72b7c62..cebaf3f 100644
--- a/arch/arm/mach-s3c2416/clock.c
+++ b/arch/arm/mach-s3c2416/clock.c
@@ -82,39 +82,38 @@ static struct clksrc_clk hsmmc_div[] = {
},
};
-static struct clksrc_clk hsmmc_mux[] = {
- [0] = {
- .clk = {
- .name = "hsmmc-if",
- .devname = "s3c-sdhci.0",
- .ctrlbit = (1 << 6),
- .enable = s3c2443_clkcon_enable_s,
- },
- .sources = &(struct clksrc_sources) {
- .nr_sources = 2,
- .sources = (struct clk *[]) {
- [0] = &hsmmc_div[0].clk,
- [1] = NULL, /* to fix */
- },
- },
- .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 16 },
+static struct clksrc_clk hsmmc_mux0 = {
+ .clk = {
+ .name = "hsmmc-if",
+ .devname = "s3c-sdhci.0",
+ .ctrlbit = (1 << 6),
+ .enable = s3c2443_clkcon_enable_s,
},
- [1] = {
- .clk = {
- .name = "hsmmc-if",
- .devname = "s3c-sdhci.1",
- .ctrlbit = (1 << 12),
- .enable = s3c2443_clkcon_enable_s,
+ .sources = &(struct clksrc_sources) {
+ .nr_sources = 2,
+ .sources = (struct clk * []) {
+ [0] = &hsmmc_div[0].clk,
+ [1] = NULL, /* to fix */
},
- .sources = &(struct clksrc_sources) {
- .nr_sources = 2,
- .sources = (struct clk *[]) {
- [0] = &hsmmc_div[1].clk,
- [1] = NULL, /* to fix */
- },
+ },
+ .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 16 },
+};
+
+static struct clksrc_clk hsmmc_mux1 = {
+ .clk = {
+ .name = "hsmmc-if",
+ .devname = "s3c-sdhci.1",
+ .ctrlbit = (1 << 12),
+ .enable = s3c2443_clkcon_enable_s,
+ },
+ .sources = &(struct clksrc_sources) {
+ .nr_sources = 2,
+ .sources = (struct clk * []) {
+ [0] = &hsmmc_div[1].clk,
+ [1] = NULL, /* to fix */
},
- .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 17 },
},
+ .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 17 },
};
static struct clk hsmmc0_clk = {
@@ -143,8 +142,14 @@ static struct clksrc_clk *clksrcs[] __initdata = {
&hsspi_mux,
&hsmmc_div[0],
&hsmmc_div[1],
- &hsmmc_mux[0],
- &hsmmc_mux[1],
+ &hsmmc_mux0,
+ &hsmmc_mux1,
+};
+
+static struct clk_lookup s3c2416_clk_lookup[] = {
+ CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &hsmmc0_clk),
+ CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &hsmmc_mux0.clk),
+ CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &hsmmc_mux1.clk),
};
void __init s3c2416_init_clocks(int xtal)
@@ -164,6 +169,7 @@ void __init s3c2416_init_clocks(int xtal)
s3c_register_clksrc(clksrcs[ptr], 1);
s3c24xx_register_clock(&hsmmc0_clk);
+ clkdev_add_table(s3c2416_clk_lookup, ARRAY_SIZE(s3c2416_clk_lookup));
s3c_pwmclk_init();
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index 39c238d..1fcaebf 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -243,24 +243,6 @@ static struct clk init_clocks[] = {
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_UHOST,
}, {
- .name = "hsmmc",
- .devname = "s3c-sdhci.0",
- .parent = &clk_h,
- .enable = s3c64xx_hclk_ctrl,
- .ctrlbit = S3C_CLKCON_HCLK_HSMMC0,
- }, {
- .name = "hsmmc",
- .devname = "s3c-sdhci.1",
- .parent = &clk_h,
- .enable = s3c64xx_hclk_ctrl,
- .ctrlbit = S3C_CLKCON_HCLK_HSMMC1,
- }, {
- .name = "hsmmc",
- .devname = "s3c-sdhci.2",
- .parent = &clk_h,
- .enable = s3c64xx_hclk_ctrl,
- .ctrlbit = S3C_CLKCON_HCLK_HSMMC2,
- }, {
.name = "otg",
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
@@ -310,6 +292,29 @@ static struct clk init_clocks[] = {
}
};
+static struct clk clk_hsmmc0 = {
+ .name = "hsmmc",
+ .devname = "s3c-sdhci.0",
+ .parent = &clk_h,
+ .enable = s3c64xx_hclk_ctrl,
+ .ctrlbit = S3C_CLKCON_HCLK_HSMMC0,
+};
+
+static struct clk clk_hsmmc1 = {
+ .name = "hsmmc",
+ .devname = "s3c-sdhci.1",
+ .parent = &clk_h,
+ .enable = s3c64xx_hclk_ctrl,
+ .ctrlbit = S3C_CLKCON_HCLK_HSMMC1,
+};
+
+static struct clk clk_hsmmc2 = {
+ .name = "hsmmc",
+ .devname = "s3c-sdhci.2",
+ .parent = &clk_h,
+ .enable = s3c64xx_hclk_ctrl,
+ .ctrlbit = S3C_CLKCON_HCLK_HSMMC2,
+};
static struct clk clk_fout_apll = {
.name = "fout_apll",
@@ -578,36 +583,6 @@ static struct clksrc_sources clkset_camif = {
static struct clksrc_clk clksrcs[] = {
{
.clk = {
- .name = "mmc_bus",
- .devname = "s3c-sdhci.0",
- .ctrlbit = S3C_CLKCON_SCLK_MMC0,
- .enable = s3c64xx_sclk_ctrl,
- },
- .reg_src = { .reg = S3C_CLK_SRC, .shift = 18, .size = 2 },
- .reg_div = { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4 },
- .sources = &clkset_spi_mmc,
- }, {
- .clk = {
- .name = "mmc_bus",
- .devname = "s3c-sdhci.1",
- .ctrlbit = S3C_CLKCON_SCLK_MMC1,
- .enable = s3c64xx_sclk_ctrl,
- },
- .reg_src = { .reg = S3C_CLK_SRC, .shift = 20, .size = 2 },
- .reg_div = { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4 },
- .sources = &clkset_spi_mmc,
- }, {
- .clk = {
- .name = "mmc_bus",
- .devname = "s3c-sdhci.2",
- .ctrlbit = S3C_CLKCON_SCLK_MMC2,
- .enable = s3c64xx_sclk_ctrl,
- },
- .reg_src = { .reg = S3C_CLK_SRC, .shift = 22, .size = 2 },
- .reg_div = { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4 },
- .sources = &clkset_spi_mmc,
- }, {
- .clk = {
.name = "usb-bus-host",
.ctrlbit = S3C_CLKCON_SCLK_UHOST,
.enable = s3c64xx_sclk_ctrl,
@@ -695,6 +670,63 @@ static struct clksrc_clk clksrcs[] = {
},
};
+static struct clksrc_clk clk_sclk_mmc0 = {
+ .clk = {
+ .name = "mmc_bus",
+ .devname = "s3c-sdhci.0",
+ .ctrlbit = S3C_CLKCON_SCLK_MMC0,
+ .enable = s3c64xx_sclk_ctrl,
+ },
+ .reg_src = { .reg = S3C_CLK_SRC, .shift = 18, .size = 2 },
+ .reg_div = { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4 },
+ .sources = &clkset_spi_mmc,
+};
+
+static struct clksrc_clk clk_sclk_mmc1 = {
+ .clk = {
+ .name = "mmc_bus",
+ .devname = "s3c-sdhci.1",
+ .ctrlbit = S3C_CLKCON_SCLK_MMC1,
+ .enable = s3c64xx_sclk_ctrl,
+ },
+ .reg_src = { .reg = S3C_CLK_SRC, .shift = 20, .size = 2 },
+ .reg_div = { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4 },
+ .sources = &clkset_spi_mmc,
+};
+
+static struct clksrc_clk clk_sclk_mmc2 = {
+ .clk = {
+ .name = "mmc_bus",
+ .devname = "s3c-sdhci.2",
+ .ctrlbit = S3C_CLKCON_SCLK_MMC2,
+ .enable = s3c64xx_sclk_ctrl,
+ },
+ .reg_src = { .reg = S3C_CLK_SRC, .shift = 22, .size = 2 },
+ .reg_div = { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4 },
+ .sources = &clkset_spi_mmc,
+};
+
+static struct clk *clk_cdev[] = {
+ &clk_hsmmc0,
+ &clk_hsmmc1,
+ &clk_hsmmc2,
+};
+
+static struct clksrc_clk *clksrc_cdev[] = {
+ &clk_sclk_mmc0,
+ &clk_sclk_mmc1,
+ &clk_sclk_mmc2,
+};
+
+static struct clk_lookup s3c64xx_clk_lookup[] = {
+ CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
+ CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
+ CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
+ CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
+ CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
+ CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
+};
+
/* Clock initialisation code */
static struct clksrc_clk *init_parents[] = {
@@ -811,17 +843,27 @@ static struct clk *clks[] __initdata = {
void __init s3c64xx_register_clocks(unsigned long xtal,
unsigned armclk_divlimit)
{
+ int ptr;
+
armclk_mask = armclk_divlimit;
s3c24xx_register_baseclocks(xtal);
s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
+ for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
+ s3c_register_clksrc(clksrc_cdev[ptr], 1);
+
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+ s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
+ for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
+ s3c_disable_clocks(clk_cdev[ptr], 1);
+
s3c24xx_register_clocks(clks1, ARRAY_SIZE(clks1));
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
+ clkdev_add_table(s3c64xx_clk_lookup, ARRAY_SIZE(s3c64xx_clk_lookup));
s3c_pwmclk_init();
}
diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c
index 8d47709..1ac421b 100644
--- a/arch/arm/mach-s5pc100/clock.c
+++ b/arch/arm/mach-s5pc100/clock.c
@@ -426,24 +426,6 @@ static struct clk init_clocks_off[] = {
.enable = s5pc100_d0_2_ctrl,
.ctrlbit = (1 << 1),
}, {
- .name = "hsmmc",
- .devname = "s3c-sdhci.2",
- .parent = &clk_div_d1_bus.clk,
- .enable = s5pc100_d1_0_ctrl,
- .ctrlbit = (1 << 7),
- }, {
- .name = "hsmmc",
- .devname = "s3c-sdhci.1",
- .parent = &clk_div_d1_bus.clk,
- .enable = s5pc100_d1_0_ctrl,
- .ctrlbit = (1 << 6),
- }, {
- .name = "hsmmc",
- .devname = "s3c-sdhci.0",
- .parent = &clk_div_d1_bus.clk,
- .enable = s5pc100_d1_0_ctrl,
- .ctrlbit = (1 << 5),
- }, {
.name = "modemif",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_0_ctrl,
@@ -711,6 +693,30 @@ static struct clk init_clocks_off[] = {
},
};
+static struct clk clk_hsmmc2 = {
+ .name = "hsmmc",
+ .devname = "s3c-sdhci.2",
+ .parent = &clk_div_d1_bus.clk,
+ .enable = s5pc100_d1_0_ctrl,
+ .ctrlbit = (1 << 7),
+};
+
+static struct clk clk_hsmmc1 = {
+ .name = "hsmmc",
+ .devname = "s3c-sdhci.1",
+ .parent = &clk_div_d1_bus.clk,
+ .enable = s5pc100_d1_0_ctrl,
+ .ctrlbit = (1 << 6),
+};
+
+static struct clk clk_hsmmc0 = {
+ .name = "hsmmc",
+ .devname = "s3c-sdhci.0",
+ .parent = &clk_div_d1_bus.clk,
+ .enable = s5pc100_d1_0_ctrl,
+ .ctrlbit = (1 << 5),
+};
+
static struct clk clk_vclk54m = {
.name = "vclk_54m",
.rate = 54000000,
@@ -1024,39 +1030,6 @@ static struct clksrc_clk clksrcs[] = {
.reg_div = { .reg = S5P_CLK_DIV3, .shift = 24, .size = 4 },
}, {
.clk = {
- .name = "sclk_mmc",
- .devname = "s3c-sdhci.0",
- .ctrlbit = (1 << 12),
- .enable = s5pc100_sclk1_ctrl,
-
- },
- .sources = &clk_src_mmc0,
- .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
- .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
- }, {
- .clk = {
- .name = "sclk_mmc",
- .devname = "s3c-sdhci.1",
- .ctrlbit = (1 << 13),
- .enable = s5pc100_sclk1_ctrl,
-
- },
- .sources = &clk_src_mmc12,
- .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
- .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
- }, {
- .clk = {
- .name = "sclk_mmc",
- .devname = "s3c-sdhci.2",
- .ctrlbit = (1 << 14),
- .enable = s5pc100_sclk1_ctrl,
-
- },
- .sources = &clk_src_mmc12,
- .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
- .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
- }, {
- .clk = {
.name = "sclk_irda",
.ctrlbit = (1 << 10),
.enable = s5pc100_sclk0_ctrl,
@@ -1098,6 +1071,63 @@ static struct clksrc_clk clksrcs[] = {
},
};
+static struct clksrc_clk clk_sclk_mmc0 = {
+ .clk = {
+ .name = "sclk_mmc",
+ .devname = "s3c-sdhci.0",
+ .ctrlbit = (1 << 12),
+ .enable = s5pc100_sclk1_ctrl,
+ },
+ .sources = &clk_src_mmc0,
+ .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
+ .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_mmc1 = {
+ .clk = {
+ .name = "sclk_mmc",
+ .devname = "s3c-sdhci.1",
+ .ctrlbit = (1 << 13),
+ .enable = s5pc100_sclk1_ctrl,
+ },
+ .sources = &clk_src_mmc12,
+ .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
+ .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_mmc2 = {
+ .clk = {
+ .name = "sclk_mmc",
+ .devname = "s3c-sdhci.2",
+ .ctrlbit = (1 << 14),
+ .enable = s5pc100_sclk1_ctrl,
+ },
+ .sources = &clk_src_mmc12,
+ .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
+ .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
+};
+
+static struct clk *clk_cdev[] = {
+ &clk_hsmmc0,
+ &clk_hsmmc1,
+ &clk_hsmmc2,
+};
+
+static struct clksrc_clk *clksrc_cdev[] = {
+ &clk_sclk_mmc0,
+ &clk_sclk_mmc1,
+ &clk_sclk_mmc2,
+};
+
+static struct clk_lookup s5pc100_clk_lookup[] = {
+ CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
+ CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
+ CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
+ CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
+ CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
+ CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
+};
+
/* Clock initialisation code */
static struct clksrc_clk *sysclks[] = {
&clk_mout_apll,
@@ -1276,12 +1306,19 @@ void __init s5pc100_register_clocks(void)
s3c_register_clksrc(sysclks[ptr], 1);
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
- s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
+ for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
+ s3c_register_clksrc(clksrc_cdev[ptr], 1);
+ s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+ s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
+ for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
+ s3c_disable_clocks(clk_cdev[ptr], 1);
+
s3c24xx_register_clock(&dummy_apb_pclk);
+ clkdev_add_table(s5pc100_clk_lookup, ARRAY_SIZE(s5pc100_clk_lookup));
s3c_pwmclk_init();
}
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index 4c5ac7a..d785279 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -399,30 +399,6 @@ static struct clk init_clocks_off[] = {
.enable = s5pv210_clk_ip1_ctrl,
.ctrlbit = (1<<25),
}, {
- .name = "hsmmc",
- .devname = "s3c-sdhci.0",
- .parent = &clk_hclk_psys.clk,
- .enable = s5pv210_clk_ip2_ctrl,
- .ctrlbit = (1<<16),
- }, {
- .name = "hsmmc",
- .devname = "s3c-sdhci.1",
- .parent = &clk_hclk_psys.clk,
- .enable = s5pv210_clk_ip2_ctrl,
- .ctrlbit = (1<<17),
- }, {
- .name = "hsmmc",
- .devname = "s3c-sdhci.2",
- .parent = &clk_hclk_psys.clk,
- .enable = s5pv210_clk_ip2_ctrl,
- .ctrlbit = (1<<18),
- }, {
- .name = "hsmmc",
- .devname = "s3c-sdhci.3",
- .parent = &clk_hclk_psys.clk,
- .enable = s5pv210_clk_ip2_ctrl,
- .ctrlbit = (1<<19),
- }, {
.name = "systimer",
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
@@ -559,6 +535,38 @@ static struct clk init_clocks[] = {
},
};
+static struct clk clk_hsmmc0 = {
+ .name = "hsmmc",
+ .devname = "s3c-sdhci.0",
+ .parent = &clk_hclk_psys.clk,
+ .enable = s5pv210_clk_ip2_ctrl,
+ .ctrlbit = (1<<16),
+};
+
+static struct clk clk_hsmmc1 = {
+ .name = "hsmmc",
+ .devname = "s3c-sdhci.1",
+ .parent = &clk_hclk_psys.clk,
+ .enable = s5pv210_clk_ip2_ctrl,
+ .ctrlbit = (1<<17),
+};
+
+static struct clk clk_hsmmc2 = {
+ .name = "hsmmc",
+ .devname = "s3c-sdhci.2",
+ .parent = &clk_hclk_psys.clk,
+ .enable = s5pv210_clk_ip2_ctrl,
+ .ctrlbit = (1<<18),
+};
+
+static struct clk clk_hsmmc3 = {
+ .name = "hsmmc",
+ .devname = "s3c-sdhci.3",
+ .parent = &clk_hclk_psys.clk,
+ .enable = s5pv210_clk_ip2_ctrl,
+ .ctrlbit = (1<<19),
+};
+
static struct clk *clkset_uart_list[] = {
[6] = &clk_mout_mpll.clk,
[7] = &clk_mout_epll.clk,
@@ -906,46 +914,6 @@ static struct clksrc_clk clksrcs[] = {
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 },
}, {
.clk = {
- .name = "sclk_mmc",
- .devname = "s3c-sdhci.0",
- .enable = s5pv210_clk_mask0_ctrl,
- .ctrlbit = (1 << 8),
- },
- .sources = &clkset_group2,
- .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
- .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 },
- }, {
- .clk = {
- .name = "sclk_mmc",
- .devname = "s3c-sdhci.1",
- .enable = s5pv210_clk_mask0_ctrl,
- .ctrlbit = (1 << 9),
- },
- .sources = &clkset_group2,
- .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
- .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 },
- }, {
- .clk = {
- .name = "sclk_mmc",
- .devname = "s3c-sdhci.2",
- .enable = s5pv210_clk_mask0_ctrl,
- .ctrlbit = (1 << 10),
- },
- .sources = &clkset_group2,
- .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
- .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 },
- }, {
- .clk = {
- .name = "sclk_mmc",
- .devname = "s3c-sdhci.3",
- .enable = s5pv210_clk_mask0_ctrl,
- .ctrlbit = (1 << 11),
- },
- .sources = &clkset_group2,
- .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
- .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
- }, {
- .clk = {
.name = "sclk_mfc",
.devname = "s5p-mfc",
.enable = s5pv210_clk_ip0_ctrl,
@@ -1022,6 +990,68 @@ static struct clksrc_clk clksrcs[] = {
},
};
+static struct clksrc_clk clk_sclk_mmc0 = {
+ .clk = {
+ .name = "sclk_mmc",
+ .devname = "s3c-sdhci.0",
+ .enable = s5pv210_clk_mask0_ctrl,
+ .ctrlbit = (1 << 8),
+ },
+ .sources = &clkset_group2,
+ .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
+ .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_mmc1 = {
+ .clk = {
+ .name = "sclk_mmc",
+ .devname = "s3c-sdhci.1",
+ .enable = s5pv210_clk_mask0_ctrl,
+ .ctrlbit = (1 << 9),
+ },
+ .sources = &clkset_group2,
+ .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
+ .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_mmc2 = {
+ .clk = {
+ .name = "sclk_mmc",
+ .devname = "s3c-sdhci.2",
+ .enable = s5pv210_clk_mask0_ctrl,
+ .ctrlbit = (1 << 10),
+ },
+ .sources = &clkset_group2,
+ .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
+ .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_mmc3 = {
+ .clk = {
+ .name = "sclk_mmc",
+ .devname = "s3c-sdhci.3",
+ .enable = s5pv210_clk_mask0_ctrl,
+ .ctrlbit = (1 << 11),
+ },
+ .sources = &clkset_group2,
+ .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
+ .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
+};
+
+static struct clk *clk_cdev[] = {
+ &clk_hsmmc0,
+ &clk_hsmmc1,
+ &clk_hsmmc2,
+ &clk_hsmmc3,
+};
+
+static struct clksrc_clk *clksrc_cdev[] = {
+ &clk_sclk_mmc0,
+ &clk_sclk_mmc1,
+ &clk_sclk_mmc2,
+ &clk_sclk_mmc3,
+};
+
/* Clock initialisation code */
static struct clksrc_clk *sysclks[] = {
&clk_mout_apll,
@@ -1045,6 +1075,17 @@ static struct clksrc_clk *sysclks[] = {
&clk_sclk_spdif,
};
+static struct clk_lookup s5pv210_clk_lookup[] = {
+ CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
+ CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
+ CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
+ CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.0", &clk_hsmmc3),
+ CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
+ CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
+ CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
+ CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),
+};
+
static u32 epll_div[][6] = {
{ 48000000, 0, 48, 3, 3, 0 },
{ 96000000, 0, 48, 3, 2, 0 },
@@ -1274,11 +1315,19 @@ void __init s5pv210_register_clocks(void)
s3c_register_clksrc(sclk_tv[ptr], 1);
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
+ for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
+ s3c_register_clksrc(clksrc_cdev[ptr], 1);
+
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+ s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
+ for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
+ s3c_disable_clocks(clk_cdev[ptr], 1);
+
+ clkdev_add_table(s5pv210_clk_lookup, ARRAY_SIZE(s5pv210_clk_lookup));
s3c24xx_register_clock(&dummy_apb_pclk);
s3c_pwmclk_init();
}
--
1.6.6.rc2
^ permalink raw reply related
* [PATCH 2/3] ARM: SAMSUNG: Remove SDHCI bus clocks from platform data
From: Rajeshwari Shinde @ 2011-10-05 5:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1317792669-19925-1-git-send-email-rajeshwari.s@samsung.com>
The bus clocks previously sent through platform data to SDHCI controller
are removed.
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
---
arch/arm/mach-exynos4/Makefile | 1 -
arch/arm/mach-exynos4/setup-sdhci.c | 22 -------------------
arch/arm/mach-s3c2416/Makefile | 1 -
arch/arm/mach-s3c2416/setup-sdhci.c | 24 ---------------------
arch/arm/mach-s3c64xx/Makefile | 1 -
arch/arm/mach-s3c64xx/setup-sdhci.c | 24 ---------------------
arch/arm/mach-s5pc100/Makefile | 1 -
arch/arm/mach-s5pc100/setup-sdhci.c | 23 --------------------
arch/arm/mach-s5pv210/Makefile | 1 -
arch/arm/mach-s5pv210/setup-sdhci.c | 22 -------------------
arch/arm/plat-samsung/include/plat/sdhci.h | 31 ----------------------------
11 files changed, 0 insertions(+), 151 deletions(-)
delete mode 100644 arch/arm/mach-exynos4/setup-sdhci.c
delete mode 100644 arch/arm/mach-s3c2416/setup-sdhci.c
delete mode 100644 arch/arm/mach-s3c64xx/setup-sdhci.c
delete mode 100644 arch/arm/mach-s5pc100/setup-sdhci.c
delete mode 100644 arch/arm/mach-s5pv210/setup-sdhci.c
diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile
index e19cd12..c18531f 100644
--- a/arch/arm/mach-exynos4/Makefile
+++ b/arch/arm/mach-exynos4/Makefile
@@ -54,7 +54,6 @@ obj-$(CONFIG_EXYNOS4_SETUP_I2C5) += setup-i2c5.o
obj-$(CONFIG_EXYNOS4_SETUP_I2C6) += setup-i2c6.o
obj-$(CONFIG_EXYNOS4_SETUP_I2C7) += setup-i2c7.o
obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD) += setup-keypad.o
-obj-$(CONFIG_EXYNOS4_SETUP_SDHCI) += setup-sdhci.o
obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
obj-$(CONFIG_EXYNOS4_SETUP_USB_PHY) += setup-usb-phy.o
diff --git a/arch/arm/mach-exynos4/setup-sdhci.c b/arch/arm/mach-exynos4/setup-sdhci.c
deleted file mode 100644
index 92937b4..0000000
--- a/arch/arm/mach-exynos4/setup-sdhci.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/* linux/arch/arm/mach-exynos4/setup-sdhci.c
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- * http://www.samsung.com
- *
- * EXYNOS4 - Helper functions for settign up SDHCI device(s) (HSMMC)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/types.h>
-
-/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
-
-char *exynos4_hsmmc_clksrcs[4] = {
- [0] = NULL,
- [1] = NULL,
- [2] = "sclk_mmc", /* mmc_bus */
- [3] = NULL,
-};
diff --git a/arch/arm/mach-s3c2416/Makefile b/arch/arm/mach-s3c2416/Makefile
index 7b805b2..ca0cd22 100644
--- a/arch/arm/mach-s3c2416/Makefile
+++ b/arch/arm/mach-s3c2416/Makefile
@@ -15,7 +15,6 @@ obj-$(CONFIG_S3C2416_PM) += pm.o
#obj-$(CONFIG_S3C2416_DMA) += dma.o
# Device setup
-obj-$(CONFIG_S3C2416_SETUP_SDHCI) += setup-sdhci.o
obj-$(CONFIG_S3C2416_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
# Machine support
diff --git a/arch/arm/mach-s3c2416/setup-sdhci.c b/arch/arm/mach-s3c2416/setup-sdhci.c
deleted file mode 100644
index cee5395..0000000
--- a/arch/arm/mach-s3c2416/setup-sdhci.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/* linux/arch/arm/mach-s3c2416/setup-sdhci.c
- *
- * Copyright 2010 Promwad Innovation Company
- * Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
- *
- * S3C2416 - Helper functions for settign up SDHCI device(s) (HSMMC)
- *
- * Based on mach-s3c64xx/setup-sdhci.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/types.h>
-
-/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
-
-char *s3c2416_hsmmc_clksrcs[4] = {
- [0] = "hsmmc",
- [1] = "hsmmc",
- [2] = "hsmmc-if",
- /* [3] = "48m", - note not successfully used yet */
-};
diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile
index 902ab9a..94de24b 100644
--- a/arch/arm/mach-s3c64xx/Makefile
+++ b/arch/arm/mach-s3c64xx/Makefile
@@ -32,7 +32,6 @@ obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o
obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o
obj-$(CONFIG_S3C64XX_SETUP_IDE) += setup-ide.o
obj-$(CONFIG_S3C64XX_SETUP_KEYPAD) += setup-keypad.o
-obj-$(CONFIG_S3C64XX_SETUP_SDHCI) += setup-sdhci.o
obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp.o
obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
diff --git a/arch/arm/mach-s3c64xx/setup-sdhci.c b/arch/arm/mach-s3c64xx/setup-sdhci.c
deleted file mode 100644
index c75a71b..0000000
--- a/arch/arm/mach-s3c64xx/setup-sdhci.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/* linux/arch/arm/mach-s3c64xx/setup-sdhci.c
- *
- * Copyright 2008 Simtec Electronics
- * Copyright 2008 Simtec Electronics
- * Ben Dooks <ben@simtec.co.uk>
- * http://armlinux.simtec.co.uk/
- *
- * S3C6400/S3C6410 - Helper functions for settign up SDHCI device(s) (HSMMC)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/types.h>
-
-/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
-
-char *s3c64xx_hsmmc_clksrcs[4] = {
- [0] = "hsmmc",
- [1] = "hsmmc",
- [2] = "mmc_bus",
- /* [3] = "48m", - note not successfully used yet */
-};
diff --git a/arch/arm/mach-s5pc100/Makefile b/arch/arm/mach-s5pc100/Makefile
index a5e6e60..2320e54 100644
--- a/arch/arm/mach-s5pc100/Makefile
+++ b/arch/arm/mach-s5pc100/Makefile
@@ -21,7 +21,6 @@ obj-$(CONFIG_S5PC100_SETUP_FB_24BPP) += setup-fb-24bpp.o
obj-$(CONFIG_S5PC100_SETUP_I2C1) += setup-i2c1.o
obj-$(CONFIG_S5PC100_SETUP_IDE) += setup-ide.o
obj-$(CONFIG_S5PC100_SETUP_KEYPAD) += setup-keypad.o
-obj-$(CONFIG_S5PC100_SETUP_SDHCI) += setup-sdhci.o
obj-$(CONFIG_S5PC100_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
# device support
diff --git a/arch/arm/mach-s5pc100/setup-sdhci.c b/arch/arm/mach-s5pc100/setup-sdhci.c
deleted file mode 100644
index 6418c6e..0000000
--- a/arch/arm/mach-s5pc100/setup-sdhci.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/* linux/arch/arm/mach-s5pc100/setup-sdhci.c
- *
- * Copyright 2008 Samsung Electronics
- *
- * S5PC100 - Helper functions for settign up SDHCI device(s) (HSMMC)
- *
- * Based on mach-s3c6410/setup-sdhci.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/types.h>
-
-/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
-
-char *s5pc100_hsmmc_clksrcs[4] = {
- [0] = "hsmmc", /* HCLK */
- /* [1] = "hsmmc", - duplicate HCLK entry */
- [2] = "sclk_mmc", /* mmc_bus */
- /* [3] = "48m", - note not successfully used yet */
-};
diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile
index ef7e466..bb5f438 100644
--- a/arch/arm/mach-s5pv210/Makefile
+++ b/arch/arm/mach-s5pv210/Makefile
@@ -35,5 +35,4 @@ obj-$(CONFIG_S5PV210_SETUP_I2C1) += setup-i2c1.o
obj-$(CONFIG_S5PV210_SETUP_I2C2) += setup-i2c2.o
obj-$(CONFIG_S5PV210_SETUP_IDE) += setup-ide.o
obj-$(CONFIG_S5PV210_SETUP_KEYPAD) += setup-keypad.o
-obj-$(CONFIG_S5PV210_SETUP_SDHCI) += setup-sdhci.o
obj-$(CONFIG_S5PV210_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
diff --git a/arch/arm/mach-s5pv210/setup-sdhci.c b/arch/arm/mach-s5pv210/setup-sdhci.c
deleted file mode 100644
index 6b8ccc4..0000000
--- a/arch/arm/mach-s5pv210/setup-sdhci.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/* linux/arch/arm/mach-s5pv210/setup-sdhci.c
- *
- * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
- * http://www.samsung.com/
- *
- * S5PV210 - Helper functions for settign up SDHCI device(s) (HSMMC)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/types.h>
-
-/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
-
-char *s5pv210_hsmmc_clksrcs[4] = {
- [0] = "hsmmc", /* HCLK */
- /* [1] = "hsmmc", - duplicate HCLK entry */
- [2] = "sclk_mmc", /* mmc_bus */
- /* [3] = NULL, - reserved */
-};
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
index 39a70ec..12f962d 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -61,8 +61,6 @@ struct s3c_sdhci_platdata {
unsigned int host_caps;
enum cd_types cd_type;
- char **clocks; /* set of clock sources */
-
int ext_cd_gpio;
bool ext_cd_gpio_invert;
int (*ext_cd_init)(void (*notify_func)(struct platform_device *,
@@ -124,12 +122,9 @@ extern void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *, int w);
/* S3C2416 SDHCI setup */
#ifdef CONFIG_S3C2416_SETUP_SDHCI
-extern char *s3c2416_hsmmc_clksrcs[4];
-
static inline void s3c2416_default_sdhci0(void)
{
#ifdef CONFIG_S3C_DEV_HSMMC
- s3c_hsmmc0_def_platdata.clocks = s3c2416_hsmmc_clksrcs;
s3c_hsmmc0_def_platdata.cfg_gpio = s3c2416_setup_sdhci0_cfg_gpio;
#endif /* CONFIG_S3C_DEV_HSMMC */
}
@@ -137,7 +132,6 @@ static inline void s3c2416_default_sdhci0(void)
static inline void s3c2416_default_sdhci1(void)
{
#ifdef CONFIG_S3C_DEV_HSMMC1
- s3c_hsmmc1_def_platdata.clocks = s3c2416_hsmmc_clksrcs;
s3c_hsmmc1_def_platdata.cfg_gpio = s3c2416_setup_sdhci1_cfg_gpio;
#endif /* CONFIG_S3C_DEV_HSMMC1 */
}
@@ -150,12 +144,9 @@ static inline void s3c2416_default_sdhci1(void) { }
/* S3C64XX SDHCI setup */
#ifdef CONFIG_S3C64XX_SETUP_SDHCI
-extern char *s3c64xx_hsmmc_clksrcs[4];
-
static inline void s3c6400_default_sdhci0(void)
{
#ifdef CONFIG_S3C_DEV_HSMMC
- s3c_hsmmc0_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio;
#endif
}
@@ -163,7 +154,6 @@ static inline void s3c6400_default_sdhci0(void)
static inline void s3c6400_default_sdhci1(void)
{
#ifdef CONFIG_S3C_DEV_HSMMC1
- s3c_hsmmc1_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio;
#endif
}
@@ -171,7 +161,6 @@ static inline void s3c6400_default_sdhci1(void)
static inline void s3c6400_default_sdhci2(void)
{
#ifdef CONFIG_S3C_DEV_HSMMC2
- s3c_hsmmc2_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio;
#endif
}
@@ -179,7 +168,6 @@ static inline void s3c6400_default_sdhci2(void)
static inline void s3c6410_default_sdhci0(void)
{
#ifdef CONFIG_S3C_DEV_HSMMC
- s3c_hsmmc0_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio;
#endif
}
@@ -187,7 +175,6 @@ static inline void s3c6410_default_sdhci0(void)
static inline void s3c6410_default_sdhci1(void)
{
#ifdef CONFIG_S3C_DEV_HSMMC1
- s3c_hsmmc1_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio;
#endif
}
@@ -195,7 +182,6 @@ static inline void s3c6410_default_sdhci1(void)
static inline void s3c6410_default_sdhci2(void)
{
#ifdef CONFIG_S3C_DEV_HSMMC2
- s3c_hsmmc2_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio;
#endif
}
@@ -213,12 +199,9 @@ static inline void s3c6400_default_sdhci2(void) { }
/* S5PC100 SDHCI setup */
#ifdef CONFIG_S5PC100_SETUP_SDHCI
-extern char *s5pc100_hsmmc_clksrcs[4];
-
static inline void s5pc100_default_sdhci0(void)
{
#ifdef CONFIG_S3C_DEV_HSMMC
- s3c_hsmmc0_def_platdata.clocks = s5pc100_hsmmc_clksrcs;
s3c_hsmmc0_def_platdata.cfg_gpio = s5pc100_setup_sdhci0_cfg_gpio;
#endif
}
@@ -226,7 +209,6 @@ static inline void s5pc100_default_sdhci0(void)
static inline void s5pc100_default_sdhci1(void)
{
#ifdef CONFIG_S3C_DEV_HSMMC1
- s3c_hsmmc1_def_platdata.clocks = s5pc100_hsmmc_clksrcs;
s3c_hsmmc1_def_platdata.cfg_gpio = s5pc100_setup_sdhci1_cfg_gpio;
#endif
}
@@ -234,7 +216,6 @@ static inline void s5pc100_default_sdhci1(void)
static inline void s5pc100_default_sdhci2(void)
{
#ifdef CONFIG_S3C_DEV_HSMMC2
- s3c_hsmmc2_def_platdata.clocks = s5pc100_hsmmc_clksrcs;
s3c_hsmmc2_def_platdata.cfg_gpio = s5pc100_setup_sdhci2_cfg_gpio;
#endif
}
@@ -249,12 +230,9 @@ static inline void s5pc100_default_sdhci2(void) { }
/* S5PV210 SDHCI setup */
#ifdef CONFIG_S5PV210_SETUP_SDHCI
-extern char *s5pv210_hsmmc_clksrcs[4];
-
static inline void s5pv210_default_sdhci0(void)
{
#ifdef CONFIG_S3C_DEV_HSMMC
- s3c_hsmmc0_def_platdata.clocks = s5pv210_hsmmc_clksrcs;
s3c_hsmmc0_def_platdata.cfg_gpio = s5pv210_setup_sdhci0_cfg_gpio;
#endif
}
@@ -262,7 +240,6 @@ static inline void s5pv210_default_sdhci0(void)
static inline void s5pv210_default_sdhci1(void)
{
#ifdef CONFIG_S3C_DEV_HSMMC1
- s3c_hsmmc1_def_platdata.clocks = s5pv210_hsmmc_clksrcs;
s3c_hsmmc1_def_platdata.cfg_gpio = s5pv210_setup_sdhci1_cfg_gpio;
#endif
}
@@ -270,7 +247,6 @@ static inline void s5pv210_default_sdhci1(void)
static inline void s5pv210_default_sdhci2(void)
{
#ifdef CONFIG_S3C_DEV_HSMMC2
- s3c_hsmmc2_def_platdata.clocks = s5pv210_hsmmc_clksrcs;
s3c_hsmmc2_def_platdata.cfg_gpio = s5pv210_setup_sdhci2_cfg_gpio;
#endif
}
@@ -278,7 +254,6 @@ static inline void s5pv210_default_sdhci2(void)
static inline void s5pv210_default_sdhci3(void)
{
#ifdef CONFIG_S3C_DEV_HSMMC3
- s3c_hsmmc3_def_platdata.clocks = s5pv210_hsmmc_clksrcs;
s3c_hsmmc3_def_platdata.cfg_gpio = s5pv210_setup_sdhci3_cfg_gpio;
#endif
}
@@ -293,12 +268,9 @@ static inline void s5pv210_default_sdhci3(void) { }
/* EXYNOS4 SDHCI setup */
#ifdef CONFIG_EXYNOS4_SETUP_SDHCI
-extern char *exynos4_hsmmc_clksrcs[4];
-
static inline void exynos4_default_sdhci0(void)
{
#ifdef CONFIG_S3C_DEV_HSMMC
- s3c_hsmmc0_def_platdata.clocks = exynos4_hsmmc_clksrcs;
s3c_hsmmc0_def_platdata.cfg_gpio = exynos4_setup_sdhci0_cfg_gpio;
#endif
}
@@ -306,7 +278,6 @@ static inline void exynos4_default_sdhci0(void)
static inline void exynos4_default_sdhci1(void)
{
#ifdef CONFIG_S3C_DEV_HSMMC1
- s3c_hsmmc1_def_platdata.clocks = exynos4_hsmmc_clksrcs;
s3c_hsmmc1_def_platdata.cfg_gpio = exynos4_setup_sdhci1_cfg_gpio;
#endif
}
@@ -314,7 +285,6 @@ static inline void exynos4_default_sdhci1(void)
static inline void exynos4_default_sdhci2(void)
{
#ifdef CONFIG_S3C_DEV_HSMMC2
- s3c_hsmmc2_def_platdata.clocks = exynos4_hsmmc_clksrcs;
s3c_hsmmc2_def_platdata.cfg_gpio = exynos4_setup_sdhci2_cfg_gpio;
#endif
}
@@ -322,7 +292,6 @@ static inline void exynos4_default_sdhci2(void)
static inline void exynos4_default_sdhci3(void)
{
#ifdef CONFIG_S3C_DEV_HSMMC3
- s3c_hsmmc3_def_platdata.clocks = exynos4_hsmmc_clksrcs;
s3c_hsmmc3_def_platdata.cfg_gpio = exynos4_setup_sdhci3_cfg_gpio;
#endif
}
--
1.6.6.rc2
^ permalink raw reply related
* [PATCH 1/3] SDHCI: S3C: Use generic clock names for sdhci bus clock options
From: Rajeshwari Shinde @ 2011-10-05 5:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1317792669-19925-1-git-send-email-rajeshwari.s@samsung.com>
This patch modifies the driver to stop depending on the clock names
being passed from the platform and switch over to bus clock lookup
using generic clock names.
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
---
drivers/mmc/host/sdhci-s3c.c | 6 ++----
1 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
index b29e734..871cf4f 100644
--- a/drivers/mmc/host/sdhci-s3c.c
+++ b/drivers/mmc/host/sdhci-s3c.c
@@ -477,14 +477,12 @@ static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
struct clk *clk;
- char *name = pdata->clocks[ptr];
+ char name[14];
- if (name == NULL)
- continue;
+ sprintf(name, "mmc_busclk.%d", ptr);
clk = clk_get(dev, name);
if (IS_ERR(clk)) {
- dev_err(dev, "failed to get clock %s\n", name);
continue;
}
--
1.6.6.rc2
^ permalink raw reply related
* [PATCH 0/3] ARM: SAMSUNG: Add support for sdhci clock lookup using generic names
From: Rajeshwari Shinde @ 2011-10-05 5:31 UTC (permalink / raw)
To: linux-arm-kernel
This patchset adds support for sdhci controller clock lookup using
generic names. With this patchset, there will be no need to pass clock
names in sdhci platform data.
This patchset depends on two other patchsets:
mmc: sdhci-s3c: Remove 'clk_type' member from platform data
Add a common macro for creating struct clk_lookup entries
Rajeshwari Shinde (3):
SDHCI: S3C: Use generic clock names for sdhci bus clock options
ARM: SAMSUNG: Remove SDHCI bus clocks from platform data
ARM: SAMSUNG: Add lookup of sdhci-s3c clocks using generic names
arch/arm/mach-exynos4/Makefile | 1 -
arch/arm/mach-exynos4/clock.c | 99 ++++++++++------
arch/arm/mach-exynos4/setup-sdhci.c | 22 ----
arch/arm/mach-s3c2416/Makefile | 1 -
arch/arm/mach-s3c2416/clock.c | 68 ++++++-----
arch/arm/mach-s3c2416/setup-sdhci.c | 24 ----
arch/arm/mach-s3c64xx/Makefile | 1 -
arch/arm/mach-s3c64xx/clock.c | 138 ++++++++++++++--------
arch/arm/mach-s3c64xx/setup-sdhci.c | 24 ----
arch/arm/mach-s5pc100/Makefile | 1 -
arch/arm/mach-s5pc100/clock.c | 141 ++++++++++++++--------
arch/arm/mach-s5pc100/setup-sdhci.c | 23 ----
arch/arm/mach-s5pv210/Makefile | 1 -
arch/arm/mach-s5pv210/clock.c | 177 ++++++++++++++++++----------
arch/arm/mach-s5pv210/setup-sdhci.c | 22 ----
arch/arm/plat-samsung/include/plat/sdhci.h | 31 -----
drivers/mmc/host/sdhci-s3c.c | 6 +-
17 files changed, 393 insertions(+), 387 deletions(-)
delete mode 100644 arch/arm/mach-exynos4/setup-sdhci.c
delete mode 100644 arch/arm/mach-s3c2416/setup-sdhci.c
delete mode 100644 arch/arm/mach-s3c64xx/setup-sdhci.c
delete mode 100644 arch/arm/mach-s5pc100/setup-sdhci.c
delete mode 100644 arch/arm/mach-s5pv210/setup-sdhci.c
^ permalink raw reply
* [PATCH 1/4] ARM: OMAP3 PM: Fix IO Daisychain sequence
From: Vishwanath Sripathy @ 2011-10-05 4:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <87r52s8owb.fsf@ti.com>
> -----Original Message-----
> From: Kevin Hilman [mailto:khilman at ti.com]
> Sent: Wednesday, October 05, 2011 2:18 AM
> To: Vishwanath BS
> Cc: linux-omap at vger.kernel.org; linux-arm-
> kernel at lists.infradead.org; mohanv at ti.com
> Subject: Re: [PATCH 1/4] ARM: OMAP3 PM: Fix IO Daisychain sequence
>
> Hi Vishwa,
>
> Vishwanath BS <vishwanath.bs@ti.com> writes:
>
> > As per OMAP3630 TRM Section 3.5.7.2.2, the right sequence for
> enabling IO Daisy
> > chain is "The I/O wake-up scheme is enabled by triggering the I/O
> daisy chain
> > control (Wu clock) by programming a dedicated register
> > (PRCM.PM_WKEN_WKUP[16] EN_IO_CHAIN) in the PRCM module.Software
> must wait for
> > the I/O daisy chain to complete before it transitions the PER
> domain to a
> > nonfunctional state. This is done by polling a dedicated status
> bit in the PRCM
> > module (PRCM.PM_WKST_WKUP[16] ST_IO_CHAIN). This status bit must
> be cleared by
> > software when the bit is read to 1".
> >
> > The original code was polling on a wrong register which is fixed
> in this patch.
> > Also omap3_enable_io_chain is made non static as it's going to be
> used in
> > subsequent patches.
> >
> > Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com>
>
> A fix for this was posted[1] by Mohan V (added to Cc) back in June.
> It
> recieved a few minor comments but an updated version was never
> posted.
>
> Maybe you can ping Mohan or update that version fixing the comments
> mentioned in that thread.
OK. I will update the original patchset from Mohan with your comments and
repost.
Vishwa
>
> Thanks,
>
> Kevin
>
> [1] http://marc.info/?l=linux-omap&w=2&r=1&s=%27Mohan+V%27&q=b
^ permalink raw reply
* "dma-mapping: fix for speculative prefetching" patch for 2.6.31.2
From: 吳信賢 @ 2011-10-05 3:40 UTC (permalink / raw)
To: linux-arm-kernel
Dear experts,
I am implementing USB and SD drivers with kernel 2.6.31.2 on
ARM1176jzf-s (ARMv6 with speculative execution), and also encountered
the cache coherence issue. I found this patch "dma-mapping: fix for
speculative prefetching" on kerneltrap.org, but It seems cannot be
applied on kernel 2.6.31.2.
So, I am looking for a patch for earlier version kernel, and found two
patches which are probably able to be applied on kernel 2.6.31.2.
One is for Cortex A9 posted in this mail list:
http://lists.arm.linux.org.uk/lurker/message/20091031.172415.7712b229.en.html
The other is similar but less modification:
http://lists.infradead.org/pipermail/linux-arm-kernel/2009-October/003163.html
Does the two patches can work fine with kernel 2.6.31.2 on ARM1176jzf-s?
Moreover, I am wondering why to remove the following code section.
Will there be any side effect I should notice or handle?
diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S
index 295e25d..d1dfd87 100644
--- a/arch/arm/mm/cache-v6.S
+++ b/arch/arm/mm/cache-v6.S
@@ -195,20 +195,7 @@ ENTRY(v6_flush_kern_dcache_page)
* - end - virtual end address of region
*/
ENTRY(v6_dma_inv_range)
- tst r0, #D_CACHE_LINE_SIZE - 1
bic r0, r0, #D_CACHE_LINE_SIZE - 1
-#ifdef HARVARD_CACHE
- mcrne p15, 0, r0, c7, c10, 1 @ clean D line
-#else
- mcrne p15, 0, r0, c7, c11, 1 @ clean unified line
-#endif
- tst r1, #D_CACHE_LINE_SIZE - 1
- bic r1, r1, #D_CACHE_LINE_SIZE - 1
-#ifdef HARVARD_CACHE
- mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D line
-#else
- mcrne p15, 0, r1, c7, c15, 1 @ clean & invalidate unified line
-#endif
1:
#ifdef HARVARD_CACHE
mcr p15, 0, r0, c7, c6, 1 @ invalidate D line
^ permalink raw reply related
* [PATCH v2] irq: support domains with non-zero hwirq base
From: Rob Herring @ 2011-10-05 2:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20111004233953.GE3009@ponder.secretlab.ca>
From: Rob Herring <rob.herring@calxeda.com>
Interrupt controllers can have non-zero starting value for h/w irq numbers.
Adding support in irq_domain allows the domain hwirq numbering to match
the interrupt controllers' numbering.
As this makes looping over irqs for a domain more complicated, add loop
iterators to iterate over all hwirqs and irqs for a domain.
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Cc: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
---
Thomas,
Please ack. I'm dependent on this for adding Calxeda highbank support, so
I'd like to take this thru arm-soc tree.
v2:
- Rebase to tglx's changes in my previous irq domain commit:
irq: Fix check for already initialized irq_domain in irq_domain_add
- drop NO_IRQ and add WARN_ON in irq_domain_to_irq
Rob
include/linux/irqdomain.h | 16 +++++++++++++++-
kernel/irq/irqdomain.c | 12 ++++++------
2 files changed, 21 insertions(+), 7 deletions(-)
diff --git a/include/linux/irqdomain.h b/include/linux/irqdomain.h
index 3ad553e..99834e58 100644
--- a/include/linux/irqdomain.h
+++ b/include/linux/irqdomain.h
@@ -47,6 +47,7 @@ struct irq_domain_ops {
* of the irq_domain is responsible for allocating the array of
* irq_desc structures.
* @nr_irq: Number of irqs managed by the irq domain
+ * @hwirq_base: Starting number for hwirqs managed by the irq domain
* @ops: pointer to irq_domain methods
* @priv: private data pointer for use by owner. Not touched by irq_domain
* core code.
@@ -57,6 +58,7 @@ struct irq_domain {
struct list_head list;
unsigned int irq_base;
unsigned int nr_irq;
+ unsigned int hwirq_base;
const struct irq_domain_ops *ops;
void *priv;
struct device_node *of_node;
@@ -72,9 +74,21 @@ struct irq_domain {
static inline unsigned int irq_domain_to_irq(struct irq_domain *d,
unsigned long hwirq)
{
- return d->ops->to_irq ? d->ops->to_irq(d, hwirq) : d->irq_base + hwirq;
+ if (d->ops->to_irq)
+ return d->ops->to_irq(d, hwirq);
+ if (WARN_ON(hwirq < d->hwirq_base))
+ return 0;
+ return d->irq_base + hwirq - d->hwirq_base;
}
+#define irq_domain_for_each_hwirq(d, hw) \
+ for (hw = d->hwirq_base; hw < d->hwirq_base + d->nr_irq; hw++)
+
+#define irq_domain_for_each_irq(d, hw, irq) \
+ for (hw = d->hwirq_base, irq = irq_domain_to_irq(d, hw); \
+ hw < d->hwirq_base + d->nr_irq; \
+ hw++, irq = irq_domain_to_irq(d, hw))
+
extern void irq_domain_add(struct irq_domain *domain);
extern void irq_domain_del(struct irq_domain *domain);
#endif /* CONFIG_IRQ_DOMAIN */
diff --git a/kernel/irq/irqdomain.c b/kernel/irq/irqdomain.c
index b57a377..200ce83 100644
--- a/kernel/irq/irqdomain.c
+++ b/kernel/irq/irqdomain.c
@@ -20,15 +20,15 @@ static DEFINE_MUTEX(irq_domain_mutex);
void irq_domain_add(struct irq_domain *domain)
{
struct irq_data *d;
- int hwirq;
+ int hwirq, irq;
/*
* This assumes that the irq_domain owner has already allocated
* the irq_descs. This block will be removed when support for dynamic
* allocation of irq_descs is added to irq_domain.
*/
- for (hwirq = 0; hwirq < domain->nr_irq; hwirq++) {
- d = irq_get_irq_data(irq_domain_to_irq(domain, hwirq));
+ irq_domain_for_each_irq(domain, hwirq, irq) {
+ d = irq_get_irq_data(irq);
if (!d) {
WARN(1, "error: assigning domain to non existant irq_desc");
return;
@@ -54,15 +54,15 @@ void irq_domain_add(struct irq_domain *domain)
void irq_domain_del(struct irq_domain *domain)
{
struct irq_data *d;
- int hwirq;
+ int hwirq, irq;
mutex_lock(&irq_domain_mutex);
list_del(&domain->list);
mutex_unlock(&irq_domain_mutex);
/* Clear the irq_domain assignments */
- for (hwirq = 0; hwirq < domain->nr_irq; hwirq++) {
- d = irq_get_irq_data(irq_domain_to_irq(domain, hwirq));
+ irq_domain_for_each_irq(domain, hwirq, irq) {
+ d = irq_get_irq_data(irq);
d->domain = NULL;
}
}
--
1.7.5.4
^ permalink raw reply related
* Please help with the OMAP static mapping mess
From: Nicolas Pitre @ 2011-10-05 2:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4E8BBC6B.7000500@gmail.com>
On Tue, 4 Oct 2011, Rob Herring wrote:
> On 10/04/2011 04:21 PM, Nicolas Pitre wrote:
> > On Tue, 4 Oct 2011, Santosh Shilimkar wrote:
> >
> >> On Tuesday 04 October 2011 04:08 AM, Tony Lindgren wrote:
> >>> * Nicolas Pitre <nico@fluxnic.net> [111003 14:36]:
> >>>> On Mon, 3 Oct 2011, Tony Lindgren wrote:
> >>>>
> >>>>> Having the SRAM base address move around with different sizes also
> >>>>> requires the SoC detection.. Otherwise we can end up mapping wrong
> >>>>> size and end up trying to access secure SRAM that will hang the system.
> >>>>>
> >>>>> The way to fix it is to move SRAM init happen much later so we don't
> >>>>> have to map it early. I guess now we could use ioremap for SRAM,
> >>>>> although we may not want device attributes for the executable code?
> >>>>> Got any suggestions here on how we should map SRAM later on?
> >>>>
> >>>> You can use a variant of ioremap() such as __arm_ioremap() which let you
> >>>> specify the memory attribute.
> >>>
> >>> OK, I'll take a look at that.
> >>>
> >> I have tried __arm_ioremap_pfn() for some DDR mapping and it didn't
> >> work as expected. The mapping was not getting created.
> >
> > Did you investigate why it wasn't created? Must have been a trivial
> > issue surely? But you have to wait until memory management is fully
> > initialized to call the real ioremap() though, which happens later
> > during the boot.
> >
>
> Isn't ioremap prevented from using main memory now?
My point is that the memory allocator has to be fully initialized
because memory might need to be allocated when ioremap() is called. At
the point where static mappings are created, the regular memory
allocator is not available yet.
Nicolas
^ permalink raw reply
* Please help with the OMAP static mapping mess
From: Rob Herring @ 2011-10-05 2:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.LFD.2.02.1110041458500.9106@xanadu.home>
On 10/04/2011 04:21 PM, Nicolas Pitre wrote:
> On Tue, 4 Oct 2011, Santosh Shilimkar wrote:
>
>> On Tuesday 04 October 2011 04:08 AM, Tony Lindgren wrote:
>>> * Nicolas Pitre <nico@fluxnic.net> [111003 14:36]:
>>>> On Mon, 3 Oct 2011, Tony Lindgren wrote:
>>>>
>>>>> Having the SRAM base address move around with different sizes also
>>>>> requires the SoC detection.. Otherwise we can end up mapping wrong
>>>>> size and end up trying to access secure SRAM that will hang the system.
>>>>>
>>>>> The way to fix it is to move SRAM init happen much later so we don't
>>>>> have to map it early. I guess now we could use ioremap for SRAM,
>>>>> although we may not want device attributes for the executable code?
>>>>> Got any suggestions here on how we should map SRAM later on?
>>>>
>>>> You can use a variant of ioremap() such as __arm_ioremap() which let you
>>>> specify the memory attribute.
>>>
>>> OK, I'll take a look at that.
>>>
>> I have tried __arm_ioremap_pfn() for some DDR mapping and it didn't
>> work as expected. The mapping was not getting created.
>
> Did you investigate why it wasn't created? Must have been a trivial
> issue surely? But you have to wait until memory management is fully
> initialized to call the real ioremap() though, which happens later
> during the boot.
>
Isn't ioremap prevented from using main memory now?
Rob
^ permalink raw reply
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