* [PATCH V3 2/3] ARM: SAMSUNG: Remove SDHCI bus clocks from platform data
From: Rajeshwari Shinde @ 2011-10-12 9:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1318412587-29987-1-git-send-email-rajeshwari.s@samsung.com>
The bus clocks previously sent through platform data to SDHCI controller
are removed.
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
---
arch/arm/mach-exynos4/Makefile | 1 -
arch/arm/mach-exynos4/setup-sdhci.c | 22 -------------------
arch/arm/mach-s3c2416/Makefile | 1 -
arch/arm/mach-s3c2416/setup-sdhci.c | 24 ---------------------
arch/arm/mach-s3c64xx/Makefile | 1 -
arch/arm/mach-s3c64xx/setup-sdhci.c | 24 ---------------------
arch/arm/mach-s5pc100/Makefile | 1 -
arch/arm/mach-s5pc100/setup-sdhci.c | 23 --------------------
arch/arm/mach-s5pv210/Makefile | 1 -
arch/arm/mach-s5pv210/setup-sdhci.c | 22 -------------------
arch/arm/plat-samsung/include/plat/sdhci.h | 31 ----------------------------
11 files changed, 0 insertions(+), 151 deletions(-)
delete mode 100644 arch/arm/mach-exynos4/setup-sdhci.c
delete mode 100644 arch/arm/mach-s3c2416/setup-sdhci.c
delete mode 100644 arch/arm/mach-s3c64xx/setup-sdhci.c
delete mode 100644 arch/arm/mach-s5pc100/setup-sdhci.c
delete mode 100644 arch/arm/mach-s5pv210/setup-sdhci.c
diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile
index 2bb18f4..c47aae3 100644
--- a/arch/arm/mach-exynos4/Makefile
+++ b/arch/arm/mach-exynos4/Makefile
@@ -55,7 +55,6 @@ obj-$(CONFIG_EXYNOS4_SETUP_I2C5) += setup-i2c5.o
obj-$(CONFIG_EXYNOS4_SETUP_I2C6) += setup-i2c6.o
obj-$(CONFIG_EXYNOS4_SETUP_I2C7) += setup-i2c7.o
obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD) += setup-keypad.o
-obj-$(CONFIG_EXYNOS4_SETUP_SDHCI) += setup-sdhci.o
obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
obj-$(CONFIG_EXYNOS4_SETUP_USB_PHY) += setup-usb-phy.o
diff --git a/arch/arm/mach-exynos4/setup-sdhci.c b/arch/arm/mach-exynos4/setup-sdhci.c
deleted file mode 100644
index 92937b4..0000000
--- a/arch/arm/mach-exynos4/setup-sdhci.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/* linux/arch/arm/mach-exynos4/setup-sdhci.c
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- * http://www.samsung.com
- *
- * EXYNOS4 - Helper functions for settign up SDHCI device(s) (HSMMC)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/types.h>
-
-/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
-
-char *exynos4_hsmmc_clksrcs[4] = {
- [0] = NULL,
- [1] = NULL,
- [2] = "sclk_mmc", /* mmc_bus */
- [3] = NULL,
-};
diff --git a/arch/arm/mach-s3c2416/Makefile b/arch/arm/mach-s3c2416/Makefile
index 7b805b2..ca0cd22 100644
--- a/arch/arm/mach-s3c2416/Makefile
+++ b/arch/arm/mach-s3c2416/Makefile
@@ -15,7 +15,6 @@ obj-$(CONFIG_S3C2416_PM) += pm.o
#obj-$(CONFIG_S3C2416_DMA) += dma.o
# Device setup
-obj-$(CONFIG_S3C2416_SETUP_SDHCI) += setup-sdhci.o
obj-$(CONFIG_S3C2416_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
# Machine support
diff --git a/arch/arm/mach-s3c2416/setup-sdhci.c b/arch/arm/mach-s3c2416/setup-sdhci.c
deleted file mode 100644
index cee5395..0000000
--- a/arch/arm/mach-s3c2416/setup-sdhci.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/* linux/arch/arm/mach-s3c2416/setup-sdhci.c
- *
- * Copyright 2010 Promwad Innovation Company
- * Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
- *
- * S3C2416 - Helper functions for settign up SDHCI device(s) (HSMMC)
- *
- * Based on mach-s3c64xx/setup-sdhci.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/types.h>
-
-/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
-
-char *s3c2416_hsmmc_clksrcs[4] = {
- [0] = "hsmmc",
- [1] = "hsmmc",
- [2] = "hsmmc-if",
- /* [3] = "48m", - note not successfully used yet */
-};
diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile
index 902ab9a..94de24b 100644
--- a/arch/arm/mach-s3c64xx/Makefile
+++ b/arch/arm/mach-s3c64xx/Makefile
@@ -32,7 +32,6 @@ obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o
obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o
obj-$(CONFIG_S3C64XX_SETUP_IDE) += setup-ide.o
obj-$(CONFIG_S3C64XX_SETUP_KEYPAD) += setup-keypad.o
-obj-$(CONFIG_S3C64XX_SETUP_SDHCI) += setup-sdhci.o
obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp.o
obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
diff --git a/arch/arm/mach-s3c64xx/setup-sdhci.c b/arch/arm/mach-s3c64xx/setup-sdhci.c
deleted file mode 100644
index c75a71b..0000000
--- a/arch/arm/mach-s3c64xx/setup-sdhci.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/* linux/arch/arm/mach-s3c64xx/setup-sdhci.c
- *
- * Copyright 2008 Simtec Electronics
- * Copyright 2008 Simtec Electronics
- * Ben Dooks <ben@simtec.co.uk>
- * http://armlinux.simtec.co.uk/
- *
- * S3C6400/S3C6410 - Helper functions for settign up SDHCI device(s) (HSMMC)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/types.h>
-
-/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
-
-char *s3c64xx_hsmmc_clksrcs[4] = {
- [0] = "hsmmc",
- [1] = "hsmmc",
- [2] = "mmc_bus",
- /* [3] = "48m", - note not successfully used yet */
-};
diff --git a/arch/arm/mach-s5pc100/Makefile b/arch/arm/mach-s5pc100/Makefile
index a5e6e60..2320e54 100644
--- a/arch/arm/mach-s5pc100/Makefile
+++ b/arch/arm/mach-s5pc100/Makefile
@@ -21,7 +21,6 @@ obj-$(CONFIG_S5PC100_SETUP_FB_24BPP) += setup-fb-24bpp.o
obj-$(CONFIG_S5PC100_SETUP_I2C1) += setup-i2c1.o
obj-$(CONFIG_S5PC100_SETUP_IDE) += setup-ide.o
obj-$(CONFIG_S5PC100_SETUP_KEYPAD) += setup-keypad.o
-obj-$(CONFIG_S5PC100_SETUP_SDHCI) += setup-sdhci.o
obj-$(CONFIG_S5PC100_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
# device support
diff --git a/arch/arm/mach-s5pc100/setup-sdhci.c b/arch/arm/mach-s5pc100/setup-sdhci.c
deleted file mode 100644
index 6418c6e..0000000
--- a/arch/arm/mach-s5pc100/setup-sdhci.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/* linux/arch/arm/mach-s5pc100/setup-sdhci.c
- *
- * Copyright 2008 Samsung Electronics
- *
- * S5PC100 - Helper functions for settign up SDHCI device(s) (HSMMC)
- *
- * Based on mach-s3c6410/setup-sdhci.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/types.h>
-
-/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
-
-char *s5pc100_hsmmc_clksrcs[4] = {
- [0] = "hsmmc", /* HCLK */
- /* [1] = "hsmmc", - duplicate HCLK entry */
- [2] = "sclk_mmc", /* mmc_bus */
- /* [3] = "48m", - note not successfully used yet */
-};
diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile
index 009fbe5..53c346a 100644
--- a/arch/arm/mach-s5pv210/Makefile
+++ b/arch/arm/mach-s5pv210/Makefile
@@ -35,5 +35,4 @@ obj-$(CONFIG_S5PV210_SETUP_I2C1) += setup-i2c1.o
obj-$(CONFIG_S5PV210_SETUP_I2C2) += setup-i2c2.o
obj-$(CONFIG_S5PV210_SETUP_IDE) += setup-ide.o
obj-$(CONFIG_S5PV210_SETUP_KEYPAD) += setup-keypad.o
-obj-$(CONFIG_S5PV210_SETUP_SDHCI) += setup-sdhci.o
obj-$(CONFIG_S5PV210_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
diff --git a/arch/arm/mach-s5pv210/setup-sdhci.c b/arch/arm/mach-s5pv210/setup-sdhci.c
deleted file mode 100644
index 6b8ccc4..0000000
--- a/arch/arm/mach-s5pv210/setup-sdhci.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/* linux/arch/arm/mach-s5pv210/setup-sdhci.c
- *
- * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
- * http://www.samsung.com/
- *
- * S5PV210 - Helper functions for settign up SDHCI device(s) (HSMMC)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/types.h>
-
-/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
-
-char *s5pv210_hsmmc_clksrcs[4] = {
- [0] = "hsmmc", /* HCLK */
- /* [1] = "hsmmc", - duplicate HCLK entry */
- [2] = "sclk_mmc", /* mmc_bus */
- /* [3] = NULL, - reserved */
-};
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
index e7b3c75..dcff7dd 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -66,8 +66,6 @@ struct s3c_sdhci_platdata {
enum cd_types cd_type;
enum clk_types clk_type;
- char **clocks; /* set of clock sources */
-
int ext_cd_gpio;
bool ext_cd_gpio_invert;
int (*ext_cd_init)(void (*notify_func)(struct platform_device *,
@@ -129,12 +127,9 @@ extern void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *, int w);
/* S3C2416 SDHCI setup */
#ifdef CONFIG_S3C2416_SETUP_SDHCI
-extern char *s3c2416_hsmmc_clksrcs[4];
-
static inline void s3c2416_default_sdhci0(void)
{
#ifdef CONFIG_S3C_DEV_HSMMC
- s3c_hsmmc0_def_platdata.clocks = s3c2416_hsmmc_clksrcs;
s3c_hsmmc0_def_platdata.cfg_gpio = s3c2416_setup_sdhci0_cfg_gpio;
#endif /* CONFIG_S3C_DEV_HSMMC */
}
@@ -142,7 +137,6 @@ static inline void s3c2416_default_sdhci0(void)
static inline void s3c2416_default_sdhci1(void)
{
#ifdef CONFIG_S3C_DEV_HSMMC1
- s3c_hsmmc1_def_platdata.clocks = s3c2416_hsmmc_clksrcs;
s3c_hsmmc1_def_platdata.cfg_gpio = s3c2416_setup_sdhci1_cfg_gpio;
#endif /* CONFIG_S3C_DEV_HSMMC1 */
}
@@ -155,12 +149,9 @@ static inline void s3c2416_default_sdhci1(void) { }
/* S3C64XX SDHCI setup */
#ifdef CONFIG_S3C64XX_SETUP_SDHCI
-extern char *s3c64xx_hsmmc_clksrcs[4];
-
static inline void s3c6400_default_sdhci0(void)
{
#ifdef CONFIG_S3C_DEV_HSMMC
- s3c_hsmmc0_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio;
#endif
}
@@ -168,7 +159,6 @@ static inline void s3c6400_default_sdhci0(void)
static inline void s3c6400_default_sdhci1(void)
{
#ifdef CONFIG_S3C_DEV_HSMMC1
- s3c_hsmmc1_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio;
#endif
}
@@ -176,7 +166,6 @@ static inline void s3c6400_default_sdhci1(void)
static inline void s3c6400_default_sdhci2(void)
{
#ifdef CONFIG_S3C_DEV_HSMMC2
- s3c_hsmmc2_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio;
#endif
}
@@ -184,7 +173,6 @@ static inline void s3c6400_default_sdhci2(void)
static inline void s3c6410_default_sdhci0(void)
{
#ifdef CONFIG_S3C_DEV_HSMMC
- s3c_hsmmc0_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio;
#endif
}
@@ -192,7 +180,6 @@ static inline void s3c6410_default_sdhci0(void)
static inline void s3c6410_default_sdhci1(void)
{
#ifdef CONFIG_S3C_DEV_HSMMC1
- s3c_hsmmc1_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio;
#endif
}
@@ -200,7 +187,6 @@ static inline void s3c6410_default_sdhci1(void)
static inline void s3c6410_default_sdhci2(void)
{
#ifdef CONFIG_S3C_DEV_HSMMC2
- s3c_hsmmc2_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio;
#endif
}
@@ -218,12 +204,9 @@ static inline void s3c6400_default_sdhci2(void) { }
/* S5PC100 SDHCI setup */
#ifdef CONFIG_S5PC100_SETUP_SDHCI
-extern char *s5pc100_hsmmc_clksrcs[4];
-
static inline void s5pc100_default_sdhci0(void)
{
#ifdef CONFIG_S3C_DEV_HSMMC
- s3c_hsmmc0_def_platdata.clocks = s5pc100_hsmmc_clksrcs;
s3c_hsmmc0_def_platdata.cfg_gpio = s5pc100_setup_sdhci0_cfg_gpio;
#endif
}
@@ -231,7 +214,6 @@ static inline void s5pc100_default_sdhci0(void)
static inline void s5pc100_default_sdhci1(void)
{
#ifdef CONFIG_S3C_DEV_HSMMC1
- s3c_hsmmc1_def_platdata.clocks = s5pc100_hsmmc_clksrcs;
s3c_hsmmc1_def_platdata.cfg_gpio = s5pc100_setup_sdhci1_cfg_gpio;
#endif
}
@@ -239,7 +221,6 @@ static inline void s5pc100_default_sdhci1(void)
static inline void s5pc100_default_sdhci2(void)
{
#ifdef CONFIG_S3C_DEV_HSMMC2
- s3c_hsmmc2_def_platdata.clocks = s5pc100_hsmmc_clksrcs;
s3c_hsmmc2_def_platdata.cfg_gpio = s5pc100_setup_sdhci2_cfg_gpio;
#endif
}
@@ -254,12 +235,9 @@ static inline void s5pc100_default_sdhci2(void) { }
/* S5PV210 SDHCI setup */
#ifdef CONFIG_S5PV210_SETUP_SDHCI
-extern char *s5pv210_hsmmc_clksrcs[4];
-
static inline void s5pv210_default_sdhci0(void)
{
#ifdef CONFIG_S3C_DEV_HSMMC
- s3c_hsmmc0_def_platdata.clocks = s5pv210_hsmmc_clksrcs;
s3c_hsmmc0_def_platdata.cfg_gpio = s5pv210_setup_sdhci0_cfg_gpio;
#endif
}
@@ -267,7 +245,6 @@ static inline void s5pv210_default_sdhci0(void)
static inline void s5pv210_default_sdhci1(void)
{
#ifdef CONFIG_S3C_DEV_HSMMC1
- s3c_hsmmc1_def_platdata.clocks = s5pv210_hsmmc_clksrcs;
s3c_hsmmc1_def_platdata.cfg_gpio = s5pv210_setup_sdhci1_cfg_gpio;
#endif
}
@@ -275,7 +252,6 @@ static inline void s5pv210_default_sdhci1(void)
static inline void s5pv210_default_sdhci2(void)
{
#ifdef CONFIG_S3C_DEV_HSMMC2
- s3c_hsmmc2_def_platdata.clocks = s5pv210_hsmmc_clksrcs;
s3c_hsmmc2_def_platdata.cfg_gpio = s5pv210_setup_sdhci2_cfg_gpio;
#endif
}
@@ -283,7 +259,6 @@ static inline void s5pv210_default_sdhci2(void)
static inline void s5pv210_default_sdhci3(void)
{
#ifdef CONFIG_S3C_DEV_HSMMC3
- s3c_hsmmc3_def_platdata.clocks = s5pv210_hsmmc_clksrcs;
s3c_hsmmc3_def_platdata.cfg_gpio = s5pv210_setup_sdhci3_cfg_gpio;
#endif
}
@@ -298,12 +273,9 @@ static inline void s5pv210_default_sdhci3(void) { }
/* EXYNOS4 SDHCI setup */
#ifdef CONFIG_EXYNOS4_SETUP_SDHCI
-extern char *exynos4_hsmmc_clksrcs[4];
-
static inline void exynos4_default_sdhci0(void)
{
#ifdef CONFIG_S3C_DEV_HSMMC
- s3c_hsmmc0_def_platdata.clocks = exynos4_hsmmc_clksrcs;
s3c_hsmmc0_def_platdata.cfg_gpio = exynos4_setup_sdhci0_cfg_gpio;
#endif
}
@@ -311,7 +283,6 @@ static inline void exynos4_default_sdhci0(void)
static inline void exynos4_default_sdhci1(void)
{
#ifdef CONFIG_S3C_DEV_HSMMC1
- s3c_hsmmc1_def_platdata.clocks = exynos4_hsmmc_clksrcs;
s3c_hsmmc1_def_platdata.cfg_gpio = exynos4_setup_sdhci1_cfg_gpio;
#endif
}
@@ -319,7 +290,6 @@ static inline void exynos4_default_sdhci1(void)
static inline void exynos4_default_sdhci2(void)
{
#ifdef CONFIG_S3C_DEV_HSMMC2
- s3c_hsmmc2_def_platdata.clocks = exynos4_hsmmc_clksrcs;
s3c_hsmmc2_def_platdata.cfg_gpio = exynos4_setup_sdhci2_cfg_gpio;
#endif
}
@@ -327,7 +297,6 @@ static inline void exynos4_default_sdhci2(void)
static inline void exynos4_default_sdhci3(void)
{
#ifdef CONFIG_S3C_DEV_HSMMC3
- s3c_hsmmc3_def_platdata.clocks = exynos4_hsmmc_clksrcs;
s3c_hsmmc3_def_platdata.cfg_gpio = exynos4_setup_sdhci3_cfg_gpio;
#endif
}
--
1.7.4.4
^ permalink raw reply related
* [PATCH V4 3/3] ARM: SAMSUNG: Add lookup of sdhci-s3c clocks using generic names
From: Rajeshwari Shinde @ 2011-10-12 9:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1318412587-29987-1-git-send-email-rajeshwari.s@samsung.com>
Add support for lookup of sdhci-s3c controller clocks using generic names
for s3c2416, s3c64xx, s5pc100, s5pv210 and exynos4 SoC's.
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
---
arch/arm/mach-exynos4/clock.c | 88 ++++++++++-------
arch/arm/mach-s3c2416/clock.c | 68 +++++++------
arch/arm/mach-s3c64xx/clock.c | 126 +++++++++++++++----------
arch/arm/mach-s5pc100/clock.c | 130 ++++++++++++++++----------
arch/arm/mach-s5pv210/clock.c | 167 ++++++++++++++++++++-------------
arch/arm/plat-s3c24xx/s3c2443-clock.c | 15 ++-
6 files changed, 359 insertions(+), 235 deletions(-)
diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c
index 9f50e33..c6383b9 100644
--- a/arch/arm/mach-exynos4/clock.c
+++ b/arch/arm/mach-exynos4/clock.c
@@ -1157,42 +1157,6 @@ static struct clksrc_clk clksrcs[] = {
.reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 },
}, {
.clk = {
- .name = "sclk_mmc",
- .devname = "s3c-sdhci.0",
- .parent = &clk_dout_mmc0.clk,
- .enable = exynos4_clksrc_mask_fsys_ctrl,
- .ctrlbit = (1 << 0),
- },
- .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
- }, {
- .clk = {
- .name = "sclk_mmc",
- .devname = "s3c-sdhci.1",
- .parent = &clk_dout_mmc1.clk,
- .enable = exynos4_clksrc_mask_fsys_ctrl,
- .ctrlbit = (1 << 4),
- },
- .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
- }, {
- .clk = {
- .name = "sclk_mmc",
- .devname = "s3c-sdhci.2",
- .parent = &clk_dout_mmc2.clk,
- .enable = exynos4_clksrc_mask_fsys_ctrl,
- .ctrlbit = (1 << 8),
- },
- .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
- }, {
- .clk = {
- .name = "sclk_mmc",
- .devname = "s3c-sdhci.3",
- .parent = &clk_dout_mmc3.clk,
- .enable = exynos4_clksrc_mask_fsys_ctrl,
- .ctrlbit = (1 << 12),
- },
- .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
- }, {
- .clk = {
.name = "sclk_dwmmc",
.parent = &clk_dout_mmc4.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl,
@@ -1250,6 +1214,50 @@ static struct clksrc_clk clk_sclk_uart3 = {
.reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
};
+static struct clksrc_clk clk_sclk_mmc0 = {
+ .clk = {
+ .name = "sclk_mmc",
+ .devname = "s3c-sdhci.0",
+ .parent = &clk_dout_mmc0.clk,
+ .enable = exynos4_clksrc_mask_fsys_ctrl,
+ .ctrlbit = (1 << 0),
+ },
+ .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
+};
+
+static struct clksrc_clk clk_sclk_mmc1 = {
+ .clk = {
+ .name = "sclk_mmc",
+ .devname = "s3c-sdhci.1",
+ .parent = &clk_dout_mmc1.clk,
+ .enable = exynos4_clksrc_mask_fsys_ctrl,
+ .ctrlbit = (1 << 4),
+ },
+ .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
+};
+
+static struct clksrc_clk clk_sclk_mmc2 = {
+ .clk = {
+ .name = "sclk_mmc",
+ .devname = "s3c-sdhci.2",
+ .parent = &clk_dout_mmc2.clk,
+ .enable = exynos4_clksrc_mask_fsys_ctrl,
+ .ctrlbit = (1 << 8),
+ },
+ .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
+};
+
+static struct clksrc_clk clk_sclk_mmc3 = {
+ .clk = {
+ .name = "sclk_mmc",
+ .devname = "s3c-sdhci.3",
+ .parent = &clk_dout_mmc3.clk,
+ .enable = exynos4_clksrc_mask_fsys_ctrl,
+ .ctrlbit = (1 << 12),
+ },
+ .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
+};
+
/* Clock initialization code */
static struct clksrc_clk *sysclks[] = {
&clk_mout_apll,
@@ -1289,6 +1297,10 @@ static struct clksrc_clk *clksrc_cdev[] = {
&clk_sclk_uart1,
&clk_sclk_uart2,
&clk_sclk_uart3,
+ &clk_sclk_mmc0,
+ &clk_sclk_mmc1,
+ &clk_sclk_mmc2,
+ &clk_sclk_mmc3,
};
static struct clk_lookup exynos4_clk_lookup[] = {
@@ -1296,6 +1308,10 @@ static struct clk_lookup exynos4_clk_lookup[] = {
CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &clk_sclk_uart1.clk),
CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &clk_sclk_uart2.clk),
CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &clk_sclk_uart3.clk),
+ CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
+ CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
+ CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
+ CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),
};
static int xtal_rate;
diff --git a/arch/arm/mach-s3c2416/clock.c b/arch/arm/mach-s3c2416/clock.c
index 72b7c62..6ece510 100644
--- a/arch/arm/mach-s3c2416/clock.c
+++ b/arch/arm/mach-s3c2416/clock.c
@@ -82,39 +82,38 @@ static struct clksrc_clk hsmmc_div[] = {
},
};
-static struct clksrc_clk hsmmc_mux[] = {
- [0] = {
- .clk = {
- .name = "hsmmc-if",
- .devname = "s3c-sdhci.0",
- .ctrlbit = (1 << 6),
- .enable = s3c2443_clkcon_enable_s,
- },
- .sources = &(struct clksrc_sources) {
- .nr_sources = 2,
- .sources = (struct clk *[]) {
- [0] = &hsmmc_div[0].clk,
- [1] = NULL, /* to fix */
- },
- },
- .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 16 },
+static struct clksrc_clk hsmmc_mux0 = {
+ .clk = {
+ .name = "hsmmc-if",
+ .devname = "s3c-sdhci.0",
+ .ctrlbit = (1 << 6),
+ .enable = s3c2443_clkcon_enable_s,
},
- [1] = {
- .clk = {
- .name = "hsmmc-if",
- .devname = "s3c-sdhci.1",
- .ctrlbit = (1 << 12),
- .enable = s3c2443_clkcon_enable_s,
+ .sources = &(struct clksrc_sources) {
+ .nr_sources = 2,
+ .sources = (struct clk * []) {
+ [0] = &hsmmc_div[0].clk,
+ [1] = NULL, /* to fix */
},
- .sources = &(struct clksrc_sources) {
- .nr_sources = 2,
- .sources = (struct clk *[]) {
- [0] = &hsmmc_div[1].clk,
- [1] = NULL, /* to fix */
- },
+ },
+ .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 16 },
+};
+
+static struct clksrc_clk hsmmc_mux1 = {
+ .clk = {
+ .name = "hsmmc-if",
+ .devname = "s3c-sdhci.1",
+ .ctrlbit = (1 << 12),
+ .enable = s3c2443_clkcon_enable_s,
+ },
+ .sources = &(struct clksrc_sources) {
+ .nr_sources = 2,
+ .sources = (struct clk * []) {
+ [0] = &hsmmc_div[1].clk,
+ [1] = NULL, /* to fix */
},
- .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 17 },
},
+ .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 17 },
};
static struct clk hsmmc0_clk = {
@@ -143,8 +142,14 @@ static struct clksrc_clk *clksrcs[] __initdata = {
&hsspi_mux,
&hsmmc_div[0],
&hsmmc_div[1],
- &hsmmc_mux[0],
- &hsmmc_mux[1],
+ &hsmmc_mux0,
+ &hsmmc_mux1,
+};
+
+static struct clk_lookup s3c2416_clk_lookup[] = {
+ CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &hsmmc0_clk),
+ CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &hsmmc_mux0.clk),
+ CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &hsmmc_mux1.clk),
};
void __init s3c2416_init_clocks(int xtal)
@@ -164,6 +169,7 @@ void __init s3c2416_init_clocks(int xtal)
s3c_register_clksrc(clksrcs[ptr], 1);
s3c24xx_register_clock(&hsmmc0_clk);
+ clkdev_add_table(s3c2416_clk_lookup, ARRAY_SIZE(s3c2416_clk_lookup));
s3c_pwmclk_init();
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index 2addd98..415c540 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -243,24 +243,6 @@ static struct clk init_clocks[] = {
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_UHOST,
}, {
- .name = "hsmmc",
- .devname = "s3c-sdhci.0",
- .parent = &clk_h,
- .enable = s3c64xx_hclk_ctrl,
- .ctrlbit = S3C_CLKCON_HCLK_HSMMC0,
- }, {
- .name = "hsmmc",
- .devname = "s3c-sdhci.1",
- .parent = &clk_h,
- .enable = s3c64xx_hclk_ctrl,
- .ctrlbit = S3C_CLKCON_HCLK_HSMMC1,
- }, {
- .name = "hsmmc",
- .devname = "s3c-sdhci.2",
- .parent = &clk_h,
- .enable = s3c64xx_hclk_ctrl,
- .ctrlbit = S3C_CLKCON_HCLK_HSMMC2,
- }, {
.name = "otg",
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
@@ -310,6 +292,29 @@ static struct clk init_clocks[] = {
}
};
+static struct clk clk_hsmmc0 = {
+ .name = "hsmmc",
+ .devname = "s3c-sdhci.0",
+ .parent = &clk_h,
+ .enable = s3c64xx_hclk_ctrl,
+ .ctrlbit = S3C_CLKCON_HCLK_HSMMC0,
+};
+
+static struct clk clk_hsmmc1 = {
+ .name = "hsmmc",
+ .devname = "s3c-sdhci.1",
+ .parent = &clk_h,
+ .enable = s3c64xx_hclk_ctrl,
+ .ctrlbit = S3C_CLKCON_HCLK_HSMMC1,
+};
+
+static struct clk clk_hsmmc2 = {
+ .name = "hsmmc",
+ .devname = "s3c-sdhci.2",
+ .parent = &clk_h,
+ .enable = s3c64xx_hclk_ctrl,
+ .ctrlbit = S3C_CLKCON_HCLK_HSMMC2,
+};
static struct clk clk_fout_apll = {
.name = "fout_apll",
@@ -578,36 +583,6 @@ static struct clksrc_sources clkset_camif = {
static struct clksrc_clk clksrcs[] = {
{
.clk = {
- .name = "mmc_bus",
- .devname = "s3c-sdhci.0",
- .ctrlbit = S3C_CLKCON_SCLK_MMC0,
- .enable = s3c64xx_sclk_ctrl,
- },
- .reg_src = { .reg = S3C_CLK_SRC, .shift = 18, .size = 2 },
- .reg_div = { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4 },
- .sources = &clkset_spi_mmc,
- }, {
- .clk = {
- .name = "mmc_bus",
- .devname = "s3c-sdhci.1",
- .ctrlbit = S3C_CLKCON_SCLK_MMC1,
- .enable = s3c64xx_sclk_ctrl,
- },
- .reg_src = { .reg = S3C_CLK_SRC, .shift = 20, .size = 2 },
- .reg_div = { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4 },
- .sources = &clkset_spi_mmc,
- }, {
- .clk = {
- .name = "mmc_bus",
- .devname = "s3c-sdhci.2",
- .ctrlbit = S3C_CLKCON_SCLK_MMC2,
- .enable = s3c64xx_sclk_ctrl,
- },
- .reg_src = { .reg = S3C_CLK_SRC, .shift = 22, .size = 2 },
- .reg_div = { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4 },
- .sources = &clkset_spi_mmc,
- }, {
- .clk = {
.name = "usb-bus-host",
.ctrlbit = S3C_CLKCON_SCLK_UHOST,
.enable = s3c64xx_sclk_ctrl,
@@ -697,6 +672,42 @@ static struct clksrc_clk clk_sclk_uclk = {
.sources = &clkset_uart,
};
+static struct clksrc_clk clk_sclk_mmc0 = {
+ .clk = {
+ .name = "mmc_bus",
+ .devname = "s3c-sdhci.0",
+ .ctrlbit = S3C_CLKCON_SCLK_MMC0,
+ .enable = s3c64xx_sclk_ctrl,
+ },
+ .reg_src = { .reg = S3C_CLK_SRC, .shift = 18, .size = 2 },
+ .reg_div = { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4 },
+ .sources = &clkset_spi_mmc,
+};
+
+static struct clksrc_clk clk_sclk_mmc1 = {
+ .clk = {
+ .name = "mmc_bus",
+ .devname = "s3c-sdhci.1",
+ .ctrlbit = S3C_CLKCON_SCLK_MMC1,
+ .enable = s3c64xx_sclk_ctrl,
+ },
+ .reg_src = { .reg = S3C_CLK_SRC, .shift = 20, .size = 2 },
+ .reg_div = { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4 },
+ .sources = &clkset_spi_mmc,
+};
+
+static struct clksrc_clk clk_sclk_mmc2 = {
+ .clk = {
+ .name = "mmc_bus",
+ .devname = "s3c-sdhci.2",
+ .ctrlbit = S3C_CLKCON_SCLK_MMC2,
+ .enable = s3c64xx_sclk_ctrl,
+ },
+ .reg_src = { .reg = S3C_CLK_SRC, .shift = 22, .size = 2 },
+ .reg_div = { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4 },
+ .sources = &clkset_spi_mmc,
+};
+
/* Clock initialisation code */
static struct clksrc_clk *init_parents[] = {
@@ -707,11 +718,26 @@ static struct clksrc_clk *init_parents[] = {
static struct clksrc_clk *clksrc_cdev[] = {
&clk_sclk_uclk,
+ &clk_sclk_mmc0,
+ &clk_sclk_mmc1,
+ &clk_sclk_mmc2,
+};
+
+static struct clk *clk_cdev[] = {
+ &clk_hsmmc0,
+ &clk_hsmmc1,
+ &clk_hsmmc2,
};
static struct clk_lookup s3c64xx_clk_lookup[] = {
CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
+ CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
+ CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
+ CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
+ CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
+ CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
+ CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
};
#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
@@ -834,6 +860,10 @@ void __init s3c64xx_register_clocks(unsigned long xtal,
s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+ s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
+ for (cnt = 0; cnt < ARRAY_SIZE(clk_cdev); cnt++)
+ s3c_disable_clocks(clk_cdev[cnt], 1);
+
s3c24xx_register_clocks(clks1, ARRAY_SIZE(clks1));
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
for (cnt = 0; cnt < ARRAY_SIZE(clksrc_cdev); cnt++)
diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c
index 9d644ec..69829ba 100644
--- a/arch/arm/mach-s5pc100/clock.c
+++ b/arch/arm/mach-s5pc100/clock.c
@@ -426,24 +426,6 @@ static struct clk init_clocks_off[] = {
.enable = s5pc100_d0_2_ctrl,
.ctrlbit = (1 << 1),
}, {
- .name = "hsmmc",
- .devname = "s3c-sdhci.2",
- .parent = &clk_div_d1_bus.clk,
- .enable = s5pc100_d1_0_ctrl,
- .ctrlbit = (1 << 7),
- }, {
- .name = "hsmmc",
- .devname = "s3c-sdhci.1",
- .parent = &clk_div_d1_bus.clk,
- .enable = s5pc100_d1_0_ctrl,
- .ctrlbit = (1 << 6),
- }, {
- .name = "hsmmc",
- .devname = "s3c-sdhci.0",
- .parent = &clk_div_d1_bus.clk,
- .enable = s5pc100_d1_0_ctrl,
- .ctrlbit = (1 << 5),
- }, {
.name = "modemif",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_0_ctrl,
@@ -711,6 +693,30 @@ static struct clk init_clocks_off[] = {
},
};
+static struct clk clk_hsmmc2 = {
+ .name = "hsmmc",
+ .devname = "s3c-sdhci.2",
+ .parent = &clk_div_d1_bus.clk,
+ .enable = s5pc100_d1_0_ctrl,
+ .ctrlbit = (1 << 7),
+};
+
+static struct clk clk_hsmmc1 = {
+ .name = "hsmmc",
+ .devname = "s3c-sdhci.1",
+ .parent = &clk_div_d1_bus.clk,
+ .enable = s5pc100_d1_0_ctrl,
+ .ctrlbit = (1 << 6),
+};
+
+static struct clk clk_hsmmc0 = {
+ .name = "hsmmc",
+ .devname = "s3c-sdhci.0",
+ .parent = &clk_div_d1_bus.clk,
+ .enable = s5pc100_d1_0_ctrl,
+ .ctrlbit = (1 << 5),
+};
+
static struct clk clk_vclk54m = {
.name = "vclk_54m",
.rate = 54000000,
@@ -1014,39 +1020,6 @@ static struct clksrc_clk clksrcs[] = {
.reg_div = { .reg = S5P_CLK_DIV3, .shift = 24, .size = 4 },
}, {
.clk = {
- .name = "sclk_mmc",
- .devname = "s3c-sdhci.0",
- .ctrlbit = (1 << 12),
- .enable = s5pc100_sclk1_ctrl,
-
- },
- .sources = &clk_src_mmc0,
- .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
- .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
- }, {
- .clk = {
- .name = "sclk_mmc",
- .devname = "s3c-sdhci.1",
- .ctrlbit = (1 << 13),
- .enable = s5pc100_sclk1_ctrl,
-
- },
- .sources = &clk_src_mmc12,
- .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
- .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
- }, {
- .clk = {
- .name = "sclk_mmc",
- .devname = "s3c-sdhci.2",
- .ctrlbit = (1 << 14),
- .enable = s5pc100_sclk1_ctrl,
-
- },
- .sources = &clk_src_mmc12,
- .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
- .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
- }, {
- .clk = {
.name = "sclk_irda",
.ctrlbit = (1 << 10),
.enable = s5pc100_sclk0_ctrl,
@@ -1099,6 +1072,42 @@ static struct clksrc_clk clk_sclk_uart = {
.reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
};
+static struct clksrc_clk clk_sclk_mmc0 = {
+ .clk = {
+ .name = "sclk_mmc",
+ .devname = "s3c-sdhci.0",
+ .ctrlbit = (1 << 12),
+ .enable = s5pc100_sclk1_ctrl,
+ },
+ .sources = &clk_src_mmc0,
+ .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
+ .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_mmc1 = {
+ .clk = {
+ .name = "sclk_mmc",
+ .devname = "s3c-sdhci.1",
+ .ctrlbit = (1 << 13),
+ .enable = s5pc100_sclk1_ctrl,
+ },
+ .sources = &clk_src_mmc12,
+ .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
+ .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_mmc2 = {
+ .clk = {
+ .name = "sclk_mmc",
+ .devname = "s3c-sdhci.2",
+ .ctrlbit = (1 << 14),
+ .enable = s5pc100_sclk1_ctrl,
+ },
+ .sources = &clk_src_mmc12,
+ .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
+ .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
+};
+
/* Clock initialisation code */
static struct clksrc_clk *sysclks[] = {
&clk_mout_apll,
@@ -1128,8 +1137,17 @@ static struct clksrc_clk *sysclks[] = {
&clk_sclk_spdif,
};
+static struct clk *clk_cdev[] = {
+ &clk_hsmmc0,
+ &clk_hsmmc1,
+ &clk_hsmmc2,
+};
+
static struct clksrc_clk *clksrc_cdev[] = {
&clk_sclk_uart,
+ &clk_sclk_mmc0,
+ &clk_sclk_mmc1,
+ &clk_sclk_mmc2,
};
void __init_or_cpufreq s5pc100_setup_clocks(void)
@@ -1274,6 +1292,12 @@ static struct clk *clks[] __initdata = {
static struct clk_lookup s5pc100_clk_lookup[] = {
CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uart.clk),
+ CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
+ CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
+ CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
+ CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
+ CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
+ CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
};
void __init s5pc100_register_clocks(void)
@@ -1294,6 +1318,10 @@ void __init s5pc100_register_clocks(void)
s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
clkdev_add_table(s5pc100_clk_lookup, ARRAY_SIZE(s5pc100_clk_lookup));
+ s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
+ for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
+ s3c_disable_clocks(clk_cdev[ptr], 1);
+
s3c24xx_register_clock(&dummy_apb_pclk);
s3c_pwmclk_init();
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index 43a045d..dc4586b 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -399,30 +399,6 @@ static struct clk init_clocks_off[] = {
.enable = s5pv210_clk_ip1_ctrl,
.ctrlbit = (1<<25),
}, {
- .name = "hsmmc",
- .devname = "s3c-sdhci.0",
- .parent = &clk_hclk_psys.clk,
- .enable = s5pv210_clk_ip2_ctrl,
- .ctrlbit = (1<<16),
- }, {
- .name = "hsmmc",
- .devname = "s3c-sdhci.1",
- .parent = &clk_hclk_psys.clk,
- .enable = s5pv210_clk_ip2_ctrl,
- .ctrlbit = (1<<17),
- }, {
- .name = "hsmmc",
- .devname = "s3c-sdhci.2",
- .parent = &clk_hclk_psys.clk,
- .enable = s5pv210_clk_ip2_ctrl,
- .ctrlbit = (1<<18),
- }, {
- .name = "hsmmc",
- .devname = "s3c-sdhci.3",
- .parent = &clk_hclk_psys.clk,
- .enable = s5pv210_clk_ip2_ctrl,
- .ctrlbit = (1<<19),
- }, {
.name = "systimer",
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
@@ -559,6 +535,38 @@ static struct clk init_clocks[] = {
},
};
+static struct clk clk_hsmmc0 = {
+ .name = "hsmmc",
+ .devname = "s3c-sdhci.0",
+ .parent = &clk_hclk_psys.clk,
+ .enable = s5pv210_clk_ip2_ctrl,
+ .ctrlbit = (1<<16),
+};
+
+static struct clk clk_hsmmc1 = {
+ .name = "hsmmc",
+ .devname = "s3c-sdhci.1",
+ .parent = &clk_hclk_psys.clk,
+ .enable = s5pv210_clk_ip2_ctrl,
+ .ctrlbit = (1<<17),
+};
+
+static struct clk clk_hsmmc2 = {
+ .name = "hsmmc",
+ .devname = "s3c-sdhci.2",
+ .parent = &clk_hclk_psys.clk,
+ .enable = s5pv210_clk_ip2_ctrl,
+ .ctrlbit = (1<<18),
+};
+
+static struct clk clk_hsmmc3 = {
+ .name = "hsmmc",
+ .devname = "s3c-sdhci.3",
+ .parent = &clk_hclk_psys.clk,
+ .enable = s5pv210_clk_ip2_ctrl,
+ .ctrlbit = (1<<19),
+};
+
static struct clk *clkset_uart_list[] = {
[6] = &clk_mout_mpll.clk,
[7] = &clk_mout_epll.clk,
@@ -866,46 +874,6 @@ static struct clksrc_clk clksrcs[] = {
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 },
}, {
.clk = {
- .name = "sclk_mmc",
- .devname = "s3c-sdhci.0",
- .enable = s5pv210_clk_mask0_ctrl,
- .ctrlbit = (1 << 8),
- },
- .sources = &clkset_group2,
- .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
- .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 },
- }, {
- .clk = {
- .name = "sclk_mmc",
- .devname = "s3c-sdhci.1",
- .enable = s5pv210_clk_mask0_ctrl,
- .ctrlbit = (1 << 9),
- },
- .sources = &clkset_group2,
- .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
- .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 },
- }, {
- .clk = {
- .name = "sclk_mmc",
- .devname = "s3c-sdhci.2",
- .enable = s5pv210_clk_mask0_ctrl,
- .ctrlbit = (1 << 10),
- },
- .sources = &clkset_group2,
- .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
- .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 },
- }, {
- .clk = {
- .name = "sclk_mmc",
- .devname = "s3c-sdhci.3",
- .enable = s5pv210_clk_mask0_ctrl,
- .ctrlbit = (1 << 11),
- },
- .sources = &clkset_group2,
- .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
- .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
- }, {
- .clk = {
.name = "sclk_mfc",
.devname = "s5p-mfc",
.enable = s5pv210_clk_ip0_ctrl,
@@ -1030,11 +998,70 @@ static struct clksrc_clk clk_sclk_uart3 = {
.reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 },
};
+static struct clksrc_clk clk_sclk_mmc0 = {
+ .clk = {
+ .name = "sclk_mmc",
+ .devname = "s3c-sdhci.0",
+ .enable = s5pv210_clk_mask0_ctrl,
+ .ctrlbit = (1 << 8),
+ },
+ .sources = &clkset_group2,
+ .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
+ .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_mmc1 = {
+ .clk = {
+ .name = "sclk_mmc",
+ .devname = "s3c-sdhci.1",
+ .enable = s5pv210_clk_mask0_ctrl,
+ .ctrlbit = (1 << 9),
+ },
+ .sources = &clkset_group2,
+ .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
+ .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_mmc2 = {
+ .clk = {
+ .name = "sclk_mmc",
+ .devname = "s3c-sdhci.2",
+ .enable = s5pv210_clk_mask0_ctrl,
+ .ctrlbit = (1 << 10),
+ },
+ .sources = &clkset_group2,
+ .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
+ .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_mmc3 = {
+ .clk = {
+ .name = "sclk_mmc",
+ .devname = "s3c-sdhci.3",
+ .enable = s5pv210_clk_mask0_ctrl,
+ .ctrlbit = (1 << 11),
+ },
+ .sources = &clkset_group2,
+ .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
+ .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
+};
+
static struct clksrc_clk *clksrc_cdev[] = {
&clk_sclk_uart0,
&clk_sclk_uart1,
&clk_sclk_uart2,
&clk_sclk_uart3,
+ &clk_sclk_mmc0,
+ &clk_sclk_mmc1,
+ &clk_sclk_mmc2,
+ &clk_sclk_mmc3,
+};
+
+static struct clk *clk_cdev[] = {
+ &clk_hsmmc0,
+ &clk_hsmmc1,
+ &clk_hsmmc2,
+ &clk_hsmmc3,
};
/* Clock initialisation code */
@@ -1282,6 +1309,14 @@ static struct clk_lookup s5pv210_clk_lookup[] = {
CLKDEV_INIT("s5pv210-uart.1", "clk_uart_baud1", &clk_sclk_uart1.clk),
CLKDEV_INIT("s5pv210-uart.2", "clk_uart_baud1", &clk_sclk_uart2.clk),
CLKDEV_INIT("s5pv210-uart.3", "clk_uart_baud1", &clk_sclk_uart3.clk),
+ CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
+ CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
+ CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
+ CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.0", &clk_hsmmc3),
+ CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
+ CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
+ CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
+ CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),
};
void __init s5pv210_register_clocks(void)
@@ -1306,6 +1341,10 @@ void __init s5pv210_register_clocks(void)
s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
clkdev_add_table(s5pv210_clk_lookup, ARRAY_SIZE(s5pv210_clk_lookup));
+ s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
+ for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
+ s3c_disable_clocks(clk_cdev[ptr], 1);
+
s3c24xx_register_clock(&dummy_apb_pclk);
s3c_pwmclk_init();
}
diff --git a/arch/arm/plat-s3c24xx/s3c2443-clock.c b/arch/arm/plat-s3c24xx/s3c2443-clock.c
index 4a24e15..2a2a255 100644
--- a/arch/arm/plat-s3c24xx/s3c2443-clock.c
+++ b/arch/arm/plat-s3c24xx/s3c2443-clock.c
@@ -309,11 +309,6 @@ static struct clk init_clocks[] = {
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_DMA5,
}, {
- .name = "hsmmc",
- .parent = &clk_h,
- .enable = s3c2443_clkcon_enable_h,
- .ctrlbit = S3C2443_HCLKCON_HSMMC,
- }, {
.name = "gpio",
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
@@ -395,6 +390,14 @@ static struct clk init_clocks[] = {
}
};
+static struct clk hsmmc1_clk = {
+ .name = "hsmmc",
+ .devname = "s3c-sdhci.1",
+ .parent = &clk_h,
+ .enable = s3c2443_clkcon_enable_h,
+ .ctrlbit = S3C2443_HCLKCON_HSMMC,
+};
+
static inline unsigned long s3c2443_get_hdiv(unsigned long clkcon0)
{
clkcon0 &= S3C2443_CLKDIV0_HCLKDIV_MASK;
@@ -460,6 +463,7 @@ static struct clk *clks[] __initdata = {
&clk_ext,
&clk_epll,
&clk_usb_bus,
+ &hsmmc1_clk,
};
static struct clksrc_clk *clksrcs[] __initdata = {
@@ -475,6 +479,7 @@ static struct clk_lookup s3c2443_clk_lookup[] = {
CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_esys_uart.clk),
+ CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &hsmmc1_clk),
};
void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
--
1.7.4.4
^ permalink raw reply related
* Update: ARM Sub-Architecture Maintainers workshop at Kernel Summit 2011
From: Catalin Marinas @ 2011-10-12 10:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACxGe6vMLeHrN7jLB2=JYQON1ykOiWTeGiH8YXkUbguV0D-HEw@mail.gmail.com>
Hi Grant,
On Tue, Aug 30, 2011 at 07:00:16AM +0100, Grant Likely wrote:
> Agenda proposals (Thanks to Nicolas and Olof):
> - DT bindings for GPIO and pin mux
> - the pin mux subsystem from linusw (especially if it is still RFC by
> then)
> - progress with the single zImage work
> - presentation/status of the DMA and memory management work wrt CMA
> (some SOC specific hacks should go away once this is available)
> - DT porting progress
> - boot architecture status
> - Report from Arnd on experiences from first arm-soc merge window
> - what worked well and where's room for improvement?
> - Any particular SoC workflow that should be tuned to make his life easier?
> - Where are the gaps where he needs help right now?
> - How did it work out for the SoC maintainers?
Some more thoughts, probably under some of the above topics like single
zImage or boot architecture if there is time on the agenda:
- Errata (CPU, cache controller etc.) workarounds - do we need some
common way to register workarounds that individual SoCs need to be
enabled during boot? With a single zImage platform, we need to enable
as many (CPU) errata workarounds as possible but, even though we check
the CPU revision, we may find that some undocumented bits cannot be
set because Linux is running in non-secure mode (and the secure code
on the SoC doesn't set the bit either) or the SoC already implemented
an ECO fix and the workaround is no longer needed.
- CPU topology - Vincent Guittot proposed patches to automatically
generate a CPU topology based on the MPIDR. I think we should be able
to override this using some DT description (and also be able to
describe the mapping between GIC CPU interfaces and the CPU numbering
via DT).
Unrelated to the above
- Different DMA coherency requirements within the same SoC - this is
linked to the work already started by Marek on dma_map_ops (though the
focus was mainly IOMMU). Basically there are SoCs where some device
requires non-cacheable memory while another device is connected via a
coherency port and can snoop the CPU caches. The arch_is_coherent()
that we currently have is not fine-grained enough for this task.
Thanks.
--
Catalin
^ permalink raw reply
* [PATCH V4 3/3] ARM: SAMSUNG: Add lookup of sdhci-s3c clocks using generic names
From: Sylwester Nawrocki @ 2011-10-12 10:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1318412587-29987-4-git-send-email-rajeshwari.s@samsung.com>
Hi Rajeshwari,
On 10/12/2011 11:43 AM, Rajeshwari Shinde wrote:
> Add support for lookup of sdhci-s3c controller clocks using generic names
> for s3c2416, s3c64xx, s5pc100, s5pv210 and exynos4 SoC's.
>
> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
> ---
> arch/arm/mach-exynos4/clock.c | 88 ++++++++++-------
> arch/arm/mach-s3c2416/clock.c | 68 +++++++------
> arch/arm/mach-s3c64xx/clock.c | 126 +++++++++++++++----------
> arch/arm/mach-s5pc100/clock.c | 130 ++++++++++++++++----------
> arch/arm/mach-s5pv210/clock.c | 167 ++++++++++++++++++++-------------
> arch/arm/plat-s3c24xx/s3c2443-clock.c | 15 ++-
> 6 files changed, 359 insertions(+), 235 deletions(-)
>
> diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c
> index 9f50e33..c6383b9 100644
> --- a/arch/arm/mach-exynos4/clock.c
> +++ b/arch/arm/mach-exynos4/clock.c
> @@ -1157,42 +1157,6 @@ static struct clksrc_clk clksrcs[] = {
> .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 },
> }, {
> .clk = {
> - .name = "sclk_mmc",
> - .devname = "s3c-sdhci.0",
> - .parent = &clk_dout_mmc0.clk,
> - .enable = exynos4_clksrc_mask_fsys_ctrl,
> - .ctrlbit = (1 << 0),
> - },
> - .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
> - }, {
> - .clk = {
> - .name = "sclk_mmc",
> - .devname = "s3c-sdhci.1",
> - .parent = &clk_dout_mmc1.clk,
> - .enable = exynos4_clksrc_mask_fsys_ctrl,
> - .ctrlbit = (1 << 4),
> - },
> - .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
> - }, {
> - .clk = {
> - .name = "sclk_mmc",
> - .devname = "s3c-sdhci.2",
> - .parent = &clk_dout_mmc2.clk,
> - .enable = exynos4_clksrc_mask_fsys_ctrl,
> - .ctrlbit = (1 << 8),
> - },
> - .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
> - }, {
> - .clk = {
> - .name = "sclk_mmc",
> - .devname = "s3c-sdhci.3",
> - .parent = &clk_dout_mmc3.clk,
> - .enable = exynos4_clksrc_mask_fsys_ctrl,
> - .ctrlbit = (1 << 12),
> - },
> - .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
> - }, {
> - .clk = {
> .name = "sclk_dwmmc",
> .parent = &clk_dout_mmc4.clk,
> .enable = exynos4_clksrc_mask_fsys_ctrl,
> @@ -1250,6 +1214,50 @@ static struct clksrc_clk clk_sclk_uart3 = {
> .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
> };
>
> +static struct clksrc_clk clk_sclk_mmc0 = {
> + .clk = {
> + .name = "sclk_mmc",
> + .devname = "s3c-sdhci.0",
Would it make sense to drop this 'devname' field here and others
until sclk_mmc3 ....
> + .parent = &clk_dout_mmc0.clk,
> + .enable = exynos4_clksrc_mask_fsys_ctrl,
> + .ctrlbit = (1 << 0),
> + },
> + .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
> +};
> +
> +static struct clksrc_clk clk_sclk_mmc1 = {
> + .clk = {
> + .name = "sclk_mmc",
> + .devname = "s3c-sdhci.1",
> + .parent = &clk_dout_mmc1.clk,
> + .enable = exynos4_clksrc_mask_fsys_ctrl,
> + .ctrlbit = (1 << 4),
> + },
> + .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
> +};
> +
> +static struct clksrc_clk clk_sclk_mmc2 = {
> + .clk = {
> + .name = "sclk_mmc",
> + .devname = "s3c-sdhci.2",
> + .parent = &clk_dout_mmc2.clk,
> + .enable = exynos4_clksrc_mask_fsys_ctrl,
> + .ctrlbit = (1 << 8),
> + },
> + .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
> +};
> +
> +static struct clksrc_clk clk_sclk_mmc3 = {
> + .clk = {
> + .name = "sclk_mmc",
> + .devname = "s3c-sdhci.3",
> + .parent = &clk_dout_mmc3.clk,
> + .enable = exynos4_clksrc_mask_fsys_ctrl,
> + .ctrlbit = (1 << 12),
> + },
> + .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
> +};
> +
> /* Clock initialization code */
> static struct clksrc_clk *sysclks[] = {
> &clk_mout_apll,
> @@ -1289,6 +1297,10 @@ static struct clksrc_clk *clksrc_cdev[] = {
> &clk_sclk_uart1,
> &clk_sclk_uart2,
> &clk_sclk_uart3,
> + &clk_sclk_mmc0,
> + &clk_sclk_mmc1,
> + &clk_sclk_mmc2,
> + &clk_sclk_mmc3,
..then drop the above 4 lines...
> };
>
> static struct clk_lookup exynos4_clk_lookup[] = {
> @@ -1296,6 +1308,10 @@ static struct clk_lookup exynos4_clk_lookup[] = {
> CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &clk_sclk_uart1.clk),
> CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &clk_sclk_uart2.clk),
> CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &clk_sclk_uart3.clk),
> + CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
> + CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
> + CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
> + CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),
..and add something like:
+ CLKDEV_INIT("s3c-sdhci.0", "sclk_mmc", &clk_sclk_mmc0.clk),
+ CLKDEV_INIT("s3c-sdhci.1", "sclk_mmc", &clk_sclk_mmc1.clk),
+ CLKDEV_INIT("s3c-sdhci.2", "sclk_mmc", &clk_sclk_mmc2.clk),
+ CLKDEV_INIT("s3c-sdhci.3", "sclk_mmc", &clk_sclk_mmc3.clk),
?
Also I'm wondering why we're using different device names for clk_sclk_mmc0..3
clocks, i.e. exynos4-sdhci.? and s3c-sdhci.? ?
Does it all work on exynos ? I would expect the device name to be same
across all the clock definitions, otherwise clk_get(dev, ..) will fail.
> };
>
Regards
--
Sylwester Nawrocki
Samsung Poland R&D Center
^ permalink raw reply
* [PATCH v6 06/16] OMAP2+: UART: Remove certain feilds from omap_uart_state struct
From: Govindraj @ 2011-10-12 10:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <87d3e4ctki.fsf@ti.com>
On Tue, Oct 11, 2011 at 5:01 AM, Kevin Hilman <khilman@ti.com> wrote:
> "Govindraj.R" <govindraj.raja@ti.com> writes:
>
>> Removing some of the uart info that is maintained in omap_uart_state struct
>> used for UART PM in serial.c.
>>
>> Remove omap_uart_state struct dependency from omap_serial_init,
>> omap_serial_init_port, omap_serial_early_init and omap_uart_idle_init
>> functions. ?And populate the same info in omap_uart_port_info struct
>> used as pdata struct.
>
> IMO, this change doesn't belong in this patch and leads to clutter. ?The
> rest of the series slowly removes/replaces all the fields from this
> struct, so the right place to remove it's usage all together is at the
> end of the series when (if) all the fields are no longer needed (or have
> been moved.)
>
Okay will move it to end.
> Stated differently, IMO, this patch should leave the uart->num and
> uart->oh and the list_head (uart->node) alone (probably uart->pdev too)
> and just cleanup the fields that are no longer used. ?Removing num, oh,
> node here causes churn because you're force to change things here that
> are then removed in later patches.
>
okay will retain the list part.
>> Added omap_uart_hwmod_lookup function to look up oh by name used in
>> serial_port_init and omap_serial_early_init functions.
>
> Because of the above change, you now are doing a hwmod lookup 2 times
> for every UART. ?Leaving the uart_list and uart->num in place will avoid
> the need for that change.
>
yes since uart_list was removed, will retain the uart_list
to avoid the look up twice.
>> A list of omap_uart_state was maintained one for each uart, the same
>> is removed. ?Number of uarts available is maintained in num_uarts
>> field, re-use the same in omap_serial_init func to register each uart.
>>
>> Remove omap_info which used details from omap_uart_state and use a
>> pdata pointer to pass platform specific info to driver.
>
> There is no omap_info. ?Did you mean omap_up_info?
yes sorry typo.
>
>> The mapbase (start_address), membase(io_remap cookie) maintained as
>> part of uart_state struct and pdata struct are removed as this is
>> handled within driver.
>
> This part makes sense.
>
okay will retain this part only.
>> Errata field is also moved to pdata.
>
> Why in this patch instead of the subsequent "Move errata handling from
> serial.c to omap-serial" patch?
>
will move to the errata patch.
>> These changes are done to cleanup serial.c file and prepare for
>> runtime changes.
>
> There are a lot of changes in this patch with very little description as
> to why, and many appear to be unrelated. ?They should probably be
> separate patches, or have a better description as to how all the changes
> are related so they belong in the same patch.
>
okay fine will split them into smaller changes.
>> Signed-off-by: Govindraj.R <govindraj.raja@ti.com>
>> ---
>> ?arch/arm/mach-omap2/serial.c ? ? ? ? ? ? ? ? ?| ?132 +++++++++---------------
>> ?arch/arm/plat-omap/include/plat/omap-serial.h | ? ?4 +-
>> ?drivers/tty/serial/omap-serial.c ? ? ? ? ? ? ?| ? 12 ++-
>> ?3 files changed, 61 insertions(+), 87 deletions(-)
>>
>> diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
>> index c98b9b4..8c43d1c 100644
>> --- a/arch/arm/mach-omap2/serial.c
>> +++ b/arch/arm/mach-omap2/serial.c
>> @@ -68,14 +68,6 @@ struct omap_uart_state {
>> ? ? ? int clocked;
>>
>> ? ? ? int regshift;
>> - ? ? void __iomem *membase;
>> - ? ? resource_size_t mapbase;
>> -
>> - ? ? struct list_head node;
>> - ? ? struct omap_hwmod *oh;
>> - ? ? struct platform_device *pdev;
>> -
>> - ? ? u32 errata;
>> ?#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
>> ? ? ? int context_valid;
>>
>> @@ -90,7 +82,6 @@ struct omap_uart_state {
>> ?#endif
>> ?};
>>
>> -static LIST_HEAD(uart_list);
>> ?static u8 num_uarts;
>>
>> ?static int uart_idle_hwmod(struct omap_device *od)
>> @@ -143,7 +134,19 @@ static inline void serial_write_reg(struct omap_uart_state *uart, int offset,
>> ? ? ? __raw_writeb(value, uart->membase + offset);
>> ?}
>>
>> -#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
>> +struct omap_hwmod *omap_uart_hwmod_lookup(int num)
>> +{
>> + ? ? struct omap_hwmod *oh;
>> + ? ? char oh_name[MAX_UART_HWMOD_NAME_LEN];
>> +
>> + ? ? snprintf(oh_name, MAX_UART_HWMOD_NAME_LEN, "uart%d", num + 1);
>> + ? ? oh = omap_hwmod_lookup(oh_name);
>> + ? ? WARN(IS_ERR(oh), "Could not lookup hmwod info for %s\n",
>> + ? ? ? ? ? ? ? ? ? ? oh_name);
>> + ? ? return oh;
>> +}
>> +
>> +#if defined(CONFIG_PM)
>
> The CONFIG_ARCH_OMAP3 part of this #if was dropped with this change with
> no mention as to why. ?(I understand why it was done, but it's not
> releveant to $SUBJECT patch so should be a separate patch.)
>
>> ?/*
>> ? * Work Around for Errata i202 (3430 - 1.12, 3630 - 1.6)
>> @@ -357,22 +360,17 @@ int omap_uart_can_sleep(void)
>> ? ? ? return can_sleep;
>> ?}
>>
>> -static void omap_uart_idle_init(struct omap_uart_state *uart)
>> +static void omap_uart_idle_init(struct omap_uart_port_info *uart,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned short num)
>> ?{
>> - ? ? int ret;
>> -
>> - ? ? uart->can_sleep = 0;
>> - ? ? omap_uart_smart_idle_enable(uart, 0);
>> -
>> ? ? ? if (cpu_is_omap34xx() && !cpu_is_ti816x()) {
>> - ? ? ? ? ? ? u32 mod = (uart->num > 1) ? OMAP3430_PER_MOD : CORE_MOD;
>> + ? ? ? ? ? ? u32 mod = (num > 1) ? OMAP3430_PER_MOD : CORE_MOD;
>> ? ? ? ? ? ? ? u32 wk_mask = 0;
>> ? ? ? ? ? ? ? u32 padconf = 0;
>>
>> - ? ? ? ? ? ? /* XXX These PRM accesses do not belong here */
>
> why?
>
>> ? ? ? ? ? ? ? uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
>> ? ? ? ? ? ? ? uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
>> - ? ? ? ? ? ? switch (uart->num) {
>> + ? ? ? ? ? ? switch (num) {
>> ? ? ? ? ? ? ? case 0:
>> ? ? ? ? ? ? ? ? ? ? ? wk_mask = OMAP3430_ST_UART1_MASK;
>> ? ? ? ? ? ? ? ? ? ? ? padconf = 0x182;
>> @@ -391,12 +389,11 @@ static void omap_uart_idle_init(struct omap_uart_state *uart)
>> ? ? ? ? ? ? ? ? ? ? ? break;
>> ? ? ? ? ? ? ? }
>> ? ? ? ? ? ? ? uart->wk_mask = wk_mask;
>> - ? ? ? ? ? ? uart->padconf = padconf;
>
> The assignment is removed here, making all the rest of the padconf stuff
> that remains useless.
>
> However, a subsequent patch removes the mux stuff entirely, so I suggest
> you just drop this change from here.
>
okay will incorporate this as part of mux changes patch.
>> ? ? ? } else if (cpu_is_omap24xx()) {
>> ? ? ? ? ? ? ? u32 wk_mask = 0;
>> ? ? ? ? ? ? ? u32 wk_en = PM_WKEN1, wk_st = PM_WKST1;
>>
>> - ? ? ? ? ? ? switch (uart->num) {
>> + ? ? ? ? ? ? switch (num) {
>> ? ? ? ? ? ? ? case 0:
>> ? ? ? ? ? ? ? ? ? ? ? wk_mask = OMAP24XX_ST_UART1_MASK;
>> ? ? ? ? ? ? ? ? ? ? ? break;
>> @@ -421,7 +418,6 @@ static void omap_uart_idle_init(struct omap_uart_state *uart)
>> ? ? ? ? ? ? ? uart->wk_en = NULL;
>> ? ? ? ? ? ? ? uart->wk_st = NULL;
>> ? ? ? ? ? ? ? uart->wk_mask = 0;
>> - ? ? ? ? ? ? uart->padconf = 0;
>> ? ? ? }
>> ?}
>>
>> @@ -436,26 +432,13 @@ static void omap_uart_block_sleep(struct omap_uart_state *uart)
>>
>> ?static int __init omap_serial_early_init(void)
>> ?{
>> - ? ? int i = 0;
>> -
>> ? ? ? do {
>> - ? ? ? ? ? ? char oh_name[MAX_UART_HWMOD_NAME_LEN];
>> ? ? ? ? ? ? ? struct omap_hwmod *oh;
>> - ? ? ? ? ? ? struct omap_uart_state *uart;
>>
>> - ? ? ? ? ? ? snprintf(oh_name, MAX_UART_HWMOD_NAME_LEN,
>> - ? ? ? ? ? ? ? ? ? ? ?"uart%d", i + 1);
>> - ? ? ? ? ? ? oh = omap_hwmod_lookup(oh_name);
>> + ? ? ? ? ? ? oh = omap_uart_hwmod_lookup(num_uarts);
>> ? ? ? ? ? ? ? if (!oh)
>> ? ? ? ? ? ? ? ? ? ? ? break;
>>
>> - ? ? ? ? ? ? uart = kzalloc(sizeof(struct omap_uart_state), GFP_KERNEL);
>> - ? ? ? ? ? ? if (WARN_ON(!uart))
>> - ? ? ? ? ? ? ? ? ? ? return -ENODEV;
>> -
>> - ? ? ? ? ? ? uart->oh = oh;
>> - ? ? ? ? ? ? uart->num = i++;
>> - ? ? ? ? ? ? list_add_tail(&uart->node, &uart_list);
>> ? ? ? ? ? ? ? num_uarts++;
>>
>> ? ? ? ? ? ? ? /*
>> @@ -468,7 +451,7 @@ static int __init omap_serial_early_init(void)
>> ? ? ? ? ? ? ? ?* to determine SoC specific init before omap_device
>> ? ? ? ? ? ? ? ?* is ready. ?Therefore, don't allow idle here
>> ? ? ? ? ? ? ? ?*/
>> - ? ? ? ? ? ? uart->oh->flags |= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET;
>> + ? ? ? ? ? ? oh->flags |= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET;
>> ? ? ? } while (1);
>>
>> ? ? ? return 0;
>> @@ -488,57 +471,47 @@ core_initcall(omap_serial_early_init);
>> ? */
>> ?void __init omap_serial_init_port(struct omap_board_data *bdata)
>> ?{
>> - ? ? struct omap_uart_state *uart;
>> ? ? ? struct omap_hwmod *oh;
>> ? ? ? struct platform_device *pdev;
>> - ? ? void *pdata = NULL;
>> + ? ? char *name = DRIVER_NAME;
>> + ? ? struct omap_uart_port_info *pdata;
>> ? ? ? u32 pdata_size = 0;
>> - ? ? char *name;
>> - ? ? struct omap_uart_port_info omap_up;
>>
>> ? ? ? if (WARN_ON(!bdata))
>> ? ? ? ? ? ? ? return;
>> ? ? ? if (WARN_ON(bdata->id < 0))
>> ? ? ? ? ? ? ? return;
>> - ? ? if (WARN_ON(bdata->id >= num_uarts))
>> + ? ? if (WARN_ON(bdata->id >= OMAP_MAX_HSUART_PORTS))
>
> why? ?because of early_init, num_uarts is already the max number
> of UARTs available (based on hwmod probe.)
>
yes will correct this and use num_uarts
>> ? ? ? ? ? ? ? return;
>>
>> - ? ? list_for_each_entry(uart, &uart_list, node)
>> - ? ? ? ? ? ? if (bdata->id == uart->num)
>> - ? ? ? ? ? ? ? ? ? ? break;
>> -
>> - ? ? oh = uart->oh;
>> - ? ? uart->dma_enabled = 0;
>> - ? ? name = DRIVER_NAME;
>> + ? ? oh = omap_uart_hwmod_lookup(bdata->id);
>> + ? ? if (!oh)
>> + ? ? ? ? ? ? return;
>>
>> - ? ? omap_up.dma_enabled = uart->dma_enabled;
>> - ? ? omap_up.uartclk = OMAP24XX_BASE_BAUD * 16;
>> - ? ? omap_up.mapbase = oh->slaves[0]->addr->pa_start;
>> - ? ? omap_up.membase = omap_hwmod_get_mpu_rt_va(oh);
>> - ? ? omap_up.flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
>> + ? ? pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
>> + ? ? if (!pdata) {
>> + ? ? ? ? ? ? pr_err("Memory allocation for UART pdata failed\n");
>> + ? ? ? ? ? ? return;
>> + ? ? }
>>
>> - ? ? pdata = &omap_up;
>> ? ? ? pdata_size = sizeof(struct omap_uart_port_info);
>> + ? ? omap_uart_idle_init(pdata, bdata->id);
>
> Why was this moved here?
>
> ISTR that the order of this call relative to the hwmod/omap_device
> enable/disable calls below was important, especially in the DEBUG_LL
> case.
>
>> - ? ? if (WARN_ON(!oh))
>> - ? ? ? ? ? ? return;
>> + ? ? pdata->uartclk = OMAP24XX_BASE_BAUD * 16;
>> + ? ? pdata->flags = UPF_BOOT_AUTOCONF;
>> +
>> + ? ? /* Enable the MDR1 errata for OMAP3 */
>> + ? ? if (cpu_is_omap34xx() && !cpu_is_ti816x())
>> + ? ? ? ? ? ? pdata->errata |= UART_ERRATA_i202_MDR1_ACCESS;
>>
>> - ? ? pdev = omap_device_build(name, uart->num, oh, pdata, pdata_size,
>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ?omap_uart_latency,
>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ?ARRAY_SIZE(omap_uart_latency), false);
>> + ? ? pdev = omap_device_build(name, bdata->id, oh, pdata,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? pdata_size, omap_uart_latency,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ARRAY_SIZE(omap_uart_latency), false);
>
> Note the unecesary whitespace changes in this change.
>
>> ? ? ? WARN(IS_ERR(pdev), "Could not build omap_device for %s: %s.\n",
>> ? ? ? ? ? ?name, oh->name);
>>
>> - ? ? omap_device_disable_idle_on_suspend(pdev);
>
> This should also be a separate patch at the end of the series, and is
> not related to the changes described in the changelog.
>
okay.
>> ? ? ? oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
>>
>> - ? ? uart->regshift = 2;
>> - ? ? uart->mapbase = oh->slaves[0]->addr->pa_start;
>> - ? ? uart->membase = omap_hwmod_get_mpu_rt_va(oh);
>> - ? ? uart->pdev = pdev;
>> -
>> - ? ? oh->dev_attr = uart;
>> -
>> ? ? ? console_lock(); /* in case the earlycon is on the UART */
>>
>> ? ? ? /*
>> @@ -546,23 +519,18 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
>> ? ? ? ?* on init. ?Now that omap_device is ready, ensure full idle
>> ? ? ? ?* before doing omap_device_enable().
>> ? ? ? ?*/
>> - ? ? omap_hwmod_idle(uart->oh);
>> + ? ? omap_hwmod_idle(oh);
>>
>> - ? ? omap_device_enable(uart->pdev);
>> - ? ? omap_uart_idle_init(uart);
>> - ? ? omap_hwmod_enable_wakeup(uart->oh);
>> - ? ? omap_device_idle(uart->pdev);
>> + ? ? omap_device_enable(pdev);
>> + ? ? omap_hwmod_enable_wakeup(oh);
>>
>> - ? ? omap_uart_block_sleep(uart);
>> ? ? ? console_unlock();
>>
>> - ? ? if ((cpu_is_omap34xx() && uart->padconf) ||
>> - ? ? ? ? (uart->wk_en && uart->wk_mask))
>> + ? ? if ((cpu_is_omap34xx() && bdata->pads) ||
>> + ? ? ? ? ? ? (pdata->wk_en && pdata->wk_mask))
>
> This change seems to belong as part of the mux patch.
>
okay moving to mux change patch.
>> ? ? ? ? ? ? ? device_init_wakeup(&pdev->dev, true);
>>
>> - ? ? /* Enable the MDR1 errata for OMAP3 */
>> - ? ? if (cpu_is_omap34xx() && !cpu_is_ti816x())
>> - ? ? ? ? ? ? uart->errata |= UART_ERRATA_i202_MDR1_ACCESS;
>> + ? ? kfree(pdata);
>> ?}
>>
>> ?/**
>> @@ -574,11 +542,11 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
>> ? */
>> ?void __init omap_serial_init(void)
>> ?{
>> - ? ? struct omap_uart_state *uart;
>> ? ? ? struct omap_board_data bdata;
>> + ? ? u8 i;
>>
>> - ? ? list_for_each_entry(uart, &uart_list, node) {
>> - ? ? ? ? ? ? bdata.id = uart->num;
>> + ? ? for (i = 0; i < num_uarts; i++) {
>> + ? ? ? ? ? ? bdata.id = i;
>> ? ? ? ? ? ? ? bdata.flags = 0;
>> ? ? ? ? ? ? ? bdata.pads = NULL;
>> ? ? ? ? ? ? ? bdata.pads_cnt = 0;
>> diff --git a/arch/arm/plat-omap/include/plat/omap-serial.h b/arch/arm/plat-omap/include/plat/omap-serial.h
>> index 307cd6f..0f061b4 100644
>> --- a/arch/arm/plat-omap/include/plat/omap-serial.h
>> +++ b/arch/arm/plat-omap/include/plat/omap-serial.h
>> @@ -59,9 +59,9 @@
>> ?struct omap_uart_port_info {
>> ? ? ? bool ? ? ? ? ? ? ? ? ? ?dma_enabled; ? ?/* To specify DMA Mode */
>> ? ? ? unsigned int ? ? ? ? ? ?uartclk; ? ? ? ?/* UART clock rate */
>> - ? ? void __iomem ? ? ? ? ? ?*membase; ? ? ? /* ioremap cookie or NULL */
>> - ? ? resource_size_t ? ? ? ? mapbase; ? ? ? ?/* resource base */
>> ? ? ? upf_t ? ? ? ? ? ? ? ? ? flags; ? ? ? ? ?/* UPF_* flags */
>> +
>> + ? ? u32 ? ? ? ? ? ? ? ? ? ? errata;
>> ?};
>>
>> ?struct uart_omap_dma {
>> diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
>> index 5e713d3..6c2ea54 100644
>> --- a/drivers/tty/serial/omap-serial.c
>> +++ b/drivers/tty/serial/omap-serial.c
>> @@ -1275,10 +1275,16 @@ static int serial_omap_probe(struct platform_device *pdev)
>> ? ? ? up->port.ops = &serial_omap_pops;
>> ? ? ? up->port.line = pdev->id;
>>
>> - ? ? up->port.membase = omap_up_info->membase;
>> - ? ? up->port.mapbase = omap_up_info->mapbase;
>> + ? ? up->port.mapbase = mem->start;
>> + ? ? up->port.membase = ioremap(mem->start, resource_size(mem));
>> +
>> + ? ? if (!up->port.membase) {
>> + ? ? ? ? ? ? dev_err(&pdev->dev, "can't ioremap UART\n");
>> + ? ? ? ? ? ? ret = -ENOMEM;
>> + ? ? ? ? ? ? goto err;
>> + ? ? }
>> +
>> ? ? ? up->port.flags = omap_up_info->flags;
>> - ? ? up->port.irqflags = omap_up_info->irqflags;
>> ? ? ? up->port.uartclk = omap_up_info->uartclk;
>> ? ? ? up->uart_dma.uart_base = mem->start;
>
> Kevin
> --
> To unsubscribe from this list: send the line "unsubscribe linux-serial" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at ?http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply
* [PATCH] mmc: mmci: Do not release spinlock in request_end
From: Adrian Hunter @ 2011-10-12 10:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACRpkdb5pn=q+hQSsrTgKbCvuKR83vHn1iAfvzMFXQeAgv--+Q@mail.gmail.com>
On 12/10/11 12:41, Linus Walleij wrote:
> On Tue, Oct 11, 2011 at 4:06 PM, Ulf Hansson <ulf.hansson@stericsson.com> wrote:
>
>> The patch "mmc: core: move ->request() call from atomic context",
>> is the reason to why this change is possible. This simplifies the
>> error handling code execution path quite a lot and potentially also
>> fixes some error handling hang problems.
>>
>> Signed-off-by: Ulf Hansson <ulf.hansson@stericsson.com>
>
> Adrian do you agree with this?
Yes
>
> To me it looks correct,
> Acked-by: Linus Walleij <linus.walleij@linaro.org>
>
> Yours,
> Linus Walleij
^ permalink raw reply
* [PATCH v6 09/16] OMAP2+: UART: Add runtime pm support for omap-serial driver
From: Govindraj @ 2011-10-12 10:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <87botobdtq.fsf@ti.com>
On Tue, Oct 11, 2011 at 5:26 AM, Kevin Hilman <khilman@ti.com> wrote:
> "Govindraj.R" <govindraj.raja@ti.com> writes:
>
>> Adapts omap-serial driver to use pm_runtime API's.
>>
>> Use runtime runtime API's to handle uart clocks and obtain
>> device_usage statics. Set runtime API's usage to irq_safe so that
>> we can use get_sync from irq context. Auto-suspend for port specific
>> activities and put for reg access. Use device_may_wakeup to check
>> whether uart has wakeup capabilities and then enable uart runtime
>> usage for the uart.
>
> OK. ?Current patch should do only this part. ?The rest should be
> separate patches with their own descriptive changelogs.
>
Yes, started splitting them.
>> Removing save_context/restore_context functions from serial.c
>> Adding context restore to .runtime_suspend and using reg values from port
>> structure to restore the uart port context based on context_loss_count.
>> Maintain internal state machine using wakeups_enabled field for avoiding
>> repeated enable/disable of uart port wakeup mechanism.
>
> This part should be a separate patch that follows.
>
okay,
>> Remove omap_uart_disable_wakeup and modify omap_uart_enable_wakeup
>> to accept pdev and bool value to enable/disable the uart wakeup mechanism
>> after uart clock's are cut.
>>
>> omap_hwmod_enable_wakeup is used to set
>> pad wakeup for the uarts. PM_WKEN reg values are left to default.
>> Removed omap_uart_enable/disable_clocks in serial.c now clock handling
>> done with runtime API's.
>
> As stated in previous reviews, this wakeup enable/disable needs more
> description as the functionality is changing compared to current code.
>
> Current version modifies wakeup enable/disable at both power-domain
> level (PM_WKEN) and at the IO ring.
>
> Updated version modifies wakeups at module-level (SYSCONFIG) and at IO
> ring using omap_hwmod_enable_wakeup()
>
> IMO, the updated version makes more sense, but needs a description as to
> why that change in functionality will have equivalent results compared
> to the existing one.
>
Okay,
>> By default uart autosuspend delay is set to -1 to avoid character loss
>> if uart's are autoidled and woken up on rx pin.
>
> OK, good.
>
>> After boot up UART's can be autoidled by setting autosuspendi delay from sysfs.
>>
>> echo 3000 > /sys/devices/platform/omap/omap_uart.X/power/autosuspend_delay_ms
>> X=0,1,2,3 for UART1/2/3/4. Number of uarts available may vary across omap_soc.
>>
>> Acked-by: Alan Cox <alan@linux.intel.com>
>> Signed-off-by: Govindraj.R <govindraj.raja@ti.com>
>
> Kevin
> --
> To unsubscribe from this list: send the line "unsubscribe linux-serial" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at ?http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply
* [PATCH v6 09/16] OMAP2+: UART: Add runtime pm support for omap-serial driver
From: Govindraj @ 2011-10-12 10:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <8739f0ct2o.fsf@ti.com>
On Tue, Oct 11, 2011 at 5:12 AM, Kevin Hilman <khilman@ti.com> wrote:
> "Govindraj.R" <govindraj.raja@ti.com> writes:
>
>> Adapts omap-serial driver to use pm_runtime API's.
>
> [...]
>
>> @@ -1065,19 +1123,18 @@ static struct uart_driver serial_omap_reg = {
>> ? ? ? .cons ? ? ? ? ? = OMAP_CONSOLE,
>> ?};
>>
>> -static int
>> -serial_omap_suspend(struct platform_device *pdev, pm_message_t state)
>> +static int serial_omap_suspend(struct device *dev)
>> ?{
>> - ? ? struct uart_omap_port *up = platform_get_drvdata(pdev);
>> + ? ? struct uart_omap_port *up = dev_get_drvdata(dev);
>>
>> ? ? ? if (up)
>> ? ? ? ? ? ? ? uart_suspend_port(&serial_omap_reg, &up->port);
>> ? ? ? return 0;
>> ?}
>>
>> -static int serial_omap_resume(struct platform_device *dev)
>> +static int serial_omap_resume(struct device *dev)
>> ?{
>> - ? ? struct uart_omap_port *up = platform_get_drvdata(dev);
>> + ? ? struct uart_omap_port *up = dev_get_drvdata(dev);
>>
>> ? ? ? if (up)
>> ? ? ? ? ? ? ? uart_resume_port(&serial_omap_reg, &up->port);
>
> These functions need to be wrapped in #ifdef CONFIG_SUSPEND, otherwise,
> when building with !CONFIG_SUSPEND you'll get :
>
> /work/kernel/omap/pm/drivers/tty/serial/omap-serial.c:1134:12: warning: 'serial_omap_suspend' defined but not used
> /work/kernel/omap/pm/drivers/tty/serial/omap-serial.c:1150:12: warning: 'serial_omap_resume' defined but not used
>
>
> [...]
>
>> +static int serial_omap_runtime_suspend(struct device *dev)
>> +{
>> + ? ? struct uart_omap_port *up = dev_get_drvdata(dev);
>> + ? ? struct omap_uart_port_info *pdata = dev->platform_data;
>> +
>> + ? ? if (!up)
>> + ? ? ? ? ? ? return -EINVAL;
>> +
>> + ? ? if (!pdata->enable_wakeup || !pdata->get_context_loss_count)
>> + ? ? ? ? ? ? return 0;
>> +
>> + ? ? if (pdata->get_context_loss_count)
>> + ? ? ? ? ? ? up->context_loss_cnt = pdata->get_context_loss_count(dev);
>> +
>> + ? ? if (device_may_wakeup(dev)) {
>> + ? ? ? ? ? ? if (!up->wakeups_enabled) {
>> + ? ? ? ? ? ? ? ? ? ? pdata->enable_wakeup(up->pdev, true);
>> + ? ? ? ? ? ? ? ? ? ? up->wakeups_enabled = true;
>> + ? ? ? ? ? ? }
>> + ? ? } else {
>> + ? ? ? ? ? ? if (up->wakeups_enabled) {
>> + ? ? ? ? ? ? ? ? ? ? pdata->enable_wakeup(up->pdev, false);
>> + ? ? ? ? ? ? ? ? ? ? up->wakeups_enabled = false;
>> + ? ? ? ? ? ? }
>> + ? ? }
>> +
>> + ? ? return 0;
>> +}
>> +
>> +static int serial_omap_runtime_resume(struct device *dev)
>> +{
>> + ? ? struct uart_omap_port *up = dev_get_drvdata(dev);
>> + ? ? struct omap_uart_port_info *pdata = dev->platform_data;
>> +
>> + ? ? if (up) {
>> + ? ? ? ? ? ? if (pdata->get_context_loss_count) {
>> + ? ? ? ? ? ? ? ? ? ? u32 loss_cnt = pdata->get_context_loss_count(dev);
>> +
>> + ? ? ? ? ? ? ? ? ? ? if (up->context_loss_cnt != loss_cnt)
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? serial_omap_restore_context(up);
>> + ? ? ? ? ? ? }
>> + ? ? }
>> +
>> ? ? ? return 0;
>> ?}
>
> Similarily, thse need to be wrapped with #ifdef CONFIG_PM_RUNTIME,
> otherwise, when !CONFIG_PM_RUNTIME:
>
> /work/kernel/omap/pm/drivers/tty/serial/omap-serial.c:1498:12: warning: 'serial_omap_runtime_suspend' defined but not used
> /work/kernel/omap/pm/drivers/tty/serial/omap-serial.c:1531:12: warning: 'serial_omap_runtime_resume' defined but not used
>
>> +static const struct dev_pm_ops serial_omap_dev_pm_ops = {
>> + ? ? SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
>> + ? ? SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? serial_omap_runtime_resume, NULL)
>> +};
>> +
>
> Note that you don't need #else parts to the above #ifdefs since
> the SET_*_OPS() macros used here take care of that.
>
Yes fine, Corrected
Thanks for catching this.
--
Govindraj.R
^ permalink raw reply
* [PATCH v6 11/16] OMAP2+: UART: Move errata handling from serial.c to omap-serial
From: Govindraj @ 2011-10-12 10:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <871uuj1bvk.fsf@ti.com>
On Wed, Oct 12, 2011 at 2:31 AM, Kevin Hilman <khilman@ti.com> wrote:
> "Govindraj.R" <govindraj.raja@ti.com> writes:
>
>> Move the errata handling mechanism from serial.c to omap-serial file
>> and utilise the same func in driver file.
>>
>> Errata i202, i291 are moved to be handled with omap-serial
>> Moving the errata macro from serial.c file to driver header file
>> as from on errata will be handled in driver file itself.
>>
>> Corrected errata id from chapter reference 2.15 to errata id i291.
>>
>> Acked-by: Alan Cox <alan@linux.intel.com>
>> Signed-off-by: Govindraj.R <govindraj.raja@ti.com>
>
> The errata handling for i291 is moved from device code to driver code
> but it's functionality is also changed (but not described.)
>
> In the current mainline code, The workaround for i291 is done whenever
> UART clocks are about to be cut. ?When the clocks are (re)enabled, the
> device is put back into no-idle.
>
> This patch puts the device into force-idle just before the idle/suspend
> transistion, but never puts it back into no-idle. ?So after the first
> idle/suspend transition, the IP remains in force-idle forever. ?I don't
> think that's what we want.
>
I was thinking no_idle will be done once we re-enable uart clocks
from omap_device_enable but that's not the case looking into the code.
Will correct it will add no_idle call from .runtime_resume as done early
where we put into no_idle(sysc) while enabling the clocks.
--
Thanks,
Govindraj.R
^ permalink raw reply
* [PATCH v6 12/16] OMAP2+: UART: Allow UART parameters to be configured from board file.
From: Govindraj @ 2011-10-12 10:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <878vor2wd0.fsf@ti.com>
On Wed, Oct 12, 2011 at 12:23 AM, Kevin Hilman <khilman@ti.com> wrote:
> "Govindraj.R" <govindraj.raja@ti.com> writes:
>
>> From: Deepak K <deepak.k@ti.com>
>>
>> The following UART parameters are defined within the UART driver:
>>
>> 1). Whether the UART uses DMA (dma_enabled), by default set to 0
>> 2). The size of dma buffer (set to 4096 bytes)
>> 3). The time after which the dma should stop if no more data is received.
>> 4). The auto suspend delay that will be passed for pm_runtime_autosuspend
>> ? ? where uart will be disabled after timeout
>>
>> Different UARTs may be used for different purpose such as the console,
>> for interfacing bluetooth chip, for interfacing to a modem chip, etc.
>> Therefore, it is necessary to be able to customize the above settings
>> for a given board on a per UART basis.
>>
>> This change allows these parameters to be configured from the board file
>> and allows the parameters to be configured for each UART independently.
>>
>> If a board does not define its own custom parameters for the UARTs, then
>> use the default parameters in the structure "omap_serial_default_info".
>> The default parameters are defined to be the same as the current settings
>> in the UART driver to avoid breaking the UART for any cuurnelty supported
>> boards. By default, make all boards use the default UART parameters.
>>
>> Signed-off-by: Deepak K <deepak.k@ti.com>
>> Signed-off-by: Jon Hunter <jon-hunter@ti.com>
>> Signed-off-by: Govindraj.R <govindraj.raja@ti.com>
>
> A couple minor comments below...
>
>> ---
>> This patch is derived and reworked from a custom 2.6.35 kernel
>> Available here:
>> http://git.omapzoom.org/?p=kernel/omap.git;
>> a=commitdiff;h=584ef316542f77312be7ba96a0f3013c8f64852b;
>> hp=7233a76cb362c0fc603f773274159adff91d3513
>>
>> ?arch/arm/mach-omap2/board-n8x0.c ? ? ? ? ? ? ?| ? ?6 +-
>> ?arch/arm/mach-omap2/serial.c ? ? ? ? ? ? ? ? ?| ? 56 ++++++++++++++++++++----
>> ?arch/arm/plat-omap/include/plat/omap-serial.h | ? ?7 ++-
>> ?arch/arm/plat-omap/include/plat/serial.h ? ? ?| ? ?5 ++-
>> ?drivers/tty/serial/omap-serial.c ? ? ? ? ? ? ?| ? ?8 +--
>> ?5 files changed, 61 insertions(+), 21 deletions(-)
>>
>> diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
>> index e11f0c5..3408726 100644
>> --- a/arch/arm/mach-omap2/board-n8x0.c
>> +++ b/arch/arm/mach-omap2/board-n8x0.c
>> @@ -656,15 +656,15 @@ static inline void board_serial_init(void)
>> ? ? ? bdata.pads_cnt = 0;
>>
>> ? ? ? bdata.id = 0;
>> - ? ? omap_serial_init_port(&bdata);
>> + ? ? omap_serial_init_port(&bdata, NULL);
>>
>> ? ? ? bdata.id = 1;
>> - ? ? omap_serial_init_port(&bdata);
>> + ? ? omap_serial_init_port(&bdata, NULL);
>>
>> ? ? ? bdata.id = 2;
>> ? ? ? bdata.pads = serial2_pads;
>> ? ? ? bdata.pads_cnt = ARRAY_SIZE(serial2_pads);
>> - ? ? omap_serial_init_port(&bdata);
>> + ? ? omap_serial_init_port(&bdata, NULL);
>> ?}
>>
>> ?#else
>> diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
>> index 0731575..78f7051 100644
>> --- a/arch/arm/mach-omap2/serial.c
>> +++ b/arch/arm/mach-omap2/serial.c
>> @@ -43,17 +43,29 @@
>> ?#include "mux.h"
>>
>> ?/*
>> - * NOTE: By default the serial timeout is disabled as it causes lost characters
>> - * over the serial ports. This means that the UART clocks will stay on until
>> - * disabled via sysfs. This also causes that any deeper omap sleep states are
>> - * blocked.
>> + * NOTE: By default the serial auto_suspend timeout is disabled as it causes
>> + * lost characters over the serial ports. This means that the UART clocks will
>> + * stay on until power/autosuspend_delay is set for the uart from sysfs.
>> + * This also causes that any deeper omap sleep states are blocked.
>> ? */
>> -#define DEFAULT_TIMEOUT 0
>> +#define DEFAULT_AUTOSUSPEND_DELAY ? ?-1
>>
>> ?#define MAX_UART_HWMOD_NAME_LEN ? ? ? ? ? ? ?16
>>
>> ?static u8 num_uarts;
>>
>> +#define DEFAULT_RXDMA_TIMEOUT ? ? ? ? ? ? ? ?1 ? ? ? /* RX DMA polling rate (us) */
>> +#define DEFAULT_RXDMA_BUFSIZE ? ? ? ? ? ? ? ?4096 ? ?/* RX DMA buffer size */
>> +
>> +static struct omap_uart_port_info omap_serial_default_info[] = {
>
> This could be __initdata
>
yes correct, will change this.
>> + ? ? {
>> + ? ? ? ? ? ? .dma_enabled ? ?= 0,
>
> This field is a bool, use 'false' instead of 0.
yes fine.
>
>> + ? ? ? ? ? ? .dma_rx_buf_size = DEFAULT_RXDMA_BUFSIZE,
>> + ? ? ? ? ? ? .dma_rx_timeout = DEFAULT_RXDMA_TIMEOUT,
>> + ? ? ? ? ? ? .autosuspend_timeout = DEFAULT_AUTOSUSPEND_DELAY,
>> + ? ? },
>> +};
>> +
>> ?static int uart_idle_hwmod(struct omap_device *od)
>> ?{
>> ? ? ? omap_hwmod_idle(od->hwmods[0]);
>> @@ -298,6 +310,7 @@ core_initcall(omap_serial_early_init);
>> ?/**
>> ? * omap_serial_init_port() - initialize single serial port
>> ? * @bdata: port specific board data pointer
>> + * @info: platform specific data pointer
>> ? *
>> ? * This function initialies serial driver for given port only.
>> ? * Platforms can call this function instead of omap_serial_init()
>> @@ -306,7 +319,8 @@ core_initcall(omap_serial_early_init);
>> ? * Don't mix calls to omap_serial_init_port() and omap_serial_init(),
>> ? * use only one of the two.
>> ? */
>> -void __init omap_serial_init_port(struct omap_board_data *bdata)
>> +void __init omap_serial_init_port(struct omap_board_data *bdata,
>> + ? ? ? ? ? ? ? ? ? ? struct omap_uart_port_info *info)
>
> alignment. ?2nd argument should align with 1st
>
>> ?{
>> ? ? ? struct omap_hwmod *oh;
>> ? ? ? struct platform_device *pdev;
>> @@ -325,6 +339,9 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
>> ? ? ? if (!oh)
>> ? ? ? ? ? ? ? return;
>>
>> + ? ? if (info == NULL)
>
> if (!info)
>
> there's another one of these elsewhere in the patch too.
>
will check and correct.
--
Thanks,
Govindraj.R
^ permalink raw reply
* [PATCH] fixup: mm: alloc_contig_range: increase min_free_kbytes during allocation
From: Marek Szyprowski @ 2011-10-12 11:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4E93F088.60006@stericsson.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
mm/page_alloc.c | 15 ++++++++++++---
1 files changed, 12 insertions(+), 3 deletions(-)
Hello Maxime,
Please check if this patch fixes your lockup issue. It is a bit cruel,
but it looks that in case of real low-memory situation page allocation
is very complex task which usually ends in waiting for the io/fs and
free pages that really don't arrive at all.
Best regards
--
Marek Szyprowski
Samsung Poland R&D Center
diff --git a/mm/page_alloc.c b/mm/page_alloc.c
index 055aa4c..45473e9 100644
--- a/mm/page_alloc.c
+++ b/mm/page_alloc.c
@@ -5872,6 +5872,7 @@ int alloc_contig_range(unsigned long start, unsigned long end,
gfp_t flags, unsigned migratetype)
{
unsigned long outer_start, outer_end;
+ unsigned int count = end - start;
int ret;
/*
@@ -5900,7 +5901,10 @@ int alloc_contig_range(unsigned long start, unsigned long end,
ret = __start_isolate_page_range(pfn_to_maxpage(start),
pfn_to_maxpage_up(end), migratetype);
if (ret)
- goto done;
+ return ret;
+
+ min_free_kbytes += count * PAGE_SIZE / 1024;
+ setup_per_zone_wmarks();
ret = __alloc_contig_migrate_range(start, end);
if (ret)
@@ -5922,8 +5926,10 @@ int alloc_contig_range(unsigned long start, unsigned long end,
ret = 0;
while (!PageBuddy(pfn_to_page(start & (~0UL << ret))))
- if (WARN_ON(++ret >= MAX_ORDER))
- return -EINVAL;
+ if (WARN_ON(++ret >= MAX_ORDER)) {
+ ret = -EINVAL;
+ goto done;
+ }
outer_start = start & (~0UL << ret);
outer_end = alloc_contig_freed_pages(outer_start, end, flags);
@@ -5936,6 +5942,9 @@ int alloc_contig_range(unsigned long start, unsigned long end,
ret = 0;
done:
+ min_free_kbytes -= count * PAGE_SIZE / 1024;
+ setup_per_zone_wmarks();
+
__undo_isolate_page_range(pfn_to_maxpage(start), pfn_to_maxpage_up(end),
migratetype);
return ret;
--
1.7.1.569.g6f426
^ permalink raw reply related
* [PATCH v6 14/16] OMAP2+: UART: Take console_lock in suspend path if not taken
From: Govindraj @ 2011-10-12 11:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <87sjmz1hfm.fsf@ti.com>
On Wed, Oct 12, 2011 at 12:31 AM, Kevin Hilman <khilman@ti.com> wrote:
> "Govindraj.R" <govindraj.raja@ti.com> writes:
>
>> In suspend path the console_lock is taken by uart_port_suspend
>> however when no_console_suspend is used console_lock is not taken.
>>
>> During system wide suspend omap_pwr_domain hooks cut all
>> clocks that are left enabled. So its unsafe to proceed printing after
>> clocks are cut by pwr_domain hooks.
>
> As I've mentioned in previous reviews, when no_console_suspend is
> enabled, the user has explicitly requested console output during
> suspend. ?In order to support that, we should not be cutting clocks at
> all in that mode.
>
> One way to address this would be to just disable runtime PM in the
> ->prepare method of the driver if no_console_suspend is enabled.
>
Okay fine exploring this option, right API's would be to use
pm_runtime_forbid/allow.
<<SNIP>>
+static int serial_omap_runtime_prepare(struct device *dev)
+{
+ if (!console_suspend_enabled)
+ pm_runtime_forbid(dev);
+
+ return 0;
+}
+
+static void serial_omap_runtime_complete(struct device *dev)
+{
+ if (!console_suspend_enabled)
+ pm_runtime_allow(dev);
+}
+
static const struct dev_pm_ops serial_omap_dev_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
serial_omap_runtime_resume, NULL)
+ .prepare = serial_omap_runtime_prepare,
+ .complete = serial_omap_runtime_complete,
};
<<SNIP>>
But to either use runtime forbid or disable we have ensure that
power_domain hooks don't go ahead and disable
the clocks with omap_device_idle as *runtime forbid or disable will
not set runtime_status to RPM_SUSPENDED*
and will stay in RPM_ACTIVE if we call runtime disable or forbid from
active state.
in power_domain hooks we just check the pm_runtime_status_suspended
this will be false even if
we do runtime disable/forbid and it will cut uart clocks always.
So we may need below check also:
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index 26aee5c..286a534 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -592,7 +592,8 @@ static int _od_suspend_noirq(struct device *dev)
ret = pm_generic_suspend_noirq(dev);
- if (!ret && !pm_runtime_status_suspended(dev)) {
+ if (!ret && pm_runtime_enabled(dev) &&
+ !pm_runtime_status_suspended(dev)) {
if (pm_generic_runtime_suspend(dev) == 0) {
omap_device_idle(pdev);
od->flags |= OMAP_DEVICE_SUSPENDED;
--
Thanks,
Govindraj.R
^ permalink raw reply related
* [RFT/PATCH 7/7] arm: omap: smartreflex: micro-optimization for sanity check
From: Sergei Shtylyov @ 2011-10-12 11:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20111011121922.GM10155@legolas.emea.dhcp.ti.com>
Hello.
On 11-10-2011 16:19, Felipe Balbi wrote:
>> On 10-10-2011 16:26, Felipe Balbi wrote:
>>> val&& (val != 1) == val> 1
>>> Signed-off-by: Felipe Balbi<balbi@ti.com>
>>> ---
>>> arch/arm/mach-omap2/smartreflex.c | 2 +-
>>> 1 files changed, 1 insertions(+), 1 deletions(-)
>>> diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
>>> index 7bdabfa..4b0d6a8 100644
>>> --- a/arch/arm/mach-omap2/smartreflex.c
>>> +++ b/arch/arm/mach-omap2/smartreflex.c
>>> @@ -866,7 +866,7 @@ static int omap_sr_autocomp_store(void *data, u64 val)
>>> }
>>>
>>> /* Sanity check */
>>> - if (val&& (val != 1)) {
>>> + if (val> 1) {
>>> pr_warning("%s: Invalid argument %lld\n", __func__, val);
>> The format specified should be "%llu"?
> and what does that have to do with $SUBJECT ??
Well, nothing. Just an idea for another patch I guess.
WBR, Sergei
^ permalink raw reply
* [PATCH] ARM: zImage: Use $(CROSS_COMPILE)size to get .bss size
From: Thomas Weber @ 2011-10-12 11:33 UTC (permalink / raw)
To: linux-arm-kernel
Use $(CROSS_COMPILE)size to determine the bss size
from vmlinux.
The problem is introduced in:
commit 8738646c02064d38f6fb056eb039ebf9138c5434
ARM: zImage: make sure appended DTB doesn't get
overwritten by kernel .bss
This fixes following error message:
size: arch/arm/boot/compressed/../../../../vmlinux:
File format is ambiguous
size: Matching formats:
elf32-littlearm
elf32-littlearm-symbian
elf32-littlearm-vxworks
Signed-off-by: Thomas Weber <weber@corscience.de>
---
arch/arm/boot/compressed/Makefile | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index e4f32a8..3103632 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -126,7 +126,7 @@ ccflags-y := -fpic -fno-builtin -I$(obj)
asflags-y := -Wa,-march=all
# Supply kernel BSS size to the decompressor via a linker symbol.
-KBSS_SZ = $(shell size $(obj)/../../../../vmlinux | awk 'END{print $$3}')
+KBSS_SZ = $(shell $(CROSS_COMPILE)size $(obj)/../../../../vmlinux | awk 'END{print $$3}')
LDFLAGS_vmlinux = --defsym _kernel_bss_size=$(KBSS_SZ)
# Supply ZRELADDR to the decompressor via a linker symbol.
ifneq ($(CONFIG_AUTO_ZRELADDR),y)
--
1.7.7
^ permalink raw reply related
* [PATCH v7 03/10] ARM: EXYNOS4: Modify platform data for pl330 driver
From: Thomas Abraham @ 2011-10-12 11:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1318270538-30450-4-git-send-email-thomas.abraham@linaro.org>
With the 'struct dma_pl330_peri' removed, the platfrom data for dma
driver can be simplified to a simple list of peripheral request ids.
Cc: Jassi Brar <jassisinghbrar@gmail.com>
Cc: Boojin Kim <boojin.kim@samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Acked-by: Boojin Kim <boojin.kim@samsung.com>
---
arch/arm/mach-exynos4/dma.c | 225 ++++++++++++-------------------------------
1 files changed, 64 insertions(+), 161 deletions(-)
diff --git a/arch/arm/mach-exynos4/dma.c b/arch/arm/mach-exynos4/dma.c
index 9667c61..141093d 100644
--- a/arch/arm/mach-exynos4/dma.c
+++ b/arch/arm/mach-exynos4/dma.c
@@ -35,95 +35,42 @@
static u64 dma_dmamask = DMA_BIT_MASK(32);
-struct dma_pl330_peri pdma0_peri[28] = {
- {
- .peri_id = (u8)DMACH_PCM0_RX,
- .rqtype = DEVTOMEM,
- }, {
- .peri_id = (u8)DMACH_PCM0_TX,
- .rqtype = MEMTODEV,
- }, {
- .peri_id = (u8)DMACH_PCM2_RX,
- .rqtype = DEVTOMEM,
- }, {
- .peri_id = (u8)DMACH_PCM2_TX,
- .rqtype = MEMTODEV,
- }, {
- .peri_id = (u8)DMACH_MSM_REQ0,
- }, {
- .peri_id = (u8)DMACH_MSM_REQ2,
- }, {
- .peri_id = (u8)DMACH_SPI0_RX,
- .rqtype = DEVTOMEM,
- }, {
- .peri_id = (u8)DMACH_SPI0_TX,
- .rqtype = MEMTODEV,
- }, {
- .peri_id = (u8)DMACH_SPI2_RX,
- .rqtype = DEVTOMEM,
- }, {
- .peri_id = (u8)DMACH_SPI2_TX,
- .rqtype = MEMTODEV,
- }, {
- .peri_id = (u8)DMACH_I2S0S_TX,
- .rqtype = MEMTODEV,
- }, {
- .peri_id = (u8)DMACH_I2S0_RX,
- .rqtype = DEVTOMEM,
- }, {
- .peri_id = (u8)DMACH_I2S0_TX,
- .rqtype = MEMTODEV,
- }, {
- .peri_id = (u8)DMACH_UART0_RX,
- .rqtype = DEVTOMEM,
- }, {
- .peri_id = (u8)DMACH_UART0_TX,
- .rqtype = MEMTODEV,
- }, {
- .peri_id = (u8)DMACH_UART2_RX,
- .rqtype = DEVTOMEM,
- }, {
- .peri_id = (u8)DMACH_UART2_TX,
- .rqtype = MEMTODEV,
- }, {
- .peri_id = (u8)DMACH_UART4_RX,
- .rqtype = DEVTOMEM,
- }, {
- .peri_id = (u8)DMACH_UART4_TX,
- .rqtype = MEMTODEV,
- }, {
- .peri_id = (u8)DMACH_SLIMBUS0_RX,
- .rqtype = DEVTOMEM,
- }, {
- .peri_id = (u8)DMACH_SLIMBUS0_TX,
- .rqtype = MEMTODEV,
- }, {
- .peri_id = (u8)DMACH_SLIMBUS2_RX,
- .rqtype = DEVTOMEM,
- }, {
- .peri_id = (u8)DMACH_SLIMBUS2_TX,
- .rqtype = MEMTODEV,
- }, {
- .peri_id = (u8)DMACH_SLIMBUS4_RX,
- .rqtype = DEVTOMEM,
- }, {
- .peri_id = (u8)DMACH_SLIMBUS4_TX,
- .rqtype = MEMTODEV,
- }, {
- .peri_id = (u8)DMACH_AC97_MICIN,
- .rqtype = DEVTOMEM,
- }, {
- .peri_id = (u8)DMACH_AC97_PCMIN,
- .rqtype = DEVTOMEM,
- }, {
- .peri_id = (u8)DMACH_AC97_PCMOUT,
- .rqtype = MEMTODEV,
- },
+u8 pdma0_peri[] = {
+ DMACH_PCM0_RX,
+ DMACH_PCM0_TX,
+ DMACH_PCM2_RX,
+ DMACH_PCM2_TX,
+ DMACH_MSM_REQ0,
+ DMACH_MSM_REQ2,
+ DMACH_SPI0_RX,
+ DMACH_SPI0_TX,
+ DMACH_SPI2_RX,
+ DMACH_SPI2_TX,
+ DMACH_I2S0S_TX,
+ DMACH_I2S0_RX,
+ DMACH_I2S0_TX,
+ DMACH_I2S2_RX,
+ DMACH_I2S2_TX,
+ DMACH_UART0_RX,
+ DMACH_UART0_TX,
+ DMACH_UART2_RX,
+ DMACH_UART2_TX,
+ DMACH_UART4_RX,
+ DMACH_UART4_TX,
+ DMACH_SLIMBUS0_RX,
+ DMACH_SLIMBUS0_TX,
+ DMACH_SLIMBUS2_RX,
+ DMACH_SLIMBUS2_TX,
+ DMACH_SLIMBUS4_RX,
+ DMACH_SLIMBUS4_TX,
+ DMACH_AC97_MICIN,
+ DMACH_AC97_PCMIN,
+ DMACH_AC97_PCMOUT,
};
struct dma_pl330_platdata exynos4_pdma0_pdata = {
.nr_valid_peri = ARRAY_SIZE(pdma0_peri),
- .peri = pdma0_peri,
+ .peri_id = pdma0_peri,
};
struct amba_device exynos4_device_pdma0 = {
@@ -142,86 +89,37 @@ struct amba_device exynos4_device_pdma0 = {
.periphid = 0x00041330,
};
-struct dma_pl330_peri pdma1_peri[25] = {
- {
- .peri_id = (u8)DMACH_PCM0_RX,
- .rqtype = DEVTOMEM,
- }, {
- .peri_id = (u8)DMACH_PCM0_TX,
- .rqtype = MEMTODEV,
- }, {
- .peri_id = (u8)DMACH_PCM1_RX,
- .rqtype = DEVTOMEM,
- }, {
- .peri_id = (u8)DMACH_PCM1_TX,
- .rqtype = MEMTODEV,
- }, {
- .peri_id = (u8)DMACH_MSM_REQ1,
- }, {
- .peri_id = (u8)DMACH_MSM_REQ3,
- }, {
- .peri_id = (u8)DMACH_SPI1_RX,
- .rqtype = DEVTOMEM,
- }, {
- .peri_id = (u8)DMACH_SPI1_TX,
- .rqtype = MEMTODEV,
- }, {
- .peri_id = (u8)DMACH_I2S0S_TX,
- .rqtype = MEMTODEV,
- }, {
- .peri_id = (u8)DMACH_I2S0_RX,
- .rqtype = DEVTOMEM,
- }, {
- .peri_id = (u8)DMACH_I2S0_TX,
- .rqtype = MEMTODEV,
- }, {
- .peri_id = (u8)DMACH_I2S1_RX,
- .rqtype = DEVTOMEM,
- }, {
- .peri_id = (u8)DMACH_I2S1_TX,
- .rqtype = MEMTODEV,
- }, {
- .peri_id = (u8)DMACH_UART0_RX,
- .rqtype = DEVTOMEM,
- }, {
- .peri_id = (u8)DMACH_UART0_TX,
- .rqtype = MEMTODEV,
- }, {
- .peri_id = (u8)DMACH_UART1_RX,
- .rqtype = DEVTOMEM,
- }, {
- .peri_id = (u8)DMACH_UART1_TX,
- .rqtype = MEMTODEV,
- }, {
- .peri_id = (u8)DMACH_UART3_RX,
- .rqtype = DEVTOMEM,
- }, {
- .peri_id = (u8)DMACH_UART3_TX,
- .rqtype = MEMTODEV,
- }, {
- .peri_id = (u8)DMACH_SLIMBUS1_RX,
- .rqtype = DEVTOMEM,
- }, {
- .peri_id = (u8)DMACH_SLIMBUS1_TX,
- .rqtype = MEMTODEV,
- }, {
- .peri_id = (u8)DMACH_SLIMBUS3_RX,
- .rqtype = DEVTOMEM,
- }, {
- .peri_id = (u8)DMACH_SLIMBUS3_TX,
- .rqtype = MEMTODEV,
- }, {
- .peri_id = (u8)DMACH_SLIMBUS5_RX,
- .rqtype = DEVTOMEM,
- }, {
- .peri_id = (u8)DMACH_SLIMBUS5_TX,
- .rqtype = MEMTODEV,
- },
+u8 pdma1_peri[] = {
+ DMACH_PCM0_RX,
+ DMACH_PCM0_TX,
+ DMACH_PCM1_RX,
+ DMACH_PCM1_TX,
+ DMACH_MSM_REQ1,
+ DMACH_MSM_REQ3,
+ DMACH_SPI1_RX,
+ DMACH_SPI1_TX,
+ DMACH_I2S0S_TX,
+ DMACH_I2S0_RX,
+ DMACH_I2S0_TX,
+ DMACH_I2S1_RX,
+ DMACH_I2S1_TX,
+ DMACH_UART0_RX,
+ DMACH_UART0_TX,
+ DMACH_UART1_RX,
+ DMACH_UART1_TX,
+ DMACH_UART3_RX,
+ DMACH_UART3_TX,
+ DMACH_SLIMBUS1_RX,
+ DMACH_SLIMBUS1_TX,
+ DMACH_SLIMBUS3_RX,
+ DMACH_SLIMBUS3_TX,
+ DMACH_SLIMBUS5_RX,
+ DMACH_SLIMBUS5_TX,
};
struct dma_pl330_platdata exynos4_pdma1_pdata = {
.nr_valid_peri = ARRAY_SIZE(pdma1_peri),
- .peri = pdma1_peri,
+ .peri_id = pdma1_peri,
};
struct amba_device exynos4_device_pdma1 = {
@@ -242,7 +140,12 @@ struct amba_device exynos4_device_pdma1 = {
static int __init exynos4_dma_init(void)
{
+ dma_cap_set(DMA_SLAVE, exynos4_pdma0_pdata.cap_mask);
+ dma_cap_set(DMA_CYCLIC, exynos4_pdma0_pdata.cap_mask);
amba_device_register(&exynos4_device_pdma0, &iomem_resource);
+
+ dma_cap_set(DMA_SLAVE, exynos4_pdma1_pdata.cap_mask);
+ dma_cap_set(DMA_CYCLIC, exynos4_pdma1_pdata.cap_mask);
amba_device_register(&exynos4_device_pdma1, &iomem_resource);
return 0;
--
1.6.6.rc2
^ permalink raw reply related
* [PATCH v7 09/10] ARM: S5PC100: Modify platform data for pl330 driver
From: Thomas Abraham @ 2011-10-12 11:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1318270538-30450-10-git-send-email-thomas.abraham@linaro.org>
With the 'struct dma_pl330_peri' removed, the platfrom data for dma
driver can be simplified to a simple list of peripheral request ids.
Cc: Jassi Brar <jassisinghbrar@gmail.com>
Cc: Boojin Kim <boojin.kim@samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Boojin Kim <boojin.kim@samsung.com>
---
arch/arm/mach-s5pc100/dma.c | 247 ++++++++++++-------------------------------
1 files changed, 69 insertions(+), 178 deletions(-)
diff --git a/arch/arm/mach-s5pc100/dma.c b/arch/arm/mach-s5pc100/dma.c
index 065a087..c841f4d 100644
--- a/arch/arm/mach-s5pc100/dma.c
+++ b/arch/arm/mach-s5pc100/dma.c
@@ -35,100 +35,42 @@
static u64 dma_dmamask = DMA_BIT_MASK(32);
-struct dma_pl330_peri pdma0_peri[30] = {
- {
- .peri_id = (u8)DMACH_UART0_RX,
- .rqtype = DEVTOMEM,
- }, {
- .peri_id = (u8)DMACH_UART0_TX,
- .rqtype = MEMTODEV,
- }, {
- .peri_id = (u8)DMACH_UART1_RX,
- .rqtype = DEVTOMEM,
- }, {
- .peri_id = (u8)DMACH_UART1_TX,
- .rqtype = MEMTODEV,
- }, {
- .peri_id = (u8)DMACH_UART2_RX,
- .rqtype = DEVTOMEM,
- }, {
- .peri_id = (u8)DMACH_UART2_TX,
- .rqtype = MEMTODEV,
- }, {
- .peri_id = (u8)DMACH_UART3_RX,
- .rqtype = DEVTOMEM,
- }, {
- .peri_id = (u8)DMACH_UART3_TX,
- .rqtype = MEMTODEV,
- }, {
- .peri_id = DMACH_IRDA,
- }, {
- .peri_id = (u8)DMACH_I2S0_RX,
- .rqtype = DEVTOMEM,
- }, {
- .peri_id = (u8)DMACH_I2S0_TX,
- .rqtype = MEMTODEV,
- }, {
- .peri_id = (u8)DMACH_I2S0S_TX,
- .rqtype = MEMTODEV,
- }, {
- .peri_id = (u8)DMACH_I2S1_RX,
- .rqtype = DEVTOMEM,
- }, {
- .peri_id = (u8)DMACH_I2S1_TX,
- .rqtype = MEMTODEV,
- }, {
- .peri_id = (u8)DMACH_I2S2_RX,
- .rqtype = DEVTOMEM,
- }, {
- .peri_id = (u8)DMACH_I2S2_TX,
- .rqtype = MEMTODEV,
- }, {
- .peri_id = (u8)DMACH_SPI0_RX,
- .rqtype = DEVTOMEM,
- }, {
- .peri_id = (u8)DMACH_SPI0_TX,
- .rqtype = MEMTODEV,
- }, {
- .peri_id = (u8)DMACH_SPI1_RX,
- .rqtype = DEVTOMEM,
- }, {
- .peri_id = (u8)DMACH_SPI1_TX,
- .rqtype = MEMTODEV,
- }, {
- .peri_id = (u8)DMACH_SPI2_RX,
- .rqtype = DEVTOMEM,
- }, {
- .peri_id = (u8)DMACH_SPI2_TX,
- .rqtype = MEMTODEV,
- }, {
- .peri_id = (u8)DMACH_AC97_MICIN,
- .rqtype = DEVTOMEM,
- }, {
- .peri_id = (u8)DMACH_AC97_PCMIN,
- .rqtype = DEVTOMEM,
- }, {
- .peri_id = (u8)DMACH_AC97_PCMOUT,
- .rqtype = MEMTODEV,
- }, {
- .peri_id = (u8)DMACH_EXTERNAL,
- }, {
- .peri_id = (u8)DMACH_PWM,
- }, {
- .peri_id = (u8)DMACH_SPDIF,
- .rqtype = MEMTODEV,
- }, {
- .peri_id = (u8)DMACH_HSI_RX,
- .rqtype = DEVTOMEM,
- }, {
- .peri_id = (u8)DMACH_HSI_TX,
- .rqtype = MEMTODEV,
- },
+u8 pdma0_peri[] = {
+ DMACH_UART0_RX,
+ DMACH_UART0_TX,
+ DMACH_UART1_RX,
+ DMACH_UART1_TX,
+ DMACH_UART2_RX,
+ DMACH_UART2_TX,
+ DMACH_UART3_RX,
+ DMACH_UART3_TX,
+ DMACH_IRDA,
+ DMACH_I2S0_RX,
+ DMACH_I2S0_TX,
+ DMACH_I2S0S_TX,
+ DMACH_I2S1_RX,
+ DMACH_I2S1_TX,
+ DMACH_I2S2_RX,
+ DMACH_I2S2_TX,
+ DMACH_SPI0_RX,
+ DMACH_SPI0_TX,
+ DMACH_SPI1_RX,
+ DMACH_SPI1_TX,
+ DMACH_SPI2_RX,
+ DMACH_SPI2_TX,
+ DMACH_AC97_MICIN,
+ DMACH_AC97_PCMIN,
+ DMACH_AC97_PCMOUT,
+ DMACH_EXTERNAL,
+ DMACH_PWM,
+ DMACH_SPDIF,
+ DMACH_HSI_RX,
+ DMACH_HSI_TX,
};
struct dma_pl330_platdata s5pc100_pdma0_pdata = {
.nr_valid_peri = ARRAY_SIZE(pdma0_peri),
- .peri = pdma0_peri,
+ .peri_id = pdma0_peri,
};
struct amba_device s5pc100_device_pdma0 = {
@@ -147,98 +89,42 @@ struct amba_device s5pc100_device_pdma0 = {
.periphid = 0x00041330,
};
-struct dma_pl330_peri pdma1_peri[30] = {
- {
- .peri_id = (u8)DMACH_UART0_RX,
- .rqtype = DEVTOMEM,
- }, {
- .peri_id = (u8)DMACH_UART0_TX,
- .rqtype = MEMTODEV,
- }, {
- .peri_id = (u8)DMACH_UART1_RX,
- .rqtype = DEVTOMEM,
- }, {
- .peri_id = (u8)DMACH_UART1_TX,
- .rqtype = MEMTODEV,
- }, {
- .peri_id = (u8)DMACH_UART2_RX,
- .rqtype = DEVTOMEM,
- }, {
- .peri_id = (u8)DMACH_UART2_TX,
- .rqtype = MEMTODEV,
- }, {
- .peri_id = (u8)DMACH_UART3_RX,
- .rqtype = DEVTOMEM,
- }, {
- .peri_id = (u8)DMACH_UART3_TX,
- .rqtype = MEMTODEV,
- }, {
- .peri_id = DMACH_IRDA,
- }, {
- .peri_id = (u8)DMACH_I2S0_RX,
- .rqtype = DEVTOMEM,
- }, {
- .peri_id = (u8)DMACH_I2S0_TX,
- .rqtype = MEMTODEV,
- }, {
- .peri_id = (u8)DMACH_I2S0S_TX,
- .rqtype = MEMTODEV,
- }, {
- .peri_id = (u8)DMACH_I2S1_RX,
- .rqtype = DEVTOMEM,
- }, {
- .peri_id = (u8)DMACH_I2S1_TX,
- .rqtype = MEMTODEV,
- }, {
- .peri_id = (u8)DMACH_I2S2_RX,
- .rqtype = DEVTOMEM,
- }, {
- .peri_id = (u8)DMACH_I2S2_TX,
- .rqtype = MEMTODEV,
- }, {
- .peri_id = (u8)DMACH_SPI0_RX,
- .rqtype = DEVTOMEM,
- }, {
- .peri_id = (u8)DMACH_SPI0_TX,
- .rqtype = MEMTODEV,
- }, {
- .peri_id = (u8)DMACH_SPI1_RX,
- .rqtype = DEVTOMEM,
- }, {
- .peri_id = (u8)DMACH_SPI1_TX,
- .rqtype = MEMTODEV,
- }, {
- .peri_id = (u8)DMACH_SPI2_RX,
- .rqtype = DEVTOMEM,
- }, {
- .peri_id = (u8)DMACH_SPI2_TX,
- .rqtype = MEMTODEV,
- }, {
- .peri_id = (u8)DMACH_PCM0_RX,
- .rqtype = DEVTOMEM,
- }, {
- .peri_id = (u8)DMACH_PCM1_TX,
- .rqtype = MEMTODEV,
- }, {
- .peri_id = (u8)DMACH_PCM1_RX,
- .rqtype = DEVTOMEM,
- }, {
- .peri_id = (u8)DMACH_PCM1_TX,
- .rqtype = MEMTODEV,
- }, {
- .peri_id = (u8)DMACH_MSM_REQ0,
- }, {
- .peri_id = (u8)DMACH_MSM_REQ1,
- }, {
- .peri_id = (u8)DMACH_MSM_REQ2,
- }, {
- .peri_id = (u8)DMACH_MSM_REQ3,
- },
+u8 pdma1_peri[] = {
+ DMACH_UART0_RX,
+ DMACH_UART0_TX,
+ DMACH_UART1_RX,
+ DMACH_UART1_TX,
+ DMACH_UART2_RX,
+ DMACH_UART2_TX,
+ DMACH_UART3_RX,
+ DMACH_UART3_TX,
+ DMACH_IRDA,
+ DMACH_I2S0_RX,
+ DMACH_I2S0_TX,
+ DMACH_I2S0S_TX,
+ DMACH_I2S1_RX,
+ DMACH_I2S1_TX,
+ DMACH_I2S2_RX,
+ DMACH_I2S2_TX,
+ DMACH_SPI0_RX,
+ DMACH_SPI0_TX,
+ DMACH_SPI1_RX,
+ DMACH_SPI1_TX,
+ DMACH_SPI2_RX,
+ DMACH_SPI2_TX,
+ DMACH_PCM0_RX,
+ DMACH_PCM0_TX,
+ DMACH_PCM1_RX,
+ DMACH_PCM1_TX,
+ DMACH_MSM_REQ0,
+ DMACH_MSM_REQ1,
+ DMACH_MSM_REQ2,
+ DMACH_MSM_REQ3,
};
struct dma_pl330_platdata s5pc100_pdma1_pdata = {
.nr_valid_peri = ARRAY_SIZE(pdma1_peri),
- .peri = pdma1_peri,
+ .peri_id = pdma1_peri,
};
struct amba_device s5pc100_device_pdma1 = {
@@ -259,7 +145,12 @@ struct amba_device s5pc100_device_pdma1 = {
static int __init s5pc100_dma_init(void)
{
+ dma_cap_set(DMA_SLAVE, s5pc100_pdma0_pdata.cap_mask);
+ dma_cap_set(DMA_CYCLIC, s5pc100_pdma0_pdata.cap_mask);
amba_device_register(&s5pc100_device_pdma0, &iomem_resource);
+
+ dma_cap_set(DMA_SLAVE, s5pc100_pdma1_pdata.cap_mask);
+ dma_cap_set(DMA_CYCLIC, s5pc100_pdma1_pdata.cap_mask);
amba_device_register(&s5pc100_device_pdma1, &iomem_resource);
return 0;
--
1.6.6.rc2
^ permalink raw reply related
* [PATCH v9 0/3] Add support for tegra2 based ventana board
From: pdeschrijver at nvidia.com @ 2011-10-12 11:53 UTC (permalink / raw)
To: linux-arm-kernel
From: Peter De Schrijver <pdeschrijver@nvidia.com>
This patch set adds support for the tegra2 based ventana development board.
Boot tested on ventana.
Uses a table based approach to select the correct init function.
Provoke kernel warning when no suitable pinmux table can be found.
Peter De Schrijver (3):
arm/tegra: prepare Seaboard pinmux code for derived boards
arm/tegra: add support for ventana pinmuxing
arm/tegra: device tree support for ventana board
arch/arm/boot/dts/tegra-ventana.dts | 32 ++++++++++++++
arch/arm/mach-tegra/Kconfig | 6 +++
arch/arm/mach-tegra/Makefile | 1 +
arch/arm/mach-tegra/Makefile.boot | 1 +
arch/arm/mach-tegra/board-dt.c | 5 ++-
arch/arm/mach-tegra/board-seaboard-pinmux.c | 63 ++++++++++++++++++++++++---
6 files changed, 101 insertions(+), 7 deletions(-)
create mode 100644 arch/arm/boot/dts/tegra-ventana.dts
^ permalink raw reply
* [PATCH v9 1/3] arm/tegra: prepare Seaboard pinmux code for derived boards
From: pdeschrijver at nvidia.com @ 2011-10-12 11:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1318420387-6802-1-git-send-email-pdeschrijver@nvidia.com>
From: Peter De Schrijver <pdeschrijver@nvidia.com>
This patch splits out the common part of pinmux and GPIO initialization for
seaboard and derived boards. This code is based on work done by Jong Kim
<jongk@nvidia.com>.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
arch/arm/mach-tegra/board-seaboard-pinmux.c | 14 ++++++++++----
1 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-tegra/board-seaboard-pinmux.c b/arch/arm/mach-tegra/board-seaboard-pinmux.c
index 74f78b7..b31c765 100644
--- a/arch/arm/mach-tegra/board-seaboard-pinmux.c
+++ b/arch/arm/mach-tegra/board-seaboard-pinmux.c
@@ -1,5 +1,6 @@
/*
- * Copyright (C) 2010 NVIDIA Corporation
+ * Copyright (C) 2010,2011 NVIDIA Corporation
+ * Copyright (C) 2011 Google, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
@@ -160,7 +161,7 @@ static __initdata struct tegra_pingroup_config seaboard_pinmux[] = {
-static struct tegra_gpio_table gpio_table[] = {
+static struct tegra_gpio_table common_gpio_table[] = {
{ .gpio = TEGRA_GPIO_SD2_CD, .enable = true },
{ .gpio = TEGRA_GPIO_SD2_WP, .enable = true },
{ .gpio = TEGRA_GPIO_SD2_POWER, .enable = true },
@@ -171,12 +172,17 @@ static struct tegra_gpio_table gpio_table[] = {
{ .gpio = TEGRA_GPIO_USB1, .enable = true },
};
-void __init seaboard_pinmux_init(void)
+static void __init seaboard_common_pinmux_init(void)
{
tegra_pinmux_config_table(seaboard_pinmux, ARRAY_SIZE(seaboard_pinmux));
tegra_drive_pinmux_config_table(seaboard_drive_pinmux,
ARRAY_SIZE(seaboard_drive_pinmux));
- tegra_gpio_config(gpio_table, ARRAY_SIZE(gpio_table));
+ tegra_gpio_config(common_gpio_table, ARRAY_SIZE(common_gpio_table));
+}
+
+void __init seaboard_pinmux_init(void)
+{
+ seaboard_common_pinmux_init();
}
--
1.7.7.rc0.72.g4b5ea.dirty
^ permalink raw reply related
* [PATCH v9 2/3] arm/tegra: add support for ventana pinmuxing
From: pdeschrijver at nvidia.com @ 2011-10-12 11:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1318420387-6802-1-git-send-email-pdeschrijver@nvidia.com>
From: Peter De Schrijver <pdeschrijver@nvidia.com>
Add support for ventana pinmuxing as a seaboard derivative. This is a cut down
version of work done by Jong Kim <jongk@nvidia.com>.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
arch/arm/mach-tegra/Makefile | 1 +
arch/arm/mach-tegra/board-seaboard-pinmux.c | 49 +++++++++++++++++++++++++-
2 files changed, 48 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index f11b910..91a07e1 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -31,6 +31,7 @@ obj-${CONFIG_MACH_SEABOARD} += board-seaboard-pinmux.o
obj-${CONFIG_MACH_TEGRA_DT} += board-dt.o
obj-${CONFIG_MACH_TEGRA_DT} += board-harmony-pinmux.o
+obj-${CONFIG_MACH_TEGRA_DT} += board-seaboard-pinmux.o
obj-${CONFIG_MACH_TRIMSLICE} += board-trimslice.o
obj-${CONFIG_MACH_TRIMSLICE} += board-trimslice-pinmux.o
diff --git a/arch/arm/mach-tegra/board-seaboard-pinmux.c b/arch/arm/mach-tegra/board-seaboard-pinmux.c
index b31c765..b62b04d 100644
--- a/arch/arm/mach-tegra/board-seaboard-pinmux.c
+++ b/arch/arm/mach-tegra/board-seaboard-pinmux.c
@@ -158,8 +158,26 @@ static __initdata struct tegra_pingroup_config seaboard_pinmux[] = {
{TEGRA_PINGROUP_XM2D, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
};
-
-
+static __initdata struct tegra_pingroup_config ventana_pinmux[] = {
+ {TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_DDC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_DTA, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_DTB, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_DTC, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_DTD, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_GMD, TEGRA_MUX_SFLASH, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_LPW0, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_LPW2, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_LSC1, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_LSCK, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_LSDA, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_PTA, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_SLXC, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_SLXK, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
+};
static struct tegra_gpio_table common_gpio_table[] = {
{ .gpio = TEGRA_GPIO_SD2_CD, .enable = true },
@@ -172,6 +190,26 @@ static struct tegra_gpio_table common_gpio_table[] = {
{ .gpio = TEGRA_GPIO_USB1, .enable = true },
};
+static void __init update_pinmux(struct tegra_pingroup_config *newtbl, int size)
+{
+ int i, j;
+ struct tegra_pingroup_config *new_pingroup, *base_pingroup;
+
+ /* Update base seaboard pinmux table with secondary board
+ * specific pinmux table table.
+ */
+ for (i = 0; i < size; i++) {
+ new_pingroup = &newtbl[i];
+ for (j = 0; j < ARRAY_SIZE(seaboard_pinmux); j++) {
+ base_pingroup = &seaboard_pinmux[j];
+ if (new_pingroup->pingroup == base_pingroup->pingroup) {
+ *base_pingroup = *new_pingroup;
+ break;
+ }
+ }
+ }
+}
+
static void __init seaboard_common_pinmux_init(void)
{
tegra_pinmux_config_table(seaboard_pinmux, ARRAY_SIZE(seaboard_pinmux));
@@ -186,3 +224,10 @@ void __init seaboard_pinmux_init(void)
{
seaboard_common_pinmux_init();
}
+
+void __init ventana_pinmux_init(void)
+{
+ update_pinmux(ventana_pinmux, ARRAY_SIZE(ventana_pinmux));
+ seaboard_common_pinmux_init();
+}
+
--
1.7.7.rc0.72.g4b5ea.dirty
^ permalink raw reply related
* [PATCH v9 3/3] arm/tegra: device tree support for ventana board
From: pdeschrijver at nvidia.com @ 2011-10-12 11:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1318420387-6802-1-git-send-email-pdeschrijver@nvidia.com>
From: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
arch/arm/boot/dts/tegra-ventana.dts | 32 ++++++++++++++++++++++++++++++++
arch/arm/mach-tegra/Kconfig | 6 ++++++
arch/arm/mach-tegra/Makefile.boot | 1 +
arch/arm/mach-tegra/board-dt.c | 26 +++++++++++++++++++++-----
4 files changed, 60 insertions(+), 5 deletions(-)
create mode 100644 arch/arm/boot/dts/tegra-ventana.dts
diff --git a/arch/arm/boot/dts/tegra-ventana.dts b/arch/arm/boot/dts/tegra-ventana.dts
new file mode 100644
index 0000000..9b29a62
--- /dev/null
+++ b/arch/arm/boot/dts/tegra-ventana.dts
@@ -0,0 +1,32 @@
+/dts-v1/;
+
+/memreserve/ 0x1c000000 0x04000000;
+/include/ "tegra20.dtsi"
+
+/ {
+ model = "NVIDIA Tegra2 Ventana evaluation board";
+ compatible = "nvidia,ventana", "nvidia,tegra20";
+
+ chosen {
+ bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/ram rdinit=/sbin/init";
+ };
+
+ memory {
+ reg = < 0x00000000 0x40000000 >;
+ };
+
+ serial at 70006300 {
+ clock-frequency = < 216000000 >;
+ };
+
+ sdhci at c8000400 {
+ cd-gpios = <&gpio 69 0>; /* gpio PI5 */
+ wp-gpios = <&gpio 57 0>; /* gpio PH1 */
+ power-gpios = <&gpio 155 0>; /* gpio PT3 */
+ };
+
+ sdhci at c8000600 {
+ power-gpios = <&gpio 70 0>; /* gpio PI6 */
+ support-8bit;
+ };
+};
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index d82ebab..91aff7c 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -69,6 +69,12 @@ config MACH_WARIO
help
Support for the Wario version of Seaboard
+config MACH_VENTANA
+ bool "Ventana board"
+ select MACH_TEGRA_DT
+ help
+ Support for the nVidia Ventana development platform
+
choice
prompt "Low-level debug console UART"
default TEGRA_DEBUG_UART_NONE
diff --git a/arch/arm/mach-tegra/Makefile.boot b/arch/arm/mach-tegra/Makefile.boot
index 5e870d2..bd12c9f 100644
--- a/arch/arm/mach-tegra/Makefile.boot
+++ b/arch/arm/mach-tegra/Makefile.boot
@@ -4,3 +4,4 @@ initrd_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00800000
dtb-$(CONFIG_MACH_HARMONY) += tegra-harmony.dtb
dtb-$(CONFIG_MACH_SEABOARD) += tegra-seaboard.dtb
+dtb-$(CONFIG_MACH_VENTANA) += tegra-ventana.dtb
diff --git a/arch/arm/mach-tegra/board-dt.c b/arch/arm/mach-tegra/board-dt.c
index 9f47e04..d368f8d 100644
--- a/arch/arm/mach-tegra/board-dt.c
+++ b/arch/arm/mach-tegra/board-dt.c
@@ -47,7 +47,7 @@
void harmony_pinmux_init(void);
void seaboard_pinmux_init(void);
-
+void ventana_pinmux_init(void);
struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC1_BASE, "sdhci-tegra.0", NULL),
@@ -80,9 +80,19 @@ static struct of_device_id tegra_dt_gic_match[] __initdata = {
{}
};
+static struct {
+ char *machine;
+ void (*init)(void);
+} pinmux_configs[] = {
+ { "nvidia,harmony", harmony_pinmux_init },
+ { "nvidia,seaboard", seaboard_pinmux_init },
+ { "nvidia,ventana", ventana_pinmux_init },
+};
+
static void __init tegra_dt_init(void)
{
struct device_node *node;
+ int i;
node = of_find_matching_node_by_address(NULL, tegra_dt_gic_match,
TEGRA_ARM_INT_DIST_BASE);
@@ -91,10 +101,15 @@ static void __init tegra_dt_init(void)
tegra_clk_init_from_table(tegra_dt_clk_init_table);
- if (of_machine_is_compatible("nvidia,harmony"))
- harmony_pinmux_init();
- else if (of_machine_is_compatible("nvidia,seaboard"))
- seaboard_pinmux_init();
+ for (i = 0; i < ARRAY_SIZE(pinmux_configs); i++) {
+ if (of_machine_is_compatible(pinmux_configs[i].machine)) {
+ pinmux_configs[i].init();
+ break;
+ }
+ }
+
+ WARN(i == ARRAY_SIZE(pinmux_configs),
+ "Unknown platform! Pinmuxing not initialized\n");
/*
* Finished with the static registrations now; fill in the missing
@@ -106,6 +121,7 @@ static void __init tegra_dt_init(void)
static const char * tegra_dt_board_compat[] = {
"nvidia,harmony",
"nvidia,seaboard",
+ "nvidia,ventana",
NULL
};
--
1.7.7.rc0.72.g4b5ea.dirty
^ permalink raw reply related
* [RFC PATCH] tty/serial: RS485 bindings for device tree
From: Nicolas Ferre @ 2011-10-12 12:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <3289709.mzRgbAUyPT@wuerfel>
On 10/11/2011 08:41 PM, Arnd Bergmann :
> On Tuesday 11 October 2011 19:28:06 Nicolas Ferre wrote:
>>
>>> +Optional properties:
>>> +- linux,rs485-enabled-at-boot-time: empty property telling to enable the rs485
>>> + feature at boot time. It can be disabled later with proper ioctl.
>>
>> +- linux,rs485-rx-during-tx: empty property that enable the receiving of data
>> + even whilst sending data.
>
> This does not sound too linux specific. If it's a hardware property, don't
> use the 'linux,' prefix and just make it 'rs484-full-duplex' or such.
Ok, I understand. Your remark may also apply to linux,rs485-rts-delay.
So we may end-up with:
- linux,rs485-enabled-at-boot-time
- rs485-rx-during-tx
- rs485-rts-delay
Best regards,
--
Nicolas Ferre
^ permalink raw reply
* [PATCH] [TRIVIAL] ARM: imx: Fix typo 'MACH_MX31_3DS_MXC_NAND_USE_BBT'
From: Paul Bolle @ 2011-10-12 12:04 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Paul Bolle <pebolle@tiscali.nl>
---
This is trivial because this is what apparently was intended. On the
other hand this should open code paths that were hidden until now. So
perhaps this needs the maintainer's approval. (I cannot meaningfully
test this.)
arch/arm/mach-imx/mach-mx31_3ds.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-imx/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c
index c20be75..5750ca5 100644
--- a/arch/arm/mach-imx/mach-mx31_3ds.c
+++ b/arch/arm/mach-imx/mach-mx31_3ds.c
@@ -542,7 +542,7 @@ static const struct mxc_nand_platform_data
mx31_3ds_nand_board_info __initconst = {
.width = 1,
.hw_ecc = 1,
-#ifdef MACH_MX31_3DS_MXC_NAND_USE_BBT
+#ifdef CONFIG_MACH_MX31_3DS_MXC_NAND_USE_BBT
.flash_bbt = 1,
#endif
};
--
1.7.4.4
^ permalink raw reply related
* [PATCH v8 REPOST 17/24] gpio/omap: fix debounce clock handling
From: Tarun Kanti DebBarma @ 2011-10-12 12:31 UTC (permalink / raw)
To: linux-arm-kernel
Currently debounce clock state is not tracked in the system. The bank->dbck
is enabled/disabled in suspend/idle paths irrespective of whether debounce
interval has been set or not. Ideally, it should be handled only for those
gpio banks where the debounce is enabled. In _set_gpio_debounce, enable
debounce clock before accessing registers.
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
---
During further internal testing it was found that image was crashing within
_set_gpio_debounce(). It is observed that we are trying to access registers
without enabling debounce clock. This patch incorporates the change whereby
the debounce clock is enabled before accessing registers and disabled at the
end of the function.
drivers/gpio/gpio-omap.c | 60 ++++++++++++++++++++++++++++++++-------------
1 files changed, 42 insertions(+), 18 deletions(-)
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index fa6c9c5..85e9c2a 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -65,6 +65,7 @@ struct gpio_bank {
struct clk *dbck;
u32 mod_usage;
u32 dbck_enable_mask;
+ bool dbck_enabled;
struct device *dev;
bool is_mpuio;
bool dbck_flag;
@@ -156,6 +157,22 @@ static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
__raw_writel(l, base + reg);
}
+static inline void _gpio_dbck_enable(struct gpio_bank *bank)
+{
+ if (bank->dbck_enable_mask && !bank->dbck_enabled) {
+ clk_enable(bank->dbck);
+ bank->dbck_enabled = true;
+ }
+}
+
+static inline void _gpio_dbck_disable(struct gpio_bank *bank)
+{
+ if (bank->dbck_enable_mask && bank->dbck_enabled) {
+ clk_disable(bank->dbck);
+ bank->dbck_enabled = false;
+ }
+}
+
/**
* _set_gpio_debounce - low level gpio debounce time
* @bank: the gpio bank we're acting upon
@@ -184,22 +201,22 @@ static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
l = GPIO_BIT(bank, gpio);
+ clk_enable(bank->dbck);
reg = bank->base + bank->regs->debounce;
__raw_writel(debounce, reg);
reg = bank->base + bank->regs->debounce_en;
val = __raw_readl(reg);
- if (debounce) {
+ if (debounce)
val |= l;
- clk_enable(bank->dbck);
- } else {
+ else
val &= ~l;
- clk_disable(bank->dbck);
- }
+
bank->dbck_enable_mask = val;
__raw_writel(val, reg);
+ clk_disable(bank->dbck);
}
static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio,
@@ -485,8 +502,10 @@ static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
* If this is the first gpio_request for the bank,
* enable the bank module.
*/
- if (!bank->mod_usage)
+ if (!bank->mod_usage) {
+ _gpio_dbck_enable(bank);
pm_runtime_get_sync(bank->dev);
+ }
spin_lock_irqsave(&bank->lock, flags);
/* Set trigger to none. You need to enable the desired trigger with
@@ -549,8 +568,10 @@ static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
* If this is the last gpio to be freed in the bank,
* disable the bank module.
*/
- if (!bank->mod_usage)
+ if (!bank->mod_usage) {
pm_runtime_put_sync(bank->dev);
+ _gpio_dbck_disable(bank);
+ }
}
/*
@@ -829,8 +850,10 @@ static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
if (!bank->dbck) {
bank->dbck = clk_get(bank->dev, "dbclk");
- if (IS_ERR(bank->dbck))
+ if (IS_ERR(bank->dbck)) {
dev_err(bank->dev, "Could not get gpio dbck\n");
+ return -EINVAL;
+ }
}
spin_lock_irqsave(&bank->lock, flags);
@@ -1086,6 +1109,8 @@ static int omap_gpio_suspend(struct device *dev)
bank->saved_wakeup = __raw_readl(wake_status);
_gpio_rmw(base, bank->regs->wkup_en, bank->suspend_wakeup, 1);
spin_unlock_irqrestore(&bank->lock, flags);
+
+ _gpio_dbck_disable(bank);
}
return 0;
@@ -1102,6 +1127,8 @@ static int omap_gpio_resume(struct device *dev)
if (!bank->regs->wkup_en)
return 0;
+ _gpio_dbck_enable(bank);
+
spin_lock_irqsave(&bank->lock, flags);
_gpio_rmw(base, bank->regs->wkup_en, bank->saved_wakeup, 1);
spin_unlock_irqrestore(&bank->lock, flags);
@@ -1120,16 +1147,14 @@ void omap2_gpio_prepare_for_idle(int off_mode)
list_for_each_entry(bank, &omap_gpio_list, node) {
u32 l1 = 0, l2 = 0;
- int j;
if (!bank->loses_context)
continue;
- for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
- clk_disable(bank->dbck);
-
- if (!off_mode)
+ if (!off_mode) {
+ _gpio_dbck_disable(bank);
continue;
+ }
/* If going to OFF, remove triggering for all
* non-wakeup GPIOs. Otherwise spurious IRQs will be
@@ -1151,15 +1176,16 @@ void omap2_gpio_prepare_for_idle(int off_mode)
__raw_writel(l2, bank->base + bank->regs->risingdetect);
save_gpio_context:
-
if (bank->get_context_loss_count)
bank->context_loss_count =
bank->get_context_loss_count(bank->dev);
omap_gpio_save_context(bank);
- if (!pm_runtime_suspended(bank->dev))
+ if (!pm_runtime_suspended(bank->dev)) {
pm_runtime_put_sync(bank->dev);
+ _gpio_dbck_disable(bank);
+ }
}
}
@@ -1170,13 +1196,11 @@ void omap2_gpio_resume_after_idle(void)
list_for_each_entry(bank, &omap_gpio_list, node) {
u32 context_lost_cnt_after;
u32 l = 0, gen, gen0, gen1;
- int j;
if (!bank->loses_context)
continue;
- for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
- clk_enable(bank->dbck);
+ _gpio_dbck_enable(bank);
if (pm_runtime_suspended(bank->dev))
pm_runtime_get_sync(bank->dev);
--
1.7.0.4
^ permalink raw reply related
* [PATCH v8 REPOST 21/24] gpio/omap: save and restore debounce registers
From: Tarun Kanti DebBarma @ 2011-10-12 12:32 UTC (permalink / raw)
To: linux-arm-kernel
From: Nishanth Menon <nm@ti.com>
GPIO debounce registers need to be saved and restored for proper functioning
of driver. To save the registers, we cannot cut the clock before the save,
hence move the clk disable after the save.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
Rebased on top of:
[PATCH v8 REPOST 17/24] gpio/omap: fix debounce clock handling
drivers/gpio/gpio-omap.c | 11 +++++++++++
1 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index d074408..6a89560 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -42,6 +42,8 @@ struct gpio_regs {
u32 risingdetect;
u32 fallingdetect;
u32 dataout;
+ u32 debounce;
+ u32 debounce_en;
};
struct gpio_bank {
@@ -219,6 +221,9 @@ static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
__raw_writel(val, reg);
clk_disable(bank->dbck);
+
+ bank->context.debounce = debounce;
+ bank->context.debounce_en = val;
}
static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio,
@@ -1350,6 +1355,12 @@ static void omap_gpio_restore_context(struct gpio_bank *bank)
__raw_writel(bank->context.fallingdetect,
bank->base + bank->regs->fallingdetect);
__raw_writel(bank->context.dataout, bank->base + bank->regs->dataout);
+ if (bank->dbck_enable_mask) {
+ __raw_writel(bank->context.debounce, bank->base +
+ bank->regs->debounce);
+ __raw_writel(bank->context.debounce_en,
+ bank->base + bank->regs->debounce_en);
+ }
}
#else
#define omap_gpio_suspend NULL
--
1.7.0.4
^ permalink raw reply related
* [PATCH V4 3/3] ARM: SAMSUNG: Add lookup of sdhci-s3c clocks using generic names
From: Rajeshwari Birje @ 2011-10-12 12:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4E956ADB.3060604@samsung.com>
Hi Sylwester,
On Wed, Oct 12, 2011 at 3:54 PM, Sylwester Nawrocki
<s.nawrocki@samsung.com> wrote:
> Hi Rajeshwari,
>
> On 10/12/2011 11:43 AM, Rajeshwari Shinde wrote:
>> Add support for lookup of sdhci-s3c controller clocks using generic names
>> for s3c2416, s3c64xx, s5pc100, s5pv210 and exynos4 SoC's.
>>
>> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
>> ---
>> ?arch/arm/mach-exynos4/clock.c ? ? ? ? | ? 88 ++++++++++-------
>> ?arch/arm/mach-s3c2416/clock.c ? ? ? ? | ? 68 +++++++------
>> ?arch/arm/mach-s3c64xx/clock.c ? ? ? ? | ?126 +++++++++++++++----------
>> ?arch/arm/mach-s5pc100/clock.c ? ? ? ? | ?130 ++++++++++++++++----------
>> ?arch/arm/mach-s5pv210/clock.c ? ? ? ? | ?167 ++++++++++++++++++++-------------
>> ?arch/arm/plat-s3c24xx/s3c2443-clock.c | ? 15 ++-
>> ?6 files changed, 359 insertions(+), 235 deletions(-)
>>
>> diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c
>> index 9f50e33..c6383b9 100644
>> --- a/arch/arm/mach-exynos4/clock.c
>> +++ b/arch/arm/mach-exynos4/clock.c
>> @@ -1157,42 +1157,6 @@ static struct clksrc_clk clksrcs[] = {
>> ? ? ? ? ? ? ? .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 },
>> ? ? ? }, {
>> ? ? ? ? ? ? ? .clk ? ? ? ? ? ?= {
>> - ? ? ? ? ? ? ? ? ? ? .name ? ? ? ? ? = "sclk_mmc",
>> - ? ? ? ? ? ? ? ? ? ? .devname ? ? ? ?= "s3c-sdhci.0",
>> - ? ? ? ? ? ? ? ? ? ? .parent ? ? ? ? = &clk_dout_mmc0.clk,
>> - ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = exynos4_clksrc_mask_fsys_ctrl,
>> - ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 0),
>> - ? ? ? ? ? ? },
>> - ? ? ? ? ? ? .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
>> - ? ? }, {
>> - ? ? ? ? ? ? .clk ? ? ? ? ? ?= {
>> - ? ? ? ? ? ? ? ? ? ? .name ? ? ? ? ? = "sclk_mmc",
>> - ? ? ? ? ? ? ? ? ? ? .devname ? ? ? ?= "s3c-sdhci.1",
>> - ? ? ? ? ? ? ? ? ? ? .parent ? ? ? ? = &clk_dout_mmc1.clk,
>> - ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = exynos4_clksrc_mask_fsys_ctrl,
>> - ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 4),
>> - ? ? ? ? ? ? },
>> - ? ? ? ? ? ? .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
>> - ? ? }, {
>> - ? ? ? ? ? ? .clk ? ? ? ? ? ?= {
>> - ? ? ? ? ? ? ? ? ? ? .name ? ? ? ? ? = "sclk_mmc",
>> - ? ? ? ? ? ? ? ? ? ? .devname ? ? ? ?= "s3c-sdhci.2",
>> - ? ? ? ? ? ? ? ? ? ? .parent ? ? ? ? = &clk_dout_mmc2.clk,
>> - ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = exynos4_clksrc_mask_fsys_ctrl,
>> - ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 8),
>> - ? ? ? ? ? ? },
>> - ? ? ? ? ? ? .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
>> - ? ? }, {
>> - ? ? ? ? ? ? .clk ? ? ? ? ? ?= {
>> - ? ? ? ? ? ? ? ? ? ? .name ? ? ? ? ? = "sclk_mmc",
>> - ? ? ? ? ? ? ? ? ? ? .devname ? ? ? ?= "s3c-sdhci.3",
>> - ? ? ? ? ? ? ? ? ? ? .parent ? ? ? ? = &clk_dout_mmc3.clk,
>> - ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = exynos4_clksrc_mask_fsys_ctrl,
>> - ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 12),
>> - ? ? ? ? ? ? },
>> - ? ? ? ? ? ? .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
>> - ? ? }, {
>> - ? ? ? ? ? ? .clk ? ? ? ? ? ?= {
>> ? ? ? ? ? ? ? ? ? ? ? .name ? ? ? ? ? = "sclk_dwmmc",
>> ? ? ? ? ? ? ? ? ? ? ? .parent ? ? ? ? = &clk_dout_mmc4.clk,
>> ? ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = exynos4_clksrc_mask_fsys_ctrl,
>> @@ -1250,6 +1214,50 @@ static struct clksrc_clk clk_sclk_uart3 = {
>> ? ? ? .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
>> ?};
>>
>> +static struct clksrc_clk clk_sclk_mmc0 = {
>> + ? ? .clk ? ? ? ? ? ?= {
>> + ? ? ? ? ? ? .name ? ? ? ? ? = "sclk_mmc",
>> + ? ? ? ? ? ? .devname ? ? ? ?= "s3c-sdhci.0",
>
> Would it make sense to drop this 'devname' field here and others
> until sclk_mmc3 ....
*** The devname here distinguishes these clocks. So it should be okay
to have a devname for these clocks.
>
>> + ? ? ? ? ? ? .parent ? ? ? ? = &clk_dout_mmc0.clk,
>> + ? ? ? ? ? ? .enable ? ? ? ? = exynos4_clksrc_mask_fsys_ctrl,
>> + ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 0),
>> + ? ? },
>> + ? ? .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
>> +};
>> +
>> +static struct clksrc_clk clk_sclk_mmc1 = {
>> + ? ? .clk ? ? ? ? ? ?= {
>> + ? ? ? ? ? ? .name ? ? ? ? ? = "sclk_mmc",
>> + ? ? ? ? ? ? .devname ? ? ? ?= "s3c-sdhci.1",
>
>> + ? ? ? ? ? ? .parent ? ? ? ? = &clk_dout_mmc1.clk,
>> + ? ? ? ? ? ? .enable ? ? ? ? = exynos4_clksrc_mask_fsys_ctrl,
>> + ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 4),
>> + ? ? },
>> + ? ? .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
>> +};
>> +
>> +static struct clksrc_clk clk_sclk_mmc2 = {
>> + ? ? .clk ? ? ? ? ? ?= {
>> + ? ? ? ? ? ? .name ? ? ? ? ? = "sclk_mmc",
>> + ? ? ? ? ? ? .devname ? ? ? ?= "s3c-sdhci.2",
>
>> + ? ? ? ? ? ? .parent ? ? ? ? = &clk_dout_mmc2.clk,
>> + ? ? ? ? ? ? .enable ? ? ? ? = exynos4_clksrc_mask_fsys_ctrl,
>> + ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 8),
>> + ? ? },
>> + ? ? .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
>> +};
>> +
>> +static struct clksrc_clk clk_sclk_mmc3 = {
>> + ? ? .clk ? ? ? ? ? ?= {
>> + ? ? ? ? ? ? .name ? ? ? ? ? = "sclk_mmc",
>> + ? ? ? ? ? ? .devname ? ? ? ?= "s3c-sdhci.3",
>
>> + ? ? ? ? ? ? .parent ? ? ? ? = &clk_dout_mmc3.clk,
>> + ? ? ? ? ? ? .enable ? ? ? ? = exynos4_clksrc_mask_fsys_ctrl,
>> + ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 12),
>> + ? ? },
>> + ? ? .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
>> +};
>> +
>> ?/* Clock initialization code */
>> ?static struct clksrc_clk *sysclks[] = {
>> ? ? ? &clk_mout_apll,
>> @@ -1289,6 +1297,10 @@ static struct clksrc_clk *clksrc_cdev[] = {
>> ? ? ? &clk_sclk_uart1,
>> ? ? ? &clk_sclk_uart2,
>> ? ? ? &clk_sclk_uart3,
>> + ? ? &clk_sclk_mmc0,
>> + ? ? &clk_sclk_mmc1,
>> + ? ? &clk_sclk_mmc2,
>> + ? ? &clk_sclk_mmc3,
>
> ..then drop the above 4 lines...
**** The registration for these clocks are important. The
s3c_register_clksrc() function sets the .ops of this clock and also
its parent. So the registration cannot be dropped.
>
>> ?};
>>
>> ?static struct clk_lookup exynos4_clk_lookup[] = {
>> @@ -1296,6 +1308,10 @@ static struct clk_lookup exynos4_clk_lookup[] = {
>> ? ? ? CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &clk_sclk_uart1.clk),
>> ? ? ? CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &clk_sclk_uart2.clk),
>> ? ? ? CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &clk_sclk_uart3.clk),
>> + ? ? CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
>> + ? ? CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
>> + ? ? CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
>> + ? ? CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),
>
> ..and add something like:
>
> ?+ ? ? ?CLKDEV_INIT("s3c-sdhci.0", "sclk_mmc", &clk_sclk_mmc0.clk),
> ?+ ? ? ?CLKDEV_INIT("s3c-sdhci.1", "sclk_mmc", &clk_sclk_mmc1.clk),
> ?+ ? ? ?CLKDEV_INIT("s3c-sdhci.2", "sclk_mmc", &clk_sclk_mmc2.clk),
> ?+ ? ? ?CLKDEV_INIT("s3c-sdhci.3", "sclk_mmc", &clk_sclk_mmc3.clk),
>
> ?
**** The driver uses a common name for the possible bus clock sources,
that is ?mmc_busclk?. This keeps the clock lookup code in the driver
simple. Also, there could be SoC?s which do no use sclk_mmc as the bus
clock name as per the user manual
>
> Also I'm wondering why we're using different device names for clk_sclk_mmc0..3
> clocks, i.e. exynos4-sdhci.? and s3c-sdhci.? ?
>
> Does it all work on exynos ? I would expect the device name to be same
> across all the clock definitions, otherwise clk_get(dev, ..) will fail.
**** There was a patch submitted to rename the device name of sdhci
for Exynos to exynos4-sdhci. I will remove this change from this patch
and let that patch handle this change.
>
>> ?};
>>
>
> Regards
> --
> Sylwester Nawrocki
> Samsung Poland R&D Center
> --
> To unsubscribe from this list: send the line "unsubscribe linux-mmc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at ?http://vger.kernel.org/majordomo-info.html
>
Regards,
Rajeshwari Shinde.
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