* [PATCH v4 0/7] uio_pruss cleanup and platform support
From: Matt Porter @ 2012-10-08 12:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5072B190.1060200@ti.com>
On Mon, Oct 08, 2012 at 04:27:20PM +0530, Sekhar Nori wrote:
> On 10/5/2012 10:34 PM, Matt Porter wrote:
>
> > This series enables uio_pruss on DA850 and removes use of the
> > private SRAM API by the driver. The driver previously was not
> > enabled by any platform and the private SRAM API was accessing
> > an invalid SRAM bank.
> >
> > It is regression tested on AM180x EVM with suspend/resume due
> > to the new use of the shared SRAM for both PM and PRUSS. The
> > uio_pruss driver is tested on the same platform using the
> > PRU_memAccessPRUDataRam and PRU_memAccessL3andDDR examples from
> > the PRU userspace tools available from http://www.ti.com/tool/sprc940
>
> I applied patches 2/7, 3/7 and 6/7 of this series for v3.8. I have some
> comments on the board patch. Rest of the patches depend on acceptance of
> 1/7 so I will take them only after that is accepted.
Ok, thanks...and I'll post a v5 of 5/7 and 7/7 and those should be ready
when 1/7 is accepted.
-Matt
^ permalink raw reply
* [PATCH v4 7/7] ARM: davinci: register pruss_uio device on DA850 EVM
From: Matt Porter @ 2012-10-08 11:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5072B091.1040007@ti.com>
On Mon, Oct 08, 2012 at 04:23:05PM +0530, Sekhar Nori wrote:
> On 10/5/2012 10:34 PM, Matt Porter wrote:
> > Configures the required pdata and registers the pruss_uio
> > platform device on the DA850 EVM.
> >
> > Tested on AM180x-EVM using the PRU_memAccessPRUDataRam and
> > PRU_memAccessL3andDDR examples from the PRU userspace tools
> > available from http://www.ti.com/tool/sprc940
> >
> > Signed-off-by: Matt Porter <mporter@ti.com>
> > ---
> > arch/arm/mach-davinci/board-da850-evm.c | 12 ++++++++++++
> > 1 file changed, 12 insertions(+)
> >
> > diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
> > index 7359375..6f9478b 100644
> > --- a/arch/arm/mach-davinci/board-da850-evm.c
> > +++ b/arch/arm/mach-davinci/board-da850-evm.c
> > @@ -31,6 +31,7 @@
> > #include <linux/platform_data/mtd-davinci.h>
> > #include <linux/platform_data/mtd-davinci-aemif.h>
> > #include <linux/platform_data/spi-davinci.h>
> > +#include <linux/platform_data/uio_pruss.h>
> > #include <linux/regulator/machine.h>
> > #include <linux/regulator/tps6507x.h>
> > #include <linux/spi/spi.h>
> > @@ -40,6 +41,7 @@
> > #include <mach/cp_intc.h>
> > #include <mach/da8xx.h>
> > #include <mach/mux.h>
> > +#include <mach/sram.h>
> >
> > #include <asm/mach-types.h>
> > #include <asm/mach/arch.h>
> > @@ -1253,6 +1255,10 @@ static __init int da850_wl12xx_init(void)
> >
> > #endif /* CONFIG_DA850_WL12XX */
> >
> > +struct uio_pruss_pdata da8xx_pruss_uio_pdata = {
> > + .pintc_base = 0x4000,
> > +};
> > +
> > #define DA850EVM_SATA_REFCLKPN_RATE (100 * 1000 * 1000)
> >
> > static __init void da850_evm_init(void)
> > @@ -1339,6 +1345,12 @@ static __init void da850_evm_init(void)
> > pr_warning("da850_evm_init: lcdcntl mux setup failed: %d\n",
> > ret);
> >
> > + da8xx_pruss_uio_pdata.sram_pool = sram_get_gen_pool();
> > + ret = da8xx_register_pruss_uio(&da8xx_pruss_uio_pdata);
> > + if (ret)
> > + pr_warning("pruss_uio initialization failed: %d\n",
> > + ret);
>
> I failed to mention this last time around, but is there any reason
> platform data will change from board to board? Looks like the pintc_base
> is SoC specific and that all platforms would use SRAM when using the
> pruss driver. Looks like you can make da8xx_register_pruss_uio() take no
> parameters at all.
No reason, just oversight here. I'll update these two patches so this is
done at the SoC level.
-Matt
^ permalink raw reply
* [PATCH 05/16] vfs: bogus warnings in fs/namei.c
From: Jan Kara @ 2012-10-08 11:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1349448930-23976-6-git-send-email-arnd@arndb.de>
On Fri 05-10-12 16:55:19, Arnd Bergmann wrote:
> The follow_link() function always initializes its *p argument,
> or returns an error, but not all versions of gcc figure this
> out, so we have to work around this using the uninitialized_var()
> macro.
Well, I'm somewhat sceptical to this approach. I agree that bogus
warnings are not nice but later when the code is changed and possibly real
use without initialization is added, we won't notice it. Without changing
anything, we'd at least have a chance of catching it with gcc versions
which were clever enough to not warn with the original code. Or
alternatively if we unconditionally initialized the variable that would get
rid of the warning and made the code more future-proof (that's what I
usually end up doing)... I don't really care that much about the chosen
solution, Al is the one to decide. But I wanted to point out there are
downsides to your solution.
Honza
>
> Without this patch, building with arm-linux-gnueabi-gcc-4.6 results in:
>
> fs/namei.c: In function 'link_path_walk':
> fs/namei.c:649:24: warning: 'cookie' may be used uninitialized in this function [-Wuninitialized]
> fs/namei.c:1544:9: note: 'cookie' was declared here
> fs/namei.c: In function 'path_lookupat':
> fs/namei.c:649:24: warning: 'cookie' may be used uninitialized in this function [-Wuninitialized]
> fs/namei.c:1934:10: note: 'cookie' was declared here
> fs/namei.c: In function 'path_openat':
> fs/namei.c:649:24: warning: 'cookie' may be used uninitialized in this function [-Wuninitialized]
> fs/namei.c:2899:9: note: 'cookie' was declared here
>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> Cc: Al Viro <viro@zeniv.linux.org.uk>
> Cc: linux-fsdevel at vger.kernel.org
> Cc: Jan Kara <jack@suse.cz>
> ---
> fs/namei.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/fs/namei.c b/fs/namei.c
> index dd1ed1b..62a1725 100644
> --- a/fs/namei.c
> +++ b/fs/namei.c
> @@ -1543,7 +1543,7 @@ static inline int nested_symlink(struct path *path, struct nameidata *nd)
>
> do {
> struct path link = *path;
> - void *cookie;
> + void *uninitialized_var(cookie);
>
> res = follow_link(&link, nd, &cookie);
> if (res)
> @@ -1933,7 +1933,7 @@ static int path_lookupat(int dfd, const char *name,
> if (!err && !(flags & LOOKUP_PARENT)) {
> err = lookup_last(nd, &path);
> while (err > 0) {
> - void *cookie;
> + void *uninitialized_var(cookie);
> struct path link = path;
> err = may_follow_link(&link, nd);
> if (unlikely(err))
> @@ -2902,7 +2902,7 @@ static struct file *path_openat(int dfd, const char *pathname,
> error = do_last(nd, &path, file, op, &opened, pathname);
> while (unlikely(error > 0)) { /* trailing symlink */
> struct path link = path;
> - void *cookie;
> + void *uninitialized_var(cookie);
> if (!(nd->flags & LOOKUP_FOLLOW)) {
> path_put_conditional(&path, nd);
> path_put(&nd->path);
> --
> 1.7.10
>
--
Jan Kara <jack@suse.cz>
SUSE Labs, CR
^ permalink raw reply
* [PATCH 2/6] ARM: bcm476x: Add system timer
From: Florian Fainelli @ 2012-10-08 11:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121007015406.470633343@gmail.com>
On Sunday 07 October 2012 03:53:02 Domenico Andreoli wrote:
> From: Domenico Andreoli <domenico.andreoli@linux.com>
>
> System timer implementation for the BCM476x SoCs.
>
> Signed-off-by: Domenico Andreoli <domenico.andreoli@linux.com>
> ---
> Documentation/devicetree/bindings/timer/brcm,bcm476x-system-timer.txt | 22 +
> arch/arm/boot/dts/bcm476x.dtsi | 8 +
> arch/arm/mach-bcm476x/bcm476x.c | 10 -
> drivers/clocksource/Makefile | 1 +
> drivers/clocksource/bcm476x_timer.c | 188 ++++++++++
> include/linux/bcm476x_timer.h | 24 +
> 6 files changed, 244 insertions(+), 9 deletions(-)
>
> Index: b/Documentation/devicetree/bindings/timer/brcm,bcm476x-system-timer.txt
> ===================================================================
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/timer/brcm,bcm476x-system-timer.txt
> @@ -0,0 +1,22 @@
> +BCM476x System Timer
> +
> +The System Timer peripheral provides either two or four 32-bit timer
> +channels. BCM476x has three timers at 0xba000, 0xbb000 and 0xd1000. The
> +first two provide four channels, the last (in the AON - Always ON power
> +domain) provides only two.
> +
> +Required properties:
> +
> +- compatible : should be "brcm,bcm476x-system-timer"
> +- reg : Specifies base physical address and size of the registers.
> +- interrupts : A list of 2 or 4 interrupt sinks; one per timer channel.
> +- clock-frequency : The frequency of the clock that drives the counter, in Hz.
> +
> +Example:
> +
> +timer {
> + compatible = "brcm,bcm476x-system-timer";
> + reg = <0xba000 0x1000>;
> + interrupts = <4>, <11>;
> + clock-frequency = <24000000>;
> +};
> Index: b/arch/arm/boot/dts/bcm476x.dtsi
> ===================================================================
> --- a/arch/arm/boot/dts/bcm476x.dtsi
> +++ b/arch/arm/boot/dts/bcm476x.dtsi
> @@ -14,6 +14,14 @@
> #size-cells = <1>;
> ranges;
>
> + timer {
> + compatible = "brcm,bcm476x-system-timer";
> + reg = <0xba000 0x1000>;
> + interrupt-parent = <&vic0>;
> + interrupts = <4>, <11>;
> + clock-frequency = <24000000>;
> + };
This should rather be timer: timer at ba0000 for this node to be uniquely named.
--
Florian
^ permalink raw reply
* [PATCH 1/6] ARM: bcm476x: Add infrastructure
From: Florian Fainelli @ 2012-10-08 11:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121007015405.958959522@gmail.com>
Hi Domenico,
On Sunday 07 October 2012 03:53:01 Domenico Andreoli wrote:
> From: Domenico Andreoli <domenico.andreoli@linux.com>
>
> BCM476x's minimal infrastructure, Kernel's great reuse.
>
> Look mom, no include/mach directory!
This is going to be in the commit, use something more sensible ;)
>
> Signed-off-by: Domenico Andreoli <domenico.andreoli@linux.com>
> ---
[snip]
> Index: b/arch/arm/boot/dts/bcm476x.dtsi
> ===================================================================
> --- /dev/null
> +++ b/arch/arm/boot/dts/bcm476x.dtsi
> @@ -0,0 +1,31 @@
> +/include/ "skeleton.dtsi"
> +
> +/ {
> + compatible = "brcm,bcm476x";
> + model = "Broadcom BCM476x";
> +
> + chosen {
> + bootargs = "earlyprintk";
> + };
> +
> + amba {
I would rather explicitely mention that the peripheral base address is at 0
so something like this:
amba at 0 {
to make it clear that the peripherals declared as leaf nodes of this one are
at a relative address.
> + compatible = "arm,amba-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + vic0: interrupt-controller at 80000 {
> + compatible = "brcm,bcm476x-pl192", "arm,pl192-vic", "arm,primecell";
> + reg = <0x80000 0x1000>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> +
> + vic1: interrupt-controller at 81000 {
> + compatible = "brcm,bcm476x-pl192", "arm,pl192-vic", "arm,primecell";
> + reg = <0x81000 0x1000>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +};
> Index: b/arch/arm/configs/bcm476x_defconfig
> ===================================================================
> --- /dev/null
> +++ b/arch/arm/configs/bcm476x_defconfig
> @@ -0,0 +1,352 @@
[snip]
> +CONFIG_ARM_APPENDED_DTB=y
> +CONFIG_ARM_ATAG_DTB_COMPAT=y
> +CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
> +CONFIG_CMDLINE="root=/dev/mmcblk0p2 ro console=ttyAMA1,115200 rootwait init=/bin/bash"
remove the specific init=, let people use the defaults.
--
Florian
^ permalink raw reply
* [PATCH v4] Enable USB peripheral on dm365 EVM
From: Sekhar Nori @ 2012-10-08 11:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1349367753-6725-1-git-send-email-const@MakeLinux.com>
Hi Constantine,
On 10/4/2012 9:52 PM, Constantine Shulyupin wrote:
> From: Constantine Shulyupin <const@MakeLinux.com>
>
> Signed-off-by: Constantine Shulyupin <const@MakeLinux.com>
> ---
>
> Note:
>
> USBPHY_CTL_PADDR and USBPHY_CLKFREQ_24MHZ are defined in board-dm365-evm.c because davinci.h can't be included from drivers/usb/musb/. May be davinci.h should be renamed and moved to arch/arm/mach-davinci/include/mach/usb.h like arch/arm/plat-omap/include/plat/usb.h
>
> Tested with usb gadget g_zero.
>
> Changelog
>
> Changes since v3 http://www.spinics.net/lists/kernel/msg1412544.html:
> - removed optional altering of pr_info
>
> Changes since v2 http://article.gmane.org/gmane.linux.kernel/1159868/
> - reordered code
> - removed alternation of GPIO33, which is multiplexed with DRVVBUS, because is not need for peripheral USB
>
> Changes since v1 http://marc.info/?l=linux-kernel&m=130894150803661&w=2:
> - removed optional code and reordered
>
> This patch is based on code from Arago, Angstom, and RidgeRun projects.
> Original patch by miguel.aguilar at ridgerun.com is three years ago:
> - http://www.mail-archive.com/davinci-linux-open-source at linux.davincidsp.com/msg14741.html
>
> ---
> arch/arm/mach-davinci/board-dm365-evm.c | 8 ++++++++
> arch/arm/mach-davinci/usb.c | 2 ++
> drivers/usb/musb/davinci.h | 1 +
> drivers/usb/musb/musb_core.c | 20 ++++++++++++--------
> 4 files changed, 23 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
> index 3a4743b..dfcb67f 100644
> --- a/arch/arm/mach-davinci/board-dm365-evm.c
> +++ b/arch/arm/mach-davinci/board-dm365-evm.c
> @@ -38,6 +38,8 @@
> #include <mach/mmc.h>
> #include <mach/nand.h>
> #include <mach/keyscan.h>
> +#include <mach/usb.h>
> +#include <mach/hardware.h>
>
> #include <media/tvp514x.h>
>
> @@ -92,6 +94,9 @@ static inline int have_tvp7002(void)
> #define CPLD_CCD_DIR3 CPLD_OFFSET(0x3f,0)
> #define CPLD_CCD_IO3 CPLD_OFFSET(0x3f,1)
>
> +#define USBPHY_CTL_PADDR 0x01c40034
> +#define USBPHY_CLKFREQ_24MHZ BIT(13)
> +
> static void __iomem *cpld;
>
>
> @@ -613,6 +618,9 @@ static __init void dm365_evm_init(void)
>
> dm365_init_spi0(BIT(0), dm365_evm_spi_info,
> ARRAY_SIZE(dm365_evm_spi_info));
> + writel(readl(IO_ADDRESS(USBPHY_CTL_PADDR)) | USBPHY_CLKFREQ_24MHZ,
> + IO_ADDRESS(USBPHY_CTL_PADDR));
> + davinci_setup_usb(500, 8);
Add a comment here on why current is limited to 500 mA? Probably coming
because of an on-board component?
> }
>
> MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM")
> diff --git a/arch/arm/mach-davinci/usb.c b/arch/arm/mach-davinci/usb.c
> index 23d2b6d..664c689 100644
> --- a/arch/arm/mach-davinci/usb.c
> +++ b/arch/arm/mach-davinci/usb.c
> @@ -49,6 +49,8 @@ static struct musb_hdrc_platform_data usb_data = {
> .mode = MUSB_PERIPHERAL,
> #elif defined(CONFIG_USB_MUSB_HOST)
> .mode = MUSB_HOST,
> +#else
> + .mode = MUSB_OTG,
This does not look to be directly related to DM365 support and should be
separated into a different patch.
> #endif
> .clock = "usb",
> .config = &musb_config,
> diff --git a/drivers/usb/musb/davinci.h b/drivers/usb/musb/davinci.h
> index 371baa0..e737d97 100644
> --- a/drivers/usb/musb/davinci.h
> +++ b/drivers/usb/musb/davinci.h
> @@ -16,6 +16,7 @@
>
> /* Integrated highspeed/otg PHY */
> #define USBPHY_CTL_PADDR 0x01c40034
> +#define USBPHY_CLKFREQ_24MHZ BIT(13)
You have added this repeat definition and do not use it anywhere.
Looks like all PHY related configuration is currently happening in
drivers/usb/musb/davinci.c and the same register is also being written
to for other platforms. Can you move the code you have included in board
file to the driver? As we move towards DT, we need to avoid register
configurations from board files anyway.
Thanks,
Sekhar
^ permalink raw reply
* [PATCH V2 1/2] ARM: remove unnecessary flush of anon pages in flush_dcache_page()
From: Catalin Marinas @ 2012-10-08 11:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1349609352-6408-2-git-send-email-gmbnomis@gmail.com>
On Sun, Oct 07, 2012 at 12:29:11PM +0100, Simon Baatz wrote:
> On non-aliasing VIPT D-caches, there is no need to flush the kernel
> mapping of anon pages in flush_dcache_page() directly. If the page is
> mapped as executable later, the necessary D/I-cache flush will be done
> in __sync_icache_dcache().
>
> Signed-off-by: Simon Baatz <gmbnomis@gmail.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Russell King <linux@arm.linux.org.uk>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
^ permalink raw reply
* [PATCH v2 2/7] ARM: virt: allow the kernel to be entered in HYP mode
From: Dave Martin @ 2012-10-08 11:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121008110109.GE2302@linaro.org>
On Mon, Oct 08, 2012 at 12:01:09PM +0100, Dave Martin wrote:
> On Sat, Oct 06, 2012 at 09:00:32AM -0700, Tony Lindgren wrote:
> > * Marc Zyngier <marc.zyngier@arm.com> [121006 03:19]:
> > >
> > > If so, that indicates some side effect of the safe_svcmode_maskall macro,
> > > and I suspect the "movs pc, lr" bit.
> > >
> > > Can you try the attached patch? It basically falls back to the previous
> > > behaviour if not entered in HYP mode.
> > ...
> >
> > > diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
> > > index 658a15d..b21b97f 100644
> > > --- a/arch/arm/include/asm/assembler.h
> > > +++ b/arch/arm/include/asm/assembler.h
> > > @@ -254,16 +254,17 @@
> > > mov lr , \reg
> > > and lr , lr , #MODE_MASK
> > > cmp lr , #HYP_MODE
> > > - orr \reg , \reg , #PSR_A_BIT | PSR_I_BIT | PSR_F_BIT
> > > + orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT
> > > bic \reg , \reg , #MODE_MASK
> > > orr \reg , \reg , #SVC_MODE
> > > THUMB( orr \reg , \reg , #PSR_T_BIT )
> > > - msr spsr_cxsf, \reg
> > > - adr lr, BSYM(2f)
> > > bne 1f
> > > + orr \reg, \reg, #PSR_A_BIT
> > > + adr lr, BSYM(2f)
> > > + msr spsr_cxsf, \reg
> > > __MSR_ELR_HYP(14)
> > > __ERET
> > > -1: movs pc, lr
> > > +1: msr cpsr_c, \reg
> > > 2:
> > > .endm
> > >
> >
> > The minimal version of this that still boots on my n800 is just
> > the last change of the above patch:
> >
> > --- a/arch/arm/include/asm/assembler.h
> > +++ b/arch/arm/include/asm/assembler.h
> > @@ -263,7 +263,7 @@ THUMB( orr \reg , \reg , #PSR_T_BIT )
> > bne 1f
> > __MSR_ELR_HYP(14)
> > __ERET
> > -1: movs pc, lr
> > +1: msr cpsr_c, \reg
> > 2:
> > .endm
> >
>
> In an attempt to narrow this down...
>
> Can you follow this (i.e., _after_ a known successful switch to SVC mode)
>
> (a)
> mrs \reg, cpsr
> msr spsr_cxsf, \reg
> adr \reg, 3f
> movs pc, lr
> 3:
>
> and (b)
>
> mrs \reg, cpsr
> orr \reg, \reg, #CPSR_A_BIT
> msr cpsr_cxsf, \reg
>
> and (c)
>
> mrs \reg, cpsr
> orr \reg, \reg, #CPSR_A_BIT
> msr spsr_cxsf, \reg
> adr \reg, 3f
> movs pc, lr
> 3:
>
>
>
>
> If only (a) works, this would suggest that the attempt to set the A bit
> is causing the problem.
>
> If only (b) works, this suggests that the A bit is OK but that some
> invalid hardware state, or something else we don't understand, is causing
> exception returns to fail in general.
>
> If (a) and (b) work but (c) fails, this suggests that specifically
> trying to set the A bit via an exception return is problematic.
>
> If all of them work then this suggests some invalid hardware state or
> something else we don't understand, but which is cleared by the initial
> msr cpsr_c which clobbers the processor mode.
Marc Z also just pointed out to me that there is one architecturally
valid explanation for why the movs route could fail: if the kernel is
entered in System mode for some reason -- this causes msr spsr and movs
pc to become UNPREDICTABLE. If this is the explanation, then
(a), (b) and (c) should all work, provided the CPU has already been forced
out of System mode.
Of course, we're not supposed to be entered in System mode ... but since
the whole purpose of this code is to force us into a sane state, we should
work around it anyway. I think Marc is busy rolling a patch for that.
Cheers
---Dave
^ permalink raw reply
* [PATCH v2 2/7] ARM: virt: allow the kernel to be entered in HYP mode
From: Marc Zyngier @ 2012-10-08 11:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121008110109.GE2302@linaro.org>
On 08/10/12 12:01, Dave Martin wrote:
> On Sat, Oct 06, 2012 at 09:00:32AM -0700, Tony Lindgren wrote:
>> * Marc Zyngier <marc.zyngier@arm.com> [121006 03:19]:
>>>
>>> If so, that indicates some side effect of the safe_svcmode_maskall macro,
>>> and I suspect the "movs pc, lr" bit.
>>>
>>> Can you try the attached patch? It basically falls back to the previous
>>> behaviour if not entered in HYP mode.
>> ...
>>
>>> diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
>>> index 658a15d..b21b97f 100644
>>> --- a/arch/arm/include/asm/assembler.h
>>> +++ b/arch/arm/include/asm/assembler.h
>>> @@ -254,16 +254,17 @@
>>> mov lr , \reg
>>> and lr , lr , #MODE_MASK
>>> cmp lr , #HYP_MODE
>>> - orr \reg , \reg , #PSR_A_BIT | PSR_I_BIT | PSR_F_BIT
>>> + orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT
>>> bic \reg , \reg , #MODE_MASK
>>> orr \reg , \reg , #SVC_MODE
>>> THUMB( orr \reg , \reg , #PSR_T_BIT )
>>> - msr spsr_cxsf, \reg
>>> - adr lr, BSYM(2f)
>>> bne 1f
>>> + orr \reg, \reg, #PSR_A_BIT
>>> + adr lr, BSYM(2f)
>>> + msr spsr_cxsf, \reg
>>> __MSR_ELR_HYP(14)
>>> __ERET
>>> -1: movs pc, lr
>>> +1: msr cpsr_c, \reg
>>> 2:
>>> .endm
>>>
>>
>> The minimal version of this that still boots on my n800 is just
>> the last change of the above patch:
>>
>> --- a/arch/arm/include/asm/assembler.h
>> +++ b/arch/arm/include/asm/assembler.h
>> @@ -263,7 +263,7 @@ THUMB( orr \reg , \reg , #PSR_T_BIT )
>> bne 1f
>> __MSR_ELR_HYP(14)
>> __ERET
>> -1: movs pc, lr
>> +1: msr cpsr_c, \reg
>> 2:
>> .endm
>>
>
> In an attempt to narrow this down...
>
> Can you follow this (i.e., _after_ a known successful switch to SVC mode)
>
> (a)
> mrs \reg, cpsr
> msr spsr_cxsf, \reg
> adr \reg, 3f
> movs pc, lr
> 3:
>
> and (b)
>
> mrs \reg, cpsr
> orr \reg, \reg, #CPSR_A_BIT
> msr cpsr_cxsf, \reg
>
> and (c)
>
> mrs \reg, cpsr
> orr \reg, \reg, #CPSR_A_BIT
> msr spsr_cxsf, \reg
> adr \reg, 3f
> movs pc, lr
> 3:
>
>
>
>
> If only (a) works, this would suggest that the attempt to set the A bit
> is causing the problem.
>
> If only (b) works, this suggests that the A bit is OK but that some
> invalid hardware state, or something else we don't understand, is causing
> exception returns to fail in general.
>
> If (a) and (b) work but (c) fails, this suggests that specifically
> trying to set the A bit via an exception return is problematic.
>
> If all of them work then this suggests some invalid hardware state or
> something else we don't understand, but which is cleared by the initial
> msr cpsr_c which clobbers the processor mode.
Playing with an Integrator-CP with a 1136 tile, the only way I could
cause the thing to fail was to boot the thing in SYSTEM mode.
Tony, can you possibly also try the attached patch?
Thanks,
M.
--
Jazz is not dead. It just smells funny...
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^ permalink raw reply
* [PATCH v4 6/7] ARM: davinci: clean up DA850 EVM include ordering
From: Sekhar Nori @ 2012-10-08 11:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1349456686-22736-7-git-send-email-mporter@ti.com>
On 10/5/2012 10:34 PM, Matt Porter wrote:
> Reorder includes so they are grouped by linux/mach/asm
>
> Signed-off-by: Matt Porter <mporter@ti.com>
Thanks for the clean-up. While committing, I changed the subject to:
"ARM: davinci: da850 evm: clean up include ordering"
which is the convention I prefer.
Thanks,
Sekhar
^ permalink raw reply
* [PATCH v2 2/7] ARM: virt: allow the kernel to be entered in HYP mode
From: Dave Martin @ 2012-10-08 11:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121006160031.GC3874@atomide.com>
On Sat, Oct 06, 2012 at 09:00:32AM -0700, Tony Lindgren wrote:
> * Marc Zyngier <marc.zyngier@arm.com> [121006 03:19]:
> >
> > If so, that indicates some side effect of the safe_svcmode_maskall macro,
> > and I suspect the "movs pc, lr" bit.
> >
> > Can you try the attached patch? It basically falls back to the previous
> > behaviour if not entered in HYP mode.
> ...
>
> > diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
> > index 658a15d..b21b97f 100644
> > --- a/arch/arm/include/asm/assembler.h
> > +++ b/arch/arm/include/asm/assembler.h
> > @@ -254,16 +254,17 @@
> > mov lr , \reg
> > and lr , lr , #MODE_MASK
> > cmp lr , #HYP_MODE
> > - orr \reg , \reg , #PSR_A_BIT | PSR_I_BIT | PSR_F_BIT
> > + orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT
> > bic \reg , \reg , #MODE_MASK
> > orr \reg , \reg , #SVC_MODE
> > THUMB( orr \reg , \reg , #PSR_T_BIT )
> > - msr spsr_cxsf, \reg
> > - adr lr, BSYM(2f)
> > bne 1f
> > + orr \reg, \reg, #PSR_A_BIT
> > + adr lr, BSYM(2f)
> > + msr spsr_cxsf, \reg
> > __MSR_ELR_HYP(14)
> > __ERET
> > -1: movs pc, lr
> > +1: msr cpsr_c, \reg
> > 2:
> > .endm
> >
>
> The minimal version of this that still boots on my n800 is just
> the last change of the above patch:
>
> --- a/arch/arm/include/asm/assembler.h
> +++ b/arch/arm/include/asm/assembler.h
> @@ -263,7 +263,7 @@ THUMB( orr \reg , \reg , #PSR_T_BIT )
> bne 1f
> __MSR_ELR_HYP(14)
> __ERET
> -1: movs pc, lr
> +1: msr cpsr_c, \reg
> 2:
> .endm
>
In an attempt to narrow this down...
Can you follow this (i.e., _after_ a known successful switch to SVC mode)
(a)
mrs \reg, cpsr
msr spsr_cxsf, \reg
adr \reg, 3f
movs pc, lr
3:
and (b)
mrs \reg, cpsr
orr \reg, \reg, #CPSR_A_BIT
msr cpsr_cxsf, \reg
and (c)
mrs \reg, cpsr
orr \reg, \reg, #CPSR_A_BIT
msr spsr_cxsf, \reg
adr \reg, 3f
movs pc, lr
3:
If only (a) works, this would suggest that the attempt to set the A bit
is causing the problem.
If only (b) works, this suggests that the A bit is OK but that some
invalid hardware state, or something else we don't understand, is causing
exception returns to fail in general.
If (a) and (b) work but (c) fails, this suggests that specifically
trying to set the A bit via an exception return is problematic.
If all of them work then this suggests some invalid hardware state or
something else we don't understand, but which is cleared by the initial
msr cpsr_c which clobbers the processor mode.
Cheers
---Dave
^ permalink raw reply
* [PATCH v4 0/7] uio_pruss cleanup and platform support
From: Sekhar Nori @ 2012-10-08 10:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1349456686-22736-1-git-send-email-mporter@ti.com>
On 10/5/2012 10:34 PM, Matt Porter wrote:
> This series enables uio_pruss on DA850 and removes use of the
> private SRAM API by the driver. The driver previously was not
> enabled by any platform and the private SRAM API was accessing
> an invalid SRAM bank.
>
> It is regression tested on AM180x EVM with suspend/resume due
> to the new use of the shared SRAM for both PM and PRUSS. The
> uio_pruss driver is tested on the same platform using the
> PRU_memAccessPRUDataRam and PRU_memAccessL3andDDR examples from
> the PRU userspace tools available from http://www.ti.com/tool/sprc940
I applied patches 2/7, 3/7 and 6/7 of this series for v3.8. I have some
comments on the board patch. Rest of the patches depend on acceptance of
1/7 so I will take them only after that is accepted.
Thanks,
Sekhar
^ permalink raw reply
* [PATCH] ARM: imx: fix the return value check in imx_clk_busy_divider()
From: Sascha Hauer @ 2012-10-08 10:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAPgLHd-0wYjWxWrmLdc+an0RVfEicv3QBEtvsuvQtphti3phdw@mail.gmail.com>
On Fri, Sep 21, 2012 at 02:14:25PM +0800, Wei Yongjun wrote:
> From: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
>
> In case of error, the function clk_register() returns ERR_PTR()
> no NULL pointer. The NULL test in the return value check should
> be replaced with IS_ERR().
>
> dpatch engine is used to auto generated this patch.
> (https://github.com/weiyj/dpatch)
>
> Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Applied, thanks
Sascha
> ---
> arch/arm/mach-imx/clk-busy.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-imx/clk-busy.c b/arch/arm/mach-imx/clk-busy.c
> index 1a7a8dd..1ab91b5 100644
> --- a/arch/arm/mach-imx/clk-busy.c
> +++ b/arch/arm/mach-imx/clk-busy.c
> @@ -108,7 +108,7 @@ struct clk *imx_clk_busy_divider(const char *name, const char *parent_name,
> busy->div.hw.init = &init;
>
> clk = clk_register(NULL, &busy->div.hw);
> - if (!clk)
> + if (IS_ERR(clk))
> kfree(busy);
>
> return clk;
>
>
>
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply
* [PATCH v4 7/7] ARM: davinci: register pruss_uio device on DA850 EVM
From: Sekhar Nori @ 2012-10-08 10:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1349456686-22736-8-git-send-email-mporter@ti.com>
On 10/5/2012 10:34 PM, Matt Porter wrote:
> Configures the required pdata and registers the pruss_uio
> platform device on the DA850 EVM.
>
> Tested on AM180x-EVM using the PRU_memAccessPRUDataRam and
> PRU_memAccessL3andDDR examples from the PRU userspace tools
> available from http://www.ti.com/tool/sprc940
>
> Signed-off-by: Matt Porter <mporter@ti.com>
> ---
> arch/arm/mach-davinci/board-da850-evm.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
> index 7359375..6f9478b 100644
> --- a/arch/arm/mach-davinci/board-da850-evm.c
> +++ b/arch/arm/mach-davinci/board-da850-evm.c
> @@ -31,6 +31,7 @@
> #include <linux/platform_data/mtd-davinci.h>
> #include <linux/platform_data/mtd-davinci-aemif.h>
> #include <linux/platform_data/spi-davinci.h>
> +#include <linux/platform_data/uio_pruss.h>
> #include <linux/regulator/machine.h>
> #include <linux/regulator/tps6507x.h>
> #include <linux/spi/spi.h>
> @@ -40,6 +41,7 @@
> #include <mach/cp_intc.h>
> #include <mach/da8xx.h>
> #include <mach/mux.h>
> +#include <mach/sram.h>
>
> #include <asm/mach-types.h>
> #include <asm/mach/arch.h>
> @@ -1253,6 +1255,10 @@ static __init int da850_wl12xx_init(void)
>
> #endif /* CONFIG_DA850_WL12XX */
>
> +struct uio_pruss_pdata da8xx_pruss_uio_pdata = {
> + .pintc_base = 0x4000,
> +};
> +
> #define DA850EVM_SATA_REFCLKPN_RATE (100 * 1000 * 1000)
>
> static __init void da850_evm_init(void)
> @@ -1339,6 +1345,12 @@ static __init void da850_evm_init(void)
> pr_warning("da850_evm_init: lcdcntl mux setup failed: %d\n",
> ret);
>
> + da8xx_pruss_uio_pdata.sram_pool = sram_get_gen_pool();
> + ret = da8xx_register_pruss_uio(&da8xx_pruss_uio_pdata);
> + if (ret)
> + pr_warning("pruss_uio initialization failed: %d\n",
> + ret);
I failed to mention this last time around, but is there any reason
platform data will change from board to board? Looks like the pintc_base
is SoC specific and that all platforms would use SRAM when using the
pruss driver. Looks like you can make da8xx_register_pruss_uio() take no
parameters at all.
Thanks,
Sekhar
^ permalink raw reply
* [PATCH] [ARM] Use AT() in the linker script to create correct program headers
From: Dave Martin @ 2012-10-08 10:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121004175907.GB2994@obsidianresearch.com>
On Thu, Oct 04, 2012 at 11:59:07AM -0600, Jason Gunthorpe wrote:
> On Thu, Oct 04, 2012 at 12:36:37PM +0100, Dave Martin wrote:
>
> > OK, so it is supported, but not for ARM, yet. I'm not sure that
> > such a patch would be rejected, since building in a DTB is not
> > really that different from building in a command-line.
>
> Maybe I will be able to look at this in a few months..
>
> > The other solution to this problem is to distribute the dtb
> > alongside the kernel as a supplementary image (similar to
> > initramfs), with the bootloader doing the bare minimum of
> > modifications to it.
>
> Yes, but we still need rely on complex code like I2C/MTD to create a
> correct DTB, which again puts us back to patching the kernel for that
> functionality.
I'm still confused as to where this complexity is coming from.
If you need to run some complex I2C and MTD code to generate the DT, what
is that code doing? If it is probing to get the information, then can you
avoid putting the info in the DT at all? Primarily the DT is to describe
those aspects of the hardware which can't be probed.
Otherwise, you that have a few static configurations: you could have one
pre-baked DT per hardware platform, and choose the correct one once you
have detected the platform.
> > Naturally, if zero modifications are needed then the bootloader does not
> > need libfdt (or equivalent code) at all.
>
> If only :)
>
> > One other option open to you would be to provide an ELF image loadable
> > by your bootloader via a simple wrapper. This would probably be a more
> > robust approach than carrying patches against head.S, since it removes
> > any intimate dependency on the kernel code itself.
>
> This is what I ment by having a 2nd stage loader, but this example is
> not complete because at this point you also have to patch into the DTB
> the initrd address (passed in r0/r1), and the various MAC addresses
> (getting them is the hard part..).
>
> The nice thing about the head.S patch is that it lives right after
> _entry, so there actually are no dependencies on the kernel code, it
> executes in the same environment as the example you presented.
Well, logically there's little difference unless your patch were to be
merged. An out-of-tree patch against head.S could be more effort to
maintain in some situations, but that code doesn't evolve rapidly.
> Anyhow, exploring a CONFIG_ARM_BUILT_IN_DTB.. I think I'd add
> something like this to head.S:
>
> #ifdef CONFIG_ARM_BUILT_IN_DTB
> adr r3,bootloader_r0
> stmia r3,{r0,r1,r2}
> mov r2, #0
> mov r1, #0
> mov r0, #0
> #else
> bl __vet_atags
> #endif
>
> And something like this to early_dt_fixup:
>
> #ifdef CONFIG_ARM_BUILT_IN_DTB
> for_each_dt_provider(dtp) {
> devtree = dtp->get_dtb();
> if (devtree)
> break;
> }
> #else
> devtree = phys_to_virt(dt_phys);
> #endif
>
> Where the 'dev tree provider' would use the stored bootloader
> registers and any other information to return the proper DTB.
It would need developing a bit, but something like that might be
possible -- it should probably be discussed via devicetree-discuss.
If it is doing anything less trivial than picking a pre-baked DT, the
rationale would need to be carefully argued.
Cheers
---Dave
^ permalink raw reply
* [PATCH 7/7] ARM: tegra30: cpuidle: add LP2 driver for CPU0
From: Joseph Lo @ 2012-10-08 10:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1349691981-31038-1-git-send-email-josephl@nvidia.com>
The cpuidle LP2 is a power gating idle mode. It support power gating
vdd_cpu rail after all cpu cores in LP2. For Tegra30, the CPU0 must
be last one to go into LP2. We need to take care and make sure whole
secondary CPUs were in LP2 by checking CPU and power gate status.
After that, the CPU0 can go into LP2 safely. Then power gating the
CPU rail.
Base on the work by:
Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
arch/arm/mach-tegra/cpuidle-tegra30.c | 39 ++++++++-
arch/arm/mach-tegra/pm.c | 152 +++++++++++++++++++++++++++++++++
arch/arm/mach-tegra/pm.h | 3 +
arch/arm/mach-tegra/sleep-tegra30.S | 44 ++++++++++
arch/arm/mach-tegra/sleep.S | 44 ++++++++++
arch/arm/mach-tegra/sleep.h | 2 +
6 files changed, 280 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-tegra/cpuidle-tegra30.c b/arch/arm/mach-tegra/cpuidle-tegra30.c
index 842fef4..1fd938b 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra30.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra30.c
@@ -28,6 +28,7 @@
#include "pm.h"
#include "sleep.h"
+#include "tegra_cpu_car.h"
#ifdef CONFIG_PM_SLEEP
static int tegra30_idle_lp2(struct cpuidle_device *dev,
@@ -59,6 +60,28 @@ static struct cpuidle_driver tegra_idle_driver = {
static DEFINE_PER_CPU(struct cpuidle_device, tegra_idle_device);
#ifdef CONFIG_PM_SLEEP
+static bool tegra30_idle_enter_lp2_cpu_0(struct cpuidle_device *dev,
+ struct cpuidle_driver *drv,
+ int index)
+{
+ struct cpuidle_state *state = &drv->states[index];
+ u32 cpu_on_time = state->exit_latency;
+ u32 cpu_off_time = state->target_residency - state->exit_latency;
+
+ if (num_online_cpus() > 1 && !tegra_cpu_rail_off_ready()) {
+ cpu_do_idle();
+ return false;
+ }
+
+ clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
+
+ tegra_idle_lp2_last(cpu_on_time, cpu_off_time);
+
+ clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
+
+ return true;
+}
+
static bool tegra30_idle_enter_lp2_cpu_n(struct cpuidle_device *dev,
struct cpuidle_driver *drv,
int index)
@@ -85,16 +108,22 @@ static int __cpuinit tegra30_idle_lp2(struct cpuidle_device *dev,
int index)
{
bool entered_lp2 = false;
+ bool last_cpu;
local_fiq_disable();
- tegra_set_cpu_in_lp2(dev->cpu);
+ last_cpu = tegra_set_cpu_in_lp2(dev->cpu);
cpu_pm_enter();
- if (dev->cpu == 0)
- cpu_do_idle();
- else
+ if (dev->cpu == 0) {
+ if (last_cpu)
+ entered_lp2 = tegra30_idle_enter_lp2_cpu_0(dev, drv,
+ index);
+ else
+ cpu_do_idle();
+ } else {
entered_lp2 = tegra30_idle_enter_lp2_cpu_n(dev, drv, index);
+ }
cpu_pm_exit();
tegra_clear_cpu_in_lp2(dev->cpu);
@@ -116,6 +145,8 @@ int __init tegra30_cpuidle_init(void)
#ifndef CONFIG_PM_SLEEP
drv->state_count = 1; /* support clockgating only */
+#else
+ tegra_tear_down_cpu = tegra30_tear_down_cpu;
#endif
ret = cpuidle_register_driver(&tegra_idle_driver);
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
index 4655383..2e71bad 100644
--- a/arch/arm/mach-tegra/pm.c
+++ b/arch/arm/mach-tegra/pm.c
@@ -20,15 +20,38 @@
#include <linux/spinlock.h>
#include <linux/io.h>
#include <linux/cpumask.h>
+#include <linux/delay.h>
+#include <linux/cpu_pm.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+
+#include <asm/smp_plat.h>
+#include <asm/cacheflush.h>
+#include <asm/suspend.h>
+#include <asm/idmap.h>
+#include <asm/proc-fns.h>
+#include <asm/tlbflush.h>
#include <mach/iomap.h>
#include "reset.h"
+#include "flowctrl.h"
+#include "sleep.h"
+#include "tegra_cpu_car.h"
+
+#define TEGRA_POWER_CPU_PWRREQ_OE (1 << 16) /* CPU pwr req enable */
+
+#define PMC_CTRL 0x0
+#define PMC_CPUPWRGOOD_TIMER 0xc8
+#define PMC_CPUPWROFF_TIMER 0xcc
#ifdef CONFIG_PM_SLEEP
static unsigned int g_diag_reg;
static DEFINE_SPINLOCK(tegra_lp2_lock);
static cpumask_t tegra_in_lp2;
+static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
+static struct clk *tegra_pclk;
+void (*tegra_tear_down_cpu)(void);
void save_cpu_arch_register(void)
{
@@ -44,6 +67,96 @@ void restore_cpu_arch_register(void)
return;
}
+static void set_power_timers(unsigned long us_on, unsigned long us_off)
+{
+ unsigned long long ticks;
+ unsigned long long pclk;
+ unsigned long rate;
+ static unsigned long tegra_last_pclk;
+
+ if (tegra_pclk == NULL) {
+ tegra_pclk = clk_get_sys(NULL, "pclk");
+ if (IS_ERR(tegra_pclk)) {
+ /*
+ * pclk not been init or not exist.
+ * Use sclk to take the place of it.
+ * The default setting was pclk=sclk.
+ */
+ tegra_pclk = clk_get_sys(NULL, "sclk");
+ }
+ }
+
+ rate = clk_get_rate(tegra_pclk);
+
+ if (WARN_ON_ONCE(rate <= 0))
+ pclk = 100000000;
+ else
+ pclk = rate;
+
+ if ((rate != tegra_last_pclk)) {
+ ticks = (us_on * pclk) + 999999ull;
+ do_div(ticks, 1000000);
+ writel((unsigned long)ticks, pmc + PMC_CPUPWRGOOD_TIMER);
+
+ ticks = (us_off * pclk) + 999999ull;
+ do_div(ticks, 1000000);
+ writel((unsigned long)ticks, pmc + PMC_CPUPWROFF_TIMER);
+ wmb();
+ }
+ tegra_last_pclk = pclk;
+}
+
+/*
+ * restore_cpu_complex
+ *
+ * restores cpu clock setting, clears flow controller
+ *
+ * Always called on CPU 0.
+ */
+static void restore_cpu_complex(void)
+{
+ int cpu = smp_processor_id();
+
+ BUG_ON(cpu != 0);
+
+#ifdef CONFIG_SMP
+ cpu = cpu_logical_map(cpu);
+#endif
+
+ /* Restore the CPU clock settings */
+ tegra_cpu_clock_resume();
+
+ flowctrl_cpu_suspend_exit(cpu);
+
+ restore_cpu_arch_register();
+}
+
+/*
+ * suspend_cpu_complex
+ *
+ * saves pll state for use by restart_plls, prepares flow controller for
+ * transition to suspend state
+ *
+ * Must always be called on cpu 0.
+ */
+static void suspend_cpu_complex(void)
+{
+ int cpu = smp_processor_id();
+
+ BUG_ON(cpu != 0);
+
+#ifdef CONFIG_SMP
+ cpu = cpu_logical_map(cpu);
+#endif
+
+ /* Save the CPU clock settings */
+ tegra_cpu_clock_suspend();
+
+ flowctrl_cpu_suspend_enter(cpu);
+
+ save_cpu_arch_register();
+}
+
void __cpuinit tegra_clear_cpu_in_lp2(int cpu)
{
spin_lock(&tegra_lp2_lock);
@@ -85,4 +198,43 @@ bool __cpuinit tegra_set_cpu_in_lp2(int cpu)
spin_unlock(&tegra_lp2_lock);
return last_cpu;
}
+
+static int tegra_sleep_cpu(unsigned long v2p)
+{
+ /* Switch to the identity mapping. */
+ cpu_switch_mm(idmap_pgd, &init_mm);
+
+ /* Flush the TLB. */
+ local_flush_tlb_all();
+
+ tegra_sleep_cpu_finish(v2p);
+
+ /* should never here */
+ BUG();
+
+ return 0;
+}
+
+void tegra_idle_lp2_last(u32 cpu_on_time, u32 cpu_off_time)
+{
+ u32 mode;
+
+ /* Only the last cpu down does the final suspend steps */
+ mode = readl(pmc + PMC_CTRL);
+ mode |= TEGRA_POWER_CPU_PWRREQ_OE;
+ writel(mode, pmc + PMC_CTRL);
+
+ set_power_timers(cpu_on_time, cpu_off_time);
+
+ cpu_cluster_pm_enter();
+ suspend_cpu_complex();
+ flush_cache_all();
+ outer_disable();
+
+ cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu);
+
+ outer_resume();
+ restore_cpu_complex();
+ cpu_cluster_pm_exit();
+}
#endif
diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h
index 21858d6..63ffe02 100644
--- a/arch/arm/mach-tegra/pm.h
+++ b/arch/arm/mach-tegra/pm.h
@@ -27,4 +27,7 @@ void restore_cpu_arch_register(void);
void tegra_clear_cpu_in_lp2(int cpu);
bool tegra_set_cpu_in_lp2(int cpu);
+void tegra_idle_lp2_last(u32 cpu_on_time, u32 cpu_off_time);
+extern void (*tegra_tear_down_cpu)(void);
+
#endif /* _MACH_TEGRA_PM_H_ */
diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
index 67b1cba..aef5ce7 100644
--- a/arch/arm/mach-tegra/sleep-tegra30.S
+++ b/arch/arm/mach-tegra/sleep-tegra30.S
@@ -130,4 +130,48 @@ ENTRY(tegra30_sleep_cpu_secondary_finish)
mov r0, #1 @ never return here
mov pc, r7
ENDPROC(tegra30_sleep_cpu_secondary_finish)
+
+/*
+ * tegra30_tear_down_cpu
+ *
+ * Switches the CPU to enter sleep.
+ */
+ENTRY(tegra30_tear_down_cpu)
+ mov32 r6, TEGRA_FLOW_CTRL_BASE
+
+ b tegra30_enter_sleep
+ENDPROC(tegra30_tear_down_cpu)
+
+/*
+ * tegra30_enter_sleep
+ *
+ * uses flow controller to enter sleep state
+ * executes from IRAM with SDRAM in selfrefresh when target state is LP0 or LP1
+ * executes from SDRAM with target state is LP2
+ * r6 = TEGRA_FLOW_CTRL_BASE
+ */
+tegra30_enter_sleep:
+ cpu_id r1
+
+ cpu_to_csr_reg r2, r1
+ ldr r0, [r6, r2]
+ orr r0, r0, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
+ orr r0, r0, #FLOW_CTRL_CSR_ENABLE
+ str r0, [r6, r2]
+
+ mov r0, #FLOW_CTRL_WAIT_FOR_INTERRUPT
+ orr r0, r0, #FLOW_CTRL_HALT_CPU_IRQ | FLOW_CTRL_HALT_CPU_FIQ
+ cpu_to_halt_reg r2, r1
+ str r0, [r6, r2]
+ dsb
+ ldr r0, [r6, r2] /* memory barrier */
+
+halted:
+ isb
+ dsb
+ wfi /* CPU should be power gated here */
+
+ /* !!!FIXME!!! Implement halt failure handler */
+ b halted
+
#endif
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S
index 7748fdb..3ab1e82 100644
--- a/arch/arm/mach-tegra/sleep.S
+++ b/arch/arm/mach-tegra/sleep.S
@@ -25,6 +25,7 @@
#include <linux/linkage.h>
#include <asm/assembler.h>
+#include <asm/cache.h>
#include <asm/cp15.h>
#include <mach/iomap.h>
@@ -96,4 +97,47 @@ finished:
mov pc, lr
ENDPROC(tegra_flush_l1_cache)
+/*
+ * tegra_sleep_cpu_finish(unsigned long v2p)
+ *
+ * enters suspend in LP2 by turning off the mmu and jumping to
+ * tegra?_tear_down_cpu
+ */
+ENTRY(tegra_sleep_cpu_finish)
+ /* Flush and disable the L1 data cache */
+ bl tegra_flush_l1_cache
+ /* Trun off coherency */
+ exit_smp r4, r5
+
+ mov32 r6, tegra_tear_down_cpu
+ ldr r1, [r6]
+ add r1, r1, r0
+
+ mov32 r3, tegra_shut_off_mmu
+ add r3, r3, r0
+ mov r0, r1
+
+ mov pc, r3
+ENDPROC(tegra_sleep_cpu_finish)
+
+/*
+ * tegra_shut_off_mmu
+ *
+ * r0 = physical address to jump to with mmu off
+ *
+ * called with VA=PA mapping
+ * turns off MMU, icache, dcache and branch prediction
+ */
+ .align L1_CACHE_SHIFT
+ .pushsection .idmap.text, "ax"
+ENTRY(tegra_shut_off_mmu)
+ mrc p15, 0, r3, c1, c0, 0
+ movw r2, #CR_I | CR_Z | CR_C | CR_M
+ bic r3, r3, r2
+ dsb
+ mcr p15, 0, r3, c1, c0, 0
+ isb
+ mov pc, r0
+ENDPROC(tegra_shut_off_mmu)
+ .popsection
#endif
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
index 220fbd1..001920f 100644
--- a/arch/arm/mach-tegra/sleep.h
+++ b/arch/arm/mach-tegra/sleep.h
@@ -73,6 +73,7 @@
.endm
#else
void tegra_resume(void);
+int tegra_sleep_cpu_finish(unsigned long);
#ifdef CONFIG_HOTPLUG_CPU
void tegra20_hotplug_init(void);
@@ -83,6 +84,7 @@ static inline void tegra30_hotplug_init(void) {}
#endif
int tegra30_sleep_cpu_secondary_finish(unsigned long);
+void tegra30_tear_down_cpu(void);
#endif
#endif
--
1.7.0.4
^ permalink raw reply related
* [PATCH 6/7] ARM: tegra30: flowctrl: add cpu_suspend_exter/exit function
From: Joseph Lo @ 2012-10-08 10:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1349691981-31038-1-git-send-email-josephl@nvidia.com>
The flow controller can help CPU to go into suspend mode (deep power
saving mode). When CPU go into deep power saving mode, it needs some
careful settings before getting into and after leaving. The enter and
exit functions do that by configuring appropriate mode for flow
controller.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
arch/arm/mach-tegra/flowctrl.c | 47 ++++++++++++++++++++++++++++++++++++++++
arch/arm/mach-tegra/flowctrl.h | 8 ++++++
2 files changed, 55 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-tegra/flowctrl.c b/arch/arm/mach-tegra/flowctrl.c
index f07488e..5967b08 100644
--- a/arch/arm/mach-tegra/flowctrl.c
+++ b/arch/arm/mach-tegra/flowctrl.c
@@ -21,6 +21,7 @@
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/io.h>
+#include <linux/cpumask.h>
#include <mach/iomap.h>
@@ -51,6 +52,14 @@ static void flowctrl_update(u8 offset, u32 value)
readl_relaxed(addr);
}
+u32 flowctrl_read_cpu_csr(unsigned int cpuid)
+{
+ u8 offset = flowctrl_offset_cpu_csr[cpuid];
+ void __iomem *addr = IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + offset;
+
+ return readl(addr);
+}
+
void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value)
{
return flowctrl_update(flowctrl_offset_cpu_csr[cpuid], value);
@@ -60,3 +69,41 @@ void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value)
{
return flowctrl_update(flowctrl_offset_halt_cpu[cpuid], value);
}
+
+void flowctrl_cpu_suspend_enter(unsigned int cpuid)
+{
+ unsigned int reg;
+ int i;
+
+ reg = flowctrl_read_cpu_csr(cpuid);
+ reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP; /* clear wfe bitmap */
+ reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP; /* clear wfi bitmap */
+ reg |= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr flag */
+ reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event flag */
+ reg |= TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 << cpuid; /* pwr gating on wfi */
+ reg |= FLOW_CTRL_CSR_ENABLE; /* pwr gating */
+ flowctrl_write_cpu_csr(cpuid, reg);
+
+ for (i = 0; i < num_possible_cpus(); i++) {
+ if (i == cpuid)
+ continue;
+ reg = flowctrl_read_cpu_csr(i);
+ reg |= FLOW_CTRL_CSR_EVENT_FLAG;
+ reg |= FLOW_CTRL_CSR_INTR_FLAG;
+ flowctrl_write_cpu_csr(i, reg);
+ }
+}
+
+void flowctrl_cpu_suspend_exit(unsigned int cpuid)
+{
+ unsigned int reg;
+
+ /* Disable powergating via flow controller for CPU0 */
+ reg = flowctrl_read_cpu_csr(cpuid);
+ reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP; /* clear wfe bitmap */
+ reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP; /* clear wfi bitmap */
+ reg &= ~FLOW_CTRL_CSR_ENABLE; /* clear enable */
+ reg |= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr */
+ reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event */
+ flowctrl_write_cpu_csr(cpuid, reg);
+}
diff --git a/arch/arm/mach-tegra/flowctrl.h b/arch/arm/mach-tegra/flowctrl.h
index 1942817..0798dec 100644
--- a/arch/arm/mach-tegra/flowctrl.h
+++ b/arch/arm/mach-tegra/flowctrl.h
@@ -34,9 +34,17 @@
#define FLOW_CTRL_HALT_CPU1_EVENTS 0x14
#define FLOW_CTRL_CPU1_CSR 0x18
+#define TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 (1 << 8)
+#define TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP (0xF << 4)
+#define TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP (0xF << 8)
+
#ifndef __ASSEMBLY__
+u32 flowctrl_read_cpu_csr(unsigned int cpuid);
void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value);
void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value);
+
+void flowctrl_cpu_suspend_enter(unsigned int cpuid);
+void flowctrl_cpu_suspend_exit(unsigned int cpuid);
#endif
#endif
--
1.7.0.4
^ permalink raw reply related
* [PATCH 5/7] ARM: tegra30: clocks: add CPU low-power function into tegra_cpu_car_ops
From: Joseph Lo @ 2012-10-08 10:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1349691981-31038-1-git-send-email-josephl@nvidia.com>
Add suspend, resume and rail_off_ready API into tegra_cpu_car_ops. These
functions were used for CPU low-power state maintenance (e.g., LP2). One
thing needs to notice the rail_off_ready API only availalbe for cpu_g
cluster not cpu_lp cluster.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
arch/arm/mach-tegra/tegra30_clocks.c | 107 ++++++++++++++++++++++++++++++++++
arch/arm/mach-tegra/tegra_cpu_car.h | 37 ++++++++++++
2 files changed, 144 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-tegra/tegra30_clocks.c b/arch/arm/mach-tegra/tegra30_clocks.c
index 5cd502c..23f513b 100644
--- a/arch/arm/mach-tegra/tegra30_clocks.c
+++ b/arch/arm/mach-tegra/tegra30_clocks.c
@@ -32,6 +32,7 @@
#include <asm/clkdev.h>
#include <mach/iomap.h>
+#include <mach/powergate.h>
#include "clock.h"
#include "fuse.h"
@@ -310,6 +311,31 @@
#define CPU_CLOCK(cpu) (0x1 << (8 + cpu))
#define CPU_RESET(cpu) (0x1111ul << (cpu))
+#define CLK_RESET_CCLK_BURST 0x20
+#define CLK_RESET_CCLK_DIVIDER 0x24
+#define CLK_RESET_PLLX_BASE 0xe0
+#define CLK_RESET_PLLX_MISC 0xe4
+
+#define CLK_RESET_SOURCE_CSITE 0x1d4
+
+#define CLK_RESET_CCLK_BURST_POLICY_SHIFT 28
+#define CLK_RESET_CCLK_RUN_POLICY_SHIFT 4
+#define CLK_RESET_CCLK_IDLE_POLICY_SHIFT 0
+#define CLK_RESET_CCLK_IDLE_POLICY 1
+#define CLK_RESET_CCLK_RUN_POLICY 2
+#define CLK_RESET_CCLK_BURST_POLICY_PLLX 8
+
+#ifdef CONFIG_PM_SLEEP
+static struct cpu_clk_suspend_context {
+ u32 pllx_misc;
+ u32 pllx_base;
+
+ u32 cpu_burst;
+ u32 clk_csite_src;
+ u32 cclk_divider;
+} tegra30_cpu_clk_sctx;
+#endif
+
/**
* Structure defining the fields for USB UTMI clocks Parameters.
*/
@@ -2281,12 +2307,93 @@ static void tegra30_disable_cpu_clock(u32 cpu)
reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
}
+#ifdef CONFIG_PM_SLEEP
+static bool tegra30_cpu_rail_off_ready(void)
+{
+ unsigned int cpu_rst_status;
+ int cpu_pwr_status;
+
+ cpu_rst_status = readl(reg_clk_base +
+ TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
+ cpu_pwr_status = tegra_powergate_is_powered(TEGRA_POWERGATE_CPU1) ||
+ tegra_powergate_is_powered(TEGRA_POWERGATE_CPU2) ||
+ tegra_powergate_is_powered(TEGRA_POWERGATE_CPU3);
+
+ if (((cpu_rst_status & 0xE) != 0xE) || cpu_pwr_status)
+ return false;
+
+ return true;
+}
+
+static void tegra30_cpu_clock_suspend(void)
+{
+ /* switch coresite to clk_m, save off original source */
+ tegra30_cpu_clk_sctx.clk_csite_src =
+ readl(reg_clk_base + CLK_RESET_SOURCE_CSITE);
+ writel(3<<30, reg_clk_base + CLK_RESET_SOURCE_CSITE);
+
+ tegra30_cpu_clk_sctx.cpu_burst =
+ readl(reg_clk_base + CLK_RESET_CCLK_BURST);
+ tegra30_cpu_clk_sctx.pllx_base =
+ readl(reg_clk_base + CLK_RESET_PLLX_BASE);
+ tegra30_cpu_clk_sctx.pllx_misc =
+ readl(reg_clk_base + CLK_RESET_PLLX_MISC);
+ tegra30_cpu_clk_sctx.cclk_divider =
+ readl(reg_clk_base + CLK_RESET_CCLK_DIVIDER);
+}
+
+static void tegra30_cpu_clock_resume(void)
+{
+ unsigned int reg, policy;
+
+ /* Is CPU complex already running on PLLX? */
+ reg = readl(reg_clk_base + CLK_RESET_CCLK_BURST);
+ policy = (reg >> CLK_RESET_CCLK_BURST_POLICY_SHIFT) & 0xF;
+
+ if (policy == CLK_RESET_CCLK_IDLE_POLICY)
+ reg = (reg >> CLK_RESET_CCLK_IDLE_POLICY_SHIFT) & 0xF;
+ else if (policy == CLK_RESET_CCLK_RUN_POLICY)
+ reg = (reg >> CLK_RESET_CCLK_RUN_POLICY_SHIFT) & 0xF;
+ else
+ BUG();
+
+ if (reg != CLK_RESET_CCLK_BURST_POLICY_PLLX) {
+ /* restore PLLX settings if CPU is on different PLL */
+ writel(tegra30_cpu_clk_sctx.pllx_misc,
+ reg_clk_base + CLK_RESET_PLLX_MISC);
+ writel(tegra30_cpu_clk_sctx.pllx_base,
+ reg_clk_base + CLK_RESET_PLLX_BASE);
+
+ /* wait for PLL stabilization if PLLX was enabled */
+ if (tegra30_cpu_clk_sctx.pllx_base & (1 << 30))
+ udelay(300);
+ }
+
+ /*
+ * Restore original burst policy setting for calls resulting from CPU
+ * LP2 in idle or system suspend.
+ */
+ writel(tegra30_cpu_clk_sctx.cclk_divider,
+ reg_clk_base + CLK_RESET_CCLK_DIVIDER);
+ writel(tegra30_cpu_clk_sctx.cpu_burst,
+ reg_clk_base + CLK_RESET_CCLK_BURST);
+
+ writel(tegra30_cpu_clk_sctx.clk_csite_src,
+ reg_clk_base + CLK_RESET_SOURCE_CSITE);
+}
+#endif
+
static struct tegra_cpu_car_ops tegra30_cpu_car_ops = {
.wait_for_reset = tegra30_wait_cpu_in_reset,
.put_in_reset = tegra30_put_cpu_in_reset,
.out_of_reset = tegra30_cpu_out_of_reset,
.enable_clock = tegra30_enable_cpu_clock,
.disable_clock = tegra30_disable_cpu_clock,
+#ifdef CONFIG_PM_SLEEP
+ .rail_off_ready = tegra30_cpu_rail_off_ready,
+ .suspend = tegra30_cpu_clock_suspend,
+ .resume = tegra30_cpu_clock_resume,
+#endif
};
void __init tegra30_cpu_car_ops_init(void)
diff --git a/arch/arm/mach-tegra/tegra_cpu_car.h b/arch/arm/mach-tegra/tegra_cpu_car.h
index 30d063a..9764d31 100644
--- a/arch/arm/mach-tegra/tegra_cpu_car.h
+++ b/arch/arm/mach-tegra/tegra_cpu_car.h
@@ -30,6 +30,12 @@
* CPU clock un-gate
* disable_clock:
* CPU clock gate
+ * rail_off_ready:
+ * CPU is ready for rail off
+ * suspend:
+ * save the clock settings when CPU go into low-power state
+ * resume:
+ * restore the clock settings when CPU exit low-power state
*/
struct tegra_cpu_car_ops {
void (*wait_for_reset)(u32 cpu);
@@ -37,6 +43,11 @@ struct tegra_cpu_car_ops {
void (*out_of_reset)(u32 cpu);
void (*enable_clock)(u32 cpu);
void (*disable_clock)(u32 cpu);
+#ifdef CONFIG_PM_SLEEP
+ bool (*rail_off_ready)(void);
+ void (*suspend)(void);
+ void (*resume)(void);
+#endif
};
extern struct tegra_cpu_car_ops *tegra_cpu_car_ops;
@@ -81,6 +92,32 @@ static inline void tegra_disable_cpu_clock(u32 cpu)
tegra_cpu_car_ops->disable_clock(cpu);
}
+#ifdef CONFIG_PM_SLEEP
+static inline bool tegra_cpu_rail_off_ready(void)
+{
+ if (WARN_ON(!tegra_cpu_car_ops->rail_off_ready))
+ return false;
+
+ return tegra_cpu_car_ops->rail_off_ready();
+}
+
+static inline void tegra_cpu_clock_suspend(void)
+{
+ if (WARN_ON(!tegra_cpu_car_ops->suspend))
+ return;
+
+ tegra_cpu_car_ops->suspend();
+}
+
+static inline void tegra_cpu_clock_resume(void)
+{
+ if (WARN_ON(!tegra_cpu_car_ops->resume))
+ return;
+
+ tegra_cpu_car_ops->resume();
+}
+#endif
+
void tegra20_cpu_car_ops_init(void);
void tegra30_cpu_car_ops_init(void);
--
1.7.0.4
^ permalink raw reply related
* [PATCH 4/7] ARM: tegra30: common: enable csite clock
From: Joseph Lo @ 2012-10-08 10:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1349691981-31038-1-git-send-email-josephl@nvidia.com>
Enable csite (debug and trace controller) clock at init to prevent it
be disabled. And this also the necessary clock for CPU be brought up or
resumed from a power-gate low power state (e.g., LP2).
Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
arch/arm/mach-tegra/common.c | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 0b0a5f5..4a2dd98 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -104,6 +104,7 @@ static __initdata struct tegra_clk_init_table tegra30_clk_init_table[] = {
{ "clk_m", NULL, 0, true },
{ "pll_p", "clk_m", 408000000, true },
{ "pll_p_out1", "pll_p", 9600000, true },
+ { "csite", NULL, 0, true },
{ NULL, NULL, 0, 0},
};
#endif
--
1.7.0.4
^ permalink raw reply related
* [PATCH 3/7] ARM: tegra30: cpuidle: add LP2 driver for secondary CPUs
From: Joseph Lo @ 2012-10-08 10:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1349691981-31038-1-git-send-email-josephl@nvidia.com>
This supports power-gated (LP2) idle on secondary CPUs for Tegra30.
The secondary CPUs can go into LP2 state independently. When CPU goes
into LP2 state, it saves it's state and puts itself to flow controlled
WFI state. After that, it will been power gated.
Based on the work by:
Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
arch/arm/mach-tegra/Makefile | 1 +
arch/arm/mach-tegra/cpuidle-tegra30.c | 79 +++++++++++++++++++++++++++++-
arch/arm/mach-tegra/pm.c | 88 +++++++++++++++++++++++++++++++++
arch/arm/mach-tegra/pm.h | 30 +++++++++++
arch/arm/mach-tegra/reset.h | 9 +++
arch/arm/mach-tegra/sleep-tegra30.S | 26 ++++++++++
arch/arm/mach-tegra/sleep.S | 66 ++++++++++++++++++++++++
arch/arm/mach-tegra/sleep.h | 2 +
8 files changed, 300 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/mach-tegra/pm.c
create mode 100644 arch/arm/mach-tegra/pm.h
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 9b80c1e..6f224f7 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -8,6 +8,7 @@ obj-y += pmc.o
obj-y += flowctrl.o
obj-y += powergate.o
obj-y += apbio.o
+obj-y += pm.o
obj-$(CONFIG_CPU_IDLE) += cpuidle.o
obj-$(CONFIG_CPU_IDLE) += sleep.o
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_clocks.o
diff --git a/arch/arm/mach-tegra/cpuidle-tegra30.c b/arch/arm/mach-tegra/cpuidle-tegra30.c
index 0f85df8..842fef4 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra30.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra30.c
@@ -19,21 +19,94 @@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/cpuidle.h>
+#include <linux/cpu_pm.h>
+#include <linux/clockchips.h>
#include <asm/cpuidle.h>
+#include <asm/proc-fns.h>
+#include <asm/suspend.h>
+
+#include "pm.h"
+#include "sleep.h"
+
+#ifdef CONFIG_PM_SLEEP
+static int tegra30_idle_lp2(struct cpuidle_device *dev,
+ struct cpuidle_driver *drv,
+ int index);
+#endif
static struct cpuidle_driver tegra_idle_driver = {
.name = "tegra_idle",
.owner = THIS_MODULE,
.en_core_tk_irqen = 1,
- .state_count = 1,
+ .state_count = 2,
.states = {
[0] = ARM_CPUIDLE_WFI_STATE_PWR(600),
+#ifdef CONFIG_PM_SLEEP
+ [1] = {
+ .enter = tegra30_idle_lp2,
+ .exit_latency = 2000,
+ .target_residency = 2200,
+ .power_usage = 0,
+ .flags = CPUIDLE_FLAG_TIME_VALID,
+ .name = "LP2",
+ .desc = "CPU power-gate",
+ },
+#endif
},
};
static DEFINE_PER_CPU(struct cpuidle_device, tegra_idle_device);
+#ifdef CONFIG_PM_SLEEP
+static bool tegra30_idle_enter_lp2_cpu_n(struct cpuidle_device *dev,
+ struct cpuidle_driver *drv,
+ int index)
+{
+#ifdef CONFIG_SMP
+ clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
+
+ smp_wmb();
+
+ save_cpu_arch_register();
+
+ cpu_suspend(0, tegra30_sleep_cpu_secondary_finish);
+
+ restore_cpu_arch_register();
+
+ clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
+#endif
+
+ return true;
+}
+
+static int __cpuinit tegra30_idle_lp2(struct cpuidle_device *dev,
+ struct cpuidle_driver *drv,
+ int index)
+{
+ bool entered_lp2 = false;
+
+ local_fiq_disable();
+
+ tegra_set_cpu_in_lp2(dev->cpu);
+ cpu_pm_enter();
+
+ if (dev->cpu == 0)
+ cpu_do_idle();
+ else
+ entered_lp2 = tegra30_idle_enter_lp2_cpu_n(dev, drv, index);
+
+ cpu_pm_exit();
+ tegra_clear_cpu_in_lp2(dev->cpu);
+
+ local_fiq_enable();
+
+ smp_rmb();
+
+ return (entered_lp2) ? index : 0;
+}
+#endif
+
int __init tegra30_cpuidle_init(void)
{
int ret;
@@ -41,6 +114,10 @@ int __init tegra30_cpuidle_init(void)
struct cpuidle_device *dev;
struct cpuidle_driver *drv = &tegra_idle_driver;
+#ifndef CONFIG_PM_SLEEP
+ drv->state_count = 1; /* support clockgating only */
+#endif
+
ret = cpuidle_register_driver(&tegra_idle_driver);
if (ret) {
pr_err("CPUidle driver registration failed\n");
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
new file mode 100644
index 0000000..4655383
--- /dev/null
+++ b/arch/arm/mach-tegra/pm.c
@@ -0,0 +1,88 @@
+/*
+ * CPU complex suspend & resume functions for Tegra SoCs
+ *
+ * Copyright (c) 2009-2012, NVIDIA Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/cpumask.h>
+
+#include <mach/iomap.h>
+
+#include "reset.h"
+
+#ifdef CONFIG_PM_SLEEP
+static unsigned int g_diag_reg;
+static DEFINE_SPINLOCK(tegra_lp2_lock);
+static cpumask_t tegra_in_lp2;
+
+void save_cpu_arch_register(void)
+{
+ /*read diagnostic register*/
+ asm("mrc p15, 0, %0, c15, c0, 1" : "=r"(g_diag_reg) : : "cc");
+ return;
+}
+
+void restore_cpu_arch_register(void)
+{
+ /*write diagnostic register*/
+ asm("mcr p15, 0, %0, c15, c0, 1" : : "r"(g_diag_reg) : "cc");
+ return;
+}
+
+void __cpuinit tegra_clear_cpu_in_lp2(int cpu)
+{
+ spin_lock(&tegra_lp2_lock);
+ BUG_ON(!cpumask_test_cpu(cpu, &tegra_in_lp2));
+ cpumask_clear_cpu(cpu, &tegra_in_lp2);
+
+ /*
+ * Update the IRAM copy used by the reset handler. The IRAM copy
+ * can't use used directly by cpumask_clear_cpu() because it uses
+ * LDREX/STREX which requires the addressed location to be inner
+ * cacheable and sharable which IRAM isn't.
+ */
+ writel(tegra_in_lp2.bits[0], tegra_cpu_lp2_mask);
+ dsb();
+
+ spin_unlock(&tegra_lp2_lock);
+}
+
+bool __cpuinit tegra_set_cpu_in_lp2(int cpu)
+{
+ bool last_cpu = false;
+
+ spin_lock(&tegra_lp2_lock);
+ BUG_ON(cpumask_test_cpu(cpu, &tegra_in_lp2));
+ cpumask_set_cpu(cpu, &tegra_in_lp2);
+
+ /*
+ * Update the IRAM copy used by the reset handler. The IRAM copy
+ * can't use used directly by cpumask_set_cpu() because it uses
+ * LDREX/STREX which requires the addressed location to be inner
+ * cacheable and sharable which IRAM isn't.
+ */
+ writel(tegra_in_lp2.bits[0], tegra_cpu_lp2_mask);
+ dsb();
+
+ if ((cpu == 0) && cpumask_equal(&tegra_in_lp2, cpu_online_mask))
+ last_cpu = true;
+
+ spin_unlock(&tegra_lp2_lock);
+ return last_cpu;
+}
+#endif
diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h
new file mode 100644
index 0000000..21858d6
--- /dev/null
+++ b/arch/arm/mach-tegra/pm.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2010 Google, Inc.
+ * Copyright (c) 2010-2012 NVIDIA Corporation. All rights reserved.
+ *
+ * Author:
+ * Colin Cross <ccross@google.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _MACH_TEGRA_PM_H_
+#define _MACH_TEGRA_PM_H_
+
+void save_cpu_arch_register(void);
+void restore_cpu_arch_register(void);
+
+void tegra_clear_cpu_in_lp2(int cpu);
+bool tegra_set_cpu_in_lp2(int cpu);
+
+#endif /* _MACH_TEGRA_PM_H_ */
diff --git a/arch/arm/mach-tegra/reset.h b/arch/arm/mach-tegra/reset.h
index de88bf8..234cd6b 100644
--- a/arch/arm/mach-tegra/reset.h
+++ b/arch/arm/mach-tegra/reset.h
@@ -29,6 +29,8 @@
#ifndef __ASSEMBLY__
+#include <mach/irammap.h>
+
extern unsigned long __tegra_cpu_reset_handler_data[TEGRA_RESET_DATA_SIZE];
void __tegra_cpu_reset_handler_start(void);
@@ -36,6 +38,13 @@ void __tegra_cpu_reset_handler(void);
void __tegra_cpu_reset_handler_end(void);
void tegra_secondary_startup(void);
+#ifdef CONFIG_PM_SLEEP
+#define tegra_cpu_lp2_mask \
+ (IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \
+ ((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_LP2] - \
+ (u32)__tegra_cpu_reset_handler_start)))
+#endif
+
#define tegra_cpu_reset_handler_offset \
((u32)__tegra_cpu_reset_handler - \
(u32)__tegra_cpu_reset_handler_start)
diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
index 777d9ce..67b1cba 100644
--- a/arch/arm/mach-tegra/sleep-tegra30.S
+++ b/arch/arm/mach-tegra/sleep-tegra30.S
@@ -17,6 +17,8 @@
#include <linux/linkage.h>
#include <asm/assembler.h>
+#include <asm/asm-offsets.h>
+#include <asm/glue-cache.h>
#include <mach/iomap.h>
@@ -82,6 +84,7 @@ delay_1:
ldr r3, [r1] @ read CSR
str r3, [r1] @ clear CSR
tst r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
+ moveq r3, #FLOW_CTRL_WAIT_FOR_INTERRUPT @ For LP2
movne r3, #FLOW_CTRL_WAITEVENT @ For hotplug
str r3, [r2]
ldr r0, [r2]
@@ -105,3 +108,26 @@ wfe_war:
ENDPROC(tegra30_cpu_shutdown)
#endif
+
+#ifdef CONFIG_PM_SLEEP
+/*
+ * tegra30_sleep_cpu_secondary_finish(unsigned long v2p)
+ *
+ * Enters LP2 on secondary CPU by exiting coherency and powergating the CPU.
+ */
+ENTRY(tegra30_sleep_cpu_secondary_finish)
+ mov r7, lr
+
+ /* Flush and disable the L1 data cache */
+ bl tegra_flush_l1_cache
+
+ /* Turn off SMP coherency */
+ exit_smp r4, r5
+
+ /* Powergate this CPU. */
+ mov r0, #0 @ power mode flags (!hotplug)
+ bl tegra30_cpu_shutdown
+ mov r0, #1 @ never return here
+ mov pc, r7
+ENDPROC(tegra30_sleep_cpu_secondary_finish)
+#endif
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S
index ea81554..7748fdb 100644
--- a/arch/arm/mach-tegra/sleep.S
+++ b/arch/arm/mach-tegra/sleep.S
@@ -25,9 +25,75 @@
#include <linux/linkage.h>
#include <asm/assembler.h>
+#include <asm/cp15.h>
#include <mach/iomap.h>
#include "flowctrl.h"
#include "sleep.h"
+#ifdef CONFIG_PM_SLEEP
+/*
+ * tegra_flush_l1_cache
+ *
+ * clean & invalidate the L1 cache
+ *
+ * The flush_cache_all flushes all caches within level of coherence, this
+ * may not be desired if all we need is to flush L1 only. Therefore this
+ * function is implemented to flush the L1 cache only.
+ *
+ * Disable is needed before flush to prevent allocation during flush.
+ * When cache is disabled, we cannot push to stack.
+ *
+ * Corrupted registers: r0-r7, r9-r11
+ */
+
+ENTRY(tegra_flush_l1_cache)
+ stmfd sp!, {r4-r5, r7, r9-r11, lr}
+ dmb @ ensure ordering
+
+ /* Disable the data cache */
+ mrc p15, 0, r2, c1, c0, 0
+ bic r2, r2, #CR_C
+ dsb
+ mcr p15, 0, r2, c1, c0, 0
+
+ /* Flush data cache */
+ mov r10, #0
+#ifdef CONFIG_PREEMPT
+ save_and_disable_irqs_notrace r9 @ make cssr&csidr read atomic
+#endif
+ mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
+ isb @ isb to sych the new cssr&csidr
+ mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
+#ifdef CONFIG_PREEMPT
+ restore_irqs_notrace r9
+#endif
+ and r2, r1, #7 @ extract the length of the cache lines
+ add r2, r2, #4 @ add 4 (line length offset)
+ ldr r4, =0x3ff
+ ands r4, r4, r1, lsr #3 @ find maximum number on the way size
+ clz r5, r4 @ find bit position of way size increment
+ ldr r7, =0x7fff
+ ands r7, r7, r1, lsr #13 @ extract max number of the index size
+loop2:
+ mov r9, r4 @ create working copy of max way size
+loop3:
+ orr r11, r10, r9, lsl r5 @ factor way and cache number into r11
+ orr r11, r11, r7, lsl r2 @ factor index number into r11
+ mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
+ subs r9, r9, #1 @ decrement the way
+ bge loop3
+ subs r7, r7, #1 @ decrement the index
+ bge loop2
+finished:
+ mov r10, #0 @ swith back to cache level 0
+ mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
+ dsb
+ isb
+
+ ldmfd sp!, {r4-r5, r7, r9-r11, lr}
+ mov pc, lr
+ENDPROC(tegra_flush_l1_cache)
+
+#endif
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
index c9dec37..220fbd1 100644
--- a/arch/arm/mach-tegra/sleep.h
+++ b/arch/arm/mach-tegra/sleep.h
@@ -82,5 +82,7 @@ static inline void tegra20_hotplug_init(void) {}
static inline void tegra30_hotplug_init(void) {}
#endif
+int tegra30_sleep_cpu_secondary_finish(unsigned long);
+
#endif
#endif
--
1.7.0.4
^ permalink raw reply related
* [PATCH 2/7] ARM: tegra: cpuidle: add LP2 resume function
From: Joseph Lo @ 2012-10-08 10:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1349691981-31038-1-git-send-email-josephl@nvidia.com>
LP2 is one of the Tegra low power states that supports power gating both
CPU cores and GICs. Adding a resume function for taking care the CPUs that
resume from LP2. This function was been hooked to reset handler. We take
care everything here before go into kernel.
Based on the work by:
Scott Williams <scwilliams@nvidia.com>
Colin Cross <ccross@android.com>
Gary King <gking@nvidia.com>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
arch/arm/mach-tegra/headsmp.S | 58 +++++++++++++++++++++++++++++++++++++++++
arch/arm/mach-tegra/reset.c | 6 ++++
arch/arm/mach-tegra/sleep.h | 1 +
3 files changed, 65 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
index 6addc78..abf86b3 100644
--- a/arch/arm/mach-tegra/headsmp.S
+++ b/arch/arm/mach-tegra/headsmp.S
@@ -69,6 +69,53 @@ ENTRY(tegra_secondary_startup)
b secondary_startup
ENDPROC(tegra_secondary_startup)
+#ifdef CONFIG_PM_SLEEP
+/*
+ * tegra_resume
+ *
+ * CPU boot vector when restarting the a CPU following
+ * an LP2 transition. Also branched to by LP0 and LP1 resume after
+ * re-enabling sdram.
+ */
+ENTRY(tegra_resume)
+ bl v7_invalidate_l1
+ /* Enable coresight */
+ mov32 r0, 0xC5ACCE55
+ mcr p14, 0, r0, c7, c12, 6
+
+ cpu_id r0
+ cmp r0, #0 @ CPU0?
+ bne cpu_resume @ no
+
+ /* Are we on Tegra20? */
+ mov32 r6, TEGRA_APB_MISC_BASE
+ ldr r0, [r6, #APB_MISC_GP_HIDREV]
+ and r0, r0, #0xff00
+ cmp r0, #(0x20 << 8)
+ beq 1f
+#ifdef CONFIG_ARCH_TEGRA_3x_SOC
+ /* Clear the flow controller flags for this CPU. */
+ mov32 r2, TEGRA_FLOW_CTRL_BASE + FLOW_CTRL_CPU0_CSR @ CPU0 CSR
+ ldr r1, [r2]
+ /* Clear event & intr flag */
+ orr r1, r1, \
+ #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
+ movw r0, #0x0FFD @ enable, cluster_switch, immed, & bitmaps
+ bic r1, r1, r0
+ str r1, [r2]
+#endif
+1:
+
+ /* enable SCU */
+ mov32 r0, TEGRA_ARM_PERIF_BASE
+ ldr r1, [r0]
+ orr r1, r1, #1
+ str r1, [r0]
+
+ b cpu_resume
+ENDPROC(tegra_resume)
+#endif
+
.align L1_CACHE_SHIFT
ENTRY(__tegra_cpu_reset_handler_start)
@@ -122,6 +169,17 @@ ENTRY(__tegra_cpu_reset_handler)
1:
#endif
+ /* Waking up from LP2? */
+ ldr r9, [r12, #RESET_DATA(MASK_LP2)]
+ tst r9, r11 @ if in_lp2
+ beq __is_not_lp2
+ ldr lr, [r12, #RESET_DATA(STARTUP_LP2)]
+ cmp lr, #0
+ bleq __die @ no LP2 startup handler
+ bx lr
+
+__is_not_lp2:
+
#ifdef CONFIG_SMP
/*
* Can only be secondary boot (initial or hotplug) but CPU 0
diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c
index 5beb7eb..c48548f 100644
--- a/arch/arm/mach-tegra/reset.c
+++ b/arch/arm/mach-tegra/reset.c
@@ -26,6 +26,7 @@
#include <mach/irammap.h>
#include "reset.h"
+#include "sleep.h"
#include "fuse.h"
#define TEGRA_IRAM_RESET_BASE (TEGRA_IRAM_BASE + \
@@ -80,5 +81,10 @@ void __init tegra_cpu_reset_handler_init(void)
virt_to_phys((void *)tegra_secondary_startup);
#endif
+#ifdef CONFIG_PM_SLEEP
+ __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP2] =
+ virt_to_phys((void *)tegra_resume);
+#endif
+
tegra_cpu_reset_handler_enable();
}
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
index e25a7cd..c9dec37 100644
--- a/arch/arm/mach-tegra/sleep.h
+++ b/arch/arm/mach-tegra/sleep.h
@@ -72,6 +72,7 @@
dsb
.endm
#else
+void tegra_resume(void);
#ifdef CONFIG_HOTPLUG_CPU
void tegra20_hotplug_init(void);
--
1.7.0.4
^ permalink raw reply related
* [PATCH 1/7] ARM: tegra: cpuidle: separate cpuidle driver for different chips
From: Joseph Lo @ 2012-10-08 10:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1349691981-31038-1-git-send-email-josephl@nvidia.com>
The different Tegra chips may have different CPU idle states and data.
Individual CPU idle driver make it more easy to maintain.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
arch/arm/mach-tegra/Makefile | 6 +++
.../mach-tegra/{cpuidle.c => cpuidle-tegra20.c} | 23 ++++-----
.../mach-tegra/{cpuidle.c => cpuidle-tegra30.c} | 26 ++++-------
arch/arm/mach-tegra/cpuidle.c | 47 +++++--------------
arch/arm/mach-tegra/cpuidle.h | 32 +++++++++++++
5 files changed, 71 insertions(+), 63 deletions(-)
copy arch/arm/mach-tegra/{cpuidle.c => cpuidle-tegra20.c} (72%)
copy arch/arm/mach-tegra/{cpuidle.c => cpuidle-tegra30.c} (65%)
create mode 100644 arch/arm/mach-tegra/cpuidle.h
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index e6929c6..9b80c1e 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -14,9 +14,15 @@ obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_clocks.o
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_clocks_data.o
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += sleep-tegra20.o
+ifeq ($(CONFIG_CPU_IDLE),y)
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += cpuidle-tegra20.o
+endif
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks.o
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks_data.o
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += sleep-tegra30.o
+ifeq ($(CONFIG_CPU_IDLE),y)
+obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += cpuidle-tegra30.o
+endif
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
obj-$(CONFIG_SMP) += reset.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
diff --git a/arch/arm/mach-tegra/cpuidle.c b/arch/arm/mach-tegra/cpuidle-tegra20.c
similarity index 72%
copy from arch/arm/mach-tegra/cpuidle.c
copy to arch/arm/mach-tegra/cpuidle-tegra20.c
index 4e0b07c..e2fc26a 100644
--- a/arch/arm/mach-tegra/cpuidle.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra20.c
@@ -1,24 +1,22 @@
/*
- * arch/arm/mach-tegra/cpuidle.c
+ * CPU idle driver for Tegra20 CPUs
*
- * CPU idle driver for Tegra CPUs
- *
- * Copyright (c) 2010-2012, NVIDIA Corporation.
+ * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
* Copyright (c) 2011 Google, Inc.
* Author: Colin Cross <ccross@android.com>
* Gary King <gking@nvidia.com>
*
- * Rework for 3.3 by Peter De Schrijver <pdeschrijver@nvidia.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <linux/kernel.h>
@@ -27,7 +25,7 @@
#include <asm/cpuidle.h>
-struct cpuidle_driver tegra_idle_driver = {
+static struct cpuidle_driver tegra_idle_driver = {
.name = "tegra_idle",
.owner = THIS_MODULE,
.en_core_tk_irqen = 1,
@@ -39,7 +37,7 @@ struct cpuidle_driver tegra_idle_driver = {
static DEFINE_PER_CPU(struct cpuidle_device, tegra_idle_device);
-static int __init tegra_cpuidle_init(void)
+int __init tegra20_cpuidle_init(void)
{
int ret;
unsigned int cpu;
@@ -66,4 +64,3 @@ static int __init tegra_cpuidle_init(void)
}
return 0;
}
-device_initcall(tegra_cpuidle_init);
diff --git a/arch/arm/mach-tegra/cpuidle.c b/arch/arm/mach-tegra/cpuidle-tegra30.c
similarity index 65%
copy from arch/arm/mach-tegra/cpuidle.c
copy to arch/arm/mach-tegra/cpuidle-tegra30.c
index 4e0b07c..0f85df8 100644
--- a/arch/arm/mach-tegra/cpuidle.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra30.c
@@ -1,24 +1,19 @@
/*
- * arch/arm/mach-tegra/cpuidle.c
+ * CPU idle driver for Tegra30 CPUs
*
- * CPU idle driver for Tegra CPUs
+ * Copyright (c) 2012, NVIDIA Corporation. All rights reserved.
*
- * Copyright (c) 2010-2012, NVIDIA Corporation.
- * Copyright (c) 2011 Google, Inc.
- * Author: Colin Cross <ccross@android.com>
- * Gary King <gking@nvidia.com>
- *
- * Rework for 3.3 by Peter De Schrijver <pdeschrijver@nvidia.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <linux/kernel.h>
@@ -27,7 +22,7 @@
#include <asm/cpuidle.h>
-struct cpuidle_driver tegra_idle_driver = {
+static struct cpuidle_driver tegra_idle_driver = {
.name = "tegra_idle",
.owner = THIS_MODULE,
.en_core_tk_irqen = 1,
@@ -39,7 +34,7 @@ struct cpuidle_driver tegra_idle_driver = {
static DEFINE_PER_CPU(struct cpuidle_device, tegra_idle_device);
-static int __init tegra_cpuidle_init(void)
+int __init tegra30_cpuidle_init(void)
{
int ret;
unsigned int cpu;
@@ -66,4 +61,3 @@ static int __init tegra_cpuidle_init(void)
}
return 0;
}
-device_initcall(tegra_cpuidle_init);
diff --git a/arch/arm/mach-tegra/cpuidle.c b/arch/arm/mach-tegra/cpuidle.c
index 4e0b07c..d065139 100644
--- a/arch/arm/mach-tegra/cpuidle.c
+++ b/arch/arm/mach-tegra/cpuidle.c
@@ -23,47 +23,26 @@
#include <linux/kernel.h>
#include <linux/module.h>
-#include <linux/cpuidle.h>
-#include <asm/cpuidle.h>
-
-struct cpuidle_driver tegra_idle_driver = {
- .name = "tegra_idle",
- .owner = THIS_MODULE,
- .en_core_tk_irqen = 1,
- .state_count = 1,
- .states = {
- [0] = ARM_CPUIDLE_WFI_STATE_PWR(600),
- },
-};
-
-static DEFINE_PER_CPU(struct cpuidle_device, tegra_idle_device);
+#include "fuse.h"
+#include "cpuidle.h"
static int __init tegra_cpuidle_init(void)
{
int ret;
- unsigned int cpu;
- struct cpuidle_device *dev;
- struct cpuidle_driver *drv = &tegra_idle_driver;
- ret = cpuidle_register_driver(&tegra_idle_driver);
- if (ret) {
- pr_err("CPUidle driver registration failed\n");
- return ret;
+ switch (tegra_chip_id) {
+ case TEGRA20:
+ ret = tegra20_cpuidle_init();
+ break;
+ case TEGRA30:
+ ret = tegra30_cpuidle_init();
+ break;
+ default:
+ ret = -ENODEV;
+ break;
}
- for_each_possible_cpu(cpu) {
- dev = &per_cpu(tegra_idle_device, cpu);
- dev->cpu = cpu;
-
- dev->state_count = drv->state_count;
- ret = cpuidle_register_device(dev);
- if (ret) {
- pr_err("CPU%u: CPUidle device registration failed\n",
- cpu);
- return ret;
- }
- }
- return 0;
+ return ret;
}
device_initcall(tegra_cpuidle_init);
diff --git a/arch/arm/mach-tegra/cpuidle.h b/arch/arm/mach-tegra/cpuidle.h
new file mode 100644
index 0000000..496204d
--- /dev/null
+++ b/arch/arm/mach-tegra/cpuidle.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2012, NVIDIA Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __MACH_TEGRA_CPUIDLE_H
+#define __MACH_TEGRA_CPUIDLE_H
+
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+int tegra20_cpuidle_init(void);
+#else
+static inline int tegra20_cpuidle_init(void) { return -ENODEV; }
+#endif
+
+#ifdef CONFIG_ARCH_TEGRA_3x_SOC
+int tegra30_cpuidle_init(void);
+#else
+static inline int tegra30_cpuidle_init(void) { return -ENODEV; }
+#endif
+
+#endif
--
1.7.0.4
^ permalink raw reply related
* [PATCH 0/7] ARM: tegra30: cpuidle: add LP2 support
From: Joseph Lo @ 2012-10-08 10:26 UTC (permalink / raw)
To: linux-arm-kernel
The CPU idle LP2 is a power gating idle mode for Tegra30. It supports the
secondary CPUs (i.e., CPU1-CPU3) to go into LP2 dynamically. When any of
the secondary CPUs go into LP2, it can be power gated alone. There is a
limitation on CPU0. The CPU0 can go into LP2 only when all secondary CPUs
are already in LP2. After CPU0 is in LP2, the CPU rail can be turned off.
Verified on Seaboard(Tegra20) and Cardhu(Tegra30).
This patch set should depend on these two patches:
d8be3dc ARM: tegra: rename the file of "sleep-tXX" to "sleep-tegraXX"
7dc7d51 ARM: tegra: cpuidle: replace LP3 with ARM_CPUIDLE_WFI_STATE
Joseph Lo (7):
ARM: tegra: cpuidle: separate cpuidle driver for different chips
ARM: tegra: cpuidle: add LP2 resume function
ARM: tegra30: cpuidle: add LP2 driver for secondary CPUs
ARM: tegra30: common: enable csite clock
ARM: tegra30: clocks: add CPU low-power function into
tegra_cpu_car_ops
ARM: tegra30: flowctrl: add cpu_suspend_exter/exit function
ARM: tegra30: cpuidle: add LP2 driver for CPU0
arch/arm/mach-tegra/Makefile | 7 +
arch/arm/mach-tegra/common.c | 1 +
.../mach-tegra/{cpuidle.c => cpuidle-tegra20.c} | 23 +-
arch/arm/mach-tegra/cpuidle-tegra30.c | 171 ++++++++++++++
arch/arm/mach-tegra/cpuidle.c | 47 +---
arch/arm/mach-tegra/cpuidle.h | 32 +++
arch/arm/mach-tegra/flowctrl.c | 47 ++++
arch/arm/mach-tegra/flowctrl.h | 8 +
arch/arm/mach-tegra/headsmp.S | 58 +++++
arch/arm/mach-tegra/pm.c | 240 ++++++++++++++++++++
arch/arm/mach-tegra/pm.h | 33 +++
arch/arm/mach-tegra/reset.c | 6 +
arch/arm/mach-tegra/reset.h | 9 +
arch/arm/mach-tegra/sleep-tegra30.S | 70 ++++++
arch/arm/mach-tegra/sleep.S | 110 +++++++++
arch/arm/mach-tegra/sleep.h | 5 +
arch/arm/mach-tegra/tegra30_clocks.c | 107 +++++++++
arch/arm/mach-tegra/tegra_cpu_car.h | 37 +++
18 files changed, 964 insertions(+), 47 deletions(-)
copy arch/arm/mach-tegra/{cpuidle.c => cpuidle-tegra20.c} (72%)
create mode 100644 arch/arm/mach-tegra/cpuidle-tegra30.c
create mode 100644 arch/arm/mach-tegra/cpuidle.h
create mode 100644 arch/arm/mach-tegra/pm.c
create mode 100644 arch/arm/mach-tegra/pm.h
^ permalink raw reply
* [PATCH] ARM: tegra: cpuidle: replace LP3 with ARM_CPUIDLE_WFI_STATE
From: Joseph Lo @ 2012-10-08 10:24 UTC (permalink / raw)
To: linux-arm-kernel
The Tegra CPU idle LP3 state is doing ARM WFI only. So it's same with
the common ARM_CPUIDLE_WFI_STATE. Using it to replace LP3 now.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
arch/arm/mach-tegra/cpuidle.c | 44 ++--------------------------------------
1 files changed, 3 insertions(+), 41 deletions(-)
diff --git a/arch/arm/mach-tegra/cpuidle.c b/arch/arm/mach-tegra/cpuidle.c
index 566e2f8..4e0b07c 100644
--- a/arch/arm/mach-tegra/cpuidle.c
+++ b/arch/arm/mach-tegra/cpuidle.c
@@ -23,60 +23,22 @@
#include <linux/kernel.h>
#include <linux/module.h>
-#include <linux/cpu.h>
#include <linux/cpuidle.h>
-#include <linux/hrtimer.h>
-#include <asm/proc-fns.h>
-
-#include <mach/iomap.h>
-
-static int tegra_idle_enter_lp3(struct cpuidle_device *dev,
- struct cpuidle_driver *drv, int index);
+#include <asm/cpuidle.h>
struct cpuidle_driver tegra_idle_driver = {
.name = "tegra_idle",
.owner = THIS_MODULE,
+ .en_core_tk_irqen = 1,
.state_count = 1,
.states = {
- [0] = {
- .enter = tegra_idle_enter_lp3,
- .exit_latency = 10,
- .target_residency = 10,
- .power_usage = 600,
- .flags = CPUIDLE_FLAG_TIME_VALID,
- .name = "LP3",
- .desc = "CPU flow-controlled",
- },
+ [0] = ARM_CPUIDLE_WFI_STATE_PWR(600),
},
};
static DEFINE_PER_CPU(struct cpuidle_device, tegra_idle_device);
-static int tegra_idle_enter_lp3(struct cpuidle_device *dev,
- struct cpuidle_driver *drv, int index)
-{
- ktime_t enter, exit;
- s64 us;
-
- local_irq_disable();
- local_fiq_disable();
-
- enter = ktime_get();
-
- cpu_do_idle();
-
- exit = ktime_sub(ktime_get(), enter);
- us = ktime_to_us(exit);
-
- local_fiq_enable();
- local_irq_enable();
-
- dev->last_residency = us;
-
- return index;
-}
-
static int __init tegra_cpuidle_init(void)
{
int ret;
--
1.7.0.4
^ permalink raw reply related
* [PATCH] [ARM] Use AT() in the linker script to create correct program headers
From: Dave Martin @ 2012-10-08 10:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121005084500.GI4625@n2100.arm.linux.org.uk>
On Fri, Oct 05, 2012 at 09:45:00AM +0100, Russell King - ARM Linux wrote:
> On Mon, Oct 01, 2012 at 10:06:39AM -0600, Jason Gunthorpe wrote:
> > On Mon, Oct 01, 2012 at 04:39:53PM +0100, Dave Martin wrote:
> > > > Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align
> > > > LOAD 0x008000 0xc0008000 0x00008000 0x372244 0x3a4310 RWE 0x8000
> > >
> > > Not related directly to your patch, but I wonder why we don't we see
> > > separate r-x and rw- segments?
> >
> > I think this is because the sections are not aligned when the
> > protections change, and the sections are not sorted by protection
> > type.
>
> They aren't sorted by protection type, they're ordered according to what's
> required for the kernel - which is to have the init sections together as
> one complete block so that it can be freed, and to place all of the kernel
> text as close to the beginning of the image as possible.
Ah, right.
Partly this came from some side speculation about whether we could do
things like privileged read-only permissions on newer CPUs, for preventing
unintended or undesired writes to the kernel's code or read-only data.
There would be various things to solve in order to make that work, so I
guess there's no great urgency for it right now.
Cheers
---Dave
^ permalink raw reply
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