* [PATCH V2 2/3] dmaengine: dw_dmac: Enhance device tree support
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-10-12 14:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <9688d98010716880c1bbd966ead312c446282204.1350051925.git.viresh.kumar@linaro.org>
On 20:01 Fri 12 Oct , Viresh Kumar wrote:
> dw_dmac driver already supports device tree but it used to have its platform
> data passed the non-DT way.
>
> This patch does following changes:
> - pass platform data via DT, non-DT way still takes precedence if both are used.
why keep it all platform are DT
Best Regards,
J.
^ permalink raw reply
* [PATCH V2 3/3] ARM: SPEAr13xx: Pass DW DMAC platform data from DT
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-10-12 14:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <2039bc164224b0068bc078b6cd8df6218e754fce.1350051925.git.viresh.kumar@linaro.org>
>
> /* others */
> -#define DMAC0_BASE UL(0xEA800000)
> -#define DMAC1_BASE UL(0xEB000000)
> #define MCIF_CF_BASE UL(0xB2800000)
>
> /* Devices present in SPEAr1310 */
> diff --git a/arch/arm/mach-spear13xx/spear1310.c b/arch/arm/mach-spear13xx/spear1310.c
> index 9fbbfc5..0e60195 100644
> --- a/arch/arm/mach-spear13xx/spear1310.c
> +++ b/arch/arm/mach-spear13xx/spear1310.c
> @@ -36,9 +36,7 @@ static struct pl022_ssp_controller ssp1_plat_data = {
>
> /* Add SPEAr1310 auxdata to pass platform data */
> static struct of_dev_auxdata spear1310_auxdata_lookup[] __initdata = {
> - OF_DEV_AUXDATA("arasan,cf-spear1340", MCIF_CF_BASE, NULL, &cf_dma_priv),
> - OF_DEV_AUXDATA("snps,dma-spear1340", DMAC0_BASE, NULL, &dmac_plat_data),
> - OF_DEV_AUXDATA("snps,dma-spear1340", DMAC1_BASE, NULL, &dmac_plat_data),
> + OF_DEV_AUXDATA("arasan,cf-spear1340", MCIF_CF_BASE, NULL, "cf"),
?/
> OF_DEV_AUXDATA("arm,pl022", SSP_BASE, NULL, &pl022_plat_data),
>
> OF_DEV_AUXDATA("arm,pl022", SPEAR1310_SSP1_BASE, NULL, &ssp1_plat_data),
> diff --git a/arch/arm/mach-spear13xx/spear1340.c b/arch/arm/mach-spear13xx/spear1340.c
> index 081014f..7301f14 100644
> --- a/arch/arm/mach-spear13xx/spear1340.c
> +++ b/arch/arm/mach-spear13xx/spear1340.c
> @@ -20,7 +20,6 @@
> #include <linux/of_platform.h>
> #include <asm/hardware/gic.h>
> #include <asm/mach/arch.h>
> -#include <mach/dma.h>
> #include <mach/generic.h>
> #include <mach/spear.h>
>
> @@ -78,26 +77,10 @@
> (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
> SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
>
Best Regards,
J.
^ permalink raw reply
* [PATCH 1/2] ARM: config: sort select statements alphanumerically
From: Russell King - ARM Linux @ 2012-10-12 14:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121012144119.GM28061@n2100.arm.linux.org.uk>
On Fri, Oct 12, 2012 at 03:41:20PM +0100, Russell King - ARM Linux wrote:
> On Fri, Oct 12, 2012 at 04:04:28PM +0200, Linus Walleij wrote:
> > On Fri, Oct 12, 2012 at 3:26 PM, Russell King
> > <rmk+kernel@arm.linux.org.uk> wrote:
> >
> > > As suggested by Andrew Morton:
> > >
> > > This is a pet peeve of mine. Any time there's a long list of items
> > > (header file inclusions, kconfig entries, array initalisers, etc) and
> > > someone wants to add a new item, they *always* go and stick it at the
> > > end of the list.
> > >
> > > Guys, don't do this. Either put the new item into a randomly-chosen
> > > position or, probably better, alphanumerically sort the list.
> > >
> > > lets sort all our select statements alphanumerically. This commit was
> > > created by the following perl:
> >
> > I applied this and tried to configure the Nomadik defconfig,
> > and I get this, sadly:
>
> Yes, I've just fixed those. Unfortunately, the patch is soo large that
> it trips the mailing list size limit, and has to be manually approved,
> so I'm not sure I can call on the list maintainers again today to do the
> approval thing.
Instead, here's the updated script:
8<===
#!/usr/bin/perl
while (<>) {
while (/\\\s*$/) {
$_ .= <>;
}
undef %selects if /^\s*config\s+/;
if (/^\s+select\s+(\w+).*/) {
if (defined($selects{$1})) {
if ($selects{$1} eq $_) {
print STDERR "Warning: removing duplicated $1 entry\n";
} else {
print STDERR "Error: $1 differently selected\n".
"\tOld: $selects{$1}\n".
"\tNew: $_\n";
exit 1;
}
}
$selects{$1} = $_;
next;
}
if (%selects and (/^\s*$/ or /^\s+help/ or /^\s+---help---/ or
/^endif/ or /^endchoice/)) {
foreach $k (sort (keys %selects)) {
print "$selects{$k}";
}
undef %selects;
}
print;
}
if (%selects) {
foreach $k (sort (keys %selects)) {
print "$selects{$k}";
}
}
8<===
Run it like this (assuming its saved as sort.pl):
for f in $(find arch/arm -name 'Kconfig*'); do perl sort.pl $f > $f.new \
&& mv $f.new $f && git update-index $f; done
Omit the "git update-index" bit if you don't want to commit the result.
("git update-index" is safer than "git add" for this as "git add" will
add new files, "git update-index" won't without an additional option.
That's not a recommendation to use it though.)
^ permalink raw reply
* alignment faults in 3.6
From: Eric Dumazet @ 2012-10-12 14:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121012142254.GG5453@kvack.org>
On Fri, 2012-10-12 at 10:22 -0400, Benjamin LaHaise wrote:
> On Fri, Oct 12, 2012 at 02:08:12PM +0200, Eric Dumazet wrote:
> > So yes, we built network stack with the prereq that IP headers are
> > aligned, but unfortunately many developers use x86 which doesnt care, so
> > its possible some bugs are added.
>
> x86 does have an alignment check flag that can be set in the flags register.
> Somehow, I doubt anyone would be willing to walk through all the noise the
> faults would likely trigger.
If this can be mapped to an event that can be used by perf tool, that
might be useful ?
^ permalink raw reply
* [PATCH 2/3] dmaengine: dw_dmac: Enhance device tree support
From: Viresh Kumar @ 2012-10-12 14:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350052912.10584.167.camel@smile>
On 12 October 2012 20:11, Shevchenko, Andriy
<andriy.shevchenko@intel.com> wrote:
> On Fri, 2012-10-12 at 19:36 +0530, Viresh Kumar wrote:
> I meant is to use that constant instead of hard coding 4 everywhere.
> It's a maximum value, not the SoC specific.
Can be done.
>> + u32 val, arr[4];
> what about to use tmp name instead of val? It's really minor, but I
> think val name is little bit unrelated to a loop counter.
Its not minor at all, its major. Even when i was coding it, i thought
about renaming
it several times during this last patch. But couldn't find a better name.
I don't like tmp. Give me something better.
viresh
^ permalink raw reply
* [PATCH] spi/pl022: Activate resourses before deactivate them in suspend
From: Ulf Hansson @ 2012-10-12 14:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1349423012-18048-1-git-send-email-ulf.hansson@stericsson.com>
Hi Mark,
Just a kind remember on this. Do you see any problem merging this?
Kind regards
Ulf Hansson
On 5 October 2012 09:43, Ulf Hansson <ulf.hansson@stericsson.com> wrote:
> From: Ulf Hansson <ulf.hansson@linaro.org>
>
> To be able to deactivate resourses in suspend, the resourses must
> first be surely active. This is done with a pm_runtime_get_sync.
> Once the resourses are restored to active state again in resume,
> the runtime pm usage count can be decreased with a pm_runtime_put.
>
> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
> ---
> drivers/spi/spi-pl022.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/spi/spi-pl022.c b/drivers/spi/spi-pl022.c
> index 9194641..c3590e0 100644
> --- a/drivers/spi/spi-pl022.c
> +++ b/drivers/spi/spi-pl022.c
> @@ -2350,6 +2350,8 @@ static int pl022_suspend(struct device *dev)
> dev_warn(dev, "cannot suspend master\n");
> return ret;
> }
> +
> + pm_runtime_get_sync(dev);
> pl022_suspend_resources(pl022);
>
> dev_dbg(dev, "suspended\n");
> @@ -2362,6 +2364,7 @@ static int pl022_resume(struct device *dev)
> int ret;
>
> pl022_resume_resources(pl022);
> + pm_runtime_put(dev);
>
> /* Start the queue running */
> ret = spi_master_resume(pl022->master);
> --
> 1.7.10
>
^ permalink raw reply
* [PATCH 2/3] dmaengine: dw_dmac: Enhance device tree support
From: Shevchenko, Andriy @ 2012-10-12 14:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAKohpok=nv2XnFdPkD_yJgUsDqx2gEh=mG_Xhbe-BvT7swVsyg@mail.gmail.com>
On Fri, 2012-10-12 at 19:36 +0530, Viresh Kumar wrote:
> On 12 October 2012 18:58, Shevchenko, Andriy
> <andriy.shevchenko@intel.com> wrote:
> > On Fri, 2012-10-12 at 11:14 +0530, Viresh Kumar wrote:
>
> >> + if (!of_property_read_u32(np, "nr_masters", &val)) {
> >> + if (val > 4)
> > I thought once that we might introduce constant like #define
> > DW_MAX_AHB_MASTERS 4. It seems a bit useless because hw is designed for
> > that number anyway, but maybe you have another opinion.
>
> Not everyone have four masters in there SoC configurations. So its better
> to export correct values.
I meant is to use that constant instead of hard coding 4 everywhere.
It's a maximum value, not the SoC specific.
> >> + if (!of_property_read_u32_array(np, "data_width", arr,
> >> + pdata->nr_masters))
> >> + for (count = 0; count < pdata->nr_masters; count++)
> >> + pdata->data_width[count] = arr[count];
> > Ah, it would be nice to have of_property_read_u8_array and so on...
>
> :)
> Maybe yes. I don't want to do it with this patchset, as that will take more
> time to go through maintainers.
Agreed, the comment just for future. I don't know if there any other
users of *_u8/u16_array().
> > it will probably require to split this part in a separate function and
> > calculate count of slave_info children before pdata memory allocation.
>
> Liked the idea partially. Check my new implementation in fixup for all
> these comments:
Let me see.
> diff --git a/drivers/dma/dw_dmac.c b/drivers/dma/dw_dmac.c
> @@ -1516,7 +1516,7 @@ __devinit dw_dma_parse_dt(struct platform_device *pdev)
> struct device_node *sn, *cn, *np = pdev->dev.of_node;
> struct dw_dma_platform_data *pdata;
> struct dw_dma_slave *sd;
> - u32 count, val, arr[4];
> + u32 val, arr[4];
what about to use tmp name instead of val? It's really minor, but I
think val name is little bit unrelated to a loop counter.
> @@ -1533,63 +1533,57 @@ __devinit dw_dma_parse_dt(struct platform_device *pdev)
> - count = 0;
> + pdata->sd = sd;
> + pdata->sd_count = val;
> +
> for_each_child_of_node(sn, cn) {
> - of_property_read_string(cn, "bus_id", &sd[count].bus_id);
> - of_property_read_u32(cn, "cfg_hi", &sd[count].cfg_hi);
> - of_property_read_u32(cn, "cfg_lo", &sd[count].cfg_lo);
> + sd->dma_dev = &pdev->dev;
> + of_property_read_string(cn, "bus_id", &sd->bus_id);
> + of_property_read_u32(cn, "cfg_hi", &sd->cfg_hi);
> + of_property_read_u32(cn, "cfg_lo", &sd->cfg_lo);
> if (!of_property_read_u32(cn, "src_master", &val))
> - sd[count].src_master = (u8)val;
> + sd->src_master = val;
>
> if (!of_property_read_u32(cn, "dst_master", &val))
> - sd[count].dst_master = (u8)val;
> -
> - sd[count].dma_dev = &pdev->dev;
> - count++;
> + sd->dst_master = val;
> + sd++;
> }
This looks good.
--
Andy Shevchenko <andriy.shevchenko@intel.com>
Intel Finland Oy
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^ permalink raw reply
* [PATCH 1/2] ARM: config: sort select statements alphanumerically
From: Russell King - ARM Linux @ 2012-10-12 14:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACRpkdba1q52bEDcWsd47QwXA-DNhq6PENf2M-tvZ6znYu+5yw@mail.gmail.com>
On Fri, Oct 12, 2012 at 04:04:28PM +0200, Linus Walleij wrote:
> On Fri, Oct 12, 2012 at 3:26 PM, Russell King
> <rmk+kernel@arm.linux.org.uk> wrote:
>
> > As suggested by Andrew Morton:
> >
> > This is a pet peeve of mine. Any time there's a long list of items
> > (header file inclusions, kconfig entries, array initalisers, etc) and
> > someone wants to add a new item, they *always* go and stick it at the
> > end of the list.
> >
> > Guys, don't do this. Either put the new item into a randomly-chosen
> > position or, probably better, alphanumerically sort the list.
> >
> > lets sort all our select statements alphanumerically. This commit was
> > created by the following perl:
>
> I applied this and tried to configure the Nomadik defconfig,
> and I get this, sadly:
Yes, I've just fixed those. Unfortunately, the patch is soo large that
it trips the mailing list size limit, and has to be manually approved,
so I'm not sure I can call on the list maintainers again today to do the
approval thing.
^ permalink raw reply
* alignment faults in 3.6
From: David Laight @ 2012-10-12 14:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121012142254.GG5453@kvack.org>
> x86 does have an alignment check flag that can be set in the flags register.
> Somehow, I doubt anyone would be willing to walk through all the noise the
> faults would likely trigger.
Someone has tried to set that (in userspace) on NetBSD.
The fault reporting has been fixed, but really nothing
works since optimised parts of libc deliberately do
misaligned transfers.
David
^ permalink raw reply
* [PATCH 1/3] i2c: omap: Do not enable the irq always
From: Kevin Hilman @ 2012-10-12 14:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1349687116-14463-1-git-send-email-shubhrajyoti@ti.com>
+Kalle, Grygorii, Huzefa
Shubhrajyoti D <shubhrajyoti@ti.com> writes:
> Enable the irq in the transfer and disable it after the
> transfer is done.
>
> Signed-off-by: Shubhrajyoti D <shubhrajyoti@ti.com>
> ---
> drivers/i2c/busses/i2c-omap.c | 3 +++
> 1 files changed, 3 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
> index b6c6b95..ce41596 100644
> --- a/drivers/i2c/busses/i2c-omap.c
> +++ b/drivers/i2c/busses/i2c-omap.c
> @@ -625,6 +625,7 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
> if (IS_ERR_VALUE(r))
> goto out;
>
> + enable_irq(dev->irq);
> r = omap_i2c_wait_for_bb(dev);
> if (r < 0)
> goto out;
> @@ -654,6 +655,7 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
>
> omap_i2c_wait_for_bb(dev);
> out:
> + disable_irq(dev->irq);
When using runtime PM with auto-suspend timeouts, why would you disable
the IRQ before the runtime suspend handlers have run?
If you really want to do this, you probably should have these in the
runtime PM callbacks. But I'll wait until you add a more descriptive
changelog before I can really tell why this is being done. Based on the
discussion in the patch from Kalle, I'm assuming this is to prevent
interrups when I2C is being used by co-processors. If so, plese
describe in the changelog.
That being said, doesn't the runtime suspend callback already disable
IRQs at the device level instead of the INTC level?
Kevin
> pm_runtime_mark_last_busy(dev->dev);
> pm_runtime_put_autosuspend(dev->dev);
> return r;
> @@ -1179,6 +1181,7 @@ omap_i2c_probe(struct platform_device *pdev)
> goto err_unuse_clocks;
> }
>
> + disable_irq(dev->irq);
> adap = &dev->adapter;
> i2c_set_adapdata(adap, dev);
> adap->owner = THIS_MODULE;
^ permalink raw reply
* [PATCH V2 3/3] ARM: SPEAr13xx: Pass DW DMAC platform data from DT
From: Viresh Kumar @ 2012-10-12 14:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <142ef9170a2c69657d8a05ac127a9970d7b04965.1350051925.git.viresh.kumar@linaro.org>
This patch adds dw_dmac's platform data to DT node. It also creates slave info
node for SPEAr13xx, for the devices which were using dw_dmac.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
---
V1->V2:
------
- renamed filter function
arch/arm/boot/dts/spear1340.dtsi | 19 ++++++++++
arch/arm/boot/dts/spear13xx.dtsi | 38 ++++++++++++++++++++
arch/arm/mach-spear13xx/include/mach/spear.h | 2 --
arch/arm/mach-spear13xx/spear1310.c | 4 +--
arch/arm/mach-spear13xx/spear1340.c | 27 +++-----------
arch/arm/mach-spear13xx/spear13xx.c | 54 ++--------------------------
6 files changed, 65 insertions(+), 79 deletions(-)
diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi
index d71fe2a..8ea3f66 100644
--- a/arch/arm/boot/dts/spear1340.dtsi
+++ b/arch/arm/boot/dts/spear1340.dtsi
@@ -24,6 +24,25 @@
status = "disabled";
};
+ dma at ea800000 {
+ slave_info {
+ uart1_tx {
+ bus_id = "uart1_tx";
+ cfg_hi = <0x6000>; /* 0xC << 11 */
+ cfg_lo = <0>;
+ src_master = <0>;
+ dst_master = <1>;
+ };
+ uart1_tx {
+ bus_id = "uart1_tx";
+ cfg_hi = <0x680>; /* 0xD << 7 */
+ cfg_lo = <0>;
+ src_master = <1>;
+ dst_master = <0>;
+ };
+ };
+ };
+
spi1: spi at 5d400000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x5d400000 0x1000>;
diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
index f7b84ac..f06bb50 100644
--- a/arch/arm/boot/dts/spear13xx.dtsi
+++ b/arch/arm/boot/dts/spear13xx.dtsi
@@ -91,6 +91,37 @@
reg = <0xea800000 0x1000>;
interrupts = <0 19 0x4>;
status = "disabled";
+
+ nr_channels = <8>;
+ chan_allocation_order = <1>;
+ chan_priority = <1>;
+ block_size = <0xfff>;
+ nr_masters = <2>;
+ data_width = <3 3 0 0>;
+
+ slave_info {
+ ssp0_tx {
+ bus_id = "ssp0_tx";
+ cfg_hi = <0x2000>; /* 0x4 << 11 */
+ cfg_lo = <0>;
+ src_master = <0>;
+ dst_master = <0>;
+ };
+ ssp0_rx {
+ bus_id = "ssp0_rx";
+ cfg_hi = <0x280>; /* 0x5 << 7 */
+ cfg_lo = <0>;
+ src_master = <0>;
+ dst_master = <0>;
+ };
+ cf {
+ bus_id = "cf";
+ cfg_hi = <0>;
+ cfg_lo = <0>;
+ src_master = <0>;
+ dst_master = <0>;
+ };
+ };
};
dma at eb000000 {
@@ -98,6 +129,13 @@
reg = <0xeb000000 0x1000>;
interrupts = <0 59 0x4>;
status = "disabled";
+
+ nr_channels = <8>;
+ chan_allocation_order = <1>;
+ chan_priority = <1>;
+ block_size = <0xfff>;
+ nr_masters = <2>;
+ data_width = <3 3 0 0>;
};
fsmc: flash at b0000000 {
diff --git a/arch/arm/mach-spear13xx/include/mach/spear.h b/arch/arm/mach-spear13xx/include/mach/spear.h
index 07d90ac..71bf5b6 100644
--- a/arch/arm/mach-spear13xx/include/mach/spear.h
+++ b/arch/arm/mach-spear13xx/include/mach/spear.h
@@ -43,8 +43,6 @@
#define VA_L2CC_BASE IOMEM(UL(0xFB000000))
/* others */
-#define DMAC0_BASE UL(0xEA800000)
-#define DMAC1_BASE UL(0xEB000000)
#define MCIF_CF_BASE UL(0xB2800000)
/* Devices present in SPEAr1310 */
diff --git a/arch/arm/mach-spear13xx/spear1310.c b/arch/arm/mach-spear13xx/spear1310.c
index 9fbbfc5..0e60195 100644
--- a/arch/arm/mach-spear13xx/spear1310.c
+++ b/arch/arm/mach-spear13xx/spear1310.c
@@ -36,9 +36,7 @@ static struct pl022_ssp_controller ssp1_plat_data = {
/* Add SPEAr1310 auxdata to pass platform data */
static struct of_dev_auxdata spear1310_auxdata_lookup[] __initdata = {
- OF_DEV_AUXDATA("arasan,cf-spear1340", MCIF_CF_BASE, NULL, &cf_dma_priv),
- OF_DEV_AUXDATA("snps,dma-spear1340", DMAC0_BASE, NULL, &dmac_plat_data),
- OF_DEV_AUXDATA("snps,dma-spear1340", DMAC1_BASE, NULL, &dmac_plat_data),
+ OF_DEV_AUXDATA("arasan,cf-spear1340", MCIF_CF_BASE, NULL, "cf"),
OF_DEV_AUXDATA("arm,pl022", SSP_BASE, NULL, &pl022_plat_data),
OF_DEV_AUXDATA("arm,pl022", SPEAR1310_SSP1_BASE, NULL, &ssp1_plat_data),
diff --git a/arch/arm/mach-spear13xx/spear1340.c b/arch/arm/mach-spear13xx/spear1340.c
index 081014f..7301f14 100644
--- a/arch/arm/mach-spear13xx/spear1340.c
+++ b/arch/arm/mach-spear13xx/spear1340.c
@@ -20,7 +20,6 @@
#include <linux/of_platform.h>
#include <asm/hardware/gic.h>
#include <asm/mach/arch.h>
-#include <mach/dma.h>
#include <mach/generic.h>
#include <mach/spear.h>
@@ -78,26 +77,10 @@
(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
-static struct dw_dma_slave uart1_dma_param[] = {
- {
- /* Tx */
- .cfg_hi = DWC_CFGH_DST_PER(SPEAR1340_DMA_REQ_UART1_TX),
- .cfg_lo = 0,
- .src_master = DMA_MASTER_MEMORY,
- .dst_master = SPEAR1340_DMA_MASTER_UART1,
- }, {
- /* Rx */
- .cfg_hi = DWC_CFGH_SRC_PER(SPEAR1340_DMA_REQ_UART1_RX),
- .cfg_lo = 0,
- .src_master = SPEAR1340_DMA_MASTER_UART1,
- .dst_master = DMA_MASTER_MEMORY,
- }
-};
-
static struct amba_pl011_data uart1_data = {
- .dma_filter = dw_dma_filter,
- .dma_tx_param = &uart1_dma_param[0],
- .dma_rx_param = &uart1_dma_param[1],
+ .dma_filter = dw_dma_generic_filter,
+ .dma_tx_param = "uart1_tx",
+ .dma_rx_param = "uart1_rx",
};
/* SATA device registration */
@@ -158,9 +141,7 @@ static struct ahci_platform_data sata_pdata = {
/* Add SPEAr1340 auxdata to pass platform data */
static struct of_dev_auxdata spear1340_auxdata_lookup[] __initdata = {
- OF_DEV_AUXDATA("arasan,cf-spear1340", MCIF_CF_BASE, NULL, &cf_dma_priv),
- OF_DEV_AUXDATA("snps,dma-spear1340", DMAC0_BASE, NULL, &dmac_plat_data),
- OF_DEV_AUXDATA("snps,dma-spear1340", DMAC1_BASE, NULL, &dmac_plat_data),
+ OF_DEV_AUXDATA("arasan,cf-spear1340", MCIF_CF_BASE, NULL, "cf"),
OF_DEV_AUXDATA("arm,pl022", SSP_BASE, NULL, &pl022_plat_data),
OF_DEV_AUXDATA("snps,spear-ahci", SPEAR1340_SATA_BASE, NULL,
diff --git a/arch/arm/mach-spear13xx/spear13xx.c b/arch/arm/mach-spear13xx/spear13xx.c
index 5633d69..0e166fa 100644
--- a/arch/arm/mach-spear13xx/spear13xx.c
+++ b/arch/arm/mach-spear13xx/spear13xx.c
@@ -22,67 +22,19 @@
#include <asm/hardware/gic.h>
#include <asm/mach/map.h>
#include <asm/smp_twd.h>
-#include <mach/dma.h>
#include <mach/generic.h>
#include <mach/spear.h>
-/* common dw_dma filter routine to be used by peripherals */
-bool dw_dma_filter(struct dma_chan *chan, void *slave)
-{
- struct dw_dma_slave *dws = (struct dw_dma_slave *)slave;
-
- if (chan->device->dev == dws->dma_dev) {
- chan->private = slave;
- return true;
- } else {
- return false;
- }
-}
-
/* ssp device registration */
-static struct dw_dma_slave ssp_dma_param[] = {
- {
- /* Tx */
- .cfg_hi = DWC_CFGH_DST_PER(DMA_REQ_SSP0_TX),
- .cfg_lo = 0,
- .src_master = DMA_MASTER_MEMORY,
- .dst_master = DMA_MASTER_SSP0,
- }, {
- /* Rx */
- .cfg_hi = DWC_CFGH_SRC_PER(DMA_REQ_SSP0_RX),
- .cfg_lo = 0,
- .src_master = DMA_MASTER_SSP0,
- .dst_master = DMA_MASTER_MEMORY,
- }
-};
-
struct pl022_ssp_controller pl022_plat_data = {
.bus_id = 0,
.enable_dma = 1,
- .dma_filter = dw_dma_filter,
- .dma_rx_param = &ssp_dma_param[1],
- .dma_tx_param = &ssp_dma_param[0],
+ .dma_filter = dw_dma_generic_filter,
+ .dma_rx_param = "ssp0_rx",
+ .dma_tx_param = "ssp0_tx",
.num_chipselect = 3,
};
-/* CF device registration */
-struct dw_dma_slave cf_dma_priv = {
- .cfg_hi = 0,
- .cfg_lo = 0,
- .src_master = 0,
- .dst_master = 0,
-};
-
-/* dmac device registeration */
-struct dw_dma_platform_data dmac_plat_data = {
- .nr_channels = 8,
- .chan_allocation_order = CHAN_ALLOCATION_DESCENDING,
- .chan_priority = CHAN_PRIORITY_DESCENDING,
- .block_size = 4095U,
- .nr_masters = 2,
- .data_width = { 3, 3, 0, 0 },
-};
-
void __init spear13xx_l2x0_init(void)
{
/*
--
1.7.12.rc2.18.g61b472e
^ permalink raw reply related
* [PATCH V2 2/3] dmaengine: dw_dmac: Enhance device tree support
From: Viresh Kumar @ 2012-10-12 14:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <142ef9170a2c69657d8a05ac127a9970d7b04965.1350051925.git.viresh.kumar@linaro.org>
dw_dmac driver already supports device tree but it used to have its platform
data passed the non-DT way.
This patch does following changes:
- pass platform data via DT, non-DT way still takes precedence if both are used.
- create generic filter routine
- Earlier slave information was made available by slave specific filter routines
in chan->private field. Now, this information would be passed from within dmac
DT node. Slave drivers would now be required to pass bus_id (a string) as
parameter to this generic filter(), which would be compared against the slave
data passed from DT, by the generic filter routine.
- Update binding document
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
---
V1->V2:
------
- Optimized filter & DT parsing routine
- Removed unnecessary casts from changes
- renamed filter function
- Fixed function prototype and return value of DT parsing routine for !CONFIG_OF
case
- use of_get_child_count()
Documentation/devicetree/bindings/dma/snps-dma.txt | 44 +++++++
drivers/dma/dw_dmac.c | 137 +++++++++++++++++++++
drivers/dma/dw_dmac_regs.h | 4 +
include/linux/dw_dmac.h | 43 ++++---
4 files changed, 211 insertions(+), 17 deletions(-)
diff --git a/Documentation/devicetree/bindings/dma/snps-dma.txt b/Documentation/devicetree/bindings/dma/snps-dma.txt
index c0d85db..5bb3dfb 100644
--- a/Documentation/devicetree/bindings/dma/snps-dma.txt
+++ b/Documentation/devicetree/bindings/dma/snps-dma.txt
@@ -6,6 +6,26 @@ Required properties:
- interrupt-parent: Should be the phandle for the interrupt controller
that services interrupts for this device
- interrupt: Should contain the DMAC interrupt number
+- nr_channels: Number of channels supported by hardware
+- is_private: The device channels should be marked as private and not for by the
+ general purpose DMA channel allocator. False if not passed.
+- chan_allocation_order: order of allocation of channel, 0 (default): ascending,
+ 1: descending
+- chan_priority: priority of channels. 0 (default): increase from chan 0->n, 1:
+ increase from chan n->0
+- block_size: Maximum block size supported by the controller
+- nr_masters: Number of AHB masters supported by the controller
+- data_width: Maximum data width supported by hardware per AHB master
+ (0 - 8bits, 1 - 16bits, ..., 5 - 256bits)
+- slave_info:
+ - bus_id: name of this device channel, not just a device name since
+ devices may have more than one channel e.g. "foo_tx". For using the
+ dw_generic_filter(), slave drivers must pass exactly this string as
+ param to filter function.
+ - cfg_hi: Platform-specific initializer for the CFG_HI register
+ - cfg_lo: Platform-specific initializer for the CFG_LO register
+ - src_master: src master for transfers on allocated channel.
+ - dst_master: dest master for transfers on allocated channel.
Example:
@@ -14,4 +34,28 @@ Example:
reg = <0xfc000000 0x1000>;
interrupt-parent = <&vic1>;
interrupts = <12>;
+
+ nr_channels = <8>;
+ chan_allocation_order = <1>;
+ chan_priority = <1>;
+ block_size = <0xfff>;
+ nr_masters = <2>;
+ data_width = <3 3 0 0>;
+
+ slave_info {
+ uart0-tx {
+ bus_id = "uart0-tx";
+ cfg_hi = <0x4000>; /* 0x8 << 11 */
+ cfg_lo = <0>;
+ src_master = <0>;
+ dst_master = <1>;
+ };
+ spi0-tx {
+ bus_id = "spi0-tx";
+ cfg_hi = <0x2000>; /* 0x4 << 11 */
+ cfg_lo = <0>;
+ src_master = <0>;
+ dst_master = <0>;
+ };
+ };
};
diff --git a/drivers/dma/dw_dmac.c b/drivers/dma/dw_dmac.c
index c4b0eb3..d72c26f 100644
--- a/drivers/dma/dw_dmac.c
+++ b/drivers/dma/dw_dmac.c
@@ -1179,6 +1179,53 @@ static void dwc_free_chan_resources(struct dma_chan *chan)
dev_vdbg(chan2dev(chan), "%s: done\n", __func__);
}
+bool dw_dma_generic_filter(struct dma_chan *chan, void *param)
+{
+ struct dw_dma *dw = to_dw_dma(chan->device);
+ static struct dw_dma *last_dw;
+ static char *last_bus_id;
+ int i = -1;
+
+ /*
+ * dmaengine framework calls this routine for all channels of all dma
+ * controller, until true is returned. If 'param' bus_id is not
+ * registered with a dma controller (dw), then there is no need of
+ * running below function for all channels of dw.
+ *
+ * This block of code does this by saving the parameters of last
+ * failure. If dw and param are same, i.e. trying on same dw with
+ * different channel, return false.
+ */
+ if (last_dw) {
+ if ((last_bus_id == param) && (last_dw == dw))
+ return false;
+ }
+
+ /*
+ * Return true:
+ * - If dw_dma's platform data is not filled with slave info, then all
+ * dma controllers are fine for transfer.
+ * - Or if param is NULL
+ */
+ if (!dw->sd || !param)
+ return true;
+
+ while (++i < dw->sd_count) {
+ if (!strcmp(dw->sd[i].bus_id, param)) {
+ chan->private = &dw->sd[i];
+ last_dw = NULL;
+ last_bus_id = NULL;
+
+ return true;
+ }
+ }
+
+ last_dw = dw;
+ last_bus_id = param;
+ return false;
+}
+EXPORT_SYMBOL(dw_dma_generic_filter);
+
/* --------------------- Cyclic DMA API extensions -------------------- */
/**
@@ -1462,6 +1509,91 @@ static void dw_dma_off(struct dw_dma *dw)
dw->chan[i].initialized = false;
}
+#ifdef CONFIG_OF
+static struct dw_dma_platform_data *
+__devinit dw_dma_parse_dt(struct platform_device *pdev)
+{
+ struct device_node *sn, *cn, *np = pdev->dev.of_node;
+ struct dw_dma_platform_data *pdata;
+ struct dw_dma_slave *sd;
+ u32 val, arr[4];
+
+ if (!np) {
+ dev_err(&pdev->dev, "Missing DT data\n");
+ return NULL;
+ }
+
+ pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
+ if (!pdata)
+ return NULL;
+
+ if (of_property_read_u32(np, "nr_channels", &pdata->nr_channels))
+ return NULL;
+
+ if (of_property_read_bool(np, "is_private"))
+ pdata->is_private = true;
+
+ if (!of_property_read_u32(np, "chan_allocation_order", &val))
+ pdata->chan_allocation_order = (unsigned char)val;
+
+ if (!of_property_read_u32(np, "chan_priority", &val))
+ pdata->chan_priority = val;
+
+ if (!of_property_read_u32(np, "block_size", &val))
+ pdata->block_size = val;
+
+ if (!of_property_read_u32(np, "nr_masters", &val)) {
+ if (val > 4)
+ return NULL;
+
+ pdata->nr_masters = val;
+ }
+
+ if (!of_property_read_u32_array(np, "data_width", arr,
+ pdata->nr_masters))
+ for (val = 0; val < pdata->nr_masters; val++)
+ pdata->data_width[val] = arr[val];
+
+ /* parse slave data */
+ sn = of_find_node_by_name(np, "slave_info");
+ if (!sn)
+ return pdata;
+
+ /* calculate number of slaves */
+ val = of_get_child_count(sn);
+ if (!val)
+ return NULL;
+
+ sd = devm_kzalloc(&pdev->dev, sizeof(*sd) * val, GFP_KERNEL);
+ if (!sd)
+ return NULL;
+
+ pdata->sd = sd;
+ pdata->sd_count = val;
+
+ for_each_child_of_node(sn, cn) {
+ sd->dma_dev = &pdev->dev;
+ of_property_read_string(cn, "bus_id", &sd->bus_id);
+ of_property_read_u32(cn, "cfg_hi", &sd->cfg_hi);
+ of_property_read_u32(cn, "cfg_lo", &sd->cfg_lo);
+ if (!of_property_read_u32(cn, "src_master", &val))
+ sd->src_master = val;
+
+ if (!of_property_read_u32(cn, "dst_master", &val))
+ sd->dst_master = val;
+ sd++;
+ }
+
+ return pdata;
+}
+#else
+static inline struct dw_dma_platform_data *
+dw_dma_parse_dt(struct platform_device *pdev)
+{
+ return NULL;
+}
+#endif
+
static int __devinit dw_probe(struct platform_device *pdev)
{
struct dw_dma_platform_data *pdata;
@@ -1478,6 +1610,9 @@ static int __devinit dw_probe(struct platform_device *pdev)
int i;
pdata = dev_get_platdata(&pdev->dev);
+ if (!pdata)
+ pdata = dw_dma_parse_dt(pdev);
+
if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS)
return -EINVAL;
@@ -1512,6 +1647,8 @@ static int __devinit dw_probe(struct platform_device *pdev)
clk_prepare_enable(dw->clk);
dw->regs = regs;
+ dw->sd = pdata->sd;
+ dw->sd_count = pdata->sd_count;
/* get hardware configuration parameters */
if (autocfg) {
diff --git a/drivers/dma/dw_dmac_regs.h b/drivers/dma/dw_dmac_regs.h
index ff39fa6..5cc61ba 100644
--- a/drivers/dma/dw_dmac_regs.h
+++ b/drivers/dma/dw_dmac_regs.h
@@ -231,6 +231,10 @@ struct dw_dma {
struct tasklet_struct tasklet;
struct clk *clk;
+ /* slave information */
+ struct dw_dma_slave *sd;
+ unsigned int sd_count;
+
u8 all_chan_mask;
/* hardware configuration */
diff --git a/include/linux/dw_dmac.h b/include/linux/dw_dmac.h
index 62a6190..41766de 100644
--- a/include/linux/dw_dmac.h
+++ b/include/linux/dw_dmac.h
@@ -15,6 +15,26 @@
#include <linux/dmaengine.h>
/**
+ * struct dw_dma_slave - Controller-specific information about a slave
+ *
+ * @dma_dev: required DMA master device. Depricated.
+ * @bus_id: name of this device channel, not just a device name since
+ * devices may have more than one channel e.g. "foo_tx"
+ * @cfg_hi: Platform-specific initializer for the CFG_HI register
+ * @cfg_lo: Platform-specific initializer for the CFG_LO register
+ * @src_master: src master for transfers on allocated channel.
+ * @dst_master: dest master for transfers on allocated channel.
+ */
+struct dw_dma_slave {
+ struct device *dma_dev;
+ const char *bus_id;
+ u32 cfg_hi;
+ u32 cfg_lo;
+ u8 src_master;
+ u8 dst_master;
+};
+
+/**
* struct dw_dma_platform_data - Controller configuration parameters
* @nr_channels: Number of channels supported by hardware (max 8)
* @is_private: The device channels should be marked as private and not for
@@ -25,6 +45,8 @@
* @nr_masters: Number of AHB masters supported by the controller
* @data_width: Maximum data width supported by hardware per AHB master
* (0 - 8bits, 1 - 16bits, ..., 5 - 256bits)
+ * @sd: slave specific data. Used for configuring channels
+ * @sd_count: count of slave data structures passed.
*/
struct dw_dma_platform_data {
unsigned int nr_channels;
@@ -38,6 +60,9 @@ struct dw_dma_platform_data {
unsigned short block_size;
unsigned char nr_masters;
unsigned char data_width[4];
+
+ struct dw_dma_slave *sd;
+ unsigned int sd_count;
};
/* bursts size */
@@ -52,23 +77,6 @@ enum dw_dma_msize {
DW_DMA_MSIZE_256,
};
-/**
- * struct dw_dma_slave - Controller-specific information about a slave
- *
- * @dma_dev: required DMA master device
- * @cfg_hi: Platform-specific initializer for the CFG_HI register
- * @cfg_lo: Platform-specific initializer for the CFG_LO register
- * @src_master: src master for transfers on allocated channel.
- * @dst_master: dest master for transfers on allocated channel.
- */
-struct dw_dma_slave {
- struct device *dma_dev;
- u32 cfg_hi;
- u32 cfg_lo;
- u8 src_master;
- u8 dst_master;
-};
-
/* Platform-configurable bits in CFG_HI */
#define DWC_CFGH_FCMODE (1 << 0)
#define DWC_CFGH_FIFO_MODE (1 << 1)
@@ -106,5 +114,6 @@ void dw_dma_cyclic_stop(struct dma_chan *chan);
dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan);
dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan);
+bool dw_dma_generic_filter(struct dma_chan *chan, void *param);
#endif /* DW_DMAC_H */
--
1.7.12.rc2.18.g61b472e
^ permalink raw reply related
* [PATCH V2 1/3] dmaengine: dw_dmac: Update documentation style comments for dw_dma_platform_data
From: Viresh Kumar @ 2012-10-12 14:31 UTC (permalink / raw)
To: linux-arm-kernel
Documentation style comments were missing for few fields in struct
dw_dma_platform_data. Add these.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
---
include/linux/dw_dmac.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/linux/dw_dmac.h b/include/linux/dw_dmac.h
index e1c8c9e..62a6190 100644
--- a/include/linux/dw_dmac.h
+++ b/include/linux/dw_dmac.h
@@ -19,6 +19,8 @@
* @nr_channels: Number of channels supported by hardware (max 8)
* @is_private: The device channels should be marked as private and not for
* by the general purpose DMA channel allocator.
+ * @chan_allocation_order: Allocate channels starting from 0 or 7
+ * @chan_priority: Set channel priority increasing from 0 to 7 or 7 to 0.
* @block_size: Maximum block size supported by the controller
* @nr_masters: Number of AHB masters supported by the controller
* @data_width: Maximum data width supported by hardware per AHB master
--
1.7.12.rc2.18.g61b472e
^ permalink raw reply related
* [PATCH v2 1/4] net: mvneta: driver for Marvell Armada 370/XP network unit
From: Jason Cooper @ 2012-10-12 14:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121011212629.GA14171@electric-eye.fr.zoreil.com>
On Thu, Oct 11, 2012 at 11:26:29PM +0200, Francois Romieu wrote:
> Thomas Petazzoni <thomas.petazzoni@free-electrons.com> :
> [...]
> > diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c
> > new file mode 100644
> > index 0000000..4f7fe08
> > --- /dev/null
> > +++ b/drivers/net/ethernet/marvell/mvneta.c
> [...]
> > +static void mvneta_rxq_desc_num_update(struct mvneta_port *pp,
> > + struct mvneta_rx_queue *rxq,
> > + int rx_done, int rx_filled)
> > +{
> > + u32 val;
> > +
> > + if ((rx_done <= 0xff) && (rx_filled <= 0xff)) {
> > + val = rx_done |
> > + (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT);
> > + mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
> > + return;
> > + }
> > +
> > + /* Only 255 descriptors can be added at once */
> > + while ((rx_done > 0) || (rx_filled > 0)) {
> > + if (rx_done <= 0xff) {
> > + val = rx_done;
> > + rx_done = 0;
> > + } else {
> > + val = 0xff;
> > + rx_done -= 0xff;
> > + }
> > + if (rx_filled <= 0xff) {
> > + val |= rx_filled
> > + << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
>
> val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
I agree with Francois on most of these. I prefer readability over hard
80 column limits. Although, 80 columns is still sound guidance. For
example, a majority of the broken lines are due to long macro and
constant names. I did a 'git grep NETA' and didn't see anything
alarming. So, above could become
val |= rx_filled << NETA_RXQ_ADD_NONOCC_SHIFT;
thx,
Jason.
^ permalink raw reply
* [PATCH 1/3] i2c: omap: Do not enable the irq always
From: Kevin Hilman @ 2012-10-12 14:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1349687116-14463-1-git-send-email-shubhrajyoti@ti.com>
+Kalle, Grygorii, Huzefa
Shubhrajyoti D <shubhrajyoti@ti.com> writes:
> Enable the irq in the transfer and disable it after the
> transfer is done.
>
> Signed-off-by: Shubhrajyoti D <shubhrajyoti@ti.com>
> ---
> drivers/i2c/busses/i2c-omap.c | 3 +++
> 1 files changed, 3 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
> index b6c6b95..ce41596 100644
> --- a/drivers/i2c/busses/i2c-omap.c
> +++ b/drivers/i2c/busses/i2c-omap.c
> @@ -625,6 +625,7 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
> if (IS_ERR_VALUE(r))
> goto out;
>
> + enable_irq(dev->irq);
> r = omap_i2c_wait_for_bb(dev);
> if (r < 0)
> goto out;
> @@ -654,6 +655,7 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
>
> omap_i2c_wait_for_bb(dev);
> out:
> + disable_irq(dev->irq);
When using runtime PM with auto-suspend timeouts, why would you disable
the IRQ before the runtime suspend handlers have run?
If you really want to do this, you probably should have these in the
runtime PM callbacks. But I'll wait until you add a more descriptive
changelog before I can really tell why this is being done. Based on the
discussion in the patch from Kalle, I'm assuming this is to prevent
interrups when I2C is being used by co-processors. If so, plese
describe in the changelog.
That being said, doesn't the runtime suspend callback already disable
IRQs at the device level instead of the INTC level?
Kevin
> pm_runtime_mark_last_busy(dev->dev);
> pm_runtime_put_autosuspend(dev->dev);
> return r;
> @@ -1179,6 +1181,7 @@ omap_i2c_probe(struct platform_device *pdev)
> goto err_unuse_clocks;
> }
>
> + disable_irq(dev->irq);
> adap = &dev->adapter;
> i2c_set_adapdata(adap, dev);
> adap->owner = THIS_MODULE;
^ permalink raw reply
* [PATCH 1/4] ARM: AT91: Add DT support to AT91RM9200 System Timer
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-10-12 14:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1349993126-9519-1-git-send-email-manabian@gmail.com>
On 00:05 Fri 12 Oct , Joachim Eastwood wrote:
> Based on AT91 PIT DT patch from Jean-Christophe PLAGNIOL-VILLARD.
ok for this one
>
> Signed-off-by: Joachim Eastwood <manabian@gmail.com>
> ---
> .../devicetree/bindings/arm/atmel-at91.txt | 6 +++
> arch/arm/mach-at91/at91rm9200_time.c | 63 +++++++++++++++++++++-
> 2 files changed, 67 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.txt b/Documentation/devicetree/bindings/arm/atmel-at91.txt
> index ecc81e3..8adc9a8 100644
> --- a/Documentation/devicetree/bindings/arm/atmel-at91.txt
> +++ b/Documentation/devicetree/bindings/arm/atmel-at91.txt
> @@ -7,6 +7,12 @@ PIT Timer required properties:
> - interrupts: Should contain interrupt for the PIT which is the IRQ line
> shared across all System Controller members.
>
> +System Timer (ST) required properties:
> +- compatible: Should be "atmel,at91rm9200-st"
> +- reg: Should contain registers location and length
> +- interrupts: Should contain interrupt for the ST which is the IRQ line
> + shared across all System Controller members.
> +
> TC/TCLIB Timer required properties:
> - compatible: Should be "atmel,<chip>-pit".
> <chip> can be "at91rm9200" or "at91sam9x5"
> diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c
> index aaa443b..cafe988 100644
> --- a/arch/arm/mach-at91/at91rm9200_time.c
> +++ b/arch/arm/mach-at91/at91rm9200_time.c
> @@ -24,6 +24,9 @@
> #include <linux/irq.h>
> #include <linux/clockchips.h>
> #include <linux/export.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>
>
> #include <asm/mach/time.h>
>
> @@ -91,7 +94,8 @@ static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id)
> static struct irqaction at91rm9200_timer_irq = {
> .name = "at91_tick",
> .flags = IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
> - .handler = at91rm9200_timer_interrupt
> + .handler = at91rm9200_timer_interrupt,
> + .irq = NR_IRQS_LEGACY + AT91_ID_SYS,
> };
>
> static cycle_t read_clk32k(struct clocksource *cs)
> @@ -179,8 +183,60 @@ static struct clock_event_device clkevt = {
> void __iomem *at91_st_base;
> EXPORT_SYMBOL_GPL(at91_st_base);
>
> +#ifdef CONFIG_OF
> +static struct of_device_id at91rm9200_st_timer_ids[] = {
> + { .compatible = "atmel,at91rm9200-st" },
> + { /* sentinel */ }
> +};
> +
> +static int __init of_at91rm9200_st_init(void)
> +{
> + struct device_node *np;
> + int ret;
> +
> + np = of_find_matching_node(NULL, at91rm9200_st_timer_ids);
> + if (!np)
> + goto err;
> +
> + at91_st_base = of_iomap(np, 0);
> + if (!at91_st_base)
> + goto node_err;
> +
> + /* Get the interrupts property */
> + ret = irq_of_parse_and_map(np, 0);
> + if (!ret)
> + goto ioremap_err;
> + at91rm9200_timer_irq.irq = ret;
> +
> + of_node_put(np);
> +
> + return 0;
> +
> +ioremap_err:
> + iounmap(at91_st_base);
> +node_err:
> + of_node_put(np);
> +err:
> + return -EINVAL;
> +}
> +#else
> +static int __init of_at91rm9200_st_init(void)
> +{
> + return -EINVAL;
> +}
> +#endif
> +
> void __init at91rm9200_ioremap_st(u32 addr)
> {
> +#ifdef CONFIG_OF
> + struct device_node *np;
> +
> + np = of_find_matching_node(NULL, at91rm9200_st_timer_ids);
> + if (np) {
> + of_node_put(np);
> + return;
> + }
> +#endif
> at91_st_base = ioremap(addr, 256);
> if (!at91_st_base)
> panic("Impossible to ioremap ST\n");
> @@ -191,13 +247,16 @@ void __init at91rm9200_ioremap_st(u32 addr)
> */
> void __init at91rm9200_timer_init(void)
> {
> + /* For device tree enabled device: initialize here */
> + of_at91rm9200_st_init();
> +
> /* Disable all timer interrupts, and clear any pending ones */
> at91_st_write(AT91_ST_IDR,
> AT91_ST_PITS | AT91_ST_WDOVF | AT91_ST_RTTINC | AT91_ST_ALMS);
> at91_st_read(AT91_ST_SR);
>
> /* Make IRQs happen for the system timer */
> - setup_irq(NR_IRQS_LEGACY + AT91_ID_SYS, &at91rm9200_timer_irq);
> + setup_irq(at91rm9200_timer_irq.irq, &at91rm9200_timer_irq);
>
> /* The 32KiHz "Slow Clock" (tick every 30517.58 nanoseconds) is used
> * directly for the clocksource and all clockevents, after adjusting
> --
> 1.7.12.2
>
^ permalink raw reply
* alignment faults in 3.6
From: Benjamin LaHaise @ 2012-10-12 14:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350043692.21172.11815.camel@edumazet-glaptop>
On Fri, Oct 12, 2012 at 02:08:12PM +0200, Eric Dumazet wrote:
> So yes, we built network stack with the prereq that IP headers are
> aligned, but unfortunately many developers use x86 which doesnt care, so
> its possible some bugs are added.
x86 does have an alignment check flag that can be set in the flags register.
Somehow, I doubt anyone would be willing to walk through all the noise the
faults would likely trigger.
-ben
--
"Thought is the essence of where you are now."
^ permalink raw reply
* [PATCH 3/4] ARM: AT91: Add AT91RM9200 support to DT board
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-10-12 14:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1349993126-9519-3-git-send-email-manabian@gmail.com>
On 00:05 Fri 12 Oct , Joachim Eastwood wrote:
> Signed-off-by: Joachim Eastwood <manabian@gmail.com>
> ---
>
> Hi,
>
> This patch has some potential issues.
> Before this patch board-dt would fail building when only AT91RM9200 was enabled because at91sam926x_timer symbol would be missing. This patch uses the at91rm9200_timer which
> will fail if AT91RM9200 is not enabled.
this need work with ot wtihout rm9200
>
> Any thoughts on solving this? As mention above this bug exists in mainline now.
duplicate the board-dt with one for rm9200 only
as rm9200 ans sam9 are 2 distict familly
>
> I had to create a new at91rm9200_dt_initialize since at91_dt_initialize will panic when it tries to add rstc and shdwc.
> Is it okay to add at91rm9200_dt_initialize or should we fix at91_dt_rstc and at91_dt_shdwc to not panic when DT nodes are not found?
it's ok
>
can you add a board too rm9200ek will be good
Best Regards,
J.
> regards
> Joachim Eastwood
>
> arch/arm/mach-at91/board-dt.c | 15 +++++++++++++++
> arch/arm/mach-at91/generic.h | 1 +
> arch/arm/mach-at91/setup.c | 14 ++++++++++++++
> 3 files changed, 30 insertions(+)
>
> diff --git a/arch/arm/mach-at91/board-dt.c b/arch/arm/mach-at91/board-dt.c
> index e8f45c4..0e73317 100644
> --- a/arch/arm/mach-at91/board-dt.c
> +++ b/arch/arm/mach-at91/board-dt.c
> @@ -45,11 +45,26 @@ static void __init at91_dt_device_init(void)
> of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
> }
>
> +static const char *at91rm9200_dt_board_compat[] __initdata = {
> + "atmel,at91rm9200",
> + NULL
> +};
> +
> static const char *at91_dt_board_compat[] __initdata = {
> "atmel,at91sam9",
> NULL
> };
>
> +DT_MACHINE_START(at91rm9200_dt, "Atmel AT91RM9200 (Device Tree)")
> + .timer = &at91rm9200_timer,
> + .map_io = at91_map_io,
> + .handle_irq = at91_aic_handle_irq,
> + .init_early = at91rm9200_dt_initialize,
> + .init_irq = at91_dt_init_irq,
> + .init_machine = at91_dt_device_init,
> + .dt_compat = at91rm9200_dt_board_compat,
> +MACHINE_END
> +
> DT_MACHINE_START(at91sam_dt, "Atmel AT91SAM (Device Tree)")
> /* Maintainer: Atmel */
> .timer = &at91sam926x_timer,
> diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
> index f496506..9bb5ce5 100644
> --- a/arch/arm/mach-at91/generic.h
> +++ b/arch/arm/mach-at91/generic.h
> @@ -20,6 +20,7 @@ extern void __init at91_init_sram(int bank, unsigned long base,
> extern void __init at91rm9200_set_type(int type);
> extern void __init at91_initialize(unsigned long main_clock);
> extern void __init at91x40_initialize(unsigned long main_clock);
> +extern void __init at91rm9200_dt_initialize(void);
> extern void __init at91_dt_initialize(void);
>
> /* Interrupts */
> diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
> index da9881b..2c1fdd4 100644
> --- a/arch/arm/mach-at91/setup.c
> +++ b/arch/arm/mach-at91/setup.c
> @@ -338,6 +338,7 @@ static void at91_dt_rstc(void)
> }
>
> static struct of_device_id ramc_ids[] = {
> + { .compatible = "atmel,at91rm9200-sdramc" },
> { .compatible = "atmel,at91sam9260-sdramc" },
> { .compatible = "atmel,at91sam9g45-ddramc" },
> { /*sentinel*/ }
> @@ -436,6 +437,19 @@ end:
> of_node_put(np);
> }
>
> +void __init at91rm9200_dt_initialize(void)
> +{
> + at91_dt_ramc();
> +
> + /* Init clock subsystem */
> + at91_dt_clock_init();
> +
> + /* Register the processor-specific clocks */
> + at91_boot_soc.register_clocks();
> +
> + at91_boot_soc.init();
> +}
> +
> void __init at91_dt_initialize(void)
> {
> at91_dt_rstc();
> --
> 1.7.12.2
>
^ permalink raw reply
* [PATCH 2/4] ARM: AT91: Add usart/tc DT clock lookup to AT91RM9200
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-10-12 14:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1349993126-9519-2-git-send-email-manabian@gmail.com>
Hi,
You need to rebase your patch over the pinctrl
Best Regards,
J.
On 00:05 Fri 12 Oct , Joachim Eastwood wrote:
> Signed-off-by: Joachim Eastwood <manabian@gmail.com>
> ---
> arch/arm/mach-at91/at91rm9200.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
> index b4f0565..eef3f53 100644
> --- a/arch/arm/mach-at91/at91rm9200.c
> +++ b/arch/arm/mach-at91/at91rm9200.c
> @@ -188,6 +188,19 @@ static struct clk_lookup periph_clocks_lookups[] = {
> CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
> CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk),
> CLKDEV_CON_DEV_ID(NULL, "i2c-at91rm9200", &twi_clk),
> + /* usart lookup table for DT entries */
> + CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
> + CLKDEV_CON_DEV_ID("usart", "fffc0000.serial", &usart0_clk),
> + CLKDEV_CON_DEV_ID("usart", "fffc4000.serial", &usart1_clk),
> + CLKDEV_CON_DEV_ID("usart", "fffc8000.serial", &usart2_clk),
> + CLKDEV_CON_DEV_ID("usart", "fffcc000.serial", &usart3_clk),
> + /* tc lookup table for DT entries */
> + CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
> + CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
> + CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
> + CLKDEV_CON_DEV_ID("t0_clk", "fffa4000.timer", &tc3_clk),
> + CLKDEV_CON_DEV_ID("t1_clk", "fffa4000.timer", &tc4_clk),
> + CLKDEV_CON_DEV_ID("t2_clk", "fffa4000.timer", &tc5_clk),
> /* fake hclk clock */
> CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
> CLKDEV_CON_ID("pioA", &pioA_clk),
> --
> 1.7.12.2
>
^ permalink raw reply
* [PATCH v2 1/4] net: mvneta: driver for Marvell Armada 370/XP network unit
From: Thomas Petazzoni @ 2012-10-12 14:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5076E9F1.60200@gmail.com>
Rob,
On Thu, 11 Oct 2012 10:46:57 -0500, Rob Herring wrote:
> > +Required properties:
> > +- compatible: should be "marvell,neta".
>
> This should be more specific such as "marvell,armada-xp-neta".
>
> Or use 370 instead of xp. It should be which ever chip came first.
Is this really useful? The name of this network unit in Marvell is
simply "neta", and since it is associated with the vendor name Marvell
in the compatible string, it is actually unique: "marvell,neta".
The thing is that this unit is used in Armada 370, Armada XP, but also
other SoCs (which I am not sure are announced publicly as of today). So
if possible, we would prefer to keep the proposed "marvell,neta" name.
We could also change it to "marvell,ebu-neta" where EBU stands for
Embedded Business Unit, just like the "ebu" in arch/arm/mach-mvebu/,
but it sounds more logical to have just "marvell,neta".
Thanks again for your review,
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply
* [PATCH 1/2] ARM: config: sort select statements alphanumerically
From: Jason Cooper @ 2012-10-12 14:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <E1TMfFr-0001Kt-W5@rmk-PC.arm.linux.org.uk>
On Fri, Oct 12, 2012 at 02:26:19PM +0100, Russell King wrote:
> As suggested by Andrew Morton:
>
> This is a pet peeve of mine. Any time there's a long list of items
> (header file inclusions, kconfig entries, array initalisers, etc) and
> someone wants to add a new item, they *always* go and stick it at the
> end of the list.
>
> Guys, don't do this. Either put the new item into a randomly-chosen
> position or, probably better, alphanumerically sort the list.
>
> lets sort all our select statements alphanumerically. This commit was
> created by the following perl:
>
> while (<>) {
> while (/\\\s*$/) {
> $_ .= <>;
> }
> undef %selects if /^\s*config\s+/;
> if (/^\s+select\s+(\w+).*/) {
> if (defined($selects{$1})) {
> if ($selects{$1} eq $_) {
> print STDERR "Warning: removing duplicated $1 entry\n";
> } else {
> print STDERR "Error: $1 differently selected\n".
> "\tOld: $selects{$1}\n".
> "\tNew: $_\n";
> exit 1;
> }
> }
> $selects{$1} = $_;
> next;
> }
> if (%selects and (/^\s*$/ or /^\s+help/)) {
> foreach $k (sort (keys %selects)) {
> print "$selects{$k}";
> }
> undef %selects;
> }
> print;
> }
> if (%selects) {
> foreach $k (sort (keys %selects)) {
> print "$selects{$k}";
> }
> }
>
> It found two duplicates:
>
> Warning: removing duplicated S5P_SETUP_MIPIPHY entry
> Warning: removing duplicated HARDIRQS_SW_RESEND entry
>
> and they are identical duplicates, hence the shrinkage in the diffstat
> of two lines.
>
> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
For ARCH_DOVE, ARCH_KIRKWOOD, ARCH_MV78XX0, ARCH_ORION5X, PLAT_ORION,
and PLAT_ORION_LEGACY:
Acked-by: Jason Cooper <jason@lakedaemon.net>
thx,
Jason.
^ permalink raw reply
* [PATCH 2/3] dmaengine: dw_dmac: Enhance device tree support
From: Viresh Kumar @ 2012-10-12 14:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350048519.10584.158.camel@smile>
On 12 October 2012 18:58, Shevchenko, Andriy
<andriy.shevchenko@intel.com> wrote:
> On Fri, 2012-10-12 at 11:14 +0530, Viresh Kumar wrote:
>> + if (!of_property_read_u32(np, "chan_allocation_order",
>> + &val))
> Fits one line?
yes.
>> + pdata->chan_allocation_order = (unsigned char)val;
> do we really need explicit casting here?
Obviously not, bigger to smaller is automatically casted. My coding standard is
going down :(
Same for all casting comments.
>> + if (!of_property_read_u32(np, "nr_masters", &val)) {
>> + if (val > 4)
> I thought once that we might introduce constant like #define
> DW_MAX_AHB_MASTERS 4. It seems a bit useless because hw is designed for
> that number anyway, but maybe you have another opinion.
Not everyone have four masters in there SoC configurations. So its better
to export correct values.
>> + if (!of_property_read_u32_array(np, "data_width", arr,
>> + pdata->nr_masters))
>> + for (count = 0; count < pdata->nr_masters; count++)
>> + pdata->data_width[count] = arr[count];
> Ah, it would be nice to have of_property_read_u8_array and so on...
:)
Maybe yes. I don't want to do it with this patchset, as that will take more
time to go through maintainers.
>> + /* calculate number of slaves */
>> + for_each_child_of_node(sn, cn)
>> + count++;
>
> of.h: static inline int of_get_child_count(const struct device_node *np)
Hehe.. Will use that.
This proves there is no efficient way of finding child nodes, than this.
>> + for_each_child_of_node(sn, cn) {
>> + of_property_read_string(cn, "bus_id", &sd[count].bus_id);
>> + of_property_read_u32(cn, "cfg_hi", &sd[count].cfg_hi);
>> + of_property_read_u32(cn, "cfg_lo", &sd[count].cfg_lo);
>> + if (!of_property_read_u32(cn, "src_master", &val))
>> + sd[count].src_master = (u8)val;
>> +
>> + if (!of_property_read_u32(cn, "dst_master", &val))
>> + sd[count].dst_master = (u8)val;
>> +
>> + sd[count].dma_dev = &pdev->dev;
>> + count++;
>> + }
>
> what about to define sd as sd[0]; in the platform_data structure and
> then use smth like following
>
> struct ... *sd = pdata->sd;
> for_each... {
> sd->... = ;
> sd++;
> }
>
> it will probably require to split this part in a separate function and
> calculate count of slave_info children before pdata memory allocation.
Liked the idea partially. Check my new implementation in fixup for all
these comments:
---------------------------8<---------------------------
From: Viresh Kumar <viresh.kumar@linaro.org>
Date: Fri, 12 Oct 2012 19:35:44 +0530
Subject: [PATCH] fixup! dmaengine: dw_dmac: Enhance device tree support
---
drivers/dma/dw_dmac.c | 50 ++++++++++++++++++++++---------------------------
include/linux/dw_dmac.h | 2 +-
2 files changed, 23 insertions(+), 29 deletions(-)
diff --git a/drivers/dma/dw_dmac.c b/drivers/dma/dw_dmac.c
index c24859e..d72c26f 100644
--- a/drivers/dma/dw_dmac.c
+++ b/drivers/dma/dw_dmac.c
@@ -1179,7 +1179,7 @@ static void dwc_free_chan_resources(struct dma_chan *chan)
dev_vdbg(chan2dev(chan), "%s: done\n", __func__);
}
-bool dw_generic_filter(struct dma_chan *chan, void *param)
+bool dw_dma_generic_filter(struct dma_chan *chan, void *param)
{
struct dw_dma *dw = to_dw_dma(chan->device);
static struct dw_dma *last_dw;
@@ -1224,7 +1224,7 @@ bool dw_generic_filter(struct dma_chan *chan, void *param)
last_bus_id = param;
return false;
}
-EXPORT_SYMBOL(dw_generic_filter);
+EXPORT_SYMBOL(dw_dma_generic_filter);
/* --------------------- Cyclic DMA API extensions -------------------- */
@@ -1516,7 +1516,7 @@ __devinit dw_dma_parse_dt(struct platform_device *pdev)
struct device_node *sn, *cn, *np = pdev->dev.of_node;
struct dw_dma_platform_data *pdata;
struct dw_dma_slave *sd;
- u32 count, val, arr[4];
+ u32 val, arr[4];
if (!np) {
dev_err(&pdev->dev, "Missing DT data\n");
@@ -1533,63 +1533,57 @@ __devinit dw_dma_parse_dt(struct platform_device *pdev)
if (of_property_read_bool(np, "is_private"))
pdata->is_private = true;
- if (!of_property_read_u32(np, "chan_allocation_order",
- &val))
+ if (!of_property_read_u32(np, "chan_allocation_order", &val))
pdata->chan_allocation_order = (unsigned char)val;
if (!of_property_read_u32(np, "chan_priority", &val))
- pdata->chan_priority = (unsigned char)val;
+ pdata->chan_priority = val;
if (!of_property_read_u32(np, "block_size", &val))
- pdata->block_size = (unsigned short)val;
+ pdata->block_size = val;
if (!of_property_read_u32(np, "nr_masters", &val)) {
if (val > 4)
return NULL;
- pdata->nr_masters = (unsigned char)val;
+ pdata->nr_masters = val;
}
if (!of_property_read_u32_array(np, "data_width", arr,
pdata->nr_masters))
- for (count = 0; count < pdata->nr_masters; count++)
- pdata->data_width[count] = arr[count];
+ for (val = 0; val < pdata->nr_masters; val++)
+ pdata->data_width[val] = arr[val];
/* parse slave data */
sn = of_find_node_by_name(np, "slave_info");
if (!sn)
return pdata;
- count = 0;
/* calculate number of slaves */
- for_each_child_of_node(sn, cn)
- count++;
-
- if (!count)
+ val = of_get_child_count(sn);
+ if (!val)
return NULL;
- sd = devm_kzalloc(&pdev->dev, sizeof(*sd) * count, GFP_KERNEL);
+ sd = devm_kzalloc(&pdev->dev, sizeof(*sd) * val, GFP_KERNEL);
if (!sd)
return NULL;
- count = 0;
+ pdata->sd = sd;
+ pdata->sd_count = val;
+
for_each_child_of_node(sn, cn) {
- of_property_read_string(cn, "bus_id", &sd[count].bus_id);
- of_property_read_u32(cn, "cfg_hi", &sd[count].cfg_hi);
- of_property_read_u32(cn, "cfg_lo", &sd[count].cfg_lo);
+ sd->dma_dev = &pdev->dev;
+ of_property_read_string(cn, "bus_id", &sd->bus_id);
+ of_property_read_u32(cn, "cfg_hi", &sd->cfg_hi);
+ of_property_read_u32(cn, "cfg_lo", &sd->cfg_lo);
if (!of_property_read_u32(cn, "src_master", &val))
- sd[count].src_master = (u8)val;
+ sd->src_master = val;
if (!of_property_read_u32(cn, "dst_master", &val))
- sd[count].dst_master = (u8)val;
-
- sd[count].dma_dev = &pdev->dev;
- count++;
+ sd->dst_master = val;
+ sd++;
}
- pdata->sd = sd;
- pdata->sd_count = count;
-
return pdata;
}
#else
diff --git a/include/linux/dw_dmac.h b/include/linux/dw_dmac.h
index 4d1c8c3..41766de 100644
--- a/include/linux/dw_dmac.h
+++ b/include/linux/dw_dmac.h
@@ -114,6 +114,6 @@ void dw_dma_cyclic_stop(struct dma_chan *chan);
dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan);
dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan);
-bool dw_generic_filter(struct dma_chan *chan, void *param);
+bool dw_dma_generic_filter(struct dma_chan *chan, void *param);
#endif /* DW_DMAC_H */
^ permalink raw reply related
* [PATCH 1/2] ARM: config: sort select statements alphanumerically
From: Linus Walleij @ 2012-10-12 14:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <E1TMfFr-0001Kt-W5@rmk-PC.arm.linux.org.uk>
On Fri, Oct 12, 2012 at 3:26 PM, Russell King
<rmk+kernel@arm.linux.org.uk> wrote:
> As suggested by Andrew Morton:
>
> This is a pet peeve of mine. Any time there's a long list of items
> (header file inclusions, kconfig entries, array initalisers, etc) and
> someone wants to add a new item, they *always* go and stick it at the
> end of the list.
>
> Guys, don't do this. Either put the new item into a randomly-chosen
> position or, probably better, alphanumerically sort the list.
>
> lets sort all our select statements alphanumerically. This commit was
> created by the following perl:
I applied this and tried to configure the Nomadik defconfig,
and I get this, sadly:
make -f Makefile ARCH=arm CROSS_COMPILE=arm-linux-gnueabi-
KBUILD_OUTPUT=/var/linus/linux/build-nomadik nhk8815_defconfig
make[1]: Entering directory `/var/linus/linux'
GEN /var/linus/linux/build-nomadik/Makefile
arch/arm/mach-footbridge/Kconfig:29: syntax error
arch/arm/mach-footbridge/Kconfig:28: unknown option "Saying"
arch/arm/mach-footbridge/Kconfig:31: syntax error
arch/arm/mach-footbridge/Kconfig:30: unknown option "The"
arch/arm/mach-footbridge/Kconfig:31: unknown option "There"
arch/arm/mach-footbridge/Kconfig:32: unknown option "prototypes"
arch/arm/mach-footbridge/Kconfig:35: syntax error
arch/arm/mach-footbridge/Kconfig:34: unknown option "http"
arch/arm/mach-footbridge/Kconfig:37: syntax error
arch/arm/mach-footbridge/Kconfig:36: unknown option "If"
arch/arm/mach-footbridge/Kconfig:37: unknown option "Server"
arch/arm/mach-pxa/Kconfig:18: syntax error
arch/arm/mach-pxa/Kconfig:3: missing end statement for this entry
arch/arm/mach-pxa/Kconfig:3: missing end statement for this entry
arch/arm/Kconfig:245: missing end statement for this entry
arch/arm/mach-pxa/Kconfig:17: invalid statement
arch/arm/mach-pxa/Kconfig:632: unexpected end statement
arch/arm/mach-pxa/Kconfig:634: syntax error
arch/arm/mach-pxa/Kconfig:633: unexpected option "select"
arch/arm/mach-pxa/Kconfig:634: unexpected option "select"
arch/arm/mach-pxa/Kconfig:733: unexpected end statement
arch/arm/Kconfig:1416: unexpected end statement
make[3]: *** [nhk8815_defconfig] Error 1
make[2]: *** [nhk8815_defconfig] Error 2
make[1]: *** [sub-make] Error 2
make[1]: Leaving directory `/var/linus/linux'
make: *** [config-base] Error 2make -f Makefile ARCH=arm
CROSS_COMPILE=arm-linux-gnueabi-
KBUILD_OUTPUT=/var/linus/linux/build-nomadik nhk8815_defconfig
make[1]: Entering directory `/var/linus/linux'
GEN /var/linus/linux/build-nomadik/Makefile
arch/arm/mach-footbridge/Kconfig:29: syntax error
arch/arm/mach-footbridge/Kconfig:28: unknown option "Saying"
arch/arm/mach-footbridge/Kconfig:31: syntax error
arch/arm/mach-footbridge/Kconfig:30: unknown option "The"
arch/arm/mach-footbridge/Kconfig:31: unknown option "There"
arch/arm/mach-footbridge/Kconfig:32: unknown option "prototypes"
arch/arm/mach-footbridge/Kconfig:35: syntax error
arch/arm/mach-footbridge/Kconfig:34: unknown option "http"
arch/arm/mach-footbridge/Kconfig:37: syntax error
arch/arm/mach-footbridge/Kconfig:36: unknown option "If"
arch/arm/mach-footbridge/Kconfig:37: unknown option "Server"
arch/arm/mach-pxa/Kconfig:18: syntax error
arch/arm/mach-pxa/Kconfig:3: missing end statement for this entry
arch/arm/mach-pxa/Kconfig:3: missing end statement for this entry
arch/arm/Kconfig:245: missing end statement for this entry
arch/arm/mach-pxa/Kconfig:17: invalid statement
arch/arm/mach-pxa/Kconfig:632: unexpected end statement
arch/arm/mach-pxa/Kconfig:634: syntax error
arch/arm/mach-pxa/Kconfig:633: unexpected option "select"
arch/arm/mach-pxa/Kconfig:634: unexpected option "select"
arch/arm/mach-pxa/Kconfig:733: unexpected end statement
arch/arm/Kconfig:1416: unexpected end statement
make[3]: *** [nhk8815_defconfig] Error 1
make[2]: *** [nhk8815_defconfig] Error 2
make[1]: *** [sub-make] Error 2
make[1]: Leaving directory `/var/linus/linux'
make: *** [config-base] Error 2
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH 1/1] pinctrl/at91: fix compatible order
From: ludovic.desroches @ 2012-10-12 14:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350033790-31028-1-git-send-email-plagnioj@jcrosoft.com>
Le 10/12/2012 11:23 AM, Jean-Christophe PLAGNIOL-VILLARD a ?crit :
> the sam9x5 is new version of the rm9200 not the invert
>
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> ---
> drivers/pinctrl/pinctrl-at91.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
> index 9c0fe11..bdb152b 100644
> --- a/drivers/pinctrl/pinctrl-at91.c
> +++ b/drivers/pinctrl/pinctrl-at91.c
> @@ -1331,8 +1331,8 @@ static void __devinit at91_gpio_probe_fixup(void)
> }
>
> static struct of_device_id at91_gpio_of_match[] __devinitdata = {
> - { .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops },
> { .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, },
> + { .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops },
> { /* sentinel */ }
> };
>
>
Do it also for at91_pinctrl_of_match[], there is the same issue.
Regards
Ludovic
^ permalink raw reply
* [PATCH] mmc: mmci: Support non-power-of-two block sizes for ux500v2 variant
From: Ulf Hansson @ 2012-10-12 14:02 UTC (permalink / raw)
To: linux-arm-kernel
From: Ulf Hansson <ulf.hansson@linaro.org>
For the ux500v2 variant non power of two block sizes are supported.
This will make it possible to decrease data overhead for SDIO
transfers. Although we need to put some constraints to the alignment
of the buffers when enabling this feature.
Buffers must be 4 bytes aligned due to restrictions that the PL18x
FIFO accesses must be done in a 4 byte aligned manner. Moreover we
need to enable DMA_REQCTL for SDIO to support write of non 32 bytes
aligned sg element lengths. In PIO mode any buffer length can be
handled as long as the buffer address is 4 byte aligned.
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Per Forlin <per.forlin@stericsson.com>
---
drivers/mmc/host/mmci.c | 56 +++++++++++++++++++++++++++++++++++++++++------
drivers/mmc/host/mmci.h | 7 ++++++
2 files changed, 56 insertions(+), 7 deletions(-)
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index edc3e9b..ca6d128 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -48,6 +48,7 @@ static unsigned int fmax = 515633;
* struct variant_data - MMCI variant-specific quirks
* @clkreg: default value for MCICLOCK register
* @clkreg_enable: enable value for MMCICLOCK register
+ * @dma_sdio_req_ctrl: enable value for DMAREQCTL register for SDIO write
* @datalength_bits: number of bits in the MMCIDATALENGTH register
* @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY
* is asserted (likewise for RX)
@@ -58,10 +59,12 @@ static unsigned int fmax = 515633;
* @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register
* @pwrreg_powerup: power up value for MMCIPOWER register
* @signal_direction: input/out direction of bus signals can be indicated
+ * @non_power_of_2_blksize: true if block sizes can be other than power of two
*/
struct variant_data {
unsigned int clkreg;
unsigned int clkreg_enable;
+ unsigned int dma_sdio_req_ctrl;
unsigned int datalength_bits;
unsigned int fifosize;
unsigned int fifohalfsize;
@@ -70,6 +73,7 @@ struct variant_data {
bool blksz_datactrl16;
u32 pwrreg_powerup;
bool signal_direction;
+ bool non_power_of_2_blksize;
};
static struct variant_data variant_arm = {
@@ -112,6 +116,7 @@ static struct variant_data variant_ux500 = {
.fifohalfsize = 8 * 4,
.clkreg = MCI_CLK_ENABLE,
.clkreg_enable = MCI_ST_UX500_HWFCEN,
+ .dma_sdio_req_ctrl = MCI_ST_DPSM_DMAREQCTL,
.datalength_bits = 24,
.sdio = true,
.st_clkdiv = true,
@@ -124,15 +129,42 @@ static struct variant_data variant_ux500v2 = {
.fifohalfsize = 8 * 4,
.clkreg = MCI_CLK_ENABLE,
.clkreg_enable = MCI_ST_UX500_HWFCEN,
+ .dma_sdio_req_ctrl = MCI_ST_DPSM_DMAREQCTL,
.datalength_bits = 24,
.sdio = true,
.st_clkdiv = true,
.blksz_datactrl16 = true,
.pwrreg_powerup = MCI_PWR_ON,
.signal_direction = true,
+ .non_power_of_2_blksize = true,
};
/*
+ * Validate mmc prerequisites
+ */
+static int mmci_validate_data(struct mmci_host *host,
+ struct mmc_data *data)
+{
+ if (!data)
+ return 0;
+
+ if (!host->variant->non_power_of_2_blksize &&
+ !is_power_of_2(data->blksz)) {
+ dev_err(mmc_dev(host->mmc),
+ "unsupported block size (%d bytes)\n", data->blksz);
+ return -EINVAL;
+ }
+
+ if (data->sg->offset & 3) {
+ dev_err(mmc_dev(host->mmc),
+ "unsupported alginment (0x%x)\n", data->sg->offset);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+/*
* This must be called with host->lock held
*/
static void mmci_write_clkreg(struct mmci_host *host, u32 clk)
@@ -446,8 +478,12 @@ static int mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data,
if (!chan)
return -EINVAL;
- /* If less than or equal to the fifo size, don't bother with DMA */
- if (data->blksz * data->blocks <= variant->fifosize)
+ /*
+ * If less than or equal to the fifo size, don't bother with DMA
+ * SDIO transfers may not be 4 bytes aligned, fall back to PIO
+ */
+ if (data->blksz * data->blocks <= variant->fifosize ||
+ (data->blksz * data->blocks) & 3)
return -EINVAL;
device = chan->device;
@@ -482,6 +518,7 @@ static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
{
int ret;
struct mmc_data *data = host->data;
+ struct variant_data *variant = host->variant;
ret = mmci_dma_prep_data(host, host->data, NULL);
if (ret)
@@ -496,6 +533,11 @@ static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
datactrl |= MCI_DPSM_DMAENABLE;
+ /* Some hardware versions need special flags for SDIO DMA write */
+ if (variant->sdio && host->mmc->card && mmc_card_sdio(host->mmc->card)
+ && (data->flags & MMC_DATA_WRITE))
+ datactrl |= variant->dma_sdio_req_ctrl;
+
/* Trigger the DMA transfer */
writel(datactrl, host->base + MMCIDATACTRL);
@@ -540,6 +582,9 @@ static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq,
if (!data)
return;
+ if (mmci_validate_data(host, mrq->data))
+ return;
+
if (data->host_cookie) {
data->host_cookie = 0;
return;
@@ -642,7 +687,6 @@ static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
writel(host->size, base + MMCIDATALENGTH);
blksz_bits = ffs(data->blksz) - 1;
- BUG_ON(1 << blksz_bits != data->blksz);
if (variant->blksz_datactrl16)
datactrl = MCI_DPSM_ENABLE | (data->blksz << 16);
@@ -1048,10 +1092,8 @@ static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
WARN_ON(host->mrq != NULL);
- if (mrq->data && !is_power_of_2(mrq->data->blksz)) {
- dev_err(mmc_dev(mmc), "unsupported block size (%d bytes)\n",
- mrq->data->blksz);
- mrq->cmd->error = -EINVAL;
+ mrq->cmd->error = mmci_validate_data(host, mrq->data);
+ if (mrq->cmd->error) {
mmc_request_done(mmc, mrq);
return;
}
diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h
index d437ccf..c2b3332 100644
--- a/drivers/mmc/host/mmci.h
+++ b/drivers/mmc/host/mmci.h
@@ -60,6 +60,13 @@
#define MCI_ST_DPSM_RWMOD (1 << 10)
#define MCI_ST_DPSM_SDIOEN (1 << 11)
/* Control register extensions in the ST Micro Ux500 versions */
+/*
+ * DMA request control is required for write
+ * if transfer size is not 32 byte aligned.
+ * DMA request control is also needed if the total
+ * transfer size is 32 byte aligned but any of the
+ * sg element lengths are not aligned with 32 byte.
+ */
#define MCI_ST_DPSM_DMAREQCTL (1 << 12)
#define MCI_ST_DPSM_DBOOTMODEEN (1 << 13)
#define MCI_ST_DPSM_BUSYMODE (1 << 14)
--
1.7.10
^ permalink raw reply related
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