* [PATCH] Nokia N9/N900/N950 -- mention product names
From: Pavel Machek @ 2012-10-17 18:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20120504181105.GL5613@atomide.com>
Hi!
This adds product names (that most users know) to Kconfig and board
comments.
Signed-off-by: Pavel Machek <pavel@ucw.cz>
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 346fd26..da08226 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -263,14 +263,14 @@ config MACH_NOKIA_N8X0
select MACH_NOKIA_N810_WIMAX
config MACH_NOKIA_RM680
- bool "Nokia RM-680/696 board"
+ bool "Nokia N9/N950 (RM-680/696) phones"
depends on ARCH_OMAP3
default y
select OMAP_PACKAGE_CBB
select MACH_NOKIA_RM696
config MACH_NOKIA_RX51
- bool "Nokia RX-51 board"
+ bool "Nokia N900 phone (RX-51)"
depends on ARCH_OMAP3
default y
select OMAP_PACKAGE_CBB
diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c
index 0ad1bb3b..26965f3 100644
--- a/arch/arm/mach-omap2/board-rm680.c
+++ b/arch/arm/mach-omap2/board-rm680.c
@@ -1,5 +1,5 @@
/*
- * Board support file for Nokia RM-680/696.
+ * Board support file for Nokia N9/N950 (aka RM-680/696).
*
* Copyright (C) 2010 Nokia
*
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index 345dd93..b60ca9d 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -1,5 +1,5 @@
/*
- * linux/arch/arm/mach-omap2/board-rx51.c
+ * Board support file for Nokia N900 (aka RX-51).
*
* Copyright (C) 2007, 2008 Nokia
*
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
^ permalink raw reply related
* [PATCH V2 0/7] support the cpts found on am335x devices
From: Richard Cochran @ 2012-10-17 18:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <EB1619762EAF8B4E97A227FB77B7E0293E9F86E9@DBDE01.ent.ti.com>
On Tue, Oct 16, 2012 at 11:11:29PM +0000, N, Mugunthan V wrote:
>
> Yes, I do agree that driver handles it. As Half roll over and Full roll
> over events are not handled in the driver, I am just curious how will
> the misaligned TS would be handled and also in cpts set time, the Lower
> 32 bit time is written to CPTS counter
#include <linux/clocksource.h>
> Since we poll for the 32bit over flow for every HZ * 8 cycle, won't
> there be a system overhead. If the CPTS ref clock is changed according
> to the ptp freq adjust api, how will the timecounter take care of change
> in frequency
There is nothing to do here. What are you asking?
> The current driver which is in vanilla kernel doesn't use extended slave
> address which are conflict between TI814x CPSW IP version and AM335x CPSW
> IP version. I have just posted my version of CPTS implementation. May be
> we can work together make the driver compatible with both CPSW versions
Okay.
> Since CPSW is a 3port Switch we should not fix time stamping will be enabled
> only for slave 0 or passing slave number through DT. Its better if we
> can configure both the slaves. This can be tested with EVM-sk which has
> both the slave ports pinned out.
I hope that you meant, "better if we can configure _either_ slave."
Considering how SO_TIMESTAMPING works, you can't use both at once.
Thanks,
Richard
^ permalink raw reply
* Fwd: [PATCH 5/5] arm/dts: am33xx: Add cpsw and mdio module nodes for AM33XX
From: Richard Cochran @ 2012-10-17 18:18 UTC (permalink / raw)
To: linux-arm-kernel
Benoit,
Would you please take this bugfix for 3.7-rc2? The suggestion to
mail you came from Toni Lindgren. The context where it came from
is here:
http://lists.arm.linux.org.uk/lurker/message/20121015.191630.bdae3c50.en.html
Thanks,
Richard
----- Forwarded message from Richard Cochran <richardcochran@gmail.com> -----
Date: Mon, 15 Oct 2012 21:16:35 +0200
From: Richard Cochran <richardcochran@gmail.com>
To: netdev at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org, Arnd Bergmann <arnd@arndb.de>,
David Miller <davem@davemloft.net>,
Russell King <linux@arm.linux.org.uk>,
Mugunthan V N <mugunthanvnm@ti.com>,
Vaibhav Hiremath <hvaibhav@ti.com>
Subject: [PATCH 5/5] arm/dts: am33xx: Add cpsw and mdio module nodes for AM33XX
X-Mailer: git-send-email 1.7.2.5
From: Mugunthan V N <mugunthanvnm@ti.com>
Add CPSW and MDIO related device tree data for AM33XX.
Also enable them into board/evm dts files by providing
respective phy-id.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
---
arch/arm/boot/dts/am335x-bone.dts | 8 ++++++
arch/arm/boot/dts/am335x-evm.dts | 8 ++++++
arch/arm/boot/dts/am33xx.dtsi | 50 +++++++++++++++++++++++++++++++++++++
3 files changed, 66 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts
index c634f87..e233cfa 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -78,3 +78,11 @@
};
};
};
+
+&cpsw_emac0 {
+ phy_id = "4a101000.mdio:00";
+};
+
+&cpsw_emac1 {
+ phy_id = "4a101000.mdio:01";
+};
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 185d632..415c3b3 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -118,3 +118,11 @@
};
};
};
+
+&cpsw_emac0 {
+ phy_id = "4a101000.mdio:00";
+};
+
+&cpsw_emac1 {
+ phy_id = "4a101000.mdio:01";
+};
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index bb31bff..f6bea04 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -210,5 +210,55 @@
interrupt-parent = <&intc>;
interrupts = <91>;
};
+
+ mac: ethernet at 4A100000 {
+ compatible = "ti,cpsw";
+ ti,hwmods = "cpgmac0";
+ cpdma_channels = <8>;
+ host_port_no = <0>;
+ cpdma_reg_ofs = <0x800>;
+ cpdma_sram_ofs = <0xa00>;
+ ale_reg_ofs = <0xd00>;
+ ale_entries = <1024>;
+ host_port_reg_ofs = <0x108>;
+ hw_stats_reg_ofs = <0x900>;
+ bd_ram_ofs = <0x2000>;
+ bd_ram_size = <0x2000>;
+ no_bd_ram = <0>;
+ rx_descs = <64>;
+ mac_control = <0x20>;
+ slaves = <2>;
+ reg = <0x4a100000 0x800
+ 0x4a101200 0x100
+ 0x4a101000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&intc>;
+ /* c0_rx_thresh_pend c0_rx_pend c0_tx_pend c0_misc_pend*/
+ interrupts = <40 41 42 43>;
+ ranges;
+ cpsw_emac0: slave at 0 {
+ slave_reg_ofs = <0x208>;
+ sliver_reg_ofs = <0xd80>;
+ /* Filled in by U-Boot */
+ mac-address = [ 00 00 00 00 00 00 ];
+ };
+ cpsw_emac1: slave at 1 {
+ slave_reg_ofs = <0x308>;
+ sliver_reg_ofs = <0xdc0>;
+ /* Filled in by U-Boot */
+ mac-address = [ 00 00 00 00 00 00 ];
+ };
+
+ davinci_mdio: mdio at 4a101000 {
+ compatible = "ti,davinci_mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "davinci_mdio";
+ bus_freq = <1000000>;
+ reg = <0x4a101000 0x100>;
+ };
+
+ };
};
};
--
1.7.2.5
----- End forwarded message -----
^ permalink raw reply related
* [PATCH] GPIO: vt8500: Add extended gpio bank for WM8505/WM8650
From: Tony Prisk @ 2012-10-17 18:18 UTC (permalink / raw)
To: linux-arm-kernel
These SoC's have an extended bank of GPIO's seperate to the main
GPIO block. This patch adds the additional 5 GPIO's located in this
block which control I2C and PWMOUT.
Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
---
drivers/gpio/gpio-vt8500.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpio/gpio-vt8500.c b/drivers/gpio/gpio-vt8500.c
index bcd8e4a..9ed2a2b 100644
--- a/drivers/gpio/gpio-vt8500.c
+++ b/drivers/gpio/gpio-vt8500.c
@@ -96,6 +96,7 @@ static struct vt8500_gpio_data wm8505_data = {
VT8500_BANK(0x5C, 0x84, 0xAC, 0xD4, 12),
VT8500_BANK(0x60, 0x88, 0xB0, 0xD8, 16),
VT8500_BANK(0x64, 0x8C, 0xB4, 0xDC, 22),
+ VT8500_BANK(0x500, 0x504, 0x508, 0x50C, 6),
},
};
@@ -115,6 +116,7 @@ static struct vt8500_gpio_data wm8650_data = {
VT8500_BANK(0x58, 0x98, 0xD8, 0x18, 32),
VT8500_BANK(0x5C, 0x9C, 0xDC, 0x1C, 32),
VT8500_BANK(0x7C, 0xBC, 0xFC, 0x3C, 32),
+ VT8500_BANK(0x500, 0x504, 0x508, 0x50C, 6),
},
};
--
1.7.9.5
^ permalink raw reply related
* [PATCH] Fix socfpga compilation with early_printk() enabled
From: Pavel Machek @ 2012-10-17 18:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20120701184110.GA30680@elf.ucw.cz>
Hi!
This fixes early_printk() compilation for
socfpga. (senduart/busyuart/waituart were missing). It does that by
making Picochip code generic.
Signed-off-by: Pavel Machek <pavel@denx.de>
Acked-by: Dinh Nguyen <dinguyen@altera.com>
Acked-by: Jamie Iles <jamie@jamieiles.com
diff --git a/arch/arm/include/debug/8250_32.S b/arch/arm/include/debug/8250_32.S
new file mode 100644
index 0000000..8db01ee
--- /dev/null
+++ b/arch/arm/include/debug/8250_32.S
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2011 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Derived from arch/arm/mach-davinci/include/mach/debug-macro.S to use 32-bit
+ * accesses to the 8250.
+ */
+
+#include <linux/serial_reg.h>
+
+ .macro senduart,rd,rx
+ str \rd, [\rx, #UART_TX << UART_SHIFT]
+ .endm
+
+ .macro busyuart,rd,rx
+1002: ldr \rd, [\rx, #UART_LSR << UART_SHIFT]
+ and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
+ teq \rd, #UART_LSR_TEMT | UART_LSR_THRE
+ bne 1002b
+ .endm
+
+ /* The UART's don't have any flow control IO's wired up. */
+ .macro waituart,rd,rx
+ .endm
diff --git a/arch/arm/include/debug/picoxcell.S b/arch/arm/include/debug/picoxcell.S
index 7419deb..bc1f07c 100644
--- a/arch/arm/include/debug/picoxcell.S
+++ b/arch/arm/include/debug/picoxcell.S
@@ -5,10 +5,7 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
- * Derived from arch/arm/mach-davinci/include/mach/debug-macro.S to use 32-bit
- * accesses to the 8250.
*/
-#include <linux/serial_reg.h>
#define UART_SHIFT 2
#define PICOXCELL_UART1_BASE 0x80230000
@@ -19,17 +16,4 @@
ldr \rp, =PICOXCELL_UART1_BASE
.endm
- .macro senduart,rd,rx
- str \rd, [\rx, #UART_TX << UART_SHIFT]
- .endm
-
- .macro busyuart,rd,rx
-1002: ldr \rd, [\rx, #UART_LSR << UART_SHIFT]
- and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
- teq \rd, #UART_LSR_TEMT | UART_LSR_THRE
- bne 1002b
- .endm
-
- /* The UART's don't have any flow control IO's wired up. */
- .macro waituart,rd,rx
- .endm
+#include "8250_32.S"
diff --git a/arch/arm/include/debug/socfpga.S b/arch/arm/include/debug/socfpga.S
index d6f26d2..966b2f9 100644
--- a/arch/arm/include/debug/socfpga.S
+++ b/arch/arm/include/debug/socfpga.S
@@ -7,6 +7,9 @@
* published by the Free Software Foundation.
*/
+#define UART_SHIFT 2
+#define DEBUG_LL_UART_OFFSET 0x00002000
+
.macro addruart, rp, rv, tmp
mov \rp, #DEBUG_LL_UART_OFFSET
orr \rp, \rp, #0x00c00000
@@ -14,3 +17,5 @@
orr \rp, \rp, #0xff000000 @ physical base
.endm
+#include "8250_32.S"
+
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
^ permalink raw reply related
* Fwd: [PATCH 2/5] ARM: OMAP3+: hwmod: Add AM33XX HWMOD data for davinci_mdio
From: Richard Cochran @ 2012-10-17 18:13 UTC (permalink / raw)
To: linux-arm-kernel
Paul,
Would you please take this bugfix for 3.7-rc2? The suggestion to mail
you came from Toni Lindgren. The context where it came from is here:
http://lists.arm.linux.org.uk/lurker/message/20121015.191630.bdae3c50.en.html
Thanks,
Richard
----- Forwarded message from Richard Cochran <richardcochran@gmail.com> -----
Date: Mon, 15 Oct 2012 21:16:32 +0200
From: Richard Cochran <richardcochran@gmail.com>
To: netdev at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org, Arnd Bergmann <arnd@arndb.de>,
David Miller <davem@davemloft.net>,
Russell King <linux@arm.linux.org.uk>,
Mugunthan V N <mugunthanvnm@ti.com>
Subject: [PATCH 2/5] ARM: OMAP3+: hwmod: Add AM33XX HWMOD data for davinci_mdio
X-Mailer: git-send-email 1.7.2.5
From: Mugunthan V N <mugunthanvnm@ti.com>
This patch adds minimal hwmod support for davinci mdio driver. This patch
requires rework on parent child relation between cpsw and davinci mdio
hwmod data to support runtime PM.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
---
arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 34 ++++++++++++++++++++++++++-
1 files changed, 32 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index 59d5c1c..f96bbc0 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -650,8 +650,7 @@ static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
.rev_offs = 0x0,
.sysc_offs = 0x8,
.syss_offs = 0x4,
- .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
- SYSS_HAS_RESET_STATUS),
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
MSTANDBY_NO),
.sysc_fields = &omap_hwmod_sysc_type3,
@@ -682,6 +681,8 @@ static struct omap_hwmod am33xx_cpgmac0_hwmod = {
.modulemode = MODULEMODE_SWCTRL,
},
},
+ .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
+ HWMOD_INIT_NO_RESET | HWMOD_INIT_NO_IDLE),
};
/*
@@ -2510,6 +2511,34 @@ static struct omap_hwmod_addr_space am33xx_elm_addr_space[] = {
{ }
};
+/* mdio class */
+static struct omap_hwmod_class am33xx_mdio_hwmod_class = {
+ .name = "davinci_mdio",
+};
+
+struct omap_hwmod_addr_space am33xx_mdio_addr_space[] = {
+ {
+ .pa_start = 0x4A101000,
+ .pa_end = 0x4A101000 + SZ_256 - 1,
+ .flags = ADDR_MAP_ON_INIT,
+ },
+ { }
+};
+
+static struct omap_hwmod am33xx_mdio_hwmod = {
+ .name = "davinci_mdio",
+ .class = &am33xx_mdio_hwmod_class,
+ .clkdm_name = "cpsw_125mhz_clkdm",
+ .main_clk = "cpsw_125mhz_gclk",
+};
+
+struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = {
+ .master = &am33xx_cpgmac0_hwmod,
+ .slave = &am33xx_mdio_hwmod,
+ .addr = am33xx_mdio_addr_space,
+ .user = OCP_USER_MPU,
+};
+
static struct omap_hwmod_ocp_if am33xx_l4_ls__elm = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_elm_hwmod,
@@ -3371,6 +3400,7 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
&am33xx_l3_main__tptc2,
&am33xx_l3_s__usbss,
&am33xx_l4_hs__cpgmac0,
+ &am33xx_cpgmac0__mdio,
NULL,
};
--
1.7.2.5
----- End forwarded message -----
^ permalink raw reply related
* [PATCH 1/2] ARM: OMAP: Trivial driver changes to remove include plat/cpu.h
From: Tony Lindgren @ 2012-10-17 18:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121016000722.GH15569@atomide.com>
* Tony Lindgren <tony@atomide.com> [121015 17:09]:
> * Tony Lindgren <tony@atomide.com> [121009 17:21]:
> > * P?ter Ujfalusi <peter.ujfalusi@ti.com> [121009 02:03]:
> > > On 10/08/2012 07:35 PM, Tony Lindgren wrote:
> > >
> > > > - omap-dma.c and omap-pcm.c can test the arch locally as
> > > > omap1 and omap2 cannot be compiled together because of
> > > > conflicting compiler flags
> > >
> > > > sound/soc/omap/omap-pcm.c | 9 +++++++--
> > >
> > > Tony: is this going to be included in 3.7?
> >
> > Hmm I guess we could try to get this out of the way
> > to cut down the dependencies. Let's if maintainers
> > of the other affected drivers this is OK for the
> > -rc series.
>
> It seems that nobody needs these until for v3.8, so I'll
> be applying this into omap-for-v3.8/cleanup-headers-prepare
> branch soon.
>
> Anybody else care to ack?
OK pushed out now with just that patch in the branch in case
driver branches need to merge it in too to avoid conflicts.
Regards,
Tony
^ permalink raw reply
* [PATCH V3 0/5] ARM: OMAP2+: Add device-tree support for timers
From: Jon Hunter @ 2012-10-17 18:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350496873-21337-1-git-send-email-jon-hunter@ti.com>
On 10/17/2012 01:01 PM, Jon Hunter wrote:
> This series adds device-tree support for the timers on OMAP2+ devices
> including AM33xx.
>
> Testing:
> 1. I have booted tested this series on OMAP2420 H4, OMAP3430 Beagle, OMAP4430
> Panda and AM335x Beagle Bone with/without ...
> a). device-tree present
> b). CONFIG_OMAP_32K_TIMER set
> c). kernel boot parameter "clocksource=gp_timer" present
> 2. I have tested the all the timers (not used by the kernel as sys-timers) on
> OMAP2420 H4, OMAP3430 Beagle and OMAP4430 Panda with/without device-tree with
> this series. The testing includes ...
> a. Configuring, starting a timer and checking the counter value is
> incrementing.
> b. Testing timer overflow interrupt when timer expires.
> c. Using different clock sources to operate the timer with.
>
> V3 changes:
> - Removed definition "TIMER_PROP_ALWON" per Rob Herring's feedback
> - Updated OMAP system timer (clock-events and clock-source) code so that
> HWMOD is NOT used for getting resource (memory and interrupt) information
> when device-tree is present.
>
> V2 changes:
> - Remove use of device-tree alias property
> - Migrate OMAP timers to request timers by property instead of device ID
> - Include OMAP2 support
Forgot to mention that this is based on top of v3.7-rc1.
Cheers
Jon
^ permalink raw reply
* [PATCH V3 5/5] ARM: OMAP: Add DT support for timer driver
From: Jon Hunter @ 2012-10-17 18:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350496873-21337-1-git-send-email-jon-hunter@ti.com>
In order to add device-tree support to the timer driver the following changes
were made ...
1. Allocate system timers (used for clock-events and clock-source) based upon
timer properties rather than using an hard-coded timer instance ID. To allow
this a new helper function called omap_dmtimer_find_by_property() has been
added for finding a timer with the particular properties in the device-tree
blob. Please note that this is an internal helper function for system timers
only to find a timer in the device-tree blob. This cannot be used by device
drivers, another API has been added for that (see below). Timers that are
allocated for system timers are dynamically disabled at boot time by adding
a status property with the value "disabled" to the timer's device-tree node.
Please note that when allocating system timers we now pass a timer ID and
timer property. The timer ID is only be used for allocating a timer when
booting without device-tree. Once device-tree migration is complete, all
the timer ID references will be removed.
2. System timer resources (memory and interrupts) are directly obtained from
the device-tree timer node when booting with device-tree, so that system
timers are no longer reliant upon the OMAP HWMOD framework to provide these
resources.
3. If DT blob is present, then let device-tree create the timer devices
dynamically.
4. When device-tree is present the "id" field in the platform_device structure
(pdev->id) is initialised to -1 and hence cannot be used to identify a timer
instance. Due to this the following changes were made ...
a). The API omap_dm_timer_request_specific() is not supported when using
device-tree, because it uses the device ID to request a specific timer.
This function will return an error if called when device-tree is present.
Users of this API should use omap_dm_timer_request_by_cap() instead.
b). When removing the DMTIMER driver, the timer "id" was used to identify the
timer instance. The remove function has been modified to use the device
name instead of the "id".
5. When device-tree is present the platform_data structure will be NULL and so
check for this.
6. The OMAP timer device tree binding has the following optional parameters ...
a). ti,timer-alwon --> Timer is in an always-on power domain
b). ti,timer-dsp --> Timer can generate an interrupt to the on-chip DSP
c). ti,timer-pwm --> Timer can generate a PWM output
d). ti,timer-secure --> Timer is reserved on a secure OMAP device
Search for the above parameters and set the appropriate timer attribute
flags.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
---
arch/arm/mach-omap2/timer.c | 146 ++++++++++++++++++++++++++++++++----------
arch/arm/plat-omap/dmtimer.c | 41 ++++++++++--
2 files changed, 146 insertions(+), 41 deletions(-)
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 96d26f2..d064afd 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -37,6 +37,8 @@
#include <linux/clockchips.h>
#include <linux/slab.h>
#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
#include <asm/mach/time.h>
#include <asm/smp_twd.h>
@@ -66,11 +68,13 @@
#define OMAP3_CLKEV_SOURCE OMAP3_32K_SOURCE
#define OMAP4_CLKEV_SOURCE OMAP4_32K_SOURCE
#define OMAP3_SECURE_TIMER 12
+#define TIMER_PROP_SECURE "ti,timer-secure"
#else
#define OMAP2_CLKEV_SOURCE OMAP2_MPU_SOURCE
#define OMAP3_CLKEV_SOURCE OMAP3_MPU_SOURCE
#define OMAP4_CLKEV_SOURCE OMAP4_MPU_SOURCE
#define OMAP3_SECURE_TIMER 1
+#define TIMER_PROP_SECURE "ti,timer-alwon"
#endif
#define REALTIME_COUNTER_BASE 0x48243200
@@ -156,6 +160,40 @@ static struct of_device_id omap_timer_match[] __initdata = {
};
/**
+ * omap_get_timer_dt - get a timer using device-tree
+ * @match - device-tree match structure for matching a device type
+ * @property - optional timer property to match
+ *
+ * Helper function to get a timer during early boot using device-tree for use
+ * as kernel system timer. Optionally, the property argument can be used to
+ * select a timer with a specific property. Once a timer is found then mark
+ * the timer node in device-tree as disabled, to prevent the kernel from
+ * registering this timer as a platform device and so no one else can use it.
+ */
+static struct device_node * __init omap_get_timer_dt(struct of_device_id *match,
+ const char *property)
+{
+ struct device_node *np;
+
+ for_each_matching_node(np, match) {
+ if (!of_device_is_available(np)) {
+ of_node_put(np);
+ continue;
+ }
+
+ if (property && !of_get_property(np, property, NULL)) {
+ of_node_put(np);
+ continue;
+ }
+
+ prom_add_property(np, &device_disabled);
+ return np;
+ }
+
+ return NULL;
+}
+
+/**
* omap_dmtimer_init - initialisation function when device tree is used
*
* For secure OMAP3 devices, timers with device type "timer-secure" cannot
@@ -172,43 +210,71 @@ void __init omap_dmtimer_init(void)
/* If we are a secure device, remove any secure timer nodes */
if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) {
- for_each_matching_node(np, omap_timer_match) {
- if (of_get_property(np, "ti,timer-secure", NULL))
- prom_add_property(np, &device_disabled);
- }
+ np = omap_get_timer_dt(omap_timer_match, "ti,timer-secure");
+ if (np)
+ of_node_put(np);
}
}
static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
int gptimer_id,
- const char *fck_source)
+ const char *fck_source,
+ const char *property)
{
char name[10]; /* 10 = sizeof("gptXX_Xck0") */
+ const char *oh_name;
+ struct device_node *np;
struct omap_hwmod *oh;
struct resource irq_rsrc, mem_rsrc;
size_t size;
int res = 0;
int r;
- sprintf(name, "timer%d", gptimer_id);
- omap_hwmod_setup_one(name);
- oh = omap_hwmod_lookup(name);
+ if (of_have_populated_dt()) {
+ np = omap_get_timer_dt(omap_timer_match, NULL);
+ if (!np)
+ return -ENODEV;
+
+ of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
+ if (!oh_name)
+ return -ENODEV;
+
+ timer->irq = irq_of_parse_and_map(np, 0);
+ if (!timer->irq)
+ return -ENXIO;
+
+ timer->io_base = of_iomap(np, 0);
+
+ of_node_put(np);
+ } else {
+ sprintf(name, "timer%d", gptimer_id);
+ oh_name = name;
+ }
+
+ omap_hwmod_setup_one(oh_name);
+ oh = omap_hwmod_lookup(oh_name);
+
if (!oh)
return -ENODEV;
- r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL, &irq_rsrc);
- if (r)
- return -ENXIO;
- timer->irq = irq_rsrc.start;
-
- r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL, &mem_rsrc);
- if (r)
- return -ENXIO;
- timer->phys_base = mem_rsrc.start;
- size = mem_rsrc.end - mem_rsrc.start;
+ if (!of_have_populated_dt()) {
+ r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL,
+ &irq_rsrc);
+ if (r)
+ return -ENXIO;
+ timer->irq = irq_rsrc.start;
+
+ r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL,
+ &mem_rsrc);
+ if (r)
+ return -ENXIO;
+ timer->phys_base = mem_rsrc.start;
+ size = mem_rsrc.end - mem_rsrc.start;
+
+ /* Static mapping, never released */
+ timer->io_base = ioremap(timer->phys_base, size);
+ }
- /* Static mapping, never released */
- timer->io_base = ioremap(timer->phys_base, size);
if (!timer->io_base)
return -ENXIO;
@@ -219,9 +285,11 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
omap_hwmod_enable(oh);
- if (omap_dm_timer_reserve_systimer(gptimer_id))
- return -ENODEV;
+ if (!of_have_populated_dt())
+ if (omap_dm_timer_reserve_systimer(gptimer_id))
+ return -ENODEV;
+ /* FIXME: Need to remove hard-coded test on timer ID */
if (gptimer_id != 12) {
struct clk *src;
@@ -231,8 +299,8 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
} else {
res = __omap_dm_timer_set_source(timer->fclk, src);
if (IS_ERR_VALUE(res))
- pr_warning("%s: timer%i cannot set source\n",
- __func__, gptimer_id);
+ pr_warn("%s: %s cannot set source\n",
+ __func__, oh->name);
clk_put(src);
}
}
@@ -248,11 +316,12 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
}
static void __init omap2_gp_clockevent_init(int gptimer_id,
- const char *fck_source)
+ const char *fck_source,
+ const char *property)
{
int res;
- res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source);
+ res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source, property);
BUG_ON(res);
omap2_gp_timer_irq.dev_id = &clkev;
@@ -356,7 +425,7 @@ static void __init omap2_gptimer_clocksource_init(int gptimer_id,
{
int res;
- res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source);
+ res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source, NULL);
BUG_ON(res);
__omap_dm_timer_load_start(&clksrc,
@@ -468,12 +537,12 @@ static inline void __init realtime_counter_init(void)
{}
#endif
-#define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src, \
+#define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop, \
clksrc_nr, clksrc_src) \
static void __init omap##name##_timer_init(void) \
{ \
omap_dmtimer_init(); \
- omap2_gp_clockevent_init((clkev_nr), clkev_src); \
+ omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \
omap2_clocksource_init((clksrc_nr), clksrc_src); \
}
@@ -483,20 +552,23 @@ struct sys_timer omap##name##_timer = { \
};
#ifdef CONFIG_ARCH_OMAP2
-OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, 2, OMAP2_MPU_SOURCE)
+OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, "ti,timer-alwon",
+ 2, OMAP2_MPU_SOURCE)
OMAP_SYS_TIMER(2)
#endif
#ifdef CONFIG_ARCH_OMAP3
-OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, 2, OMAP3_MPU_SOURCE)
+OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, "ti,timer-alwon",
+ 2, OMAP3_MPU_SOURCE)
OMAP_SYS_TIMER(3)
OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE,
- 2, OMAP3_MPU_SOURCE)
+ TIMER_PROP_SECURE, 2, OMAP3_MPU_SOURCE)
OMAP_SYS_TIMER(3_secure)
#endif
#ifdef CONFIG_SOC_AM33XX
-OMAP_SYS_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, 2, OMAP4_MPU_SOURCE)
+OMAP_SYS_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, "ti,timer-alwon",
+ 2, OMAP4_MPU_SOURCE)
OMAP_SYS_TIMER(3_am33xx)
#endif
@@ -508,7 +580,7 @@ static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
static void __init omap4_timer_init(void)
{
- omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
+ omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE, "ti,timer-alwon");
omap2_clocksource_init(2, OMAP4_MPU_SOURCE);
#ifdef CONFIG_LOCAL_TIMERS
/* Local timers are not supprted on OMAP4430 ES1.0 */
@@ -534,7 +606,7 @@ static void __init omap5_timer_init(void)
{
int err;
- omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
+ omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE, "ti,timer-alwon");
omap2_clocksource_init(2, OMAP4_MPU_SOURCE);
realtime_counter_init();
@@ -619,6 +691,10 @@ static int __init omap2_dm_timer_init(void)
{
int ret;
+ /* If dtb is there, the devices will be created dynamically */
+ if (of_have_populated_dt())
+ return -ENODEV;
+
ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL);
if (unlikely(ret)) {
pr_err("%s: device registration failed.\n", __func__);
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 2574b86..b09e556 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -40,6 +40,8 @@
#include <linux/device.h>
#include <linux/err.h>
#include <linux/pm_runtime.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
#include <plat/dmtimer.h>
#include <plat/omap-pm.h>
@@ -212,6 +214,13 @@ struct omap_dm_timer *omap_dm_timer_request_specific(int id)
unsigned long flags;
int ret = 0;
+ /* Requesting timer by ID is not supported when device tree is used */
+ if (of_have_populated_dt()) {
+ pr_warn("%s: Please use omap_dm_timer_request_by_cap()\n",
+ __func__);
+ return NULL;
+ }
+
spin_lock_irqsave(&dm_timer_lock, flags);
list_for_each_entry(t, &omap_timer_list, node) {
if (t->pdev->id == id && !t->reserved) {
@@ -466,7 +475,7 @@ int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
* use the clock framework to set the parent clock. To be removed
* once OMAP1 migrated to using clock framework for dmtimers
*/
- if (pdata->set_timer_src)
+ if (pdata && pdata->set_timer_src)
return pdata->set_timer_src(timer->pdev, source);
fclk = clk_get(&timer->pdev->dev, "fck");
@@ -747,7 +756,7 @@ static int __devinit omap_dm_timer_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct dmtimer_platform_data *pdata = pdev->dev.platform_data;
- if (!pdata) {
+ if (!pdata && !dev->of_node) {
dev_err(dev, "%s: no platform data.\n", __func__);
return -ENODEV;
}
@@ -776,11 +785,23 @@ static int __devinit omap_dm_timer_probe(struct platform_device *pdev)
return -ENOMEM;
}
- timer->id = pdev->id;
+ if (dev->of_node) {
+ if (of_find_property(dev->of_node, "ti,timer-alwon", NULL))
+ timer->capability |= OMAP_TIMER_ALWON;
+ if (of_find_property(dev->of_node, "ti,timer-dsp", NULL))
+ timer->capability |= OMAP_TIMER_HAS_DSP_IRQ;
+ if (of_find_property(dev->of_node, "ti,timer-pwm", NULL))
+ timer->capability |= OMAP_TIMER_HAS_PWM;
+ if (of_find_property(dev->of_node, "ti,timer-secure", NULL))
+ timer->capability |= OMAP_TIMER_SECURE;
+ } else {
+ timer->id = pdev->id;
+ timer->capability = pdata->timer_capability;
+ timer->reserved = omap_dm_timer_reserved_systimer(timer->id);
+ }
+
timer->irq = irq->start;
- timer->reserved = omap_dm_timer_reserved_systimer(timer->id);
timer->pdev = pdev;
- timer->capability = pdata->timer_capability;
/* Skip pm_runtime_enable for OMAP1 */
if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) {
@@ -820,7 +841,8 @@ static int __devexit omap_dm_timer_remove(struct platform_device *pdev)
spin_lock_irqsave(&dm_timer_lock, flags);
list_for_each_entry(timer, &omap_timer_list, node)
- if (timer->pdev->id == pdev->id) {
+ if (!strcmp(dev_name(&timer->pdev->dev),
+ dev_name(&pdev->dev))) {
list_del(&timer->node);
ret = 0;
break;
@@ -830,11 +852,18 @@ static int __devexit omap_dm_timer_remove(struct platform_device *pdev)
return ret;
}
+static const struct of_device_id omap_timer_match[] = {
+ { .compatible = "ti,omap2-timer", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, omap_timer_match);
+
static struct platform_driver omap_dm_timer_driver = {
.probe = omap_dm_timer_probe,
.remove = __devexit_p(omap_dm_timer_remove),
.driver = {
.name = "omap_timer",
+ .of_match_table = of_match_ptr(omap_timer_match),
},
};
--
1.7.9.5
^ permalink raw reply related
* [PATCH V3 4/5] ARM: OMAP3: Add generic machine descriptor for boards with OMAP3 GP devices
From: Jon Hunter @ 2012-10-17 18:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350496873-21337-1-git-send-email-jon-hunter@ti.com>
OMAP3 devices may or may not have security features enabled. Security enabled
devices are known as high-secure (HS) and devices without security are known as
general purpose (GP).
Some OMAP3 boards, such as the OMAP3 beagle board, only use GP devices and for
GP devices there is a 12th timer available on-chip that can operate at 32kHz.
The clock for 12th timer is generated by an internal oscillator and is unique
this timer. Boards such as the beagle board use this timer as a 32kHz based
clock-events timer because early versions of the board had a hardware problem
preventing them from using other on-chip timers clocked by a external 32kHz
clock.
When booting with device-tree all OMAP3 devices use timer 1 by default for
the clock-events timer. Therefore, add a generic machine descriptor for boards
with OMAP3 GP devices so that they can use the 12th timer as the clock-events
timer instead of the default.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
---
arch/arm/mach-omap2/board-generic.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 601ecdf..d690180 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -97,6 +97,23 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
.dt_compat = omap3_boards_compat,
.restart = omap_prcm_restart,
MACHINE_END
+
+static const char *omap3_gp_boards_compat[] __initdata = {
+ "ti,omap3-beagle",
+ NULL,
+};
+
+DT_MACHINE_START(OMAP3_GP_DT, "Generic OMAP3-GP (Flattened Device Tree)")
+ .reserve = omap_reserve,
+ .map_io = omap3_map_io,
+ .init_early = omap3430_init_early,
+ .init_irq = omap_intc_of_init,
+ .handle_irq = omap3_intc_handle_irq,
+ .init_machine = omap_generic_init,
+ .timer = &omap3_secure_timer,
+ .dt_compat = omap3_gp_boards_compat,
+ .restart = omap_prcm_restart,
+MACHINE_END
#endif
#ifdef CONFIG_SOC_AM33XX
--
1.7.9.5
^ permalink raw reply related
* [PATCH V3 3/5] ARM: OMAP: Add function to request a timer by capability
From: Jon Hunter @ 2012-10-17 18:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350496873-21337-1-git-send-email-jon-hunter@ti.com>
Currently OMAP timers can be requested by requesting any available or by a
numerical device ID. If a specific timer is required because it has a particular
capability, such as can interrupt the on-chip DSP in addition to the ARM CPU,
then the user needs to know the device ID of the timer with this feature.
Therefore, add a new API called omap_dm_timer_request_by_cap() that allows
drivers to request a timer by capability.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
---
arch/arm/plat-omap/dmtimer.c | 52 +++++++++++++++++++++++++++++
arch/arm/plat-omap/include/plat/dmtimer.h | 1 +
2 files changed, 53 insertions(+)
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 938b50a..2574b86 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -237,6 +237,58 @@ struct omap_dm_timer *omap_dm_timer_request_specific(int id)
}
EXPORT_SYMBOL_GPL(omap_dm_timer_request_specific);
+/**
+ * omap_dm_timer_request_by_cap - Request a timer by capability
+ * @cap: Bit mask of capabilities to match
+ *
+ * Find a timer based upon capabilities bit mask. Callers of this function
+ * should use the definitions found in the plat/dmtimer.h file under the
+ * comment "timer capabilities used in hwmod database". Returns pointer to
+ * timer handle on success and a NULL pointer on failure.
+ */
+struct omap_dm_timer *omap_dm_timer_request_by_cap(u32 cap)
+{
+ struct omap_dm_timer *timer = NULL, *t;
+ unsigned long flags;
+
+ if (!cap)
+ return NULL;
+
+ spin_lock_irqsave(&dm_timer_lock, flags);
+ list_for_each_entry(t, &omap_timer_list, node) {
+ if ((!t->reserved) && ((t->capability & cap) == cap)) {
+ /*
+ * If timer is not NULL, we have already found one timer
+ * but it was not an exact match because it had more
+ * capabilites that what was required. Therefore,
+ * unreserve the last timer found and see if this one
+ * is a better match.
+ */
+ if (timer)
+ timer->reserved = 0;
+
+ timer = t;
+ timer->reserved = 1;
+
+ /* Exit loop early if we find an exact match */
+ if (t->capability == cap)
+ break;
+ }
+ }
+ spin_unlock_irqrestore(&dm_timer_lock, flags);
+
+ if (timer && omap_dm_timer_prepare(timer)) {
+ timer->reserved = 0;
+ timer = NULL;
+ }
+
+ if (!timer)
+ pr_debug("%s: timer request failed!\n", __func__);
+
+ return timer;
+}
+EXPORT_SYMBOL_GPL(omap_dm_timer_request_by_cap);
+
int omap_dm_timer_free(struct omap_dm_timer *timer)
{
if (unlikely(!timer))
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index 85868e9..348f855 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -99,6 +99,7 @@ struct dmtimer_platform_data {
int omap_dm_timer_reserve_systimer(int id);
struct omap_dm_timer *omap_dm_timer_request(void);
struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id);
+struct omap_dm_timer *omap_dm_timer_request_by_cap(u32 cap);
int omap_dm_timer_free(struct omap_dm_timer *timer);
void omap_dm_timer_enable(struct omap_dm_timer *timer);
void omap_dm_timer_disable(struct omap_dm_timer *timer);
--
1.7.9.5
^ permalink raw reply related
* [PATCH V3 2/5] ARM: OMAP3: Dynamically disable secure timer nodes for secure devices
From: Jon Hunter @ 2012-10-17 18:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350496873-21337-1-git-send-email-jon-hunter@ti.com>
OMAP3 devices may or may not have security features enabled. Security enabled
devices are known as high-secure (HS) and devices without security are known as
general purpose (GP).
For OMAP3 devices there are 12 general purpose timers available. On secure
devices the 12th timer is reserved for secure usage and so cannot be used by
the kernel, where as for a GP device it is available. We can detect the OMAP
device type, secure or GP, at runtime via an on-chip register. Today, when not
using DT, we do not register the 12th timer as a linux device if the device is
secure.
When using device tree, device tree is going to register all the timer devices
it finds in the device tree blob. To prevent device tree from registering 12th
timer on a secure OMAP3 device we can add a status property to the timer
binding with the value "disabled" at boot time. Note that timer 12 on a OMAP3
device has a property "ti,timer-secure" to indicate that it will not be
available on a secure device and so for secure OMAP3 devices, we search for
timers with this property and then disable them. Using the prom_add_property()
function to dynamically add a property was a recommended approach suggested by
Rob Herring [1].
I have tested this on an OMAP3 GP device and faking it to pretend to be a
secure device to ensure that any timers marked with "ti,timer-secure" are not
registered on boot. I have also made sure that all timers are registered as
expected on a GP device by default.
[1] http://comments.gmane.org/gmane.linux.ports.arm.omap/79203
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
---
arch/arm/mach-omap2/timer.c | 36 ++++++++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 44f9aa7..96d26f2 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -144,6 +144,41 @@ static struct clock_event_device clockevent_gpt = {
.set_mode = omap2_gp_timer_set_mode,
};
+static struct property device_disabled = {
+ .name = "status",
+ .length = sizeof("disabled"),
+ .value = "disabled",
+};
+
+static struct of_device_id omap_timer_match[] __initdata = {
+ { .compatible = "ti,omap2-timer", },
+ { }
+};
+
+/**
+ * omap_dmtimer_init - initialisation function when device tree is used
+ *
+ * For secure OMAP3 devices, timers with device type "timer-secure" cannot
+ * be used by the kernel as they are reserved. Therefore, to prevent the
+ * kernel registering these devices remove them dynamically from the device
+ * tree on boot.
+ */
+void __init omap_dmtimer_init(void)
+{
+ struct device_node *np;
+
+ if (!cpu_is_omap34xx())
+ return;
+
+ /* If we are a secure device, remove any secure timer nodes */
+ if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) {
+ for_each_matching_node(np, omap_timer_match) {
+ if (of_get_property(np, "ti,timer-secure", NULL))
+ prom_add_property(np, &device_disabled);
+ }
+ }
+}
+
static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
int gptimer_id,
const char *fck_source)
@@ -437,6 +472,7 @@ static inline void __init realtime_counter_init(void)
clksrc_nr, clksrc_src) \
static void __init omap##name##_timer_init(void) \
{ \
+ omap_dmtimer_init(); \
omap2_gp_clockevent_init((clkev_nr), clkev_src); \
omap2_clocksource_init((clksrc_nr), clksrc_src); \
}
--
1.7.9.5
^ permalink raw reply related
* [PATCH V3 1/5] ARM: dts: OMAP: Add timer nodes
From: Jon Hunter @ 2012-10-17 18:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350496873-21337-1-git-send-email-jon-hunter@ti.com>
Add the 12 GP timers nodes present in OMAP2.
Add the 12 GP timers nodes present in OMAP3.
Add the 11 GP timers nodes present in OMAP4.
Add the 7 GP timers nodes present in AM33xx.
Add documentation for timer properties specific to OMAP.
Please note that for OMAP2/3 devices, there is only one interrupt controller
for the ARM CPU (which has the label "intc") and so globally define this as the
interrupt parent to save duplicating the interrupt parent for all device nodes.
Thanks to Vaibhav Hiremath for creating the AM33xx timer nodes. I have modified
Vaibhav's original nodes adding information on which timers support a PWM
output.
Cc: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
---
.../devicetree/bindings/arm/omap/timer.txt | 29 ++++++
arch/arm/boot/dts/am33xx.dtsi | 61 +++++++++++++
arch/arm/boot/dts/omap2.dtsi | 86 ++++++++++++++++++
arch/arm/boot/dts/omap2420.dtsi | 8 ++
arch/arm/boot/dts/omap2430.dtsi | 8 ++
arch/arm/boot/dts/omap3.dtsi | 96 ++++++++++++++++++++
arch/arm/boot/dts/omap4.dtsi | 86 ++++++++++++++++++
7 files changed, 374 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/omap/timer.txt
diff --git a/Documentation/devicetree/bindings/arm/omap/timer.txt b/Documentation/devicetree/bindings/arm/omap/timer.txt
new file mode 100644
index 0000000..d9449d0
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/omap/timer.txt
@@ -0,0 +1,29 @@
+OMAP Timer bindings
+
+Required properties:
+- compatible: Must be "ti,omap2-timer" for OMAP2+ controllers
+- reg: Contains timer register address range (base address and length)
+- interrupts: Contains the interrupt information for the timer. The format is
+ being dependent on which interrupt controller the OMAP device
+ uses.
+- ti,hwmods: Name of the hwmod associated to the timer, "timer<X>", where
+ <X> is the instance number of the timer from the HW spec.
+
+Optional properties:
+- ti,timer-alwon: Indicates the timer is in an alway-on power domain.
+- ti,timer-dsp: Indicates the timer can interrupt the on-chip DSP in
+ addition to the ARM CPU.
+- ti,timer-pwm: Indicates the timer can generate a PWM output.
+- ti,timer-secure: Indicates the timer is reserved on a secure OMAP device
+ and therefore cannot be used by the kernel.
+
+Example:
+
+timer12: timer at 48304000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x48304000 0xfff>;
+ interrupts = <95>;
+ ti,hwmods = "timer12"
+ ti,timer-alwon;
+ ti,timer-secure;
+};
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index bb31bff..fd5074c 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -210,5 +210,66 @@
interrupt-parent = <&intc>;
interrupts = <91>;
};
+
+ timer1: timer at 44e31000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x44e31000 0x1000>;
+ interrupt-parent = <&intc>;
+ interrupts = <67>;
+ ti,hwmods = "timer1";
+ ti,timer-alwon;
+ };
+
+ timer2: timer at 48040000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x48040000 0x1000>;
+ interrupt-parent = <&intc>;
+ interrupts = <68>;
+ ti,hwmods = "timer2";
+ };
+
+ timer3: timer at 48042000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x48042000 0x1000>;
+ interrupt-parent = <&intc>;
+ interrupts = <69>;
+ ti,hwmods = "timer3";
+ };
+
+ timer4: timer at 48044000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x48044000 0x1000>;
+ interrupt-parent = <&intc>;
+ interrupts = <92>;
+ ti,hwmods = "timer4";
+ ti,timer-pwm;
+ };
+
+ timer5: timer at 48046000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x48046000 0x1000>;
+ interrupt-parent = <&intc>;
+ interrupts = <93>;
+ ti,hwmods = "timer5";
+ ti,timer-pwm;
+ };
+
+ timer6: timer at 48048000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x48048000 0x1000>;
+ interrupt-parent = <&intc>;
+ interrupts = <94>;
+ ti,hwmods = "timer6";
+ ti,timer-pwm;
+ };
+
+ timer7: timer at 4804a000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x4804a000 0x1000>;
+ interrupt-parent = <&intc>;
+ interrupts = <95>;
+ ti,hwmods = "timer7";
+ ti,timer-pwm;
+ };
};
};
diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi
index 581cb08..731de55 100644
--- a/arch/arm/boot/dts/omap2.dtsi
+++ b/arch/arm/boot/dts/omap2.dtsi
@@ -12,6 +12,7 @@
/ {
compatible = "ti,omap2430", "ti,omap2420", "ti,omap2";
+ interrupt-parent = <&intc>;
aliases {
serial0 = &uart1;
@@ -65,5 +66,90 @@
ti,hwmods = "uart3";
clock-frequency = <48000000>;
};
+
+ timer2: timer at 4802a000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x4802a000 0xfff>;
+ interrupts = <38>;
+ ti,hwmods = "timer2";
+ };
+
+ timer3: timer at 48078000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x48078000 0xfff>;
+ interrupts = <39>;
+ ti,hwmods = "timer3";
+ };
+
+ timer4: timer at 4807a000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x4807a000 0xfff>;
+ interrupts = <40>;
+ ti,hwmods = "timer4";
+ };
+
+ timer5: timer at 4807c000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x4807c000 0xfff>;
+ interrupts = <41>;
+ ti,hwmods = "timer5";
+ ti,timer-dsp;
+ };
+
+ timer6: timer at 4807e000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x4807e000 0xfff>;
+ interrupts = <42>;
+ ti,hwmods = "timer6";
+ ti,timer-dsp;
+ };
+
+ timer7: timer at 48080000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x48080000 0xfff>;
+ interrupts = <43>;
+ ti,hwmods = "timer7";
+ ti,timer-dsp;
+ };
+
+ timer8: timer at 48082000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x48082000 0xfff>;
+ interrupts = <44>;
+ ti,hwmods = "timer8";
+ ti,timer-dsp;
+ };
+
+ timer9: timer at 48084000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x48084000 0xfff>;
+ interrupts = <45>;
+ ti,hwmods = "timer9";
+ ti,timer-pwm;
+ };
+
+ timer10: timer at 48086000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x48086000 0xfff>;
+ interrupts = <46>;
+ ti,hwmods = "timer10";
+ ti,timer-pwm;
+ };
+
+ timer11: timer at 48088000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x48088000 0xfff>;
+ interrupts = <47>;
+ ti,hwmods = "timer11";
+ ti,timer-pwm;
+ };
+
+ timer12: timer at 4808a000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x4808a000 0xfff>;
+ interrupts = <48>;
+ ti,hwmods = "timer12";
+ ti,timer-pwm;
+ };
};
};
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi
index bfd76b4..5f68a70 100644
--- a/arch/arm/boot/dts/omap2420.dtsi
+++ b/arch/arm/boot/dts/omap2420.dtsi
@@ -44,5 +44,13 @@
interrupt-parent = <&intc>;
ti,hwmods = "mcbsp2";
};
+
+ timer1: timer at 48028000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x48028000 0xfff>;
+ interrupts = <37>;
+ ti,hwmods = "timer1";
+ ti,timer-alwon;
+ };
};
};
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
index 4565d97..7439987 100644
--- a/arch/arm/boot/dts/omap2430.dtsi
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -88,5 +88,13 @@
ti,buffer-size = <128>;
ti,hwmods = "mcbsp5";
};
+
+ timer1: timer at 49018000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x49018000 0xfff>;
+ interrupts = <37>;
+ ti,hwmods = "timer1";
+ ti,timer-alwon;
+ };
};
};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index f38ea87..3fb910f 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -12,6 +12,7 @@
/ {
compatible = "ti,omap3430", "ti,omap3";
+ interrupt-parent = <&intc>;
aliases {
serial0 = &uart1;
@@ -300,5 +301,100 @@
ti,buffer-size = <128>;
ti,hwmods = "mcbsp5";
};
+
+ timer1: timer at 48318000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x48318000 0xfff>;
+ interrupts = <37>;
+ ti,hwmods = "timer1";
+ ti,timer-alwon;
+ };
+
+ timer2: timer at 49032000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x49032000 0xfff>;
+ interrupts = <38>;
+ ti,hwmods = "timer2";
+ };
+
+ timer3: timer at 49034000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x49034000 0xfff>;
+ interrupts = <39>;
+ ti,hwmods = "timer3";
+ };
+
+ timer4: timer at 49036000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x49036000 0xfff>;
+ interrupts = <40>;
+ ti,hwmods = "timer4";
+ };
+
+ timer5: timer at 49038000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x49038000 0xfff>;
+ interrupts = <41>;
+ ti,hwmods = "timer5";
+ ti,timer-dsp;
+ };
+
+ timer6: timer at 4903a000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x4903a000 0xfff>;
+ interrupts = <42>;
+ ti,hwmods = "timer6";
+ ti,timer-dsp;
+ };
+
+ timer7: timer at 4903c000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x4903c000 0xfff>;
+ interrupts = <43>;
+ ti,hwmods = "timer7";
+ ti,timer-dsp;
+ };
+
+ timer8: timer at 4903e000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x4903e000 0xfff>;
+ interrupts = <44>;
+ ti,hwmods = "timer8";
+ ti,timer-pwm;
+ ti,timer-dsp;
+ };
+
+ timer9: timer at 49040000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x49040000 0xfff>;
+ interrupts = <45>;
+ ti,hwmods = "timer9";
+ ti,timer-pwm;
+ };
+
+ timer10: timer at 48086000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x48086000 0xfff>;
+ interrupts = <46>;
+ ti,hwmods = "timer10";
+ ti,timer-pwm;
+ };
+
+ timer11: timer at 48088000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x48088000 0xfff>;
+ interrupts = <47>;
+ ti,hwmods = "timer11";
+ ti,timer-pwm;
+ };
+
+ timer12: timer at 48304000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x48304000 0xfff>;
+ interrupts = <95>;
+ ti,hwmods = "timer12";
+ ti,timer-alwon;
+ ti,timer-secure;
+ };
};
};
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 3883f94..f6ac2b7 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -438,5 +438,91 @@
ranges;
ti,hwmods = "ocp2scp_usb_phy";
};
+
+ timer1: timer at 4a318000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x4a318000 0x7f>;
+ interrupts = <0 37 0x4>;
+ ti,hwmods = "timer1";
+ ti,timer-alwon;
+ };
+
+ timer2: timer at 48032000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x48032000 0x7f>;
+ interrupts = <0 38 0x4>;
+ ti,hwmods = "timer2";
+ };
+
+ timer3: timer at 48034000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x48034000 0x7f>;
+ interrupts = <0 39 0x4>;
+ ti,hwmods = "timer3";
+ };
+
+ timer4: timer at 48036000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x48036000 0x7f>;
+ interrupts = <0 40 0x4>;
+ ti,hwmods = "timer4";
+ };
+
+ timer5: timer at 49038000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x49038000 0x7f>;
+ interrupts = <0 41 0x4>;
+ ti,hwmods = "timer5";
+ ti,timer-dsp;
+ };
+
+ timer6: timer at 4903a000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x4903a000 0x7f>;
+ interrupts = <0 42 0x4>;
+ ti,hwmods = "timer6";
+ ti,timer-dsp;
+ };
+
+ timer7: timer at 4903c000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x4903c000 0x7f>;
+ interrupts = <0 43 0x4>;
+ ti,hwmods = "timer7";
+ ti,timer-dsp;
+ };
+
+ timer8: timer at 4903e000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x4903e000 0x7f>;
+ interrupts = <0 44 0x4>;
+ ti,hwmods = "timer8";
+ ti,timer-pwm;
+ ti,timer-dsp;
+ };
+
+ timer9: timer at 4803e000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x4803e000 0x7f>;
+ interrupts = <0 45 0x4>;
+ ti,hwmods = "timer9";
+ ti,timer-pwm;
+ };
+
+ timer10: timer at 48086000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x48086000 0x7f>;
+ interrupts = <0 46 0x4>;
+ ti,hwmods = "timer10";
+ ti,timer-pwm;
+ };
+
+ timer11: timer at 48088000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x48088000 0x7f>;
+ interrupts = <0 47 0x4>;
+ ti,hwmods = "timer11";
+ ti,timer-pwm;
+ };
};
};
--
1.7.9.5
^ permalink raw reply related
* [PATCH V3 0/5] ARM: OMAP2+: Add device-tree support for timers
From: Jon Hunter @ 2012-10-17 18:01 UTC (permalink / raw)
To: linux-arm-kernel
This series adds device-tree support for the timers on OMAP2+ devices
including AM33xx.
Testing:
1. I have booted tested this series on OMAP2420 H4, OMAP3430 Beagle, OMAP4430
Panda and AM335x Beagle Bone with/without ...
a). device-tree present
b). CONFIG_OMAP_32K_TIMER set
c). kernel boot parameter "clocksource=gp_timer" present
2. I have tested the all the timers (not used by the kernel as sys-timers) on
OMAP2420 H4, OMAP3430 Beagle and OMAP4430 Panda with/without device-tree with
this series. The testing includes ...
a. Configuring, starting a timer and checking the counter value is
incrementing.
b. Testing timer overflow interrupt when timer expires.
c. Using different clock sources to operate the timer with.
V3 changes:
- Removed definition "TIMER_PROP_ALWON" per Rob Herring's feedback
- Updated OMAP system timer (clock-events and clock-source) code so that
HWMOD is NOT used for getting resource (memory and interrupt) information
when device-tree is present.
V2 changes:
- Remove use of device-tree alias property
- Migrate OMAP timers to request timers by property instead of device ID
- Include OMAP2 support
Jon Hunter (5):
ARM: dts: OMAP: Add timer nodes
ARM: OMAP3: Dynamically disable secure timer nodes for secure devices
ARM: OMAP: Add function to request a timer by capability
ARM: OMAP3: Add generic machine descriptor for boards with OMAP3 GP
devices
ARM: OMAP: Add DT support for timer driver
.../devicetree/bindings/arm/omap/timer.txt | 29 ++++
arch/arm/boot/dts/am33xx.dtsi | 61 +++++++
arch/arm/boot/dts/omap2.dtsi | 86 ++++++++++
arch/arm/boot/dts/omap2420.dtsi | 8 +
arch/arm/boot/dts/omap2430.dtsi | 8 +
arch/arm/boot/dts/omap3.dtsi | 96 +++++++++++
arch/arm/boot/dts/omap4.dtsi | 86 ++++++++++
arch/arm/mach-omap2/board-generic.c | 17 ++
arch/arm/mach-omap2/timer.c | 174 ++++++++++++++++----
arch/arm/plat-omap/dmtimer.c | 93 ++++++++++-
arch/arm/plat-omap/include/plat/dmtimer.h | 1 +
11 files changed, 622 insertions(+), 37 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/omap/timer.txt
--
1.7.9.5
^ permalink raw reply
* [PATCH 9/9] ARM: add uprobes support
From: Oleg Nesterov @ 2012-10-17 17:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350242593-17761-9-git-send-email-rabin@rab.in>
On 10/14, Rabin Vincent wrote:
>
> @@ -655,6 +656,9 @@ do_work_pending(struct pt_regs *regs, unsigned int thread_flags, int syscall)
> return restart;
> }
> syscall = 0;
> + } else if (thread_flags & _TIF_UPROBE) {
> + clear_thread_flag(TIF_UPROBE);
> + uprobe_notify_resume(regs);
> } else {
> clear_thread_flag(TIF_NOTIFY_RESUME);
> tracehook_notify_resume(regs);
This doesn't look right. do_signal() can modify instruction pointer
after we hit the breakpoint. IOW, uprobe_notify_resume() should be
called before do_signal().
Oleg.
^ permalink raw reply
* [RFC PATCH] ARM: SMP: consolidate holding pen
From: Russell King - ARM Linux @ 2012-10-17 17:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350487967-2555-1-git-send-email-marc.zyngier@arm.com>
On Wed, Oct 17, 2012 at 04:32:47PM +0100, Marc Zyngier wrote:
> As with other bits of the SMP code, platforms have duplicated a lot
> of the RealView implementation. As an effort to slightly reduce
> the clutter, make the plat-versatile version of the holding pen
> a standard part of the SMP framework.
>
> Platforms can still provide their own, but those who carried an exact
> duplicate of the Realview code are switched to the common implementation.
My position on this hasn't changed.
^ permalink raw reply
* [PATCH] ARM: OMAP: move plat-omap/include/plat/sdrc.h into mach-omap2/sdrc.h
From: Tony Lindgren @ 2012-10-17 17:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.DEB.2.00.1210170038200.9767@utopia.booyaka.com>
* Paul Walmsley <paul@pwsan.com> [121016 17:48]:
>
> Remove arch/arm/plat-omap/include/plat/sdrc.h by folding its contents
> into arch/arm/mach-omap2/sdrc.h. The objective is to assist Tony in
> cleaning out arch/arm/plat-omap/, as his upstreams request.
>
> Signed-off-by: Paul Walmsley <paul@pwsan.com>
> Cc: Tony Lindgren <tony@atomide.com>
> ---
>
> This has a dependency on Tomi's "OMAP: VRFB: convert to platform device"
> series.
Thanks applying this into omap-for-v3.8/cleanup-headers-dss.
Regards,
Tony
^ permalink raw reply
* [PATCH 3/9] uprobes: allow ignoring of probe hits
From: Oleg Nesterov @ 2012-10-17 17:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAH+eYFBHXAWTinnVO8vEnEhFDQLibwo+BtxYJJYdPcG9__n5OQ@mail.gmail.com>
On 10/16, Rabin Vincent wrote:
>
> 2012/10/15 Oleg Nesterov <oleg@redhat.com>:
> >
> > Not sure I understand why we shouldn't call handlers in this case,
> > but OK, I know nothing about arm.
>
> This old discussion about kprobes should be useful:
>
> http://lists.infradead.org/pipermail/linux-arm-kernel/2011-March/045755.html
Thanks... Not sure I understand this discussion...
And, to clarify, I am not arguing. Just curious.
So, is this like cmov on x86? And this patch allows to not report if
the condition is not true? Or there are other issues on arm?
Oleg.
^ permalink raw reply
* [PATCH] ARM: U300: bump IRQs to offset 32
From: Linus Walleij @ 2012-10-17 17:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAOesGMjk_97+zhsQTczYLJ0ztL2vHxsGp5cNOef2ArBR=zTc5w@mail.gmail.com>
On Wed, Oct 17, 2012 at 7:26 PM, Olof Johansson <olof@lixom.net> wrote:
> But if you truly think this is the last time you're touching these
> lines to renumber them all, then:
>
> Acked-by: Olof Johansson <olof@lixom.net>
I think so, I'm prepping the move to device tree...
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH] ARM: U300: bump IRQs to offset 32
From: Olof Johansson @ 2012-10-17 17:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350491679-32685-1-git-send-email-linus.walleij@stericsson.com>
Hi,
On Wed, Oct 17, 2012 at 9:34 AM, Linus Walleij
<linus.walleij@stericsson.com> wrote:
[..]
> -#define IRQ_U300_INTCON0_START 1
> -#define IRQ_U300_INTCON1_START 33
> +#define IRQ_U300_INTCON0_START 32
> +#define IRQ_U300_INTCON1_START 64
[...]
> +#define IRQ_U300_IRQ0_EXT 32
> +#define IRQ_U300_IRQ1_EXT 33
Since you're touching these lines anyway, it might be nice to just
have them as a (base + offset) define instead (if you already had
that, this patch would have been a three-liner).
But if you truly think this is the last time you're touching these
lines to renumber them all, then:
Acked-by: Olof Johansson <olof@lixom.net>
-Olof
^ permalink raw reply
* [PATCH] ARM: U300: bump IRQs to offset 32
From: Linus Walleij @ 2012-10-17 17:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350491679-32685-1-git-send-email-linus.walleij@stericsson.com>
On Wed, Oct 17, 2012 at 6:34 PM, Linus Walleij
<linus.walleij@stericsson.com> wrote:
> From: Linus Walleij <linus.walleij@linaro.org>
>
> The U300 IRQs were bumped once to offset to 1 (in order to avoid
> using IRQ 0 which is now NO_IRQ). This was OK as we were still
> passing the number of irqs in the .nr_irqs field of the machine,
> with descriptors allocated at boot time.
>
> However .nr_irqs should be 0, leading the system to reserve the
> first 16 IRQs. Then the VIC driver will complain that IRQs 1
> thru 15 are pre-allocated, so to avoid this and use free
> descriptors, move all IRQs up to offset 32.
>
> This will all be done away with as we migrate to device tree,
> so it is an interim solution.
>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Oooups, requsting an ACK from the ARM SoC maintainers to
take this in through the pinctrl tree. Later patches also touch this
file so to avoid unnecessary conflicts it's better to bring it in there.
Yours,
Linus Walleij
^ permalink raw reply
* [RFC PATCH] ARM: SMP: consolidate holding pen
From: Pawel Moll @ 2012-10-17 17:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350487967-2555-1-git-send-email-marc.zyngier@arm.com>
On Wed, 2012-10-17 at 16:32 +0100, Marc Zyngier wrote:
> As with other bits of the SMP code, platforms have duplicated a lot
> of the RealView implementation. As an effort to slightly reduce
> the clutter, make the plat-versatile version of the holding pen
> a standard part of the SMP framework.
>
> Platforms can still provide their own, but those who carried an exact
> duplicate of the Realview code are switched to the common implementation.
This bit:
> arch/arm/mach-vexpress/platsmp.c | 2 +-
Acked-by: Pawel Moll <pawel.moll@arm.com>
Cheers!
Pawel
^ permalink raw reply
* [PATCH 3/3] pinctrl/u300: use managed resources
From: Linus Walleij @ 2012-10-17 17:19 UTC (permalink / raw)
To: linux-arm-kernel
From: Linus Walleij <linus.walleij@linaro.org>
This converts the U300 pin controller to use managed resources
(devm_*) for it's memory region.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/pinctrl-u300.c | 32 ++++----------------------------
1 file changed, 4 insertions(+), 28 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-u300.c b/drivers/pinctrl/pinctrl-u300.c
index 309f5b9..2e9825e 100644
--- a/drivers/pinctrl/pinctrl-u300.c
+++ b/drivers/pinctrl/pinctrl-u300.c
@@ -663,8 +663,6 @@ static const struct pinctrl_pin_desc u300_pads[] = {
struct u300_pmx {
struct device *dev;
struct pinctrl_dev *pctl;
- u32 phybase;
- u32 physize;
void __iomem *virtbase;
};
@@ -1110,7 +1108,6 @@ static int __devinit u300_pmx_probe(struct platform_device *pdev)
struct u300_pmx *upmx;
struct resource *res;
struct gpio_chip *gpio_chip = dev_get_platdata(&pdev->dev);
- int ret;
int i;
/* Create state holders etc for this driver */
@@ -1123,26 +1120,15 @@ static int __devinit u300_pmx_probe(struct platform_device *pdev)
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res)
return -ENOENT;
- upmx->phybase = res->start;
- upmx->physize = resource_size(res);
-
- if (request_mem_region(upmx->phybase, upmx->physize,
- DRIVER_NAME) == NULL) {
- ret = -ENOMEM;
- goto out_no_memregion;
- }
- upmx->virtbase = ioremap(upmx->phybase, upmx->physize);
- if (!upmx->virtbase) {
- ret = -ENOMEM;
- goto out_no_remap;
- }
+ upmx->virtbase = devm_request_and_ioremap(&pdev->dev, res);
+ if (!upmx->virtbase)
+ return -ENOMEM;
upmx->pctl = pinctrl_register(&u300_pmx_desc, &pdev->dev, upmx);
if (!upmx->pctl) {
dev_err(&pdev->dev, "could not register U300 pinmux driver\n");
- ret = -EINVAL;
- goto out_no_pmx;
+ return -EINVAL;
}
/* We will handle a range of GPIO pins */
@@ -1156,14 +1142,6 @@ static int __devinit u300_pmx_probe(struct platform_device *pdev)
dev_info(&pdev->dev, "initialized U300 pin control driver\n");
return 0;
-
-out_no_pmx:
- iounmap(upmx->virtbase);
-out_no_remap:
- platform_set_drvdata(pdev, NULL);
-out_no_memregion:
- release_mem_region(upmx->phybase, upmx->physize);
- return ret;
}
static int __devexit u300_pmx_remove(struct platform_device *pdev)
@@ -1171,8 +1149,6 @@ static int __devexit u300_pmx_remove(struct platform_device *pdev)
struct u300_pmx *upmx = platform_get_drvdata(pdev);
pinctrl_unregister(upmx->pctl);
- iounmap(upmx->virtbase);
- release_mem_region(upmx->phybase, upmx->physize);
platform_set_drvdata(pdev, NULL);
return 0;
--
1.7.11.3
^ permalink raw reply related
* [PATCH 2/3] pinctrl/coh901: convert to use managed resources
From: Linus Walleij @ 2012-10-17 17:19 UTC (permalink / raw)
To: linux-arm-kernel
From: Linus Walleij <linus.walleij@linaro.org>
This switches the COH 901 pin controller to use managed
resources (devm_*) for memory remaps, clocks, etc.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/pinctrl-coh901.c | 62 ++++++++++++----------------------------
1 file changed, 19 insertions(+), 43 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-coh901.c b/drivers/pinctrl/pinctrl-coh901.c
index 152efae..5c7daf9 100644
--- a/drivers/pinctrl/pinctrl-coh901.c
+++ b/drivers/pinctrl/pinctrl-coh901.c
@@ -65,7 +65,6 @@ struct u300_gpio {
struct gpio_chip chip;
struct list_head port_list;
struct clk *clk;
- struct resource *memres;
void __iomem *base;
struct device *dev;
u32 stride;
@@ -663,17 +662,16 @@ static int __init u300_gpio_probe(struct platform_device *pdev)
{
struct u300_gpio_platform *plat = dev_get_platdata(&pdev->dev);
struct u300_gpio *gpio;
+ struct resource *memres;
int err = 0;
int portno;
u32 val;
u32 ifr;
int i;
- gpio = kzalloc(sizeof(struct u300_gpio), GFP_KERNEL);
- if (gpio == NULL) {
- dev_err(&pdev->dev, "failed to allocate memory\n");
+ gpio = devm_kzalloc(&pdev->dev, sizeof(struct u300_gpio), GFP_KERNEL);
+ if (gpio == NULL)
return -ENOMEM;
- }
gpio->chip = u300_gpio_chip;
gpio->chip.ngpio = plat->ports * U300_GPIO_PINS_PER_PORT;
@@ -681,37 +679,29 @@ static int __init u300_gpio_probe(struct platform_device *pdev)
gpio->chip.base = plat->gpio_base;
gpio->dev = &pdev->dev;
- /* Get GPIO clock */
- gpio->clk = clk_get(gpio->dev, NULL);
+ memres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!memres) {
+ dev_err(gpio->dev, "could not get GPIO memory resource\n");
+ return -ENODEV;
+ }
+
+ gpio->base = devm_request_and_ioremap(&pdev->dev, memres);
+ if (!gpio->base) {
+ dev_err(gpio->dev, "could not get remap memory\n");
+ return -ENOMEM;
+ }
+
+ gpio->clk = devm_clk_get(gpio->dev, NULL);
if (IS_ERR(gpio->clk)) {
err = PTR_ERR(gpio->clk);
dev_err(gpio->dev, "could not get GPIO clock\n");
- goto err_no_clk;
+ return err;
}
+
err = clk_prepare_enable(gpio->clk);
if (err) {
dev_err(gpio->dev, "could not enable GPIO clock\n");
- goto err_no_clk_enable;
- }
-
- gpio->memres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (!gpio->memres) {
- dev_err(gpio->dev, "could not get GPIO memory resource\n");
- err = -ENODEV;
- goto err_no_resource;
- }
-
- if (!request_mem_region(gpio->memres->start,
- resource_size(gpio->memres),
- "GPIO Controller")) {
- err = -ENODEV;
- goto err_no_ioregion;
- }
-
- gpio->base = ioremap(gpio->memres->start, resource_size(gpio->memres));
- if (!gpio->base) {
- err = -ENOMEM;
- goto err_no_ioremap;
+ return err;
}
dev_info(gpio->dev,
@@ -810,16 +800,7 @@ err_no_chip:
err_no_domain:
err_no_port:
u300_gpio_free_ports(gpio);
- iounmap(gpio->base);
-err_no_ioremap:
- release_mem_region(gpio->memres->start, resource_size(gpio->memres));
-err_no_ioregion:
-err_no_resource:
clk_disable_unprepare(gpio->clk);
-err_no_clk_enable:
- clk_put(gpio->clk);
-err_no_clk:
- kfree(gpio);
dev_info(&pdev->dev, "module ERROR:%d\n", err);
return err;
}
@@ -838,13 +819,8 @@ static int __exit u300_gpio_remove(struct platform_device *pdev)
return err;
}
u300_gpio_free_ports(gpio);
- iounmap(gpio->base);
- release_mem_region(gpio->memres->start,
- resource_size(gpio->memres));
clk_disable_unprepare(gpio->clk);
- clk_put(gpio->clk);
platform_set_drvdata(pdev, NULL);
- kfree(gpio);
return 0;
}
--
1.7.11.3
^ permalink raw reply related
* [PATCH 1/3] pinctrl/coh901: use irqdomain, allocate irqdescs
From: Linus Walleij @ 2012-10-17 17:19 UTC (permalink / raw)
To: linux-arm-kernel
From: Linus Walleij <linus.walleij@linaro.org>
This switches the COH 901 pinctrl driver to allocate its GPIO
IRQs dynamically, and start to use a linear irqdomain to map
from the hardware IRQs.
This way we can cut away the complex allocation of IRQ numbers
from the <mach/irqs.h> file.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/mach-u300/core.c | 1 -
arch/arm/mach-u300/include/mach/irqs.h | 10 -----
drivers/pinctrl/pinctrl-coh901.c | 60 +++++++++++++++++++++-------
include/linux/platform_data/pinctrl-coh901.h | 2 -
4 files changed, 46 insertions(+), 27 deletions(-)
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 603c08e..ce2de0d 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -1445,7 +1445,6 @@ static struct platform_device pinctrl_device = {
static struct u300_gpio_platform u300_gpio_plat = {
.ports = 7,
.gpio_base = 0,
- .gpio_irq_base = IRQ_U300_GPIO_BASE,
.pinctrl_device = &pinctrl_device,
};
diff --git a/arch/arm/mach-u300/include/mach/irqs.h b/arch/arm/mach-u300/include/mach/irqs.h
index e85ec38..21d5e76 100644
--- a/arch/arm/mach-u300/include/mach/irqs.h
+++ b/arch/arm/mach-u300/include/mach/irqs.h
@@ -77,14 +77,4 @@
#define IRQ_U300_GPIO_PORT6 87
#define U300_VIC_IRQS_END 88
-/* Maximum 8*7 GPIO lines */
-#ifdef CONFIG_PINCTRL_COH901
-#define IRQ_U300_GPIO_BASE (U300_VIC_IRQS_END)
-#define IRQ_U300_GPIO_END (IRQ_U300_GPIO_BASE + 56)
-#else
-#define IRQ_U300_GPIO_END (U300_VIC_IRQS_END)
-#endif
-
-#define NR_IRQS_U300 (IRQ_U300_GPIO_END - IRQ_U300_INTCON0_START)
-
#endif
diff --git a/drivers/pinctrl/pinctrl-coh901.c b/drivers/pinctrl/pinctrl-coh901.c
index b446c96..152efae 100644
--- a/drivers/pinctrl/pinctrl-coh901.c
+++ b/drivers/pinctrl/pinctrl-coh901.c
@@ -13,6 +13,7 @@
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/io.h>
+#include <linux/irqdomain.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/platform_device.h>
@@ -67,7 +68,6 @@ struct u300_gpio {
struct resource *memres;
void __iomem *base;
struct device *dev;
- int irq_base;
u32 stride;
/* Register offsets */
u32 pcr;
@@ -83,6 +83,7 @@ struct u300_gpio_port {
struct list_head node;
struct u300_gpio *gpio;
char name[8];
+ struct irq_domain *domain;
int irq;
int number;
u8 toggle_edge_mode;
@@ -314,10 +315,30 @@ static int u300_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
static int u300_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
{
struct u300_gpio *gpio = to_u300_gpio(chip);
- int retirq = gpio->irq_base + offset;
+ int portno = offset >> 3;
+ struct u300_gpio_port *port = NULL;
+ struct list_head *p;
+ int retirq;
- dev_dbg(gpio->dev, "request IRQ for GPIO %d, return %d\n", offset,
- retirq);
+ list_for_each(p, &gpio->port_list) {
+ port = list_entry(p, struct u300_gpio_port, node);
+ if (port->number == portno)
+ break;
+ }
+ if (port == NULL) {
+ dev_err(gpio->dev, "could not locate port for GPIO %d IRQ\n",
+ offset);
+ return -EINVAL;
+ }
+
+ /*
+ * The local hwirqs on the port are the lower three bits, there
+ * are exactly 8 IRQs per port since they are 8-bit
+ */
+ retirq = irq_find_mapping(port->domain, (offset & 0x7));
+
+ dev_dbg(gpio->dev, "request IRQ for GPIO %d, return %d from port %d\n",
+ offset, retirq, port->number);
return retirq;
}
@@ -467,7 +488,7 @@ static int u300_gpio_irq_type(struct irq_data *d, unsigned trigger)
{
struct u300_gpio_port *port = irq_data_get_irq_chip_data(d);
struct u300_gpio *gpio = port->gpio;
- int offset = d->irq - gpio->irq_base;
+ int offset = (port->number << 3) + d->hwirq;
u32 val;
if ((trigger & IRQF_TRIGGER_RISING) &&
@@ -503,10 +524,12 @@ static void u300_gpio_irq_enable(struct irq_data *d)
{
struct u300_gpio_port *port = irq_data_get_irq_chip_data(d);
struct u300_gpio *gpio = port->gpio;
- int offset = d->irq - gpio->irq_base;
+ int offset = (port->number << 3) + d->hwirq;
u32 val;
unsigned long flags;
+ dev_dbg(gpio->dev, "enable IRQ for hwirq %lu on port %s, offset %d\n",
+ d->hwirq, port->name, offset);
local_irq_save(flags);
val = readl(U300_PIN_REG(offset, ien));
writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, ien));
@@ -517,7 +540,7 @@ static void u300_gpio_irq_disable(struct irq_data *d)
{
struct u300_gpio_port *port = irq_data_get_irq_chip_data(d);
struct u300_gpio *gpio = port->gpio;
- int offset = d->irq - gpio->irq_base;
+ int offset = (port->number << 3) + d->hwirq;
u32 val;
unsigned long flags;
@@ -555,8 +578,7 @@ static void u300_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
int irqoffset;
for_each_set_bit(irqoffset, &val, U300_GPIO_PINS_PER_PORT) {
- int pin_irq = gpio->irq_base + (port->number << 3)
- + irqoffset;
+ int pin_irq = irq_find_mapping(port->domain, irqoffset);
int offset = pinoffset + irqoffset;
dev_dbg(gpio->dev, "GPIO IRQ %d on pin %d\n",
@@ -631,6 +653,8 @@ static inline void u300_gpio_free_ports(struct u300_gpio *gpio)
list_for_each_safe(p, n, &gpio->port_list) {
port = list_entry(p, struct u300_gpio_port, node);
list_del(&port->node);
+ if (port->domain)
+ irq_domain_remove(port->domain);
kfree(port);
}
}
@@ -653,7 +677,6 @@ static int __init u300_gpio_probe(struct platform_device *pdev)
gpio->chip = u300_gpio_chip;
gpio->chip.ngpio = plat->ports * U300_GPIO_PINS_PER_PORT;
- gpio->irq_base = plat->gpio_irq_base;
gpio->chip.dev = &pdev->dev;
gpio->chip.base = plat->gpio_base;
gpio->dev = &pdev->dev;
@@ -732,18 +755,26 @@ static int __init u300_gpio_probe(struct platform_device *pdev)
port->irq = platform_get_irq_byname(pdev,
port->name);
- dev_dbg(gpio->dev, "register IRQ %d for %s\n", port->irq,
+ dev_dbg(gpio->dev, "register IRQ %d for port %s\n", port->irq,
port->name);
+ port->domain = irq_domain_add_linear(pdev->dev.of_node,
+ U300_GPIO_PINS_PER_PORT,
+ &irq_domain_simple_ops,
+ port);
+ if (!port->domain)
+ goto err_no_domain;
+
irq_set_chained_handler(port->irq, u300_gpio_irq_handler);
irq_set_handler_data(port->irq, port);
/* For each GPIO pin set the unique IRQ handler */
for (i = 0; i < U300_GPIO_PINS_PER_PORT; i++) {
- int irqno = gpio->irq_base + (portno << 3) + i;
+ int irqno = irq_create_mapping(port->domain, i);
- dev_dbg(gpio->dev, "handler for IRQ %d on %s\n",
- irqno, port->name);
+ dev_dbg(gpio->dev, "GPIO%d on port %s gets IRQ %d\n",
+ gpio->chip.base + (port->number << 3) + i,
+ port->name, irqno);
irq_set_chip_and_handler(irqno, &u300_gpio_irqchip,
handle_simple_irq);
set_irq_flags(irqno, IRQF_VALID);
@@ -776,6 +807,7 @@ static int __init u300_gpio_probe(struct platform_device *pdev)
err_no_pinctrl:
err = gpiochip_remove(&gpio->chip);
err_no_chip:
+err_no_domain:
err_no_port:
u300_gpio_free_ports(gpio);
iounmap(gpio->base);
diff --git a/include/linux/platform_data/pinctrl-coh901.h b/include/linux/platform_data/pinctrl-coh901.h
index 30dea25..27a23b3 100644
--- a/include/linux/platform_data/pinctrl-coh901.h
+++ b/include/linux/platform_data/pinctrl-coh901.h
@@ -13,13 +13,11 @@
* struct u300_gpio_platform - U300 GPIO platform data
* @ports: number of GPIO block ports
* @gpio_base: first GPIO number for this block (use a free range)
- * @gpio_irq_base: first GPIO IRQ number for this block (use a free range)
* @pinctrl_device: pin control device to spawn as child
*/
struct u300_gpio_platform {
u8 ports;
int gpio_base;
- int gpio_irq_base;
struct platform_device *pinctrl_device;
};
--
1.7.11.3
^ permalink raw reply related
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