* [RFC PATCH v3 16/16] ARM: dts: add AM33XX SPI support
From: Matt Porter @ 2012-10-18 13:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350566815-409-1-git-send-email-mporter@ti.com>
Adds AM33XX SPI support for am335x-bone and am335x-evm.
Signed-off-by: Matt Porter <mporter@ti.com>
---
arch/arm/boot/dts/am335x-bone.dts | 17 +++++++++++++++
arch/arm/boot/dts/am335x-evm.dts | 9 ++++++++
arch/arm/boot/dts/am33xx.dtsi | 43 +++++++++++++++++++++++++++++++++++++
3 files changed, 69 insertions(+)
diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts
index 5510979..23edfd8 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -18,6 +18,17 @@
reg = <0x80000000 0x10000000>; /* 256 MB */
};
+ am3358_pinmux: pinmux at 44e10800 {
+ spi1_pins: pinmux_spi1_pins {
+ pinctrl-single,pins = <
+ 0x190 0x13 /* mcasp0_aclkx.spi1_sclk, OUTPUT_PULLUP | MODE3 */
+ 0x194 0x33 /* mcasp0_fsx.spi1_d0, INPUT_PULLUP | MODE3 */
+ 0x198 0x13 /* mcasp0_axr0.spi1_d1, OUTPUT_PULLUP | MODE3 */
+ 0x19c 0x13 /* mcasp0_ahclkr.spi1_cs0, OUTPUT_PULLUP | MODE3 */
+ >;
+ };
+ };
+
ocp {
uart1: serial at 44e09000 {
status = "okay";
@@ -84,3 +95,9 @@
&mmc1 {
vmmc-supply = <&ldo3_reg>;
};
+
+&spi1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_pins>;
+};
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index d63fce8..8d5f660 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -124,3 +124,12 @@
&mmc1 {
vmmc-supply = <&vmmc_reg>;
};
+
+&spi0 {
+ status = "okay";
+ spi-flash at 0 {
+ compatible = "spansion,s25fl064k", "m25p80";
+ spi-max-frequency = <24000000>;
+ reg = <0>;
+ };
+};
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 26a6af7..063ecea 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -40,6 +40,15 @@
};
};
+ am3358_pinmux: pinmux at 44e10800 {
+ compatible = "pinctrl-single";
+ reg = <0x44e10800 0x0238>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x7f>;
+ };
+
/*
* XXX: Use a flat representation of the AM33XX interconnect.
* The real AM33XX interconnect network is quite complex.Since
@@ -261,6 +270,40 @@
status = "disabled";
};
+ spi0: spi at 48030000 {
+ compatible = "ti,omap4-mcspi";
+ ti,hwmods = "spi0";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x48030000 0x400>;
+ interrupt-parent = <&intc>;
+ interrupt = <65>;
+ dmas = <&edma 16
+ &edma 17
+ &edma 18
+ &edma 19>;
+ dma-names = "tx0", "rx0", "tx1", "rx1";
+ ti,spi-num-cs = <2>;
+ status = "disabled";
+ };
+
+ spi1: spi at 481a0000 {
+ compatible = "ti,omap4-mcspi";
+ ti,hwmods = "spi1";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x481a0000 0x400>;
+ interrupt-parent = <&intc>;
+ interrupt = <125>;
+ dmas = <&edma 42
+ &edma 43
+ &edma 44
+ &edma 45>;
+ dma-names = "tx0", "rx0", "tx1", "rx1";
+ ti,spi-num-cs = <2>;
+ status = "disabled";
+ };
+
wdt2: wdt at 44e35000 {
compatible = "ti,omap3-wdt";
ti,hwmods = "wd_timer2";
--
1.7.9.5
^ permalink raw reply related
* [RFC PATCH v3 15/16] spi: omap2-mcspi: add generic DMA request support to the DT binding
From: Matt Porter @ 2012-10-18 13:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350566815-409-1-git-send-email-mporter@ti.com>
The binding definition is based on the generic DMA request binding.
Signed-off-by: Matt Porter <mporter@ti.com>
---
Documentation/devicetree/bindings/spi/omap-spi.txt | 27 +++++++++++++++++++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/spi/omap-spi.txt b/Documentation/devicetree/bindings/spi/omap-spi.txt
index 81df374..11aff04 100644
--- a/Documentation/devicetree/bindings/spi/omap-spi.txt
+++ b/Documentation/devicetree/bindings/spi/omap-spi.txt
@@ -7,8 +7,18 @@ Required properties:
- ti,spi-num-cs : Number of chipselect supported by the instance.
- ti,hwmods: Name of the hwmod associated to the McSPI
+Optional properties:
+- dmas: List of DMA controller phandle and DMA request ordered
+ pairs. One tx and one rx pair is required for each chip
+ select.
+- dma-names: List of DMA request names. These strings correspond
+ 1:1 with the ordered pairs in dmas. The string naming is
+ to be "rxN" and "txN" for RX and TX requests,
+ respectively, where N equals the chip select number.
-Example:
+Examples:
+
+[hwmod populated DMA resources]
mcspi1: mcspi at 1 {
#address-cells = <1>;
@@ -18,3 +28,18 @@ mcspi1: mcspi at 1 {
ti,spi-num-cs = <4>;
};
+[generic DMA request binding]
+
+mcspi1: mcspi at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "ti,omap4-mcspi";
+ ti,hwmods = "mcspi1";
+ ti,spi-num-cs = <2>;
+ dmas = <&edma 42
+ &edma 43
+ &edma 44
+ &edma 45>;
+ dma-names = "tx0", "rx0", "tx1", "rx1";
+};
+
--
1.7.9.5
^ permalink raw reply related
* [RFC PATCH v3 14/16] spi: omap2-mcspi: convert to dma_request_slave_channel_compat()
From: Matt Porter @ 2012-10-18 13:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350566815-409-1-git-send-email-mporter@ti.com>
Convert dmaengine channel requests to use
dma_request_slave_channel_compat(). This supports the DT case of
platforms requiring channel selection from either the OMAP DMA or
the EDMA engine. AM33xx only boots from DT and is the only user
implementing EDMA so in the !DT case we can default to the OMAP DMA
filter.
Signed-off-by: Matt Porter <mporter@ti.com>
---
drivers/spi/spi-omap2-mcspi.c | 65 ++++++++++++++++++++++++++++-------------
1 file changed, 45 insertions(+), 20 deletions(-)
diff --git a/drivers/spi/spi-omap2-mcspi.c b/drivers/spi/spi-omap2-mcspi.c
index 3542fdc..793ae8c 100644
--- a/drivers/spi/spi-omap2-mcspi.c
+++ b/drivers/spi/spi-omap2-mcspi.c
@@ -103,6 +103,9 @@ struct omap2_mcspi_dma {
struct completion dma_tx_completion;
struct completion dma_rx_completion;
+
+ char dma_rx_ch_name[14];
+ char dma_tx_ch_name[14];
};
/* use PIO for small transfers, avoiding DMA setup/teardown overhead and
@@ -819,14 +822,23 @@ static int omap2_mcspi_request_dma(struct spi_device *spi)
dma_cap_zero(mask);
dma_cap_set(DMA_SLAVE, mask);
sig = mcspi_dma->dma_rx_sync_dev;
- mcspi_dma->dma_rx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
+
+ mcspi_dma->dma_rx =
+ dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
+ &sig, &master->dev,
+ mcspi_dma->dma_rx_ch_name);
+
if (!mcspi_dma->dma_rx) {
dev_err(&spi->dev, "no RX DMA engine channel for McSPI\n");
return -EAGAIN;
}
sig = mcspi_dma->dma_tx_sync_dev;
- mcspi_dma->dma_tx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
+ mcspi_dma->dma_tx =
+ dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
+ &sig, &master->dev,
+ mcspi_dma->dma_tx_ch_name);
+
if (!mcspi_dma->dma_tx) {
dev_err(&spi->dev, "no TX DMA engine channel for McSPI\n");
dma_release_channel(mcspi_dma->dma_rx);
@@ -1217,29 +1229,42 @@ static int __devinit omap2_mcspi_probe(struct platform_device *pdev)
goto free_master;
for (i = 0; i < master->num_chipselect; i++) {
- char dma_ch_name[14];
+ char *dma_rx_ch_name = mcspi->dma_channels[i].dma_rx_ch_name;
+ char *dma_tx_ch_name = mcspi->dma_channels[i].dma_tx_ch_name;
struct resource *dma_res;
- sprintf(dma_ch_name, "rx%d", i);
- dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
- dma_ch_name);
- if (!dma_res) {
- dev_dbg(&pdev->dev, "cannot get DMA RX channel\n");
- status = -ENODEV;
- break;
- }
+ sprintf(dma_rx_ch_name, "rx%d", i);
+ if (!pdev->dev.of_node) {
+ dma_res =
+ platform_get_resource_byname(pdev,
+ IORESOURCE_DMA,
+ dma_rx_ch_name);
+ if (!dma_res) {
+ dev_dbg(&pdev->dev,
+ "cannot get DMA RX channel\n");
+ status = -ENODEV;
+ break;
+ }
- mcspi->dma_channels[i].dma_rx_sync_dev = dma_res->start;
- sprintf(dma_ch_name, "tx%d", i);
- dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
- dma_ch_name);
- if (!dma_res) {
- dev_dbg(&pdev->dev, "cannot get DMA TX channel\n");
- status = -ENODEV;
- break;
+ mcspi->dma_channels[i].dma_rx_sync_dev =
+ dma_res->start;
}
+ sprintf(dma_tx_ch_name, "tx%d", i);
+ if (!pdev->dev.of_node) {
+ dma_res =
+ platform_get_resource_byname(pdev,
+ IORESOURCE_DMA,
+ dma_tx_ch_name);
+ if (!dma_res) {
+ dev_dbg(&pdev->dev,
+ "cannot get DMA TX channel\n");
+ status = -ENODEV;
+ break;
+ }
- mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start;
+ mcspi->dma_channels[i].dma_tx_sync_dev =
+ dma_res->start;
+ }
}
if (status < 0)
--
1.7.9.5
^ permalink raw reply related
* [RFC PATCH v3 13/16] ARM: dts: add AM33XX MMC support
From: Matt Porter @ 2012-10-18 13:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350566815-409-1-git-send-email-mporter@ti.com>
Adds AM33XX MMC support for am335x-bone and am335x-evm.
Signed-off-by: Matt Porter <mporter@ti.com>
---
arch/arm/boot/dts/am335x-bone.dts | 6 ++++++
arch/arm/boot/dts/am335x-evm.dts | 6 ++++++
arch/arm/boot/dts/am33xx.dtsi | 27 +++++++++++++++++++++++++++
3 files changed, 39 insertions(+)
diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts
index c634f87..5510979 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -70,6 +70,8 @@
};
ldo3_reg: regulator at 5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
regulator-always-on;
};
@@ -78,3 +80,7 @@
};
};
};
+
+&mmc1 {
+ vmmc-supply = <&ldo3_reg>;
+};
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 185d632..d63fce8 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -114,7 +114,13 @@
};
vmmc_reg: regulator at 12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
+
+&mmc1 {
+ vmmc-supply = <&vmmc_reg>;
+};
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index ab9c78f..26a6af7 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -234,6 +234,33 @@
status = "disabled";
};
+ mmc1: mmc at 48060000 {
+ compatible = "ti,omap3-hsmmc";
+ ti,hwmods = "mmc1";
+ ti,dual-volt;
+ ti,needs-special-reset;
+ dmas = <&edma 24
+ &edma 25>;
+ dma-names = "tx", "rx";
+ };
+
+ mmc2: mmc at 481d8000 {
+ compatible = "ti,omap3-hsmmc";
+ ti,hwmods = "mmc2";
+ ti,needs-special-reset;
+ dmas = <&edma 2
+ &edma 3>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ mmc3: mmc at 47810000 {
+ compatible = "ti,omap3-hsmmc";
+ ti,hwmods = "mmc3";
+ ti,needs-special-reset;
+ status = "disabled";
+ };
+
wdt2: wdt at 44e35000 {
compatible = "ti,omap3-wdt";
ti,hwmods = "wd_timer2";
--
1.7.9.5
^ permalink raw reply related
* [RFC PATCH v3 12/16] mmc: omap_hsmmc: add generic DMA request support to the DT binding
From: Matt Porter @ 2012-10-18 13:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350566815-409-1-git-send-email-mporter@ti.com>
The binding definition is based on the generic DMA request binding.
Signed-off-by: Matt Porter <mporter@ti.com>
---
.../devicetree/bindings/mmc/ti-omap-hsmmc.txt | 25 +++++++++++++++++++-
1 file changed, 24 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
index be76a23..d1b8932 100644
--- a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
+++ b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
@@ -19,8 +19,28 @@ ti,dual-volt: boolean, supports dual voltage cards
"supply-name" examples are "vmmc", "vmmc_aux" etc
ti,non-removable: non-removable slot (like eMMC)
ti,needs-special-reset: Requires a special softreset sequence
+dmas: DMA controller phandle and DMA request value ordered pair
+One tx and one rx pair is required.
+dma-names: DMA request names. These strings correspond 1:1 with
+the ordered pairs in dmas. The RX request must be "rx" and the
+TX request must be "tx".
+
+Examples:
+
+[hwmod populated DMA resources]
+
+ mmc1: mmc at 0x4809c000 {
+ compatible = "ti,omap4-hsmmc";
+ reg = <0x4809c000 0x400>;
+ ti,hwmods = "mmc1";
+ ti,dual-volt;
+ bus-width = <4>;
+ vmmc-supply = <&vmmc>; /* phandle to regulator node */
+ ti,non-removable;
+ };
+
+[generic DMA request binding]
-Example:
mmc1: mmc at 0x4809c000 {
compatible = "ti,omap4-hsmmc";
reg = <0x4809c000 0x400>;
@@ -29,4 +49,7 @@ Example:
bus-width = <4>;
vmmc-supply = <&vmmc>; /* phandle to regulator node */
ti,non-removable;
+ dmas = <&edma 24
+ &edma 25>;
+ dma-names = "tx", "rx";
};
--
1.7.9.5
^ permalink raw reply related
* [RFC PATCH v3 11/16] mmc: omap_hsmmc: limit max_segs with the EDMA DMAC
From: Matt Porter @ 2012-10-18 13:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350566815-409-1-git-send-email-mporter@ti.com>
The EDMA DMAC has a hardware limitation that prevents supporting
scatter gather lists with any number of segments. Since the EDMA
DMA Engine driver sets the maximum segments to 16, we do the
same.
TODO: this will be replaced once the DMA Engine API supports an
API to query the DMAC's segment size limit.
Signed-off-by: Matt Porter <mporter@ti.com>
---
drivers/mmc/host/omap_hsmmc.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index b327cd0..52bab01 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -1828,6 +1828,16 @@ static int __devinit omap_hsmmc_probe(struct platform_device *pdev)
* as we want. */
mmc->max_segs = 1024;
+ /* Eventually we should get our max_segs limitation for EDMA by
+ * querying the dmaengine API */
+ if (pdev->dev.of_node) {
+ struct device_node *parent = pdev->dev.of_node->parent;
+ struct device_node *node;
+ node = of_find_node_by_name(parent, "edma");
+ if (node)
+ mmc->max_segs = 16;
+ }
+
mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
--
1.7.9.5
^ permalink raw reply related
* [RFC PATCH v3 10/16] mmc: omap_hsmmc: convert to dma_request_slave_channel_compat()
From: Matt Porter @ 2012-10-18 13:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350566815-409-1-git-send-email-mporter@ti.com>
Convert dmaengine channel requests to use
dma_request_slave_channel_compat(). This supports the DT case of
platforms requiring channel selection from either the OMAP DMA or
the EDMA engine. AM33xx only boots from DT and is the only user
implementing EDMA so in the !DT case we can default to the OMAP DMA
filter.
Signed-off-by: Matt Porter <mporter@ti.com>
---
drivers/mmc/host/omap_hsmmc.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index 54bfd0c..b327cd0 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -1866,14 +1866,20 @@ static int __devinit omap_hsmmc_probe(struct platform_device *pdev)
dma_cap_zero(mask);
dma_cap_set(DMA_SLAVE, mask);
- host->rx_chan = dma_request_channel(mask, omap_dma_filter_fn, &rx_req);
+ host->rx_chan =
+ dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
+ &rx_req, &pdev->dev, "rx");
+
if (!host->rx_chan) {
dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req);
ret = -ENXIO;
goto err_irq;
}
- host->tx_chan = dma_request_channel(mask, omap_dma_filter_fn, &tx_req);
+ host->tx_chan =
+ dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
+ &tx_req, &pdev->dev, "tx");
+
if (!host->tx_chan) {
dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req);
ret = -ENXIO;
--
1.7.9.5
^ permalink raw reply related
* [RFC PATCH v3 09/16] dmaengine: add dma_request_slave_channel_compat()
From: Matt Porter @ 2012-10-18 13:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350566815-409-1-git-send-email-mporter@ti.com>
Adds a dma_request_slave_channel_compat() wrapper which accepts
both the arguments from dma_request_channel() and
dma_request_slave_channel(). Based on whether the driver is
instantiated via DT, the appropriate channel request call will be
made.
This allows for a much cleaner migration of drivers to the
dmaengine DT API as platforms continue to be mixed between those
that boot using DT and those that do not.
Suggested-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Matt Porter <mporter@ti.com>
---
include/linux/dmaengine.h | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
index c88f302..11d9e25 100644
--- a/include/linux/dmaengine.h
+++ b/include/linux/dmaengine.h
@@ -1007,6 +1007,16 @@ void dma_run_dependencies(struct dma_async_tx_descriptor *tx);
struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type);
struct dma_chan *net_dma_find_channel(void);
#define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y)
+static inline struct dma_chan
+*dma_request_slave_channel_compat(dma_cap_mask_t mask, dma_filter_fn fn,
+ void *fn_param, struct device *dev,
+ char *name)
+{
+ if (dev->of_node)
+ return dma_request_slave_channel(dev, name);
+ else
+ return dma_request_channel(mask, fn, fn_param);
+}
/* --- Helper iov-locking functions --- */
--
1.7.9.5
^ permalink raw reply related
* [RFC PATCH v3 08/16] ARM: dts: add AM33XX EDMA support
From: Matt Porter @ 2012-10-18 13:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350566815-409-1-git-send-email-mporter@ti.com>
Adds AM33XX EDMA support to the am33xx.dtsi as documented in
Documentation/devicetree/bindings/dma/ti-edma.txt
Signed-off-by: Matt Porter <mporter@ti.com>
---
arch/arm/boot/dts/am33xx.dtsi | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index bb31bff..ab9c78f 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -62,6 +62,37 @@
reg = <0x48200000 0x1000>;
};
+ edma: edma at 49000000 {
+ compatible = "ti,edma3";
+ ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
+ reg = <0x49000000 0x10000>,
+ <0x44e10f90 0x10>;
+ interrupt-parent = <&intc>;
+ interrupts = <12 13 14>;
+ #dma-cells = <1>;
+ dma-channels = <64>;
+ ti,edma-regions = <4>;
+ ti,edma-slots = <256>;
+ ti,edma-reserved-channels = <0 2
+ 14 2
+ 26 6
+ 48 4
+ 56 8>;
+ ti,edma-reserved-slots = <0 2
+ 14 2
+ 26 6
+ 48 4
+ 56 8
+ 64 127>;
+ ti,edma-queue-tc-map = <0 0
+ 1 1
+ 2 2>;
+ ti,edma-queue-priority-map = <0 0
+ 1 1
+ 2 2>;
+ ti,edma-default-queue = <0>;
+ };
+
gpio1: gpio at 44e07000 {
compatible = "ti,omap4-gpio";
ti,hwmods = "gpio1";
--
1.7.9.5
^ permalink raw reply related
* [RFC PATCH v3 07/16] dmaengine: edma: Add TI EDMA device tree binding
From: Matt Porter @ 2012-10-18 13:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350566815-409-1-git-send-email-mporter@ti.com>
The binding definition is based on the generic DMA controller
binding.
Signed-off-by: Matt Porter <mporter@ti.com>
---
Documentation/devicetree/bindings/dma/ti-edma.txt | 51 +++++++++++++++++++++
1 file changed, 51 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/ti-edma.txt
diff --git a/Documentation/devicetree/bindings/dma/ti-edma.txt b/Documentation/devicetree/bindings/dma/ti-edma.txt
new file mode 100644
index 0000000..3344345
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/ti-edma.txt
@@ -0,0 +1,51 @@
+TI EDMA
+
+Required properties:
+- compatible : "ti,edma3"
+- ti,hwmods: Name of the hwmods associated to the EDMA
+- ti,edma-regions: Number of regions
+- ti,edma-slots: Number of slots
+- ti,edma-queue-tc-map: List of transfer control to queue mappings
+- ti,edma-queue-priority-map: List of queue priority mappings
+- ti,edma-default-queue: Default queue value
+
+Optional properties:
+- ti,edma-reserved-channels: List of reserved channel regions
+- ti,edma-reserved-slots: List of reserved slot regions
+- ti,edma-xbar-event-map: Crossbar event to channel map
+
+Example:
+
+edma: edma at 49000000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x49000000 0x10000>;
+ interrupt-parent = <&intc>;
+ interrupts = <12 13 14>;
+ compatible = "ti,edma3";
+ ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
+ #dma-cells = <1>;
+ dma-channels = <64>;
+ ti,edma-regions = <4>;
+ ti,edma-slots = <256>;
+ ti,edma-reserved-channels = <0 2
+ 14 2
+ 26 6
+ 48 4
+ 56 8>;
+ ti,edma-reserved-slots = <0 2
+ 14 2
+ 26 6
+ 48 4
+ 56 8
+ 64 127>;
+ ti,edma-queue-tc-map = <0 0
+ 1 1
+ 2 2>;
+ ti,edma-queue-priority-map = <0 0
+ 1 1
+ 2 2>;
+ ti,edma-default-queue = <0>;
+ ti,edma-xbar-event-map = <1 12
+ 2 13>;
+};
--
1.7.9.5
^ permalink raw reply related
* [RFC PATCH v3 06/16] dmaengine: edma: enable build for AM33XX
From: Matt Porter @ 2012-10-18 13:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350566815-409-1-git-send-email-mporter@ti.com>
Enable TI EDMA option on OMAP.
Signed-off-by: Matt Porter <mporter@ti.com>
---
drivers/dma/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 677cd6e..eaea1c2 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -210,7 +210,7 @@ config SIRF_DMA
config TI_EDMA
tristate "TI EDMA support"
- depends on ARCH_DAVINCI
+ depends on ARCH_DAVINCI || ARCH_OMAP
select DMA_ENGINE
select DMA_VIRTUAL_CHANNELS
default n
--
1.7.9.5
^ permalink raw reply related
* [RFC PATCH v3 05/16] ARM: edma: add AM33XX crossbar event support
From: Matt Porter @ 2012-10-18 13:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350566815-409-1-git-send-email-mporter@ti.com>
Adds support for the per-EDMA channel event mux. This is required
for any peripherals using DMA crossbar mapped events.
Signed-off-by: Matt Porter <mporter@ti.com>
---
arch/arm/common/edma.c | 63 +++++++++++++++++++++++++++++++++++-
include/linux/platform_data/edma.h | 1 +
2 files changed, 63 insertions(+), 1 deletion(-)
diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c
index 6d2a590..b761b7a 100644
--- a/arch/arm/common/edma.c
+++ b/arch/arm/common/edma.c
@@ -1425,6 +1425,53 @@ static int edma_of_read_u32_to_s16_array(const struct device_node *np,
return 0;
}
+static int edma_xbar_event_map(struct device *dev,
+ struct device_node *node,
+ struct edma_soc_info *pdata, int len)
+{
+ int ret = 0;
+ int i;
+ struct resource res;
+ void *xbar;
+ s16 (*xbar_chans)[2];
+ u32 shift, offset, mux;
+
+ xbar_chans = devm_kzalloc(dev,
+ len/sizeof(s16) + 2*sizeof(s16),
+ GFP_KERNEL);
+ if (!xbar_chans)
+ return -ENOMEM;
+
+ ret = of_address_to_resource(node, 1, &res);
+ if (IS_ERR_VALUE(ret))
+ return -EIO;
+
+ xbar = devm_ioremap(dev, res.start, resource_size(&res));
+ if (!xbar)
+ return -EIO;
+
+ ret = edma_of_read_u32_to_s16_array(node,
+ "ti,edma-xbar-event-map",
+ (s16 *)xbar_chans,
+ len/sizeof(u32));
+ if (IS_ERR_VALUE(ret))
+ return -EIO;
+
+ for (i = 0; xbar_chans[i][0] != -1; i++) {
+ shift = (xbar_chans[i][1] % 4) * 8;
+ offset = xbar_chans[i][1] >> 2;
+ offset <<= 2;
+ mux = __raw_readl((void *)((u32)xbar + offset));
+ mux &= (~(0xff << shift));
+ mux |= (xbar_chans[i][0] << shift);
+ __raw_writel(mux, (void *)((u32)xbar + offset));
+ }
+
+ pdata->xbar_chans = xbar_chans;
+
+ return 0;
+}
+
static int edma_of_parse_dt(struct device *dev,
struct device_node *node,
struct edma_soc_info *pdata)
@@ -1453,7 +1500,6 @@ static int edma_of_parse_dt(struct device *dev,
pdata->n_slot = value;
pdata->n_cc = 1;
- /* This is unused */
pdata->n_tc = 3;
rsv_info =
@@ -1538,6 +1584,10 @@ static int edma_of_parse_dt(struct device *dev,
return ret;
pdata->default_queue = value;
+ prop = of_find_property(node, "ti,edma-xbar-event-map", &sz);
+ if (prop)
+ ret = edma_xbar_event_map(dev, node, pdata, sz);
+
return ret;
}
@@ -1554,6 +1604,7 @@ static int __init edma_probe(struct platform_device *pdev)
int status = -1;
s16 (*rsv_chans)[2];
s16 (*rsv_slots)[2];
+ s16 (*xbar_chans)[2];
int irq[EDMA_MAX_CC] = {0, 0};
int err_irq[EDMA_MAX_CC] = {0, 0};
struct resource *r[EDMA_MAX_CC] = {NULL, NULL};
@@ -1678,6 +1729,16 @@ static int __init edma_probe(struct platform_device *pdev)
}
}
+ /* Clear the xbar mapped channels in unused list */
+ xbar_chans = info[j]->xbar_chans;
+ if (xbar_chans) {
+ for (i = 0; xbar_chans[i][1] != -1; i++) {
+ off = xbar_chans[i][1];
+ clear_bits(off, 1,
+ edma_cc[j]->edma_unused);
+ }
+ }
+
if (node)
irq[j] = irq_of_parse_and_map(node, 0);
else {
diff --git a/include/linux/platform_data/edma.h b/include/linux/platform_data/edma.h
index b20b586..888a3c6 100644
--- a/include/linux/platform_data/edma.h
+++ b/include/linux/platform_data/edma.h
@@ -191,6 +191,7 @@ struct edma_soc_info {
/* Resource reservation for other cores */
struct edma_rsv_info *rsv;
+ s16 (*xbar_chans)[2];
s8 (*queue_tc_mapping)[2];
s8 (*queue_priority_mapping)[2];
};
--
1.7.9.5
^ permalink raw reply related
* [RFC PATCH v3 04/16] ARM: edma: add DT and runtime PM support for AM33XX
From: Matt Porter @ 2012-10-18 13:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350566815-409-1-git-send-email-mporter@ti.com>
Adds support for parsing the TI EDMA DT data into the required
EDMA private API platform data.
Calls runtime PM API only in the DT case in order to unidle the
associated hwmods on AM33XX.
Signed-off-by: Matt Porter <mporter@ti.com>
---
arch/arm/common/edma.c | 255 +++++++++++++++++++++++++--
arch/arm/mach-davinci/board-da830-evm.c | 4 +-
arch/arm/mach-davinci/board-da850-evm.c | 8 +-
arch/arm/mach-davinci/board-dm646x-evm.c | 4 +-
arch/arm/mach-davinci/board-omapl138-hawk.c | 8 +-
arch/arm/mach-davinci/devices-da8xx.c | 8 +-
arch/arm/mach-davinci/devices-tnetv107x.c | 4 +-
arch/arm/mach-davinci/dm355.c | 4 +-
arch/arm/mach-davinci/dm365.c | 4 +-
arch/arm/mach-davinci/dm644x.c | 4 +-
arch/arm/mach-davinci/dm646x.c | 4 +-
include/linux/platform_data/edma.h | 8 +-
12 files changed, 272 insertions(+), 43 deletions(-)
diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c
index a3d189d..6d2a590 100644
--- a/arch/arm/common/edma.c
+++ b/arch/arm/common/edma.c
@@ -24,6 +24,13 @@
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/slab.h>
+#include <linux/edma.h>
+#include <linux/err.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/of_dma.h>
+#include <linux/of_irq.h>
+#include <linux/pm_runtime.h>
#include <linux/platform_data/edma.h>
@@ -1366,31 +1373,237 @@ void edma_clear_event(unsigned channel)
EXPORT_SYMBOL(edma_clear_event);
/*-----------------------------------------------------------------------*/
+static int edma_of_read_u32_to_s8_array(const struct device_node *np,
+ const char *propname, s8 *out_values,
+ size_t sz)
+{
+ struct property *prop = of_find_property(np, propname, NULL);
+ const __be32 *val;
+
+ if (!prop)
+ return -EINVAL;
+ if (!prop->value)
+ return -ENODATA;
+ if ((sz * sizeof(u32)) > prop->length)
+ return -EOVERFLOW;
+
+ val = prop->value;
+
+ while (sz--)
+ *out_values++ = (s8)(be32_to_cpup(val++) & 0xff);
+
+ /* Terminate it */
+ *out_values++ = -1;
+ *out_values++ = -1;
+
+ return 0;
+}
+
+static int edma_of_read_u32_to_s16_array(const struct device_node *np,
+ const char *propname, s16 *out_values,
+ size_t sz)
+{
+ struct property *prop = of_find_property(np, propname, NULL);
+ const __be32 *val;
+
+ if (!prop)
+ return -EINVAL;
+ if (!prop->value)
+ return -ENODATA;
+ if ((sz * sizeof(u32)) > prop->length)
+ return -EOVERFLOW;
+
+ val = prop->value;
+
+ while (sz--)
+ *out_values++ = (s16)(be32_to_cpup(val++) & 0xffff);
+
+ /* Terminate it */
+ *out_values++ = -1;
+ *out_values++ = -1;
+
+ return 0;
+}
+
+static int edma_of_parse_dt(struct device *dev,
+ struct device_node *node,
+ struct edma_soc_info *pdata)
+{
+ int ret = 0;
+ u32 value;
+ struct property *prop;
+ size_t sz;
+ struct edma_rsv_info *rsv_info;
+ s16 (*rsv_chans)[2], (*rsv_slots)[2];
+ s8 (*queue_tc_map)[2], (*queue_priority_map)[2];
+
+ ret = of_property_read_u32(node, "dma-channels", &value);
+ if (ret < 0)
+ return ret;
+ pdata->n_channel = value;
+
+ ret = of_property_read_u32(node, "ti,edma-regions", &value);
+ if (ret < 0)
+ return ret;
+ pdata->n_region = value;
+
+ ret = of_property_read_u32(node, "ti,edma-slots", &value);
+ if (ret < 0)
+ return ret;
+ pdata->n_slot = value;
+
+ pdata->n_cc = 1;
+ /* This is unused */
+ pdata->n_tc = 3;
+
+ rsv_info =
+ devm_kzalloc(dev, sizeof(struct edma_rsv_info), GFP_KERNEL);
+ if (!rsv_info)
+ return -ENOMEM;
+ pdata->rsv = rsv_info;
+
+ /* Build the reserved channel/slots arrays */
+ prop = of_find_property(node, "ti,edma-reserved-channels", &sz);
+ if (prop) {
+ rsv_chans = devm_kzalloc(dev,
+ sz/sizeof(s16) + 2*sizeof(s16),
+ GFP_KERNEL);
+ if (!rsv_chans)
+ return -ENOMEM;
+ pdata->rsv->rsv_chans = rsv_chans;
+
+ ret = edma_of_read_u32_to_s16_array(node,
+ "ti,edma-reserved-channels",
+ (s16 *)rsv_chans,
+ sz/sizeof(u32));
+ if (ret < 0)
+ return ret;
+ }
+
+ prop = of_find_property(node, "ti,edma-reserved-slots", &sz);
+ if (prop) {
+ rsv_slots = devm_kzalloc(dev,
+ sz/sizeof(s16) + 2*sizeof(s16),
+ GFP_KERNEL);
+ if (!rsv_slots)
+ return -ENOMEM;
+ pdata->rsv->rsv_slots = rsv_slots;
+
+ ret = edma_of_read_u32_to_s16_array(node,
+ "ti,edma-reserved-slots",
+ (s16 *)rsv_slots,
+ sz/sizeof(u32));
+ if (ret < 0)
+ return ret;
+ }
+
+ prop = of_find_property(node, "ti,edma-queue-tc-map", &sz);
+ if (!prop)
+ return -EINVAL;
+
+ queue_tc_map = devm_kzalloc(dev,
+ sz/sizeof(s8) + 2*sizeof(s8),
+ GFP_KERNEL);
+ if (!queue_tc_map)
+ return -ENOMEM;
+ pdata->queue_tc_mapping = queue_tc_map;
+
+ ret = edma_of_read_u32_to_s8_array(node,
+ "ti,edma-queue-tc-map",
+ (s8 *)queue_tc_map,
+ sz/sizeof(u32));
+ if (ret < 0)
+ return ret;
+
+ prop = of_find_property(node, "ti,edma-queue-priority-map", &sz);
+ if (!prop)
+ return -EINVAL;
+
+ queue_priority_map = devm_kzalloc(dev,
+ sz/sizeof(s8) + 2*sizeof(s8),
+ GFP_KERNEL);
+ if (!queue_priority_map)
+ return -ENOMEM;
+ pdata->queue_priority_mapping = queue_priority_map;
+
+ ret = edma_of_read_u32_to_s8_array(node,
+ "ti,edma-queue-tc-map",
+ (s8 *)queue_priority_map,
+ sz/sizeof(u32));
+ if (ret < 0)
+ return ret;
+
+ ret = of_property_read_u32(node, "ti,edma-default-queue", &value);
+ if (ret < 0)
+ return ret;
+ pdata->default_queue = value;
+
+ return ret;
+}
+
+static struct of_dma_filter_info edma_filter_info = {
+ .filter_fn = edma_filter_fn,
+};
static int __init edma_probe(struct platform_device *pdev)
{
struct edma_soc_info **info = pdev->dev.platform_data;
- const s8 (*queue_priority_mapping)[2];
- const s8 (*queue_tc_mapping)[2];
+ s8 (*queue_priority_mapping)[2];
+ s8 (*queue_tc_mapping)[2];
int i, j, off, ln, found = 0;
int status = -1;
- const s16 (*rsv_chans)[2];
- const s16 (*rsv_slots)[2];
+ s16 (*rsv_chans)[2];
+ s16 (*rsv_slots)[2];
int irq[EDMA_MAX_CC] = {0, 0};
int err_irq[EDMA_MAX_CC] = {0, 0};
- struct resource *r[EDMA_MAX_CC] = {NULL};
+ struct resource *r[EDMA_MAX_CC] = {NULL, NULL};
+ struct resource res[EDMA_MAX_CC];
resource_size_t len[EDMA_MAX_CC];
char res_name[10];
char irq_name[10];
+ struct device_node *node = pdev->dev.of_node;
+ struct device *dev = &pdev->dev;
+ struct edma_soc_info *pdata;
+ int ret;
+
+ if (node) {
+ pdata = devm_kzalloc(dev,
+ sizeof(struct edma_soc_info),
+ GFP_KERNEL);
+ edma_of_parse_dt(dev, node, pdata);
+ info = &pdata;
+ dma_cap_set(DMA_SLAVE, edma_filter_info.dma_cap);
+ of_dma_controller_register(dev->of_node,
+ of_dma_simple_xlate,
+ &edma_filter_info);
+ pm_runtime_enable(dev);
+ ret = pm_runtime_get_sync(dev);
+ if (IS_ERR_VALUE(ret)) {
+ dev_err(dev, "pm_runtime_get_sync() failed\n");
+ return ret;
+ }
+ }
if (!info)
return -ENODEV;
for (j = 0; j < EDMA_MAX_CC; j++) {
- sprintf(res_name, "edma_cc%d", j);
- r[j] = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+ if (!info[j]) {
+ if (!found)
+ return -ENODEV;
+ break;
+ }
+ if (node) {
+ ret = of_address_to_resource(node, j, &res[j]);
+ if (!IS_ERR_VALUE(ret))
+ r[j] = &res[j];
+ } else {
+ sprintf(res_name, "edma_cc%d", j);
+ r[j] = platform_get_resource_byname(pdev,
+ IORESOURCE_MEM,
res_name);
- if (!r[j] || !info[j]) {
+ }
+ if (!r[j]) {
if (found)
break;
else
@@ -1465,8 +1678,12 @@ static int __init edma_probe(struct platform_device *pdev)
}
}
- sprintf(irq_name, "edma%d", j);
- irq[j] = platform_get_irq_byname(pdev, irq_name);
+ if (node)
+ irq[j] = irq_of_parse_and_map(node, 0);
+ else {
+ sprintf(irq_name, "edma%d", j);
+ irq[j] = platform_get_irq_byname(pdev, irq_name);
+ }
edma_cc[j]->irq_res_start = irq[j];
status = request_irq(irq[j], dma_irq_handler, 0, "edma",
&pdev->dev);
@@ -1476,8 +1693,12 @@ static int __init edma_probe(struct platform_device *pdev)
goto fail;
}
- sprintf(irq_name, "edma%d_err", j);
- err_irq[j] = platform_get_irq_byname(pdev, irq_name);
+ if (node)
+ err_irq[j] = irq_of_parse_and_map(node, 2);
+ else {
+ sprintf(irq_name, "edma%d_err", j);
+ err_irq[j] = platform_get_irq_byname(pdev, irq_name);
+ }
edma_cc[j]->irq_res_end = err_irq[j];
status = request_irq(err_irq[j], dma_ccerr_handler, 0,
"edma_error", &pdev->dev);
@@ -1538,9 +1759,17 @@ fail1:
return status;
}
+static const struct of_device_id edma_of_ids[] = {
+ { .compatible = "ti,edma3", },
+ {}
+};
static struct platform_driver edma_driver = {
- .driver.name = "edma",
+ .driver = {
+ .name = "edma",
+ .of_match_table = edma_of_ids,
+ },
+ .probe = edma_probe,
};
static int __init edma_init(void)
diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index 95b5e10..ffcbec1 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -512,7 +512,7 @@ static struct davinci_i2c_platform_data da830_evm_i2c_0_pdata = {
* example: Timer, GPIO, UART events etc) on da830/omap-l137 EVM, hence
* they are being reserved for codecs on the DSP side.
*/
-static const s16 da830_dma_rsv_chans[][2] = {
+static s16 da830_dma_rsv_chans[][2] = {
/* (offset, number) */
{ 8, 2},
{12, 2},
@@ -521,7 +521,7 @@ static const s16 da830_dma_rsv_chans[][2] = {
{-1, -1}
};
-static const s16 da830_dma_rsv_slots[][2] = {
+static s16 da830_dma_rsv_slots[][2] = {
/* (offset, number) */
{ 8, 2},
{12, 2},
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index 32ee3f8..f207965 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -1097,7 +1097,7 @@ device_initcall(da850_evm_config_emac);
* example: Timer, GPIO, UART events etc) on da850/omap-l138 EVM, hence
* they are being reserved for codecs on the DSP side.
*/
-static const s16 da850_dma0_rsv_chans[][2] = {
+static s16 da850_dma0_rsv_chans[][2] = {
/* (offset, number) */
{ 8, 6},
{24, 4},
@@ -1105,7 +1105,7 @@ static const s16 da850_dma0_rsv_chans[][2] = {
{-1, -1}
};
-static const s16 da850_dma0_rsv_slots[][2] = {
+static s16 da850_dma0_rsv_slots[][2] = {
/* (offset, number) */
{ 8, 6},
{24, 4},
@@ -1113,14 +1113,14 @@ static const s16 da850_dma0_rsv_slots[][2] = {
{-1, -1}
};
-static const s16 da850_dma1_rsv_chans[][2] = {
+static s16 da850_dma1_rsv_chans[][2] = {
/* (offset, number) */
{ 0, 28},
{30, 2},
{-1, -1}
};
-static const s16 da850_dma1_rsv_slots[][2] = {
+static s16 da850_dma1_rsv_slots[][2] = {
/* (offset, number) */
{ 0, 28},
{30, 90},
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index 1dbf85b..6c5b814 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -764,7 +764,7 @@ static struct davinci_uart_config uart_config __initdata = {
* example: Timer, GPIO, UART events etc) on dm646x, hence they are being
* reserved for codecs on the DSP side.
*/
-static const s16 dm646x_dma_rsv_chans[][2] = {
+static s16 dm646x_dma_rsv_chans[][2] = {
/* (offset, number) */
{ 0, 4},
{13, 3},
@@ -774,7 +774,7 @@ static const s16 dm646x_dma_rsv_chans[][2] = {
{-1, -1}
};
-static const s16 dm646x_dma_rsv_slots[][2] = {
+static s16 dm646x_dma_rsv_slots[][2] = {
/* (offset, number) */
{ 0, 4},
{13, 3},
diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c b/arch/arm/mach-davinci/board-omapl138-hawk.c
index dc1208e..09c34f8 100644
--- a/arch/arm/mach-davinci/board-omapl138-hawk.c
+++ b/arch/arm/mach-davinci/board-omapl138-hawk.c
@@ -70,7 +70,7 @@ static __init void omapl138_hawk_config_emac(void)
* example: Timer, GPIO, UART events etc) on da850/omap-l138 EVM/Hawkboard,
* hence they are being reserved for codecs on the DSP side.
*/
-static const s16 da850_dma0_rsv_chans[][2] = {
+static s16 da850_dma0_rsv_chans[][2] = {
/* (offset, number) */
{ 8, 6},
{24, 4},
@@ -78,7 +78,7 @@ static const s16 da850_dma0_rsv_chans[][2] = {
{-1, -1}
};
-static const s16 da850_dma0_rsv_slots[][2] = {
+static s16 da850_dma0_rsv_slots[][2] = {
/* (offset, number) */
{ 8, 6},
{24, 4},
@@ -86,14 +86,14 @@ static const s16 da850_dma0_rsv_slots[][2] = {
{-1, -1}
};
-static const s16 da850_dma1_rsv_chans[][2] = {
+static s16 da850_dma1_rsv_chans[][2] = {
/* (offset, number) */
{ 0, 28},
{30, 2},
{-1, -1}
};
-static const s16 da850_dma1_rsv_slots[][2] = {
+static s16 da850_dma1_rsv_slots[][2] = {
/* (offset, number) */
{ 0, 28},
{30, 90},
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index bd2f72b..1f9c6ff 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -103,27 +103,27 @@ struct platform_device da8xx_serial_device = {
},
};
-static const s8 da8xx_queue_tc_mapping[][2] = {
+static s8 da8xx_queue_tc_mapping[][2] = {
/* {event queue no, TC no} */
{0, 0},
{1, 1},
{-1, -1}
};
-static const s8 da8xx_queue_priority_mapping[][2] = {
+static s8 da8xx_queue_priority_mapping[][2] = {
/* {event queue no, Priority} */
{0, 3},
{1, 7},
{-1, -1}
};
-static const s8 da850_queue_tc_mapping[][2] = {
+static s8 da850_queue_tc_mapping[][2] = {
/* {event queue no, TC no} */
{0, 0},
{-1, -1}
};
-static const s8 da850_queue_priority_mapping[][2] = {
+static s8 da850_queue_priority_mapping[][2] = {
/* {event queue no, Priority} */
{0, 3},
{-1, -1}
diff --git a/arch/arm/mach-davinci/devices-tnetv107x.c b/arch/arm/mach-davinci/devices-tnetv107x.c
index 59efd7f..d2453c9 100644
--- a/arch/arm/mach-davinci/devices-tnetv107x.c
+++ b/arch/arm/mach-davinci/devices-tnetv107x.c
@@ -58,14 +58,14 @@
#define TNETV107X_DMACH_SDIO1_RX 28
#define TNETV107X_DMACH_SDIO1_TX 29
-static const s8 edma_tc_mapping[][2] = {
+static s8 edma_tc_mapping[][2] = {
/* event queue no TC no */
{ 0, 0 },
{ 1, 1 },
{ -1, -1 }
};
-static const s8 edma_priority_mapping[][2] = {
+static s8 edma_priority_mapping[][2] = {
/* event queue no Prio */
{ 0, 3 },
{ 1, 7 },
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index b165c27..cdefef3 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -567,7 +567,7 @@ static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
/*----------------------------------------------------------------------*/
-static const s8
+static s8
queue_tc_mapping[][2] = {
/* {event queue no, TC no} */
{0, 0},
@@ -575,7 +575,7 @@ queue_tc_mapping[][2] = {
{-1, -1},
};
-static const s8
+static s8
queue_priority_mapping[][2] = {
/* {event queue no, Priority} */
{0, 3},
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index a611716..801e162 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -822,7 +822,7 @@ static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = {
};
/* Four Transfer Controllers on DM365 */
-static const s8
+static s8
dm365_queue_tc_mapping[][2] = {
/* {event queue no, TC no} */
{0, 0},
@@ -832,7 +832,7 @@ dm365_queue_tc_mapping[][2] = {
{-1, -1},
};
-static const s8
+static s8
dm365_queue_priority_mapping[][2] = {
/* {event queue no, Priority} */
{0, 7},
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 90f5639..4799fd9 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -497,7 +497,7 @@ static u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
/*----------------------------------------------------------------------*/
-static const s8
+static s8
queue_tc_mapping[][2] = {
/* {event queue no, TC no} */
{0, 0},
@@ -505,7 +505,7 @@ queue_tc_mapping[][2] = {
{-1, -1},
};
-static const s8
+static s8
queue_priority_mapping[][2] = {
/* {event queue no, Priority} */
{0, 3},
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 08f9dab..b4a4da6 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -531,7 +531,7 @@ static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
/*----------------------------------------------------------------------*/
/* Four Transfer Controllers on DM646x */
-static const s8
+static s8
dm646x_queue_tc_mapping[][2] = {
/* {event queue no, TC no} */
{0, 0},
@@ -541,7 +541,7 @@ dm646x_queue_tc_mapping[][2] = {
{-1, -1},
};
-static const s8
+static s8
dm646x_queue_priority_mapping[][2] = {
/* {event queue no, Priority} */
{0, 4},
diff --git a/include/linux/platform_data/edma.h b/include/linux/platform_data/edma.h
index 7396f0b3..b20b586 100644
--- a/include/linux/platform_data/edma.h
+++ b/include/linux/platform_data/edma.h
@@ -168,8 +168,8 @@ void edma_resume(unsigned channel);
struct edma_rsv_info {
- const s16 (*rsv_chans)[2];
- const s16 (*rsv_slots)[2];
+ s16 (*rsv_chans)[2];
+ s16 (*rsv_slots)[2];
};
/* platform_data for EDMA driver */
@@ -191,8 +191,8 @@ struct edma_soc_info {
/* Resource reservation for other cores */
struct edma_rsv_info *rsv;
- const s8 (*queue_tc_mapping)[2];
- const s8 (*queue_priority_mapping)[2];
+ s8 (*queue_tc_mapping)[2];
+ s8 (*queue_priority_mapping)[2];
};
#endif
--
1.7.9.5
^ permalink raw reply related
* [RFC PATCH v3 03/16] ARM: edma: remove unused transfer controller handlers
From: Matt Porter @ 2012-10-18 13:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350566815-409-1-git-send-email-mporter@ti.com>
Fix build on OMAP, the irqs are undefined on AM33xx.
These error interrupt handlers were hardcoded as disabled
so since they are unused code, simply remove them.
Signed-off-by: Matt Porter <mporter@ti.com>
---
arch/arm/common/edma.c | 37 -------------------------------------
1 file changed, 37 deletions(-)
diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c
index 4411087..a3d189d 100644
--- a/arch/arm/common/edma.c
+++ b/arch/arm/common/edma.c
@@ -494,26 +494,6 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
return IRQ_HANDLED;
}
-/******************************************************************************
- *
- * Transfer controller error interrupt handlers
- *
- *****************************************************************************/
-
-#define tc_errs_handled false /* disabled as long as they're NOPs */
-
-static irqreturn_t dma_tc0err_handler(int irq, void *data)
-{
- dev_dbg(data, "dma_tc0err_handler\n");
- return IRQ_HANDLED;
-}
-
-static irqreturn_t dma_tc1err_handler(int irq, void *data)
-{
- dev_dbg(data, "dma_tc1err_handler\n");
- return IRQ_HANDLED;
-}
-
static int reserve_contiguous_slots(int ctlr, unsigned int id,
unsigned int num_slots,
unsigned int start_slot)
@@ -1538,23 +1518,6 @@ static int __init edma_probe(struct platform_device *pdev)
arch_num_cc++;
}
- if (tc_errs_handled) {
- status = request_irq(IRQ_TCERRINT0, dma_tc0err_handler, 0,
- "edma_tc0", &pdev->dev);
- if (status < 0) {
- dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n",
- IRQ_TCERRINT0, status);
- return status;
- }
- status = request_irq(IRQ_TCERRINT, dma_tc1err_handler, 0,
- "edma_tc1", &pdev->dev);
- if (status < 0) {
- dev_dbg(&pdev->dev, "request_irq %d --> %d\n",
- IRQ_TCERRINT, status);
- return status;
- }
- }
-
return 0;
fail:
--
1.7.9.5
^ permalink raw reply related
* [RFC PATCH v3 02/16] ARM: davinci: move private EDMA API to arm/common
From: Matt Porter @ 2012-10-18 13:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350566815-409-1-git-send-email-mporter@ti.com>
Move mach-davinci/dma.c to common/edma.c so it can be used
by OMAP (specifically AM33xx) as well. This just moves the
private EDMA API but does not support OMAP.
Signed-off-by: Matt Porter <mporter@ti.com>
---
arch/arm/Kconfig | 1 +
arch/arm/common/Kconfig | 3 +
arch/arm/common/Makefile | 1 +
arch/arm/{mach-davinci/dma.c => common/edma.c} | 2 +-
arch/arm/mach-davinci/Makefile | 2 +-
arch/arm/mach-davinci/board-tnetv107x-evm.c | 2 +-
arch/arm/mach-davinci/davinci.h | 2 +-
arch/arm/mach-davinci/devices-tnetv107x.c | 2 +-
arch/arm/mach-davinci/devices.c | 7 +-
arch/arm/mach-davinci/dm355.c | 2 +-
arch/arm/mach-davinci/dm365.c | 2 +-
arch/arm/mach-davinci/dm644x.c | 2 +-
arch/arm/mach-davinci/dm646x.c | 2 +-
arch/arm/mach-davinci/include/mach/da8xx.h | 2 +-
arch/arm/mach-davinci/include/mach/edma.h | 267 ------------------------
arch/arm/plat-omap/Kconfig | 1 +
drivers/dma/edma.c | 2 +-
drivers/mmc/host/davinci_mmc.c | 1 +
include/linux/mfd/davinci_voicecodec.h | 3 +-
include/linux/platform_data/edma.h | 198 ++++++++++++++++++
include/linux/platform_data/spi-davinci.h | 2 +-
sound/soc/davinci/davinci-evm.c | 1 +
sound/soc/davinci/davinci-pcm.c | 1 +
sound/soc/davinci/davinci-pcm.h | 2 +-
sound/soc/davinci/davinci-sffsdr.c | 6 +-
25 files changed, 228 insertions(+), 288 deletions(-)
rename arch/arm/{mach-davinci/dma.c => common/edma.c} (99%)
delete mode 100644 arch/arm/mach-davinci/include/mach/edma.h
create mode 100644 include/linux/platform_data/edma.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 73067ef..23c2343 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -924,6 +924,7 @@ config ARCH_DAVINCI
select GENERIC_IRQ_CHIP
select HAVE_IDE
select NEED_MACH_GPIO_H
+ select TI_PRIV_EDMA
select ZONE_DMA
help
Support for TI's DaVinci platform.
diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig
index 45ceeb0..9e32d0d 100644
--- a/arch/arm/common/Kconfig
+++ b/arch/arm/common/Kconfig
@@ -40,3 +40,6 @@ config SHARP_PARAM
config SHARP_SCOOP
bool
+
+config TI_PRIV_EDMA
+ bool
diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
index e8a4e58..d09a39b 100644
--- a/arch/arm/common/Makefile
+++ b/arch/arm/common/Makefile
@@ -13,3 +13,4 @@ obj-$(CONFIG_SHARP_PARAM) += sharpsl_param.o
obj-$(CONFIG_SHARP_SCOOP) += scoop.o
obj-$(CONFIG_PCI_HOST_ITE8152) += it8152.o
obj-$(CONFIG_ARM_TIMER_SP804) += timer-sp.o
+obj-$(CONFIG_TI_PRIV_EDMA) += edma.o
diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/common/edma.c
similarity index 99%
rename from arch/arm/mach-davinci/dma.c
rename to arch/arm/common/edma.c
index a685e97..4411087 100644
--- a/arch/arm/mach-davinci/dma.c
+++ b/arch/arm/common/edma.c
@@ -25,7 +25,7 @@
#include <linux/io.h>
#include <linux/slab.h>
-#include <mach/edma.h>
+#include <linux/platform_data/edma.h>
/* Offsets matching "struct edmacc_param" */
#define PARM_OPT 0x00
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index 2227eff..97c639e 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -5,7 +5,7 @@
# Common objects
obj-y := time.o clock.o serial.o psc.o \
- dma.o usb.o common.o sram.o aemif.o
+ usb.o common.o sram.o aemif.o
obj-$(CONFIG_DAVINCI_MUX) += mux.o
diff --git a/arch/arm/mach-davinci/board-tnetv107x-evm.c b/arch/arm/mach-davinci/board-tnetv107x-evm.c
index be30997..86f55ba 100644
--- a/arch/arm/mach-davinci/board-tnetv107x-evm.c
+++ b/arch/arm/mach-davinci/board-tnetv107x-evm.c
@@ -26,12 +26,12 @@
#include <linux/input.h>
#include <linux/input/matrix_keypad.h>
#include <linux/spi/spi.h>
+#include <linux/platform_data/edma.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
#include <mach/irqs.h>
-#include <mach/edma.h>
#include <mach/mux.h>
#include <mach/cp_intc.h>
#include <mach/tnetv107x.h>
diff --git a/arch/arm/mach-davinci/davinci.h b/arch/arm/mach-davinci/davinci.h
index 12d544b..d26a6bc 100644
--- a/arch/arm/mach-davinci/davinci.h
+++ b/arch/arm/mach-davinci/davinci.h
@@ -23,9 +23,9 @@
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/platform_data/davinci_asp.h>
+#include <linux/platform_data/edma.h>
#include <linux/platform_data/keyscan-davinci.h>
#include <mach/hardware.h>
-#include <mach/edma.h>
#include <media/davinci/vpfe_capture.h>
#include <media/davinci/vpif_types.h>
diff --git a/arch/arm/mach-davinci/devices-tnetv107x.c b/arch/arm/mach-davinci/devices-tnetv107x.c
index 29b17f7..59efd7f 100644
--- a/arch/arm/mach-davinci/devices-tnetv107x.c
+++ b/arch/arm/mach-davinci/devices-tnetv107x.c
@@ -18,10 +18,10 @@
#include <linux/dma-mapping.h>
#include <linux/clk.h>
#include <linux/slab.h>
+#include <linux/platform_data/edma.h>
#include <mach/common.h>
#include <mach/irqs.h>
-#include <mach/edma.h>
#include <mach/tnetv107x.h>
#include "clock.h"
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index 4c48a36..f45d591 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -19,9 +19,10 @@
#include <mach/irqs.h>
#include <mach/cputype.h>
#include <mach/mux.h>
-#include <mach/edma.h>
#include <linux/platform_data/mmc-davinci.h>
#include <mach/time.h>
+#include <linux/platform_data/edma.h>
+
#include "davinci.h"
#include "clock.h"
@@ -141,10 +142,10 @@ static struct resource mmcsd0_resources[] = {
},
/* DMA channels: RX, then TX */
{
- .start = EDMA_CTLR_CHAN(0, DAVINCI_DMA_MMCRXEVT),
+ .start = EDMA_CTLR_CHAN(0, 26),
.flags = IORESOURCE_DMA,
}, {
- .start = EDMA_CTLR_CHAN(0, DAVINCI_DMA_MMCTXEVT),
+ .start = EDMA_CTLR_CHAN(0, 27),
.flags = IORESOURCE_DMA,
},
};
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index a255434..b165c27 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -19,7 +19,6 @@
#include <asm/mach/map.h>
#include <mach/cputype.h>
-#include <mach/edma.h>
#include <mach/psc.h>
#include <mach/mux.h>
#include <mach/irqs.h>
@@ -28,6 +27,7 @@
#include <mach/common.h>
#include <linux/platform_data/spi-davinci.h>
#include <mach/gpio-davinci.h>
+#include <linux/platform_data/edma.h>
#include "davinci.h"
#include "clock.h"
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index b680c83..a611716 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -18,11 +18,11 @@
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/spi/spi.h>
+#include <linux/platform_data/edma.h>
#include <asm/mach/map.h>
#include <mach/cputype.h>
-#include <mach/edma.h>
#include <mach/psc.h>
#include <mach/mux.h>
#include <mach/irqs.h>
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index cd0c8b1..90f5639 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -12,11 +12,11 @@
#include <linux/clk.h>
#include <linux/serial_8250.h>
#include <linux/platform_device.h>
+#include <linux/platform_data/edma.h>
#include <asm/mach/map.h>
#include <mach/cputype.h>
-#include <mach/edma.h>
#include <mach/irqs.h>
#include <mach/psc.h>
#include <mach/mux.h>
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 97c0f8e..08f9dab 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -13,11 +13,11 @@
#include <linux/clk.h>
#include <linux/serial_8250.h>
#include <linux/platform_device.h>
+#include <linux/platform_data/edma.h>
#include <asm/mach/map.h>
#include <mach/cputype.h>
-#include <mach/edma.h>
#include <mach/irqs.h>
#include <mach/psc.h>
#include <mach/mux.h>
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index aaccdc4..4380691 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -20,8 +20,8 @@
#include <linux/videodev2.h>
#include <mach/serial.h>
-#include <mach/edma.h>
#include <mach/pm.h>
+#include <linux/platform_data/edma.h>
#include <linux/platform_data/i2c-davinci.h>
#include <linux/platform_data/mmc-davinci.h>
#include <linux/platform_data/usb-davinci.h>
diff --git a/arch/arm/mach-davinci/include/mach/edma.h b/arch/arm/mach-davinci/include/mach/edma.h
deleted file mode 100644
index 7e84c90..0000000
--- a/arch/arm/mach-davinci/include/mach/edma.h
+++ /dev/null
@@ -1,267 +0,0 @@
-/*
- * TI DAVINCI dma definitions
- *
- * Copyright (C) 2006-2009 Texas Instruments.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-/*
- * This EDMA3 programming framework exposes two basic kinds of resource:
- *
- * Channel Triggers transfers, usually from a hardware event but
- * also manually or by "chaining" from DMA completions.
- * Each channel is coupled to a Parameter RAM (PaRAM) slot.
- *
- * Slot Each PaRAM slot holds a DMA transfer descriptor (PaRAM
- * "set"), source and destination addresses, a link to a
- * next PaRAM slot (if any), options for the transfer, and
- * instructions for updating those addresses. There are
- * more than twice as many slots as event channels.
- *
- * Each PaRAM set describes a sequence of transfers, either for one large
- * buffer or for several discontiguous smaller buffers. An EDMA transfer
- * is driven only from a channel, which performs the transfers specified
- * in its PaRAM slot until there are no more transfers. When that last
- * transfer completes, the "link" field may be used to reload the channel's
- * PaRAM slot with a new transfer descriptor.
- *
- * The EDMA Channel Controller (CC) maps requests from channels into physical
- * Transfer Controller (TC) requests when the channel triggers (by hardware
- * or software events, or by chaining). The two physical DMA channels provided
- * by the TCs are thus shared by many logical channels.
- *
- * DaVinci hardware also has a "QDMA" mechanism which is not currently
- * supported through this interface. (DSP firmware uses it though.)
- */
-
-#ifndef EDMA_H_
-#define EDMA_H_
-
-/* PaRAM slots are laid out like this */
-struct edmacc_param {
- unsigned int opt;
- unsigned int src;
- unsigned int a_b_cnt;
- unsigned int dst;
- unsigned int src_dst_bidx;
- unsigned int link_bcntrld;
- unsigned int src_dst_cidx;
- unsigned int ccnt;
-};
-
-#define CCINT0_INTERRUPT 16
-#define CCERRINT_INTERRUPT 17
-#define TCERRINT0_INTERRUPT 18
-#define TCERRINT1_INTERRUPT 19
-
-/* fields in edmacc_param.opt */
-#define SAM BIT(0)
-#define DAM BIT(1)
-#define SYNCDIM BIT(2)
-#define STATIC BIT(3)
-#define EDMA_FWID (0x07 << 8)
-#define TCCMODE BIT(11)
-#define EDMA_TCC(t) ((t) << 12)
-#define TCINTEN BIT(20)
-#define ITCINTEN BIT(21)
-#define TCCHEN BIT(22)
-#define ITCCHEN BIT(23)
-
-#define TRWORD (0x7<<2)
-#define PAENTRY (0x1ff<<5)
-
-/* Drivers should avoid using these symbolic names for dm644x
- * channels, and use platform_device IORESOURCE_DMA resources
- * instead. (Other DaVinci chips have different peripherals
- * and thus have different DMA channel mappings.)
- */
-#define DAVINCI_DMA_MCBSP_TX 2
-#define DAVINCI_DMA_MCBSP_RX 3
-#define DAVINCI_DMA_VPSS_HIST 4
-#define DAVINCI_DMA_VPSS_H3A 5
-#define DAVINCI_DMA_VPSS_PRVU 6
-#define DAVINCI_DMA_VPSS_RSZ 7
-#define DAVINCI_DMA_IMCOP_IMXINT 8
-#define DAVINCI_DMA_IMCOP_VLCDINT 9
-#define DAVINCI_DMA_IMCO_PASQINT 10
-#define DAVINCI_DMA_IMCOP_DSQINT 11
-#define DAVINCI_DMA_SPI_SPIX 16
-#define DAVINCI_DMA_SPI_SPIR 17
-#define DAVINCI_DMA_UART0_URXEVT0 18
-#define DAVINCI_DMA_UART0_UTXEVT0 19
-#define DAVINCI_DMA_UART1_URXEVT1 20
-#define DAVINCI_DMA_UART1_UTXEVT1 21
-#define DAVINCI_DMA_UART2_URXEVT2 22
-#define DAVINCI_DMA_UART2_UTXEVT2 23
-#define DAVINCI_DMA_MEMSTK_MSEVT 24
-#define DAVINCI_DMA_MMCRXEVT 26
-#define DAVINCI_DMA_MMCTXEVT 27
-#define DAVINCI_DMA_I2C_ICREVT 28
-#define DAVINCI_DMA_I2C_ICXEVT 29
-#define DAVINCI_DMA_GPIO_GPINT0 32
-#define DAVINCI_DMA_GPIO_GPINT1 33
-#define DAVINCI_DMA_GPIO_GPINT2 34
-#define DAVINCI_DMA_GPIO_GPINT3 35
-#define DAVINCI_DMA_GPIO_GPINT4 36
-#define DAVINCI_DMA_GPIO_GPINT5 37
-#define DAVINCI_DMA_GPIO_GPINT6 38
-#define DAVINCI_DMA_GPIO_GPINT7 39
-#define DAVINCI_DMA_GPIO_GPBNKINT0 40
-#define DAVINCI_DMA_GPIO_GPBNKINT1 41
-#define DAVINCI_DMA_GPIO_GPBNKINT2 42
-#define DAVINCI_DMA_GPIO_GPBNKINT3 43
-#define DAVINCI_DMA_GPIO_GPBNKINT4 44
-#define DAVINCI_DMA_TIMER0_TINT0 48
-#define DAVINCI_DMA_TIMER1_TINT1 49
-#define DAVINCI_DMA_TIMER2_TINT2 50
-#define DAVINCI_DMA_TIMER3_TINT3 51
-#define DAVINCI_DMA_PWM0 52
-#define DAVINCI_DMA_PWM1 53
-#define DAVINCI_DMA_PWM2 54
-
-/* DA830 specific EDMA3 information */
-#define EDMA_DA830_NUM_DMACH 32
-#define EDMA_DA830_NUM_TCC 32
-#define EDMA_DA830_NUM_PARAMENTRY 128
-#define EDMA_DA830_NUM_EVQUE 2
-#define EDMA_DA830_NUM_TC 2
-#define EDMA_DA830_CHMAP_EXIST 0
-#define EDMA_DA830_NUM_REGIONS 4
-#define DA830_DMACH2EVENT_MAP0 0x000FC03Fu
-#define DA830_DMACH2EVENT_MAP1 0x00000000u
-#define DA830_EDMA_ARM_OWN 0x30FFCCFFu
-
-/*ch_status paramater of callback function possible values*/
-#define DMA_COMPLETE 1
-#define DMA_CC_ERROR 2
-#define DMA_TC1_ERROR 3
-#define DMA_TC2_ERROR 4
-
-enum address_mode {
- INCR = 0,
- FIFO = 1
-};
-
-enum fifo_width {
- W8BIT = 0,
- W16BIT = 1,
- W32BIT = 2,
- W64BIT = 3,
- W128BIT = 4,
- W256BIT = 5
-};
-
-enum dma_event_q {
- EVENTQ_0 = 0,
- EVENTQ_1 = 1,
- EVENTQ_2 = 2,
- EVENTQ_3 = 3,
- EVENTQ_DEFAULT = -1
-};
-
-enum sync_dimension {
- ASYNC = 0,
- ABSYNC = 1
-};
-
-#define EDMA_CTLR_CHAN(ctlr, chan) (((ctlr) << 16) | (chan))
-#define EDMA_CTLR(i) ((i) >> 16)
-#define EDMA_CHAN_SLOT(i) ((i) & 0xffff)
-
-#define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */
-#define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */
-#define EDMA_CONT_PARAMS_ANY 1001
-#define EDMA_CONT_PARAMS_FIXED_EXACT 1002
-#define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003
-
-#define EDMA_MAX_CC 2
-
-/* alloc/free DMA channels and their dedicated parameter RAM slots */
-int edma_alloc_channel(int channel,
- void (*callback)(unsigned channel, u16 ch_status, void *data),
- void *data, enum dma_event_q);
-void edma_free_channel(unsigned channel);
-
-/* alloc/free parameter RAM slots */
-int edma_alloc_slot(unsigned ctlr, int slot);
-void edma_free_slot(unsigned slot);
-
-/* alloc/free a set of contiguous parameter RAM slots */
-int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count);
-int edma_free_cont_slots(unsigned slot, int count);
-
-/* calls that operate on part of a parameter RAM slot */
-void edma_set_src(unsigned slot, dma_addr_t src_port,
- enum address_mode mode, enum fifo_width);
-void edma_set_dest(unsigned slot, dma_addr_t dest_port,
- enum address_mode mode, enum fifo_width);
-void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst);
-void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx);
-void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx);
-void edma_set_transfer_params(unsigned slot, u16 acnt, u16 bcnt, u16 ccnt,
- u16 bcnt_rld, enum sync_dimension sync_mode);
-void edma_link(unsigned from, unsigned to);
-void edma_unlink(unsigned from);
-
-/* calls that operate on an entire parameter RAM slot */
-void edma_write_slot(unsigned slot, const struct edmacc_param *params);
-void edma_read_slot(unsigned slot, struct edmacc_param *params);
-
-/* channel control operations */
-int edma_start(unsigned channel);
-void edma_stop(unsigned channel);
-void edma_clean_channel(unsigned channel);
-void edma_clear_event(unsigned channel);
-void edma_pause(unsigned channel);
-void edma_resume(unsigned channel);
-
-struct edma_rsv_info {
-
- const s16 (*rsv_chans)[2];
- const s16 (*rsv_slots)[2];
-};
-
-/* platform_data for EDMA driver */
-struct edma_soc_info {
-
- /* how many dma resources of each type */
- unsigned n_channel;
- unsigned n_region;
- unsigned n_slot;
- unsigned n_tc;
- unsigned n_cc;
- /*
- * Default queue is expected to be a low-priority queue.
- * This way, long transfers on the default queue started
- * by the codec engine will not cause audio defects.
- */
- enum dma_event_q default_queue;
-
- /* Resource reservation for other cores */
- struct edma_rsv_info *rsv;
-
- const s8 (*queue_tc_mapping)[2];
- const s8 (*queue_priority_mapping)[2];
-};
-
-#endif
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index 7cd56ed..153fab8 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -28,6 +28,7 @@ config ARCH_OMAP2PLUS
select OMAP_DM_TIMER
select PROC_DEVICETREE if PROC_FS
select SPARSE_IRQ
+ select TI_PRIV_EDMA
select USE_OF
help
"Systems based on OMAP2, OMAP3, OMAP4 or OMAP5"
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
index fdcf079..47ba7bf 100644
--- a/drivers/dma/edma.c
+++ b/drivers/dma/edma.c
@@ -24,7 +24,7 @@
#include <linux/slab.h>
#include <linux/spinlock.h>
-#include <mach/edma.h>
+#include <linux/platform_data/edma.h>
#include "dmaengine.h"
#include "virt-dma.h"
diff --git a/drivers/mmc/host/davinci_mmc.c b/drivers/mmc/host/davinci_mmc.c
index 2063677..f5d46ea 100644
--- a/drivers/mmc/host/davinci_mmc.c
+++ b/drivers/mmc/host/davinci_mmc.c
@@ -35,6 +35,7 @@
#include <linux/edma.h>
#include <linux/mmc/mmc.h>
+#include <linux/platform_data/edma.h>
#include <linux/platform_data/mmc-davinci.h>
/*
diff --git a/include/linux/mfd/davinci_voicecodec.h b/include/linux/mfd/davinci_voicecodec.h
index 0ab6132..7dd6524 100644
--- a/include/linux/mfd/davinci_voicecodec.h
+++ b/include/linux/mfd/davinci_voicecodec.h
@@ -26,8 +26,7 @@
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/mfd/core.h>
-
-#include <mach/edma.h>
+#include <linux/platform_data/edma.h>
/*
* Register values.
diff --git a/include/linux/platform_data/edma.h b/include/linux/platform_data/edma.h
new file mode 100644
index 0000000..7396f0b3
--- /dev/null
+++ b/include/linux/platform_data/edma.h
@@ -0,0 +1,198 @@
+/*
+ * TI DAVINCI dma definitions
+ *
+ * Copyright (C) 2006-2009 Texas Instruments.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+/*
+ * This EDMA3 programming framework exposes two basic kinds of resource:
+ *
+ * Channel Triggers transfers, usually from a hardware event but
+ * also manually or by "chaining" from DMA completions.
+ * Each channel is coupled to a Parameter RAM (PaRAM) slot.
+ *
+ * Slot Each PaRAM slot holds a DMA transfer descriptor (PaRAM
+ * "set"), source and destination addresses, a link to a
+ * next PaRAM slot (if any), options for the transfer, and
+ * instructions for updating those addresses. There are
+ * more than twice as many slots as event channels.
+ *
+ * Each PaRAM set describes a sequence of transfers, either for one large
+ * buffer or for several discontiguous smaller buffers. An EDMA transfer
+ * is driven only from a channel, which performs the transfers specified
+ * in its PaRAM slot until there are no more transfers. When that last
+ * transfer completes, the "link" field may be used to reload the channel's
+ * PaRAM slot with a new transfer descriptor.
+ *
+ * The EDMA Channel Controller (CC) maps requests from channels into physical
+ * Transfer Controller (TC) requests when the channel triggers (by hardware
+ * or software events, or by chaining). The two physical DMA channels provided
+ * by the TCs are thus shared by many logical channels.
+ *
+ * DaVinci hardware also has a "QDMA" mechanism which is not currently
+ * supported through this interface. (DSP firmware uses it though.)
+ */
+
+#ifndef EDMA_H_
+#define EDMA_H_
+
+/* PaRAM slots are laid out like this */
+struct edmacc_param {
+ unsigned int opt;
+ unsigned int src;
+ unsigned int a_b_cnt;
+ unsigned int dst;
+ unsigned int src_dst_bidx;
+ unsigned int link_bcntrld;
+ unsigned int src_dst_cidx;
+ unsigned int ccnt;
+};
+
+/* fields in edmacc_param.opt */
+#define SAM BIT(0)
+#define DAM BIT(1)
+#define SYNCDIM BIT(2)
+#define STATIC BIT(3)
+#define EDMA_FWID (0x07 << 8)
+#define TCCMODE BIT(11)
+#define EDMA_TCC(t) ((t) << 12)
+#define TCINTEN BIT(20)
+#define ITCINTEN BIT(21)
+#define TCCHEN BIT(22)
+#define ITCCHEN BIT(23)
+
+/*ch_status paramater of callback function possible values*/
+#define DMA_COMPLETE 1
+#define DMA_CC_ERROR 2
+#define DMA_TC1_ERROR 3
+#define DMA_TC2_ERROR 4
+
+enum address_mode {
+ INCR = 0,
+ FIFO = 1
+};
+
+enum fifo_width {
+ W8BIT = 0,
+ W16BIT = 1,
+ W32BIT = 2,
+ W64BIT = 3,
+ W128BIT = 4,
+ W256BIT = 5
+};
+
+enum dma_event_q {
+ EVENTQ_0 = 0,
+ EVENTQ_1 = 1,
+ EVENTQ_2 = 2,
+ EVENTQ_3 = 3,
+ EVENTQ_DEFAULT = -1
+};
+
+enum sync_dimension {
+ ASYNC = 0,
+ ABSYNC = 1
+};
+
+#define EDMA_CTLR_CHAN(ctlr, chan) (((ctlr) << 16) | (chan))
+#define EDMA_CTLR(i) ((i) >> 16)
+#define EDMA_CHAN_SLOT(i) ((i) & 0xffff)
+
+#define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */
+#define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */
+#define EDMA_CONT_PARAMS_ANY 1001
+#define EDMA_CONT_PARAMS_FIXED_EXACT 1002
+#define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003
+
+#define EDMA_MAX_CC 2
+
+/* alloc/free DMA channels and their dedicated parameter RAM slots */
+int edma_alloc_channel(int channel,
+ void (*callback)(unsigned channel, u16 ch_status, void *data),
+ void *data, enum dma_event_q);
+void edma_free_channel(unsigned channel);
+
+/* alloc/free parameter RAM slots */
+int edma_alloc_slot(unsigned ctlr, int slot);
+void edma_free_slot(unsigned slot);
+
+/* alloc/free a set of contiguous parameter RAM slots */
+int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count);
+int edma_free_cont_slots(unsigned slot, int count);
+
+/* calls that operate on part of a parameter RAM slot */
+void edma_set_src(unsigned slot, dma_addr_t src_port,
+ enum address_mode mode, enum fifo_width);
+void edma_set_dest(unsigned slot, dma_addr_t dest_port,
+ enum address_mode mode, enum fifo_width);
+void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst);
+void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx);
+void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx);
+void edma_set_transfer_params(unsigned slot, u16 acnt, u16 bcnt, u16 ccnt,
+ u16 bcnt_rld, enum sync_dimension sync_mode);
+void edma_link(unsigned from, unsigned to);
+void edma_unlink(unsigned from);
+
+/* calls that operate on an entire parameter RAM slot */
+void edma_write_slot(unsigned slot, const struct edmacc_param *params);
+void edma_read_slot(unsigned slot, struct edmacc_param *params);
+
+/* channel control operations */
+int edma_start(unsigned channel);
+void edma_stop(unsigned channel);
+void edma_clean_channel(unsigned channel);
+void edma_clear_event(unsigned channel);
+void edma_pause(unsigned channel);
+void edma_resume(unsigned channel);
+
+struct edma_rsv_info {
+
+ const s16 (*rsv_chans)[2];
+ const s16 (*rsv_slots)[2];
+};
+
+/* platform_data for EDMA driver */
+struct edma_soc_info {
+
+ /* how many dma resources of each type */
+ unsigned n_channel;
+ unsigned n_region;
+ unsigned n_slot;
+ unsigned n_tc;
+ unsigned n_cc;
+ /*
+ * Default queue is expected to be a low-priority queue.
+ * This way, long transfers on the default queue started
+ * by the codec engine will not cause audio defects.
+ */
+ enum dma_event_q default_queue;
+
+ /* Resource reservation for other cores */
+ struct edma_rsv_info *rsv;
+
+ const s8 (*queue_tc_mapping)[2];
+ const s8 (*queue_priority_mapping)[2];
+};
+
+#endif
diff --git a/include/linux/platform_data/spi-davinci.h b/include/linux/platform_data/spi-davinci.h
index 7af305b..8dc2fa47 100644
--- a/include/linux/platform_data/spi-davinci.h
+++ b/include/linux/platform_data/spi-davinci.h
@@ -19,7 +19,7 @@
#ifndef __ARCH_ARM_DAVINCI_SPI_H
#define __ARCH_ARM_DAVINCI_SPI_H
-#include <mach/edma.h>
+#include <linux/platform_data/edma.h>
#define SPI_INTERN_CS 0xFF
diff --git a/sound/soc/davinci/davinci-evm.c b/sound/soc/davinci/davinci-evm.c
index 6fac5af..44365d5 100644
--- a/sound/soc/davinci/davinci-evm.c
+++ b/sound/soc/davinci/davinci-evm.c
@@ -14,6 +14,7 @@
#include <linux/timer.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
+#include <linux/platform_data/edma.h>
#include <linux/i2c.h>
#include <sound/core.h>
#include <sound/pcm.h>
diff --git a/sound/soc/davinci/davinci-pcm.c b/sound/soc/davinci/davinci-pcm.c
index 93ea3bf..c9d1b7a 100644
--- a/sound/soc/davinci/davinci-pcm.c
+++ b/sound/soc/davinci/davinci-pcm.c
@@ -16,6 +16,7 @@
#include <linux/slab.h>
#include <linux/dma-mapping.h>
#include <linux/kernel.h>
+#include <linux/platform_data/edma.h>
#include <sound/core.h>
#include <sound/pcm.h>
diff --git a/sound/soc/davinci/davinci-pcm.h b/sound/soc/davinci/davinci-pcm.h
index fc4d01c..deab6c3 100644
--- a/sound/soc/davinci/davinci-pcm.h
+++ b/sound/soc/davinci/davinci-pcm.h
@@ -13,7 +13,7 @@
#define _DAVINCI_PCM_H
#include <linux/platform_data/davinci_asp.h>
-#include <mach/edma.h>
+#include <linux/platform_data/edma.h>
struct davinci_pcm_dma_params {
int channel; /* sync dma channel ID */
diff --git a/sound/soc/davinci/davinci-sffsdr.c b/sound/soc/davinci/davinci-sffsdr.c
index 5be65aa..5345e63 100644
--- a/sound/soc/davinci/davinci-sffsdr.c
+++ b/sound/soc/davinci/davinci-sffsdr.c
@@ -17,6 +17,7 @@
#include <linux/timer.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
+#include <linux/platform_data/edma.h>
#include <linux/gpio.h>
#include <sound/core.h>
#include <sound/pcm.h>
@@ -28,7 +29,6 @@
#include <asm/plat-sffsdr/sffsdr-fpga.h>
#endif
-#include <mach/edma.h>
#include "../codecs/pcm3008.h"
#include "davinci-pcm.h"
@@ -123,8 +123,8 @@ static struct resource sffsdr_snd_resources[] = {
};
static struct evm_snd_platform_data sffsdr_snd_data = {
- .tx_dma_ch = DAVINCI_DMA_MCBSP_TX,
- .rx_dma_ch = DAVINCI_DMA_MCBSP_RX,
+ .tx_dma_ch = 2,
+ .rx_dma_ch = 3,
};
static struct platform_device *sffsdr_snd_device;
--
1.7.9.5
^ permalink raw reply related
* [RFC PATCH v3 01/16] dmaengine: edma: fix slave config dependency on direction
From: Matt Porter @ 2012-10-18 13:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350566815-409-1-git-send-email-mporter@ti.com>
The edma_slave_config() implementation depends on the
direction field such that it will not properly configure
a slave channel when called without direction set.
This fixes the implementation so that the slave config
is copied as is and prep_slave_sg() handles the
direction dependent handling. spi-omap2-mcspi and
omap_hsmmc both expose this bug as they configure the
slave channel config from a common path with an unconfigured
direction field.
Signed-off-by: Matt Porter <mporter@ti.com>
---
drivers/dma/edma.c | 55 ++++++++++++++++++++++++++--------------------------
1 file changed, 27 insertions(+), 28 deletions(-)
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
index 05aea3c..fdcf079 100644
--- a/drivers/dma/edma.c
+++ b/drivers/dma/edma.c
@@ -69,9 +69,7 @@ struct edma_chan {
int ch_num;
bool alloced;
int slot[EDMA_MAX_SLOTS];
- dma_addr_t addr;
- int addr_width;
- int maxburst;
+ struct dma_slave_config cfg;
};
struct edma_cc {
@@ -178,29 +176,14 @@ static int edma_terminate_all(struct edma_chan *echan)
return 0;
}
-
static int edma_slave_config(struct edma_chan *echan,
- struct dma_slave_config *config)
+ struct dma_slave_config *cfg)
{
- if ((config->src_addr_width > DMA_SLAVE_BUSWIDTH_4_BYTES) ||
- (config->dst_addr_width > DMA_SLAVE_BUSWIDTH_4_BYTES))
+ if (cfg->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES ||
+ cfg->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES)
return -EINVAL;
- if (config->direction == DMA_MEM_TO_DEV) {
- if (config->dst_addr)
- echan->addr = config->dst_addr;
- if (config->dst_addr_width)
- echan->addr_width = config->dst_addr_width;
- if (config->dst_maxburst)
- echan->maxburst = config->dst_maxburst;
- } else if (config->direction == DMA_DEV_TO_MEM) {
- if (config->src_addr)
- echan->addr = config->src_addr;
- if (config->src_addr_width)
- echan->addr_width = config->src_addr_width;
- if (config->src_maxburst)
- echan->maxburst = config->src_maxburst;
- }
+ memcpy(&echan->cfg, cfg, sizeof(echan->cfg));
return 0;
}
@@ -235,6 +218,9 @@ static struct dma_async_tx_descriptor *edma_prep_slave_sg(
struct edma_chan *echan = to_edma_chan(chan);
struct device *dev = chan->device->dev;
struct edma_desc *edesc;
+ dma_addr_t dev_addr;
+ enum dma_slave_buswidth dev_width;
+ u32 burst;
struct scatterlist *sg;
int i;
int acnt, bcnt, ccnt, src, dst, cidx;
@@ -243,7 +229,20 @@ static struct dma_async_tx_descriptor *edma_prep_slave_sg(
if (unlikely(!echan || !sgl || !sg_len))
return NULL;
- if (echan->addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) {
+ if (direction == DMA_DEV_TO_MEM) {
+ dev_addr = echan->cfg.src_addr;
+ dev_width = echan->cfg.src_addr_width;
+ burst = echan->cfg.src_maxburst;
+ } else if (direction == DMA_MEM_TO_DEV) {
+ dev_addr = echan->cfg.dst_addr;
+ dev_width = echan->cfg.dst_addr_width;
+ burst = echan->cfg.dst_maxburst;
+ } else {
+ dev_err(dev, "%s: bad direction?\n", __func__);
+ return NULL;
+ }
+
+ if (dev_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) {
dev_err(dev, "Undefined slave buswidth\n");
return NULL;
}
@@ -275,14 +274,14 @@ static struct dma_async_tx_descriptor *edma_prep_slave_sg(
}
}
- acnt = echan->addr_width;
+ acnt = dev_width;
/*
* If the maxburst is equal to the fifo width, use
* A-synced transfers. This allows for large contiguous
* buffer transfers using only one PaRAM set.
*/
- if (echan->maxburst == 1) {
+ if (burst == 1) {
edesc->absync = false;
ccnt = sg_dma_len(sg) / acnt / (SZ_64K - 1);
bcnt = sg_dma_len(sg) / acnt - ccnt * (SZ_64K - 1);
@@ -302,7 +301,7 @@ static struct dma_async_tx_descriptor *edma_prep_slave_sg(
*/
} else {
edesc->absync = true;
- bcnt = echan->maxburst;
+ bcnt = burst;
ccnt = sg_dma_len(sg) / (acnt * bcnt);
if (ccnt > (SZ_64K - 1)) {
dev_err(dev, "Exceeded max SG segment size\n");
@@ -313,13 +312,13 @@ static struct dma_async_tx_descriptor *edma_prep_slave_sg(
if (direction == DMA_MEM_TO_DEV) {
src = sg_dma_address(sg);
- dst = echan->addr;
+ dst = dev_addr;
src_bidx = acnt;
src_cidx = cidx;
dst_bidx = 0;
dst_cidx = 0;
} else {
- src = echan->addr;
+ src = dev_addr;
dst = sg_dma_address(sg);
src_bidx = 0;
src_cidx = 0;
--
1.7.9.5
^ permalink raw reply related
* [RFC PATCH v3 00/16] DMA Engine support for AM33XX
From: Matt Porter @ 2012-10-18 13:26 UTC (permalink / raw)
To: linux-arm-kernel
Changes since v2:
- Rebased on 3.7-rc1
- Fixed bug in DT/pdata parsing first found by Gururaja
that turned out to be masked by some toolchains
- Dropped unused mach-omap2/devices.c hsmmc patch
- Added AM33XX crossbar DMA event mux support
- Added am335x-evm support
Changes since v1:
- Rebased on top of mainline from 12250d8
- Dropped the feature removal schedule patch
- Implemented dma_request_slave_channel_compat() and
converted the mmc and spi drivers to use it
- Dropped unneeded #address-cells and #size-cells from
EDMA DT support
- Moved private EDMA header to linux/platform_data/ and
removed some unneeded definitions
- Fixed parsing of optional properties
TODO:
- Add dmaengine support for per-channel caps so the
hack to set the maximum segments can be replaced with
a query to the dmaengine driver
This series adds DMA Engine support for AM33xx, which uses
an EDMA DMAC. The EDMA DMAC has been previously supported by only
a private API implementation (much like the situation with OMAP
DMA) found on the DaVinci family of SoCs.
The series applies on top of 3.7-rc1 and the following patches:
- GPMC fails to reserve memory fix:
http://www.spinics.net/lists/linux-omap/msg79675.html
- TPS65910 regulator fix:
https://patchwork.kernel.org/patch/1593651/
- dmaengine DT support from Vinod's dmaengine_dt branch in
git://git.infradead.org/users/vkoul/slave-dma.git since
027478851791df751176398be02a3b1c5f6aa824
The approach taken is similar to how OMAP DMA is being converted to
DMA Engine support. With the functional EDMA private API already
existing in mach-davinci/dma.c, we first move that to an ARM common
area so it can be shared. Adding DT and runtime PM support to the
private EDMA API implementation allows it to run on AM33xx. AM33xx
*only* boots using DT so we leverage Jon's generic DT DMA helpers to
register EDMA DMAC with the of_dma framework and then add support
for calling the dma_request_slave_channel() API to both the mmc
and spi drivers.
With this series both BeagleBone and the AM335x EVM have working
MMC and SPI support.
This is tested on BeagleBone with a SPI framebuffer driver and MMC
rootfs. A trivial gpio DMA event misc driver was used to test the
crossbar DMA event support. It is also tested on the AM335x EVM
with the onboard SPI flash and MMC rootfs. The branch at
https://github.com/ohporter/linux/tree/edma-dmaengine-v3 has the
complete series, dependencies, and some test drivers/defconfigs.
Regression testing was done on AM180x-EVM (which also makes use
of the EDMA dmaengine driver and the EDMA private API) using SD,
SPI flash, and the onboard audio supported by the ASoC Davinci
driver.
After this series, the plan is to convert the last in-tree user
of the private EDMA API (davinci-pcm/mcasp) and then eliminate
the private EDMA API by folding its functionality into
drivers/dma/edma.c.
Matt Porter (16):
dmaengine: edma: fix slave config dependency on direction
ARM: davinci: move private EDMA API to arm/common
ARM: edma: remove unused transfer controller handlers
ARM: edma: add DT and runtime PM support for AM33XX
ARM: edma: add AM33XX crossbar event support
dmaengine: edma: enable build for AM33XX
dmaengine: edma: Add TI EDMA device tree binding
ARM: dts: add AM33XX EDMA support
dmaengine: add dma_request_slave_channel_compat()
mmc: omap_hsmmc: convert to dma_request_slave_channel_compat()
mmc: omap_hsmmc: limit max_segs with the EDMA DMAC
mmc: omap_hsmmc: add generic DMA request support to the DT binding
ARM: dts: add AM33XX MMC support
spi: omap2-mcspi: convert to dma_request_slave_channel_compat()
spi: omap2-mcspi: add generic DMA request support to the DT binding
ARM: dts: add AM33XX SPI support
Documentation/devicetree/bindings/dma/ti-edma.txt | 51 +
.../devicetree/bindings/mmc/ti-omap-hsmmc.txt | 25 +-
Documentation/devicetree/bindings/spi/omap-spi.txt | 27 +-
arch/arm/Kconfig | 1 +
arch/arm/boot/dts/am335x-bone.dts | 23 +
arch/arm/boot/dts/am335x-evm.dts | 15 +
arch/arm/boot/dts/am33xx.dtsi | 101 ++
arch/arm/common/Kconfig | 3 +
arch/arm/common/Makefile | 1 +
arch/arm/common/edma.c | 1841 ++++++++++++++++++++
arch/arm/mach-davinci/Makefile | 2 +-
arch/arm/mach-davinci/board-da830-evm.c | 4 +-
arch/arm/mach-davinci/board-da850-evm.c | 8 +-
arch/arm/mach-davinci/board-dm646x-evm.c | 4 +-
arch/arm/mach-davinci/board-omapl138-hawk.c | 8 +-
arch/arm/mach-davinci/board-tnetv107x-evm.c | 2 +-
arch/arm/mach-davinci/davinci.h | 2 +-
arch/arm/mach-davinci/devices-da8xx.c | 8 +-
arch/arm/mach-davinci/devices-tnetv107x.c | 6 +-
arch/arm/mach-davinci/devices.c | 7 +-
arch/arm/mach-davinci/dm355.c | 6 +-
arch/arm/mach-davinci/dm365.c | 6 +-
arch/arm/mach-davinci/dm644x.c | 6 +-
arch/arm/mach-davinci/dm646x.c | 6 +-
arch/arm/mach-davinci/dma.c | 1588 -----------------
arch/arm/mach-davinci/include/mach/da8xx.h | 2 +-
arch/arm/mach-davinci/include/mach/edma.h | 267 ---
arch/arm/plat-omap/Kconfig | 1 +
drivers/dma/Kconfig | 2 +-
drivers/dma/edma.c | 57 +-
drivers/mmc/host/davinci_mmc.c | 1 +
drivers/mmc/host/omap_hsmmc.c | 20 +-
drivers/spi/spi-omap2-mcspi.c | 65 +-
include/linux/dmaengine.h | 10 +
include/linux/mfd/davinci_voicecodec.h | 3 +-
include/linux/platform_data/edma.h | 199 +++
include/linux/platform_data/spi-davinci.h | 2 +-
sound/soc/davinci/davinci-evm.c | 1 +
sound/soc/davinci/davinci-pcm.c | 1 +
sound/soc/davinci/davinci-pcm.h | 2 +-
sound/soc/davinci/davinci-sffsdr.c | 6 +-
41 files changed, 2436 insertions(+), 1954 deletions(-)
create mode 100644 Documentation/devicetree/bindings/dma/ti-edma.txt
create mode 100644 arch/arm/common/edma.c
delete mode 100644 arch/arm/mach-davinci/dma.c
delete mode 100644 arch/arm/mach-davinci/include/mach/edma.h
create mode 100644 include/linux/platform_data/edma.h
--
1.7.9.5
^ permalink raw reply
* [PATCH 0/5] ARM: OMAP2+: PRM/CM cleanup series for 3.8
From: Santosh Shilimkar @ 2012-10-18 12:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121015224455.18306.89030.stgit@dusk.lan>
On Tuesday 16 October 2012 04:35 AM, Paul Walmsley wrote:
> Consolidate and remove some PRM/CM code in preparation for a future move
> into drivers/:
>
> - Remove some obsolete weak functions that allowed old OMAP4 code to
> reference OMAP2/3 PRM functions
>
> - Split many of the functions in prm2xxx_3xxx.c and cm2xxx_3xxx.c into
> 2xxx- and 3xxx-specific PRM/CM C files
>
> - Move low-level powerdomain and clockdomain register access into the
> appropriate 2xxx- and 3xxx-specific PRM/CM files, and remove
> {power,clock}domainXXXX.c
>
> This series shouldn't have any functional impact.
>
>
Nice work Paul !!
This series and part2 both looks good to me.
Sorry for not being able to help in some of these clean-ups
because of other work priorities as talked at LPC.
Feel free to add my ack for the whole series if you need one.
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
^ permalink raw reply
* [PATCHv9 8/8] ARM: OMAP4: USB: power down MUSB PHY if not used
From: Tero Kristo @ 2012-10-18 12:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121018103334.GA1449@arwen.pp.htv.fi>
On Thu, 2012-10-18 at 13:33 +0300, Felipe Balbi wrote:
> Hi,
>
> On Thu, Oct 18, 2012 at 12:20:10PM +0300, Tero Kristo wrote:
> > Commit c9e4412ab8eb8ef82d645d8749c4ce96ad490007 removed all of the USB
> > PHY functions for OMAP4, but this causes a problem with core retention
> > as the MUSB module remains enabled if omap-usb2 phy driver is not used.
> > This keeps the USB DPLL enabled and prevents l3_init pwrdm from idling.
> >
> > Fixed by adding a minimal function back that disables the USB PHY in
> > case omap-usb2 driver is not used.
> >
> > Signed-off-by: Tero Kristo <t-kristo@ti.com>
> > Cc: Kishon Vijay Abraham I <kishon@ti.com>
> > Cc: Felipe Balbi <balbi@ti.com>
> > Cc: Tony Lindgren <tony@atomide.com>
> > ---
> > arch/arm/mach-omap2/omap_phy_internal.c | 27 +++++++++++++++++++++++++++
> > 1 files changed, 27 insertions(+), 0 deletions(-)
> >
> > diff --git a/arch/arm/mach-omap2/omap_phy_internal.c b/arch/arm/mach-omap2/omap_phy_internal.c
> > index d992db8..6a4b9cf 100644
> > --- a/arch/arm/mach-omap2/omap_phy_internal.c
> > +++ b/arch/arm/mach-omap2/omap_phy_internal.c
> > @@ -33,6 +33,33 @@
> > #include "soc.h"
> > #include "control.h"
> >
> > +#define CONTROL_DEV_CONF 0x300
> > +#define PHY_PD 0x1
> > +
> > +#ifndef CONFIG_OMAP_USB2
>
> this is a tristate, meaning that can be a module.
Ok, so extra check for that needed.
>
> > +static int __init omap4430_phy_power_down(void)
> > +{
> > + void __iomem *ctrl_base;
> > +
> > + if (!cpu_is_omap44xx())
> > + return 0;
> > +
> > + ctrl_base = ioremap(OMAP443X_SCM_BASE, SZ_1K);
> > + if (!ctrl_base) {
> > + pr_err("control module ioremap failed\n");
> > + return -ENOMEM;
> > + }
> > +
> > + /* Power down the phy */
> > + __raw_writel(PHY_PD, ctrl_base + CONTROL_DEV_CONF);
> > +
> > + iounmap(ctrl_base);
> > +
> > + return 0;
> > +}
> > +early_initcall(omap4430_phy_power_down);
> > +#endif
>
> I think you could do it even if the driver is enabled.
Actually not at least now, it looks like the driver is not controlling
this bit at all, so the driver would fail if we do this.
>
> Just to make sure I understand the issue right: is the PHY enabled by
> default or did bootloader left this enabled ?
The reset value for the register is zero (at least according to TRM), so
it is enabled from boot. Also, I couldn't find any code from the u-boot
that would touch this bit with a quick look.
-Tero
^ permalink raw reply
* [PATCH 5/5] ARM: OMAP2/3: clockdomain/PRM/CM: move the low-level clockdomain functions into PRM/CM
From: Russ Dill @ 2012-10-18 12:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121015230545.18306.36852.stgit@dusk.lan>
On Mon, Oct 15, 2012 at 4:05 PM, Paul Walmsley <paul@pwsan.com> wrote:
> Move the low-level SoC-specific clockdomain control functions into
> cm*.c and prm*.c. For example, OMAP2xxx low-level clockdomain
> functions go into cm2xxx.c. Then remove the unnecessary
> clockdomain*xxx*.c files.
>
> The objective is to centralize low-level CM and PRM register accesses
> into the cm*.[ch] and prm*.[ch] files, and then to export an OMAP
> SoC-independent API to higher-level OMAP power management code.
The series looks good
Reviewed-by: Russ.Dill at ti.com
> Signed-off-by: Paul Walmsley <paul@pwsan.com>
> Cc: Rajendra Nayak <rnayak@ti.com>
> Cc: Vaibhav Hiremath <hvaibhav@ti.com>
> ---
> arch/arm/mach-omap2/Makefile | 5
> arch/arm/mach-omap2/clockdomain2xxx_3xxx.c | 340 ----------------------------
> arch/arm/mach-omap2/clockdomain33xx.c | 74 ------
> arch/arm/mach-omap2/clockdomain44xx.c | 151 ------------
> arch/arm/mach-omap2/cm2xxx.c | 86 +++++++
> arch/arm/mach-omap2/cm2xxx_3xxx.h | 12 +
> arch/arm/mach-omap2/cm33xx.c | 56 +++++
> arch/arm/mach-omap2/cm3xxx.c | 169 ++++++++++++++
> arch/arm/mach-omap2/cminst44xx.c | 139 +++++++++++
> arch/arm/mach-omap2/prm2xxx.c | 17 +
> arch/arm/mach-omap2/prm2xxx.h | 6
> arch/arm/mach-omap2/prm2xxx_3xxx.c | 43 ++++
> arch/arm/mach-omap2/prm2xxx_3xxx.h | 8 +
> 13 files changed, 536 insertions(+), 570 deletions(-)
> delete mode 100644 arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
> delete mode 100644 arch/arm/mach-omap2/clockdomain33xx.c
> delete mode 100644 arch/arm/mach-omap2/clockdomain44xx.c
>
> diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
> index 56a3386..3751d56 100644
> --- a/arch/arm/mach-omap2/Makefile
> +++ b/arch/arm/mach-omap2/Makefile
> @@ -133,22 +133,17 @@ obj-$(CONFIG_SOC_OMAP5) += $(powerdomain-common)
> # PRCM clockdomain control
> clockdomain-common += clockdomain.o
> obj-$(CONFIG_ARCH_OMAP2) += $(clockdomain-common)
> -obj-$(CONFIG_ARCH_OMAP2) += clockdomain2xxx_3xxx.o
> obj-$(CONFIG_ARCH_OMAP2) += clockdomains2xxx_3xxx_data.o
> obj-$(CONFIG_SOC_OMAP2420) += clockdomains2420_data.o
> obj-$(CONFIG_SOC_OMAP2430) += clockdomains2430_data.o
> obj-$(CONFIG_ARCH_OMAP3) += $(clockdomain-common)
> -obj-$(CONFIG_ARCH_OMAP3) += clockdomain2xxx_3xxx.o
> obj-$(CONFIG_ARCH_OMAP3) += clockdomains2xxx_3xxx_data.o
> obj-$(CONFIG_ARCH_OMAP3) += clockdomains3xxx_data.o
> obj-$(CONFIG_ARCH_OMAP4) += $(clockdomain-common)
> -obj-$(CONFIG_ARCH_OMAP4) += clockdomain44xx.o
> obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o
> obj-$(CONFIG_SOC_AM33XX) += $(clockdomain-common)
> -obj-$(CONFIG_SOC_AM33XX) += clockdomain33xx.o
> obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o
> obj-$(CONFIG_SOC_OMAP5) += $(clockdomain-common)
> -obj-$(CONFIG_SOC_OMAP5) += clockdomain44xx.o
>
> # Clock framework
> obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o
> diff --git a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
> deleted file mode 100644
> index 658487c..0000000
> --- a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
> +++ /dev/null
> @@ -1,340 +0,0 @@
> -/*
> - * OMAP2 and OMAP3 clockdomain control
> - *
> - * Copyright (C) 2008-2010 Texas Instruments, Inc.
> - * Copyright (C) 2008-2010 Nokia Corporation
> - *
> - * Derived from mach-omap2/clockdomain.c written by Paul Walmsley
> - * Rajendra Nayak <rnayak@ti.com>
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License version 2 as
> - * published by the Free Software Foundation.
> - */
> -
> -#include <linux/types.h>
> -#include <plat/prcm.h>
> -#include "prm.h"
> -#include "prm2xxx_3xxx.h"
> -#include "cm.h"
> -#include "cm2xxx.h"
> -#include "cm3xxx.h"
> -#include "cm-regbits-24xx.h"
> -#include "cm-regbits-34xx.h"
> -#include "prm-regbits-24xx.h"
> -#include "clockdomain.h"
> -
> -static int omap2_clkdm_add_wkdep(struct clockdomain *clkdm1,
> - struct clockdomain *clkdm2)
> -{
> - omap2_prm_set_mod_reg_bits((1 << clkdm2->dep_bit),
> - clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);
> - return 0;
> -}
> -
> -static int omap2_clkdm_del_wkdep(struct clockdomain *clkdm1,
> - struct clockdomain *clkdm2)
> -{
> - omap2_prm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
> - clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);
> - return 0;
> -}
> -
> -static int omap2_clkdm_read_wkdep(struct clockdomain *clkdm1,
> - struct clockdomain *clkdm2)
> -{
> - return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs,
> - PM_WKDEP, (1 << clkdm2->dep_bit));
> -}
> -
> -static int omap2_clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
> -{
> - struct clkdm_dep *cd;
> - u32 mask = 0;
> -
> - for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {
> - if (!cd->clkdm)
> - continue; /* only happens if data is erroneous */
> -
> - /* PRM accesses are slow, so minimize them */
> - mask |= 1 << cd->clkdm->dep_bit;
> - atomic_set(&cd->wkdep_usecount, 0);
> - }
> -
> - omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,
> - PM_WKDEP);
> - return 0;
> -}
> -
> -static int omap3_clkdm_add_sleepdep(struct clockdomain *clkdm1,
> - struct clockdomain *clkdm2)
> -{
> - omap2_cm_set_mod_reg_bits((1 << clkdm2->dep_bit),
> - clkdm1->pwrdm.ptr->prcm_offs,
> - OMAP3430_CM_SLEEPDEP);
> - return 0;
> -}
> -
> -static int omap3_clkdm_del_sleepdep(struct clockdomain *clkdm1,
> - struct clockdomain *clkdm2)
> -{
> - omap2_cm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
> - clkdm1->pwrdm.ptr->prcm_offs,
> - OMAP3430_CM_SLEEPDEP);
> - return 0;
> -}
> -
> -static int omap3_clkdm_read_sleepdep(struct clockdomain *clkdm1,
> - struct clockdomain *clkdm2)
> -{
> - return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs,
> - OMAP3430_CM_SLEEPDEP, (1 << clkdm2->dep_bit));
> -}
> -
> -static int omap3_clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
> -{
> - struct clkdm_dep *cd;
> - u32 mask = 0;
> -
> - for (cd = clkdm->sleepdep_srcs; cd && cd->clkdm_name; cd++) {
> - if (!cd->clkdm)
> - continue; /* only happens if data is erroneous */
> -
> - /* PRM accesses are slow, so minimize them */
> - mask |= 1 << cd->clkdm->dep_bit;
> - atomic_set(&cd->sleepdep_usecount, 0);
> - }
> - omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,
> - OMAP3430_CM_SLEEPDEP);
> - return 0;
> -}
> -
> -static int omap2_clkdm_sleep(struct clockdomain *clkdm)
> -{
> - omap2_cm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
> - clkdm->pwrdm.ptr->prcm_offs,
> - OMAP2_PM_PWSTCTRL);
> - return 0;
> -}
> -
> -static int omap2_clkdm_wakeup(struct clockdomain *clkdm)
> -{
> - omap2_cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
> - clkdm->pwrdm.ptr->prcm_offs,
> - OMAP2_PM_PWSTCTRL);
> - return 0;
> -}
> -
> -static void omap2_clkdm_allow_idle(struct clockdomain *clkdm)
> -{
> - if (atomic_read(&clkdm->usecount) > 0)
> - _clkdm_add_autodeps(clkdm);
> -
> - omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
> - clkdm->clktrctrl_mask);
> -}
> -
> -static void omap2_clkdm_deny_idle(struct clockdomain *clkdm)
> -{
> - omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
> - clkdm->clktrctrl_mask);
> -
> - if (atomic_read(&clkdm->usecount) > 0)
> - _clkdm_del_autodeps(clkdm);
> -}
> -
> -static void _enable_hwsup(struct clockdomain *clkdm)
> -{
> - if (cpu_is_omap24xx())
> - omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
> - clkdm->clktrctrl_mask);
> - else if (cpu_is_omap34xx())
> - omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
> - clkdm->clktrctrl_mask);
> -}
> -
> -static void _disable_hwsup(struct clockdomain *clkdm)
> -{
> - if (cpu_is_omap24xx())
> - omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
> - clkdm->clktrctrl_mask);
> - else if (cpu_is_omap34xx())
> - omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
> - clkdm->clktrctrl_mask);
> -}
> -
> -static int omap3_clkdm_sleep(struct clockdomain *clkdm)
> -{
> - omap3xxx_cm_clkdm_force_sleep(clkdm->pwrdm.ptr->prcm_offs,
> - clkdm->clktrctrl_mask);
> - return 0;
> -}
> -
> -static int omap3_clkdm_wakeup(struct clockdomain *clkdm)
> -{
> - omap3xxx_cm_clkdm_force_wakeup(clkdm->pwrdm.ptr->prcm_offs,
> - clkdm->clktrctrl_mask);
> - return 0;
> -}
> -
> -static int omap2xxx_clkdm_clk_enable(struct clockdomain *clkdm)
> -{
> - bool hwsup = false;
> -
> - if (!clkdm->clktrctrl_mask)
> - return 0;
> -
> - hwsup = omap3xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
> - clkdm->clktrctrl_mask);
> -
> - if (hwsup) {
> - /* Disable HW transitions when we are changing deps */
> - _disable_hwsup(clkdm);
> - _clkdm_add_autodeps(clkdm);
> - _enable_hwsup(clkdm);
> - } else {
> - if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
> - omap2_clkdm_wakeup(clkdm);
> - }
> -
> - return 0;
> -}
> -
> -static int omap2xxx_clkdm_clk_disable(struct clockdomain *clkdm)
> -{
> - bool hwsup = false;
> -
> - if (!clkdm->clktrctrl_mask)
> - return 0;
> -
> - hwsup = omap3xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
> - clkdm->clktrctrl_mask);
> -
> - if (hwsup) {
> - /* Disable HW transitions when we are changing deps */
> - _disable_hwsup(clkdm);
> - _clkdm_del_autodeps(clkdm);
> - _enable_hwsup(clkdm);
> - } else {
> - if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)
> - omap2_clkdm_sleep(clkdm);
> - }
> -
> - return 0;
> -}
> -
> -static void omap3_clkdm_allow_idle(struct clockdomain *clkdm)
> -{
> - if (atomic_read(&clkdm->usecount) > 0)
> - _clkdm_add_autodeps(clkdm);
> -
> - omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
> - clkdm->clktrctrl_mask);
> -}
> -
> -static void omap3_clkdm_deny_idle(struct clockdomain *clkdm)
> -{
> - omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
> - clkdm->clktrctrl_mask);
> -
> - if (atomic_read(&clkdm->usecount) > 0)
> - _clkdm_del_autodeps(clkdm);
> -}
> -
> -static int omap3xxx_clkdm_clk_enable(struct clockdomain *clkdm)
> -{
> - bool hwsup = false;
> -
> - if (!clkdm->clktrctrl_mask)
> - return 0;
> -
> - /*
> - * The CLKDM_MISSING_IDLE_REPORTING flag documentation has
> - * more details on the unpleasant problem this is working
> - * around
> - */
> - if ((clkdm->flags & CLKDM_MISSING_IDLE_REPORTING) &&
> - (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)) {
> - omap3_clkdm_wakeup(clkdm);
> - return 0;
> - }
> -
> - hwsup = omap2xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
> - clkdm->clktrctrl_mask);
> -
> - if (hwsup) {
> - /* Disable HW transitions when we are changing deps */
> - _disable_hwsup(clkdm);
> - _clkdm_add_autodeps(clkdm);
> - _enable_hwsup(clkdm);
> - } else {
> - if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
> - omap3_clkdm_wakeup(clkdm);
> - }
> -
> - return 0;
> -}
> -
> -static int omap3xxx_clkdm_clk_disable(struct clockdomain *clkdm)
> -{
> - bool hwsup = false;
> -
> - if (!clkdm->clktrctrl_mask)
> - return 0;
> -
> - /*
> - * The CLKDM_MISSING_IDLE_REPORTING flag documentation has
> - * more details on the unpleasant problem this is working
> - * around
> - */
> - if (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING &&
> - !(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) {
> - _enable_hwsup(clkdm);
> - return 0;
> - }
> -
> - hwsup = omap2xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
> - clkdm->clktrctrl_mask);
> -
> - if (hwsup) {
> - /* Disable HW transitions when we are changing deps */
> - _disable_hwsup(clkdm);
> - _clkdm_del_autodeps(clkdm);
> - _enable_hwsup(clkdm);
> - } else {
> - if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)
> - omap3_clkdm_sleep(clkdm);
> - }
> -
> - return 0;
> -}
> -
> -struct clkdm_ops omap2_clkdm_operations = {
> - .clkdm_add_wkdep = omap2_clkdm_add_wkdep,
> - .clkdm_del_wkdep = omap2_clkdm_del_wkdep,
> - .clkdm_read_wkdep = omap2_clkdm_read_wkdep,
> - .clkdm_clear_all_wkdeps = omap2_clkdm_clear_all_wkdeps,
> - .clkdm_sleep = omap2_clkdm_sleep,
> - .clkdm_wakeup = omap2_clkdm_wakeup,
> - .clkdm_allow_idle = omap2_clkdm_allow_idle,
> - .clkdm_deny_idle = omap2_clkdm_deny_idle,
> - .clkdm_clk_enable = omap2xxx_clkdm_clk_enable,
> - .clkdm_clk_disable = omap2xxx_clkdm_clk_disable,
> -};
> -
> -struct clkdm_ops omap3_clkdm_operations = {
> - .clkdm_add_wkdep = omap2_clkdm_add_wkdep,
> - .clkdm_del_wkdep = omap2_clkdm_del_wkdep,
> - .clkdm_read_wkdep = omap2_clkdm_read_wkdep,
> - .clkdm_clear_all_wkdeps = omap2_clkdm_clear_all_wkdeps,
> - .clkdm_add_sleepdep = omap3_clkdm_add_sleepdep,
> - .clkdm_del_sleepdep = omap3_clkdm_del_sleepdep,
> - .clkdm_read_sleepdep = omap3_clkdm_read_sleepdep,
> - .clkdm_clear_all_sleepdeps = omap3_clkdm_clear_all_sleepdeps,
> - .clkdm_sleep = omap3_clkdm_sleep,
> - .clkdm_wakeup = omap3_clkdm_wakeup,
> - .clkdm_allow_idle = omap3_clkdm_allow_idle,
> - .clkdm_deny_idle = omap3_clkdm_deny_idle,
> - .clkdm_clk_enable = omap3xxx_clkdm_clk_enable,
> - .clkdm_clk_disable = omap3xxx_clkdm_clk_disable,
> -};
> diff --git a/arch/arm/mach-omap2/clockdomain33xx.c b/arch/arm/mach-omap2/clockdomain33xx.c
> deleted file mode 100644
> index aca6388..0000000
> --- a/arch/arm/mach-omap2/clockdomain33xx.c
> +++ /dev/null
> @@ -1,74 +0,0 @@
> -/*
> - * AM33XX clockdomain control
> - *
> - * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
> - * Vaibhav Hiremath <hvaibhav@ti.com>
> - *
> - * Derived from mach-omap2/clockdomain44xx.c written by Rajendra Nayak
> - *
> - * This program is free software; you can redistribute it and/or
> - * modify it under the terms of the GNU General Public License as
> - * published by the Free Software Foundation version 2.
> - *
> - * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> - * kind, whether express or implied; without even the implied warranty
> - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> - * GNU General Public License for more details.
> - */
> -
> -#include <linux/kernel.h>
> -
> -#include "clockdomain.h"
> -#include "cm33xx.h"
> -
> -
> -static int am33xx_clkdm_sleep(struct clockdomain *clkdm)
> -{
> - am33xx_cm_clkdm_force_sleep(clkdm->cm_inst, clkdm->clkdm_offs);
> - return 0;
> -}
> -
> -static int am33xx_clkdm_wakeup(struct clockdomain *clkdm)
> -{
> - am33xx_cm_clkdm_force_wakeup(clkdm->cm_inst, clkdm->clkdm_offs);
> - return 0;
> -}
> -
> -static void am33xx_clkdm_allow_idle(struct clockdomain *clkdm)
> -{
> - am33xx_cm_clkdm_enable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
> -}
> -
> -static void am33xx_clkdm_deny_idle(struct clockdomain *clkdm)
> -{
> - am33xx_cm_clkdm_disable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
> -}
> -
> -static int am33xx_clkdm_clk_enable(struct clockdomain *clkdm)
> -{
> - if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
> - return am33xx_clkdm_wakeup(clkdm);
> -
> - return 0;
> -}
> -
> -static int am33xx_clkdm_clk_disable(struct clockdomain *clkdm)
> -{
> - bool hwsup = false;
> -
> - hwsup = am33xx_cm_is_clkdm_in_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
> -
> - if (!hwsup && (clkdm->flags & CLKDM_CAN_FORCE_SLEEP))
> - am33xx_clkdm_sleep(clkdm);
> -
> - return 0;
> -}
> -
> -struct clkdm_ops am33xx_clkdm_operations = {
> - .clkdm_sleep = am33xx_clkdm_sleep,
> - .clkdm_wakeup = am33xx_clkdm_wakeup,
> - .clkdm_allow_idle = am33xx_clkdm_allow_idle,
> - .clkdm_deny_idle = am33xx_clkdm_deny_idle,
> - .clkdm_clk_enable = am33xx_clkdm_clk_enable,
> - .clkdm_clk_disable = am33xx_clkdm_clk_disable,
> -};
> diff --git a/arch/arm/mach-omap2/clockdomain44xx.c b/arch/arm/mach-omap2/clockdomain44xx.c
> deleted file mode 100644
> index 6fc6155..0000000
> --- a/arch/arm/mach-omap2/clockdomain44xx.c
> +++ /dev/null
> @@ -1,151 +0,0 @@
> -/*
> - * OMAP4 clockdomain control
> - *
> - * Copyright (C) 2008-2010 Texas Instruments, Inc.
> - * Copyright (C) 2008-2010 Nokia Corporation
> - *
> - * Derived from mach-omap2/clockdomain.c written by Paul Walmsley
> - * Rajendra Nayak <rnayak@ti.com>
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License version 2 as
> - * published by the Free Software Foundation.
> - */
> -
> -#include <linux/kernel.h>
> -#include "clockdomain.h"
> -#include "cminst44xx.h"
> -#include "cm44xx.h"
> -
> -static int omap4_clkdm_add_wkup_sleep_dep(struct clockdomain *clkdm1,
> - struct clockdomain *clkdm2)
> -{
> - omap4_cminst_set_inst_reg_bits((1 << clkdm2->dep_bit),
> - clkdm1->prcm_partition,
> - clkdm1->cm_inst, clkdm1->clkdm_offs +
> - OMAP4_CM_STATICDEP);
> - return 0;
> -}
> -
> -static int omap4_clkdm_del_wkup_sleep_dep(struct clockdomain *clkdm1,
> - struct clockdomain *clkdm2)
> -{
> - omap4_cminst_clear_inst_reg_bits((1 << clkdm2->dep_bit),
> - clkdm1->prcm_partition,
> - clkdm1->cm_inst, clkdm1->clkdm_offs +
> - OMAP4_CM_STATICDEP);
> - return 0;
> -}
> -
> -static int omap4_clkdm_read_wkup_sleep_dep(struct clockdomain *clkdm1,
> - struct clockdomain *clkdm2)
> -{
> - return omap4_cminst_read_inst_reg_bits(clkdm1->prcm_partition,
> - clkdm1->cm_inst, clkdm1->clkdm_offs +
> - OMAP4_CM_STATICDEP,
> - (1 << clkdm2->dep_bit));
> -}
> -
> -static int omap4_clkdm_clear_all_wkup_sleep_deps(struct clockdomain *clkdm)
> -{
> - struct clkdm_dep *cd;
> - u32 mask = 0;
> -
> - if (!clkdm->prcm_partition)
> - return 0;
> -
> - for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {
> - if (!cd->clkdm)
> - continue; /* only happens if data is erroneous */
> -
> - mask |= 1 << cd->clkdm->dep_bit;
> - atomic_set(&cd->wkdep_usecount, 0);
> - }
> -
> - omap4_cminst_clear_inst_reg_bits(mask, clkdm->prcm_partition,
> - clkdm->cm_inst, clkdm->clkdm_offs +
> - OMAP4_CM_STATICDEP);
> - return 0;
> -}
> -
> -static int omap4_clkdm_sleep(struct clockdomain *clkdm)
> -{
> - omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition,
> - clkdm->cm_inst, clkdm->clkdm_offs);
> - return 0;
> -}
> -
> -static int omap4_clkdm_wakeup(struct clockdomain *clkdm)
> -{
> - omap4_cminst_clkdm_force_wakeup(clkdm->prcm_partition,
> - clkdm->cm_inst, clkdm->clkdm_offs);
> - return 0;
> -}
> -
> -static void omap4_clkdm_allow_idle(struct clockdomain *clkdm)
> -{
> - omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition,
> - clkdm->cm_inst, clkdm->clkdm_offs);
> -}
> -
> -static void omap4_clkdm_deny_idle(struct clockdomain *clkdm)
> -{
> - if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
> - omap4_clkdm_wakeup(clkdm);
> - else
> - omap4_cminst_clkdm_disable_hwsup(clkdm->prcm_partition,
> - clkdm->cm_inst,
> - clkdm->clkdm_offs);
> -}
> -
> -static int omap4_clkdm_clk_enable(struct clockdomain *clkdm)
> -{
> - if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
> - return omap4_clkdm_wakeup(clkdm);
> -
> - return 0;
> -}
> -
> -static int omap4_clkdm_clk_disable(struct clockdomain *clkdm)
> -{
> - bool hwsup = false;
> -
> - if (!clkdm->prcm_partition)
> - return 0;
> -
> - /*
> - * The CLKDM_MISSING_IDLE_REPORTING flag documentation has
> - * more details on the unpleasant problem this is working
> - * around
> - */
> - if (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING &&
> - !(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) {
> - omap4_clkdm_allow_idle(clkdm);
> - return 0;
> - }
> -
> - hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition,
> - clkdm->cm_inst, clkdm->clkdm_offs);
> -
> - if (!hwsup && (clkdm->flags & CLKDM_CAN_FORCE_SLEEP))
> - omap4_clkdm_sleep(clkdm);
> -
> - return 0;
> -}
> -
> -struct clkdm_ops omap4_clkdm_operations = {
> - .clkdm_add_wkdep = omap4_clkdm_add_wkup_sleep_dep,
> - .clkdm_del_wkdep = omap4_clkdm_del_wkup_sleep_dep,
> - .clkdm_read_wkdep = omap4_clkdm_read_wkup_sleep_dep,
> - .clkdm_clear_all_wkdeps = omap4_clkdm_clear_all_wkup_sleep_deps,
> - .clkdm_add_sleepdep = omap4_clkdm_add_wkup_sleep_dep,
> - .clkdm_del_sleepdep = omap4_clkdm_del_wkup_sleep_dep,
> - .clkdm_read_sleepdep = omap4_clkdm_read_wkup_sleep_dep,
> - .clkdm_clear_all_sleepdeps = omap4_clkdm_clear_all_wkup_sleep_deps,
> - .clkdm_sleep = omap4_clkdm_sleep,
> - .clkdm_wakeup = omap4_clkdm_wakeup,
> - .clkdm_allow_idle = omap4_clkdm_allow_idle,
> - .clkdm_deny_idle = omap4_clkdm_deny_idle,
> - .clkdm_clk_enable = omap4_clkdm_clk_enable,
> - .clkdm_clk_disable = omap4_clkdm_clk_disable,
> -};
> diff --git a/arch/arm/mach-omap2/cm2xxx.c b/arch/arm/mach-omap2/cm2xxx.c
> index 19cee91..0160893 100644
> --- a/arch/arm/mach-omap2/cm2xxx.c
> +++ b/arch/arm/mach-omap2/cm2xxx.c
> @@ -19,9 +19,11 @@
> #include "soc.h"
> #include "iomap.h"
> #include "common.h"
> +#include "prm2xxx.h"
> #include "cm.h"
> #include "cm2xxx.h"
> #include "cm-regbits-24xx.h"
> +#include "clockdomain.h"
>
> /* CM_AUTOIDLE_PLL.AUTO_* bit values for DPLLs */
> #define DPLL_AUTOIDLE_DISABLE 0x0
> @@ -165,3 +167,87 @@ int omap2xxx_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift)
>
> return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
> }
> +
> +/* Clockdomain low-level functions */
> +
> +static void omap2xxx_clkdm_allow_idle(struct clockdomain *clkdm)
> +{
> + if (atomic_read(&clkdm->usecount) > 0)
> + _clkdm_add_autodeps(clkdm);
> +
> + omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
> + clkdm->clktrctrl_mask);
> +}
> +
> +static void omap2xxx_clkdm_deny_idle(struct clockdomain *clkdm)
> +{
> + omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
> + clkdm->clktrctrl_mask);
> +
> + if (atomic_read(&clkdm->usecount) > 0)
> + _clkdm_del_autodeps(clkdm);
> +}
> +
> +static int omap2xxx_clkdm_clk_enable(struct clockdomain *clkdm)
> +{
> + bool hwsup = false;
> +
> + if (!clkdm->clktrctrl_mask)
> + return 0;
> +
> + hwsup = omap2xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
> + clkdm->clktrctrl_mask);
> +
> + if (hwsup) {
> + /* Disable HW transitions when we are changing deps */
> + omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
> + clkdm->clktrctrl_mask);
> + _clkdm_add_autodeps(clkdm);
> + omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
> + clkdm->clktrctrl_mask);
> + } else {
> + if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
> + omap2xxx_clkdm_wakeup(clkdm);
> + }
> +
> + return 0;
> +}
> +
> +static int omap2xxx_clkdm_clk_disable(struct clockdomain *clkdm)
> +{
> + bool hwsup = false;
> +
> + if (!clkdm->clktrctrl_mask)
> + return 0;
> +
> + hwsup = omap2xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
> + clkdm->clktrctrl_mask);
> +
> + if (hwsup) {
> + /* Disable HW transitions when we are changing deps */
> + omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
> + clkdm->clktrctrl_mask);
> + _clkdm_del_autodeps(clkdm);
> + omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
> + clkdm->clktrctrl_mask);
> + } else {
> + if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)
> + omap2xxx_clkdm_sleep(clkdm);
> + }
> +
> + return 0;
> +}
> +
> +struct clkdm_ops omap2_clkdm_operations = {
> + .clkdm_add_wkdep = omap2_clkdm_add_wkdep,
> + .clkdm_del_wkdep = omap2_clkdm_del_wkdep,
> + .clkdm_read_wkdep = omap2_clkdm_read_wkdep,
> + .clkdm_clear_all_wkdeps = omap2_clkdm_clear_all_wkdeps,
> + .clkdm_sleep = omap2xxx_clkdm_sleep,
> + .clkdm_wakeup = omap2xxx_clkdm_wakeup,
> + .clkdm_allow_idle = omap2xxx_clkdm_allow_idle,
> + .clkdm_deny_idle = omap2xxx_clkdm_deny_idle,
> + .clkdm_clk_enable = omap2xxx_clkdm_clk_enable,
> + .clkdm_clk_disable = omap2xxx_clkdm_clk_disable,
> +};
> +
> diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.h b/arch/arm/mach-omap2/cm2xxx_3xxx.h
> index 64df725..78c218c 100644
> --- a/arch/arm/mach-omap2/cm2xxx_3xxx.h
> +++ b/arch/arm/mach-omap2/cm2xxx_3xxx.h
> @@ -73,6 +73,18 @@ static inline u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module,
> return v;
> }
>
> +/* Read a CM register, AND it, and shift the result down to bit 0 */
> +static inline u32 omap2_cm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
> +{
> + u32 v;
> +
> + v = omap2_cm_read_mod_reg(domain, idx);
> + v &= mask;
> + v >>= __ffs(mask);
> +
> + return v;
> +}
> +
> static inline u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
> {
> return omap2_cm_rmw_mod_reg_bits(bits, bits, module, idx);
> diff --git a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c
> index 13f56ea..9b3bcff1 100644
> --- a/arch/arm/mach-omap2/cm33xx.c
> +++ b/arch/arm/mach-omap2/cm33xx.c
> @@ -24,6 +24,7 @@
>
> #include <plat/common.h>
>
> +#include "clockdomain.h"
> #include "cm.h"
> #include "cm33xx.h"
> #include "cm-regbits-34xx.h"
> @@ -311,3 +312,58 @@ void am33xx_cm_module_disable(u16 inst, s16 cdoffs, u16 clkctrl_offs)
> v &= ~AM33XX_MODULEMODE_MASK;
> am33xx_cm_write_reg(v, inst, clkctrl_offs);
> }
> +
> +/*
> + * Clockdomain low-level functions
> + */
> +
> +static int am33xx_clkdm_sleep(struct clockdomain *clkdm)
> +{
> + am33xx_cm_clkdm_force_sleep(clkdm->cm_inst, clkdm->clkdm_offs);
> + return 0;
> +}
> +
> +static int am33xx_clkdm_wakeup(struct clockdomain *clkdm)
> +{
> + am33xx_cm_clkdm_force_wakeup(clkdm->cm_inst, clkdm->clkdm_offs);
> + return 0;
> +}
> +
> +static void am33xx_clkdm_allow_idle(struct clockdomain *clkdm)
> +{
> + am33xx_cm_clkdm_enable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
> +}
> +
> +static void am33xx_clkdm_deny_idle(struct clockdomain *clkdm)
> +{
> + am33xx_cm_clkdm_disable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
> +}
> +
> +static int am33xx_clkdm_clk_enable(struct clockdomain *clkdm)
> +{
> + if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
> + return am33xx_clkdm_wakeup(clkdm);
> +
> + return 0;
> +}
> +
> +static int am33xx_clkdm_clk_disable(struct clockdomain *clkdm)
> +{
> + bool hwsup = false;
> +
> + hwsup = am33xx_cm_is_clkdm_in_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
> +
> + if (!hwsup && (clkdm->flags & CLKDM_CAN_FORCE_SLEEP))
> + am33xx_clkdm_sleep(clkdm);
> +
> + return 0;
> +}
> +
> +struct clkdm_ops am33xx_clkdm_operations = {
> + .clkdm_sleep = am33xx_clkdm_sleep,
> + .clkdm_wakeup = am33xx_clkdm_wakeup,
> + .clkdm_allow_idle = am33xx_clkdm_allow_idle,
> + .clkdm_deny_idle = am33xx_clkdm_deny_idle,
> + .clkdm_clk_enable = am33xx_clkdm_clk_enable,
> + .clkdm_clk_disable = am33xx_clkdm_clk_disable,
> +};
> diff --git a/arch/arm/mach-omap2/cm3xxx.c b/arch/arm/mach-omap2/cm3xxx.c
> index 075cabe..3493fef 100644
> --- a/arch/arm/mach-omap2/cm3xxx.c
> +++ b/arch/arm/mach-omap2/cm3xxx.c
> @@ -19,9 +19,11 @@
> #include "soc.h"
> #include "iomap.h"
> #include "common.h"
> +#include "prm2xxx_3xxx.h"
> #include "cm.h"
> #include "cm3xxx.h"
> #include "cm-regbits-34xx.h"
> +#include "clockdomain.h"
>
> static const u8 omap3xxx_cm_idlest_offs[] = { CM_IDLEST1, CM_IDLEST2 };
>
> @@ -104,6 +106,173 @@ int omap3xxx_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift)
> return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
> }
>
> +/* Clockdomain low-level operations */
> +
> +static int omap3xxx_clkdm_add_sleepdep(struct clockdomain *clkdm1,
> + struct clockdomain *clkdm2)
> +{
> + omap2_cm_set_mod_reg_bits((1 << clkdm2->dep_bit),
> + clkdm1->pwrdm.ptr->prcm_offs,
> + OMAP3430_CM_SLEEPDEP);
> + return 0;
> +}
> +
> +static int omap3xxx_clkdm_del_sleepdep(struct clockdomain *clkdm1,
> + struct clockdomain *clkdm2)
> +{
> + omap2_cm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
> + clkdm1->pwrdm.ptr->prcm_offs,
> + OMAP3430_CM_SLEEPDEP);
> + return 0;
> +}
> +
> +static int omap3xxx_clkdm_read_sleepdep(struct clockdomain *clkdm1,
> + struct clockdomain *clkdm2)
> +{
> + return omap2_cm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs,
> + OMAP3430_CM_SLEEPDEP,
> + (1 << clkdm2->dep_bit));
> +}
> +
> +static int omap3xxx_clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
> +{
> + struct clkdm_dep *cd;
> + u32 mask = 0;
> +
> + for (cd = clkdm->sleepdep_srcs; cd && cd->clkdm_name; cd++) {
> + if (!cd->clkdm)
> + continue; /* only happens if data is erroneous */
> +
> + mask |= 1 << cd->clkdm->dep_bit;
> + atomic_set(&cd->sleepdep_usecount, 0);
> + }
> + omap2_cm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,
> + OMAP3430_CM_SLEEPDEP);
> + return 0;
> +}
> +
> +static int omap3xxx_clkdm_sleep(struct clockdomain *clkdm)
> +{
> + omap3xxx_cm_clkdm_force_sleep(clkdm->pwrdm.ptr->prcm_offs,
> + clkdm->clktrctrl_mask);
> + return 0;
> +}
> +
> +static int omap3xxx_clkdm_wakeup(struct clockdomain *clkdm)
> +{
> + omap3xxx_cm_clkdm_force_wakeup(clkdm->pwrdm.ptr->prcm_offs,
> + clkdm->clktrctrl_mask);
> + return 0;
> +}
> +
> +static void omap3xxx_clkdm_allow_idle(struct clockdomain *clkdm)
> +{
> + if (atomic_read(&clkdm->usecount) > 0)
> + _clkdm_add_autodeps(clkdm);
> +
> + omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
> + clkdm->clktrctrl_mask);
> +}
> +
> +static void omap3xxx_clkdm_deny_idle(struct clockdomain *clkdm)
> +{
> + omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
> + clkdm->clktrctrl_mask);
> +
> + if (atomic_read(&clkdm->usecount) > 0)
> + _clkdm_del_autodeps(clkdm);
> +}
> +
> +static int omap3xxx_clkdm_clk_enable(struct clockdomain *clkdm)
> +{
> + bool hwsup = false;
> +
> + if (!clkdm->clktrctrl_mask)
> + return 0;
> +
> + /*
> + * The CLKDM_MISSING_IDLE_REPORTING flag documentation has
> + * more details on the unpleasant problem this is working
> + * around
> + */
> + if ((clkdm->flags & CLKDM_MISSING_IDLE_REPORTING) &&
> + (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)) {
> + omap3xxx_clkdm_wakeup(clkdm);
> + return 0;
> + }
> +
> + hwsup = omap3xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
> + clkdm->clktrctrl_mask);
> +
> + if (hwsup) {
> + /* Disable HW transitions when we are changing deps */
> + omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
> + clkdm->clktrctrl_mask);
> + _clkdm_add_autodeps(clkdm);
> + omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
> + clkdm->clktrctrl_mask);
> + } else {
> + if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
> + omap3xxx_clkdm_wakeup(clkdm);
> + }
> +
> + return 0;
> +}
> +
> +static int omap3xxx_clkdm_clk_disable(struct clockdomain *clkdm)
> +{
> + bool hwsup = false;
> +
> + if (!clkdm->clktrctrl_mask)
> + return 0;
> +
> + /*
> + * The CLKDM_MISSING_IDLE_REPORTING flag documentation has
> + * more details on the unpleasant problem this is working
> + * around
> + */
> + if (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING &&
> + !(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) {
> + omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
> + clkdm->clktrctrl_mask);
> + return 0;
> + }
> +
> + hwsup = omap3xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
> + clkdm->clktrctrl_mask);
> +
> + if (hwsup) {
> + /* Disable HW transitions when we are changing deps */
> + omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
> + clkdm->clktrctrl_mask);
> + _clkdm_del_autodeps(clkdm);
> + omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
> + clkdm->clktrctrl_mask);
> + } else {
> + if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)
> + omap3xxx_clkdm_sleep(clkdm);
> + }
> +
> + return 0;
> +}
> +
> +struct clkdm_ops omap3_clkdm_operations = {
> + .clkdm_add_wkdep = omap2_clkdm_add_wkdep,
> + .clkdm_del_wkdep = omap2_clkdm_del_wkdep,
> + .clkdm_read_wkdep = omap2_clkdm_read_wkdep,
> + .clkdm_clear_all_wkdeps = omap2_clkdm_clear_all_wkdeps,
> + .clkdm_add_sleepdep = omap3xxx_clkdm_add_sleepdep,
> + .clkdm_del_sleepdep = omap3xxx_clkdm_del_sleepdep,
> + .clkdm_read_sleepdep = omap3xxx_clkdm_read_sleepdep,
> + .clkdm_clear_all_sleepdeps = omap3xxx_clkdm_clear_all_sleepdeps,
> + .clkdm_sleep = omap3xxx_clkdm_sleep,
> + .clkdm_wakeup = omap3xxx_clkdm_wakeup,
> + .clkdm_allow_idle = omap3xxx_clkdm_allow_idle,
> + .clkdm_deny_idle = omap3xxx_clkdm_deny_idle,
> + .clkdm_clk_enable = omap3xxx_clkdm_clk_enable,
> + .clkdm_clk_disable = omap3xxx_clkdm_clk_disable,
> +};
> +
> /*
> * Context save/restore code - OMAP3 only
> */
> diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
> index 1894015..9dca0ee 100644
> --- a/arch/arm/mach-omap2/cminst44xx.c
> +++ b/arch/arm/mach-omap2/cminst44xx.c
> @@ -22,6 +22,7 @@
>
> #include "iomap.h"
> #include "common.h"
> +#include "clockdomain.h"
> #include "cm.h"
> #include "cm1_44xx.h"
> #include "cm2_44xx.h"
> @@ -343,3 +344,141 @@ void omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs,
> v &= ~OMAP4430_MODULEMODE_MASK;
> omap4_cminst_write_inst_reg(v, part, inst, clkctrl_offs);
> }
> +
> +/*
> + * Clockdomain low-level functions
> + */
> +
> +static int omap4_clkdm_add_wkup_sleep_dep(struct clockdomain *clkdm1,
> + struct clockdomain *clkdm2)
> +{
> + omap4_cminst_set_inst_reg_bits((1 << clkdm2->dep_bit),
> + clkdm1->prcm_partition,
> + clkdm1->cm_inst, clkdm1->clkdm_offs +
> + OMAP4_CM_STATICDEP);
> + return 0;
> +}
> +
> +static int omap4_clkdm_del_wkup_sleep_dep(struct clockdomain *clkdm1,
> + struct clockdomain *clkdm2)
> +{
> + omap4_cminst_clear_inst_reg_bits((1 << clkdm2->dep_bit),
> + clkdm1->prcm_partition,
> + clkdm1->cm_inst, clkdm1->clkdm_offs +
> + OMAP4_CM_STATICDEP);
> + return 0;
> +}
> +
> +static int omap4_clkdm_read_wkup_sleep_dep(struct clockdomain *clkdm1,
> + struct clockdomain *clkdm2)
> +{
> + return omap4_cminst_read_inst_reg_bits(clkdm1->prcm_partition,
> + clkdm1->cm_inst,
> + clkdm1->clkdm_offs +
> + OMAP4_CM_STATICDEP,
> + (1 << clkdm2->dep_bit));
> +}
> +
> +static int omap4_clkdm_clear_all_wkup_sleep_deps(struct clockdomain *clkdm)
> +{
> + struct clkdm_dep *cd;
> + u32 mask = 0;
> +
> + if (!clkdm->prcm_partition)
> + return 0;
> +
> + for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {
> + if (!cd->clkdm)
> + continue; /* only happens if data is erroneous */
> +
> + mask |= 1 << cd->clkdm->dep_bit;
> + atomic_set(&cd->wkdep_usecount, 0);
> + }
> +
> + omap4_cminst_clear_inst_reg_bits(mask, clkdm->prcm_partition,
> + clkdm->cm_inst, clkdm->clkdm_offs +
> + OMAP4_CM_STATICDEP);
> + return 0;
> +}
> +
> +static int omap4_clkdm_sleep(struct clockdomain *clkdm)
> +{
> + omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition,
> + clkdm->cm_inst, clkdm->clkdm_offs);
> + return 0;
> +}
> +
> +static int omap4_clkdm_wakeup(struct clockdomain *clkdm)
> +{
> + omap4_cminst_clkdm_force_wakeup(clkdm->prcm_partition,
> + clkdm->cm_inst, clkdm->clkdm_offs);
> + return 0;
> +}
> +
> +static void omap4_clkdm_allow_idle(struct clockdomain *clkdm)
> +{
> + omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition,
> + clkdm->cm_inst, clkdm->clkdm_offs);
> +}
> +
> +static void omap4_clkdm_deny_idle(struct clockdomain *clkdm)
> +{
> + if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
> + omap4_clkdm_wakeup(clkdm);
> + else
> + omap4_cminst_clkdm_disable_hwsup(clkdm->prcm_partition,
> + clkdm->cm_inst,
> + clkdm->clkdm_offs);
> +}
> +
> +static int omap4_clkdm_clk_enable(struct clockdomain *clkdm)
> +{
> + if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
> + return omap4_clkdm_wakeup(clkdm);
> +
> + return 0;
> +}
> +
> +static int omap4_clkdm_clk_disable(struct clockdomain *clkdm)
> +{
> + bool hwsup = false;
> +
> + if (!clkdm->prcm_partition)
> + return 0;
> +
> + /*
> + * The CLKDM_MISSING_IDLE_REPORTING flag documentation has
> + * more details on the unpleasant problem this is working
> + * around
> + */
> + if (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING &&
> + !(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) {
> + omap4_clkdm_allow_idle(clkdm);
> + return 0;
> + }
> +
> + hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition,
> + clkdm->cm_inst, clkdm->clkdm_offs);
> +
> + if (!hwsup && (clkdm->flags & CLKDM_CAN_FORCE_SLEEP))
> + omap4_clkdm_sleep(clkdm);
> +
> + return 0;
> +}
> +
> +struct clkdm_ops omap4_clkdm_operations = {
> + .clkdm_add_wkdep = omap4_clkdm_add_wkup_sleep_dep,
> + .clkdm_del_wkdep = omap4_clkdm_del_wkup_sleep_dep,
> + .clkdm_read_wkdep = omap4_clkdm_read_wkup_sleep_dep,
> + .clkdm_clear_all_wkdeps = omap4_clkdm_clear_all_wkup_sleep_deps,
> + .clkdm_add_sleepdep = omap4_clkdm_add_wkup_sleep_dep,
> + .clkdm_del_sleepdep = omap4_clkdm_del_wkup_sleep_dep,
> + .clkdm_read_sleepdep = omap4_clkdm_read_wkup_sleep_dep,
> + .clkdm_clear_all_sleepdeps = omap4_clkdm_clear_all_wkup_sleep_deps,
> + .clkdm_sleep = omap4_clkdm_sleep,
> + .clkdm_wakeup = omap4_clkdm_wakeup,
> + .clkdm_allow_idle = omap4_clkdm_allow_idle,
> + .clkdm_deny_idle = omap4_clkdm_deny_idle,
> + .clkdm_clk_enable = omap4_clkdm_clk_enable,
> + .clkdm_clk_disable = omap4_clkdm_clk_disable,
> +};
> diff --git a/arch/arm/mach-omap2/prm2xxx.c b/arch/arm/mach-omap2/prm2xxx.c
> index 14940c4..d08a2b9 100644
> --- a/arch/arm/mach-omap2/prm2xxx.c
> +++ b/arch/arm/mach-omap2/prm2xxx.c
> @@ -23,10 +23,27 @@
>
> #include "vp.h"
> #include "powerdomain.h"
> +#include "clockdomain.h"
> #include "prm2xxx.h"
> #include "cm2xxx_3xxx.h"
> #include "prm-regbits-24xx.h"
>
> +int omap2xxx_clkdm_sleep(struct clockdomain *clkdm)
> +{
> + omap2_prm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
> + clkdm->pwrdm.ptr->prcm_offs,
> + OMAP2_PM_PWSTCTRL);
> + return 0;
> +}
> +
> +int omap2xxx_clkdm_wakeup(struct clockdomain *clkdm)
> +{
> + omap2_prm_clear_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
> + clkdm->pwrdm.ptr->prcm_offs,
> + OMAP2_PM_PWSTCTRL);
> + return 0;
> +}
> +
> struct pwrdm_ops omap2_pwrdm_operations = {
> .pwrdm_set_next_pwrst = omap2_pwrdm_set_next_pwrst,
> .pwrdm_read_next_pwrst = omap2_pwrdm_read_next_pwrst,
> diff --git a/arch/arm/mach-omap2/prm2xxx.h b/arch/arm/mach-omap2/prm2xxx.h
> index 6490e1a..6d76716 100644
> --- a/arch/arm/mach-omap2/prm2xxx.h
> +++ b/arch/arm/mach-omap2/prm2xxx.h
> @@ -119,4 +119,10 @@
> #define OMAP24XX_PRCM_IRQSTATUS_IVA 0x00f8
> #define OMAP24XX_PRCM_IRQENABLE_IVA 0x00fc
>
> +#ifndef __ASSEMBLER__
> +/* Function prototypes */
> +extern int omap2xxx_clkdm_sleep(struct clockdomain *clkdm);
> +extern int omap2xxx_clkdm_wakeup(struct clockdomain *clkdm);
> +#endif
> +
> #endif
> diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
> index bdddf5c..30517f5 100644
> --- a/arch/arm/mach-omap2/prm2xxx_3xxx.c
> +++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
> @@ -20,6 +20,7 @@
> #include "powerdomain.h"
> #include "prm2xxx_3xxx.h"
> #include "prm-regbits-24xx.h"
> +#include "clockdomain.h"
>
> /**
> * omap2_prm_is_hardreset_asserted - read the HW reset line state of
> @@ -208,3 +209,45 @@ int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm)
> return 0;
> }
>
> +int omap2_clkdm_add_wkdep(struct clockdomain *clkdm1,
> + struct clockdomain *clkdm2)
> +{
> + omap2_prm_set_mod_reg_bits((1 << clkdm2->dep_bit),
> + clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);
> + return 0;
> +}
> +
> +int omap2_clkdm_del_wkdep(struct clockdomain *clkdm1,
> + struct clockdomain *clkdm2)
> +{
> + omap2_prm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
> + clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);
> + return 0;
> +}
> +
> +int omap2_clkdm_read_wkdep(struct clockdomain *clkdm1,
> + struct clockdomain *clkdm2)
> +{
> + return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs,
> + PM_WKDEP, (1 << clkdm2->dep_bit));
> +}
> +
> +int omap2_clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
> +{
> + struct clkdm_dep *cd;
> + u32 mask = 0;
> +
> + for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {
> + if (!cd->clkdm)
> + continue; /* only happens if data is erroneous */
> +
> + /* PRM accesses are slow, so minimize them */
> + mask |= 1 << cd->clkdm->dep_bit;
> + atomic_set(&cd->wkdep_usecount, 0);
> + }
> +
> + omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,
> + PM_WKDEP);
> + return 0;
> +}
> +
> diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h
> index 706b026..22a405a 100644
> --- a/arch/arm/mach-omap2/prm2xxx_3xxx.h
> +++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h
> @@ -116,6 +116,14 @@ extern int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank);
> extern int omap2_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst);
> extern int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm);
>
> +extern int omap2_clkdm_add_wkdep(struct clockdomain *clkdm1,
> + struct clockdomain *clkdm2);
> +extern int omap2_clkdm_del_wkdep(struct clockdomain *clkdm1,
> + struct clockdomain *clkdm2);
> +extern int omap2_clkdm_read_wkdep(struct clockdomain *clkdm1,
> + struct clockdomain *clkdm2);
> +extern int omap2_clkdm_clear_all_wkdeps(struct clockdomain *clkdm);
> +
> #endif /* __ASSEMBLER */
>
> /*
>
>
> --
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* [PATCH 4/5] ARM: OMAP2+: CM/hwmod: split CM functions into OMAP2, OMAP3-specific files
From: Russ Dill @ 2012-10-18 11:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121015230544.18306.15215.stgit@dusk.lan>
On Mon, Oct 15, 2012 at 4:05 PM, Paul Walmsley <paul@pwsan.com> wrote:
> Move OMAP3xxx-specific CM functions & macros into cm3xxx.[ch] and
> OMAP2xxx-specific macros into cm2xxx.[ch]. Move basic CM register
> access functions into static inline functions in cm2xxx_3xxx.h,
> leaving only OMAP2/3 hardreset functions in cm2xxx_3xxx.c.
>
> As part of this, split the CM and hwmod code that waits for devices to
> become ready into SoC-specific functions.
>
> This is in preparation for the upcoming move of this code to drivers/.
Looks pretty good except for confusion in clockdomain2xxx_3xxx.c
Reviewed-by: Russ.Dill at ti.com
> Signed-off-by: Paul Walmsley <paul@pwsan.com>
> ---
> arch/arm/mach-omap2/Makefile | 6 -
> arch/arm/mach-omap2/clkt2xxx_apll.c | 2
> arch/arm/mach-omap2/clkt2xxx_dpll.c | 2
> arch/arm/mach-omap2/clock.c | 3 -
> arch/arm/mach-omap2/clock2420_data.c | 2
> arch/arm/mach-omap2/clock2430.c | 2
> arch/arm/mach-omap2/clock2430_data.c | 2
> arch/arm/mach-omap2/clock34xx.c | 2
> arch/arm/mach-omap2/clock3517.c | 2
> arch/arm/mach-omap2/clock3xxx_data.c | 2
> arch/arm/mach-omap2/clockdomain2xxx_3xxx.c | 27 ++---
> arch/arm/mach-omap2/cm2xxx.c | 167 ++++++++++++++++++++++++++++
> arch/arm/mach-omap2/cm2xxx.h | 68 +++++++++++
> arch/arm/mach-omap2/cm2xxx_3xxx.h | 112 +++++--------------
> arch/arm/mach-omap2/cm3xxx.c | 160 ++-------------------------
> arch/arm/mach-omap2/cm3xxx.h | 86 +-------------
> arch/arm/mach-omap2/control.c | 2
> arch/arm/mach-omap2/omap_hwmod.c | 49 +++++++-
> arch/arm/mach-omap2/pm24xx.c | 2
> arch/arm/mach-omap2/pm34xx.c | 3 -
> arch/arm/mach-omap2/sleep34xx.S | 2
> arch/arm/mach-omap2/sram242x.S | 2
> arch/arm/mach-omap2/sram243x.S | 2
> arch/arm/mach-omap2/sram34xx.S | 2
> 24 files changed, 360 insertions(+), 349 deletions(-)
> create mode 100644 arch/arm/mach-omap2/cm2xxx.c
> create mode 100644 arch/arm/mach-omap2/cm2xxx.h
> rename arch/arm/mach-omap2/{cm2xxx_3xxx.c => cm3xxx.c} (80%)
> copy arch/arm/mach-omap2/{cm2xxx_3xxx.h => cm3xxx.h} (50%)
>
> diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
> index 7404e3d..56a3386 100644
> --- a/arch/arm/mach-omap2/Makefile
> +++ b/arch/arm/mach-omap2/Makefile
> @@ -94,10 +94,8 @@ endif
>
> # PRCM
> obj-y += prcm.o prm_common.o
> -obj-$(CONFIG_ARCH_OMAP2) += cm2xxx_3xxx.o prm2xxx_3xxx.o
> -obj-$(CONFIG_ARCH_OMAP2) += prm2xxx.o
> -obj-$(CONFIG_ARCH_OMAP3) += cm2xxx_3xxx.o prm2xxx_3xxx.o
> -obj-$(CONFIG_ARCH_OMAP3) += prm3xxx.o
> +obj-$(CONFIG_ARCH_OMAP2) += prm2xxx_3xxx.o prm2xxx.o cm2xxx.o
> +obj-$(CONFIG_ARCH_OMAP3) += prm2xxx_3xxx.o prm3xxx.o cm3xxx.o
> obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o
> obj-$(CONFIG_SOC_AM33XX) += prm33xx.o cm33xx.o
> omap-prcm-4-5-common = cminst44xx.o cm44xx.o prm44xx.o \
> diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c
> index c2d15212..3d2f67e 100644
> --- a/arch/arm/mach-omap2/clkt2xxx_apll.c
> +++ b/arch/arm/mach-omap2/clkt2xxx_apll.c
> @@ -26,7 +26,7 @@
>
> #include "clock.h"
> #include "clock2xxx.h"
> -#include "cm2xxx_3xxx.h"
> +#include "cm2xxx.h"
> #include "cm-regbits-24xx.h"
>
> /* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
> diff --git a/arch/arm/mach-omap2/clkt2xxx_dpll.c b/arch/arm/mach-omap2/clkt2xxx_dpll.c
> index 1502a7b..0f58779 100644
> --- a/arch/arm/mach-omap2/clkt2xxx_dpll.c
> +++ b/arch/arm/mach-omap2/clkt2xxx_dpll.c
> @@ -17,7 +17,7 @@
> #include <plat/clock.h>
>
> #include "clock.h"
> -#include "cm2xxx_3xxx.h"
> +#include "cm2xxx.h"
> #include "cm-regbits-24xx.h"
>
> /* Private functions */
> diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
> index 961ac8f..d0c6d9b 100644
> --- a/arch/arm/mach-omap2/clock.c
> +++ b/arch/arm/mach-omap2/clock.c
> @@ -33,7 +33,8 @@
> #include "soc.h"
> #include "clockdomain.h"
> #include "clock.h"
> -#include "cm2xxx_3xxx.h"
> +#include "cm2xxx.h"
> +#include "cm3xxx.h"
> #include "cm-regbits-24xx.h"
> #include "cm-regbits-34xx.h"
>
> diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
> index c3cde1a..969bc58 100644
> --- a/arch/arm/mach-omap2/clock2420_data.c
> +++ b/arch/arm/mach-omap2/clock2420_data.c
> @@ -25,7 +25,7 @@
> #include "clock.h"
> #include "clock2xxx.h"
> #include "opp2xxx.h"
> -#include "cm2xxx_3xxx.h"
> +#include "cm2xxx.h"
> #include "prm2xxx_3xxx.h"
> #include "prm-regbits-24xx.h"
> #include "cm-regbits-24xx.h"
> diff --git a/arch/arm/mach-omap2/clock2430.c b/arch/arm/mach-omap2/clock2430.c
> index a8e3261..e786733 100644
> --- a/arch/arm/mach-omap2/clock2430.c
> +++ b/arch/arm/mach-omap2/clock2430.c
> @@ -27,7 +27,7 @@
> #include "iomap.h"
> #include "clock.h"
> #include "clock2xxx.h"
> -#include "cm2xxx_3xxx.h"
> +#include "cm2xxx.h"
> #include "cm-regbits-24xx.h"
>
> /**
> diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
> index 22404fe..186f06a 100644
> --- a/arch/arm/mach-omap2/clock2430_data.c
> +++ b/arch/arm/mach-omap2/clock2430_data.c
> @@ -24,7 +24,7 @@
> #include "clock.h"
> #include "clock2xxx.h"
> #include "opp2xxx.h"
> -#include "cm2xxx_3xxx.h"
> +#include "cm2xxx.h"
> #include "prm2xxx_3xxx.h"
> #include "prm-regbits-24xx.h"
> #include "cm-regbits-24xx.h"
> diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
> index 1fc96b9..150f42b 100644
> --- a/arch/arm/mach-omap2/clock34xx.c
> +++ b/arch/arm/mach-omap2/clock34xx.c
> @@ -25,7 +25,7 @@
>
> #include "clock.h"
> #include "clock34xx.h"
> -#include "cm2xxx_3xxx.h"
> +#include "cm3xxx.h"
> #include "cm-regbits-34xx.h"
>
> /**
> diff --git a/arch/arm/mach-omap2/clock3517.c b/arch/arm/mach-omap2/clock3517.c
> index 2e97d08..3e610c8 100644
> --- a/arch/arm/mach-omap2/clock3517.c
> +++ b/arch/arm/mach-omap2/clock3517.c
> @@ -25,7 +25,7 @@
>
> #include "clock.h"
> #include "clock3517.h"
> -#include "cm2xxx_3xxx.h"
> +#include "cm3xxx.h"
> #include "cm-regbits-34xx.h"
>
> /*
> diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
> index 1f42c9d..7879c84 100644
> --- a/arch/arm/mach-omap2/clock3xxx_data.c
> +++ b/arch/arm/mach-omap2/clock3xxx_data.c
> @@ -30,7 +30,7 @@
> #include "clock34xx.h"
> #include "clock36xx.h"
> #include "clock3517.h"
> -#include "cm2xxx_3xxx.h"
> +#include "cm3xxx.h"
> #include "cm-regbits-34xx.h"
> #include "prm2xxx_3xxx.h"
> #include "prm-regbits-34xx.h"
> diff --git a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
> index 70294f5..658487c 100644
> --- a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
> +++ b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
> @@ -17,7 +17,8 @@
> #include "prm.h"
> #include "prm2xxx_3xxx.h"
> #include "cm.h"
> -#include "cm2xxx_3xxx.h"
> +#include "cm2xxx.h"
> +#include "cm3xxx.h"
> #include "cm-regbits-24xx.h"
> #include "cm-regbits-34xx.h"
> #include "prm-regbits-24xx.h"
> @@ -176,15 +177,15 @@ static int omap3_clkdm_wakeup(struct clockdomain *clkdm)
> return 0;
> }
>
> -static int omap2_clkdm_clk_enable(struct clockdomain *clkdm)
> +static int omap2xxx_clkdm_clk_enable(struct clockdomain *clkdm)
> {
> bool hwsup = false;
>
> if (!clkdm->clktrctrl_mask)
> return 0;
>
> - hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
> - clkdm->clktrctrl_mask);
> + hwsup = omap3xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
> + clkdm->clktrctrl_mask);
>
> if (hwsup) {
> /* Disable HW transitions when we are changing deps */
> @@ -199,15 +200,15 @@ static int omap2_clkdm_clk_enable(struct clockdomain *clkdm)
> return 0;
> }
>
> -static int omap2_clkdm_clk_disable(struct clockdomain *clkdm)
> +static int omap2xxx_clkdm_clk_disable(struct clockdomain *clkdm)
> {
> bool hwsup = false;
>
> if (!clkdm->clktrctrl_mask)
> return 0;
>
> - hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
> - clkdm->clktrctrl_mask);
> + hwsup = omap3xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
> + clkdm->clktrctrl_mask);
>
> if (hwsup) {
> /* Disable HW transitions when we are changing deps */
> @@ -258,8 +259,8 @@ static int omap3xxx_clkdm_clk_enable(struct clockdomain *clkdm)
> return 0;
> }
>
> - hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
> - clkdm->clktrctrl_mask);
> + hwsup = omap2xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
> + clkdm->clktrctrl_mask);
>
> if (hwsup) {
> /* Disable HW transitions when we are changing deps */
> @@ -292,8 +293,8 @@ static int omap3xxx_clkdm_clk_disable(struct clockdomain *clkdm)
> return 0;
> }
>
> - hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
> - clkdm->clktrctrl_mask);
> + hwsup = omap2xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
> + clkdm->clktrctrl_mask);
>
> if (hwsup) {
> /* Disable HW transitions when we are changing deps */
Looks like you have the 2xxx/3xxx reversed in the above functions.
> @@ -317,8 +318,8 @@ struct clkdm_ops omap2_clkdm_operations = {
> .clkdm_wakeup = omap2_clkdm_wakeup,
> .clkdm_allow_idle = omap2_clkdm_allow_idle,
> .clkdm_deny_idle = omap2_clkdm_deny_idle,
> - .clkdm_clk_enable = omap2_clkdm_clk_enable,
> - .clkdm_clk_disable = omap2_clkdm_clk_disable,
> + .clkdm_clk_enable = omap2xxx_clkdm_clk_enable,
> + .clkdm_clk_disable = omap2xxx_clkdm_clk_disable,
> };
>
> struct clkdm_ops omap3_clkdm_operations = {
> diff --git a/arch/arm/mach-omap2/cm2xxx.c b/arch/arm/mach-omap2/cm2xxx.c
> new file mode 100644
> index 0000000..19cee91
> --- /dev/null
> +++ b/arch/arm/mach-omap2/cm2xxx.c
> @@ -0,0 +1,167 @@
> +/*
> + * OMAP2/3 CM module functions
> + *
> + * Copyright (C) 2009 Nokia Corporation
> + * Paul Walmsley
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/types.h>
> +#include <linux/delay.h>
> +#include <linux/errno.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +
> +#include "soc.h"
> +#include "iomap.h"
> +#include "common.h"
> +#include "cm.h"
> +#include "cm2xxx.h"
> +#include "cm-regbits-24xx.h"
> +
> +/* CM_AUTOIDLE_PLL.AUTO_* bit values for DPLLs */
> +#define DPLL_AUTOIDLE_DISABLE 0x0
> +#define OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP 0x3
> +
> +/* CM_AUTOIDLE_PLL.AUTO_* bit values for APLLs (OMAP2xxx only) */
> +#define OMAP2XXX_APLL_AUTOIDLE_DISABLE 0x0
> +#define OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP 0x3
> +
> +static const u8 omap2xxx_cm_idlest_offs[] = {
> + CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3, OMAP24XX_CM_IDLEST4
> +};
> +
> +/*
> + *
> + */
> +
> +static void _write_clktrctrl(u8 c, s16 module, u32 mask)
> +{
> + u32 v;
> +
> + v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
> + v &= ~mask;
> + v |= c << __ffs(mask);
> + omap2_cm_write_mod_reg(v, module, OMAP2_CM_CLKSTCTRL);
> +}
> +
> +bool omap2xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask)
> +{
> + u32 v;
> +
> + v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
> + v &= mask;
> + v >>= __ffs(mask);
> +
> + return (v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
> +}
> +
> +void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask)
> +{
> + _write_clktrctrl(OMAP24XX_CLKSTCTRL_ENABLE_AUTO, module, mask);
> +}
> +
> +void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask)
> +{
> + _write_clktrctrl(OMAP24XX_CLKSTCTRL_DISABLE_AUTO, module, mask);
> +}
> +
> +/*
> + * DPLL autoidle control
> + */
> +
> +static void _omap2xxx_set_dpll_autoidle(u8 m)
> +{
> + u32 v;
> +
> + v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
> + v &= ~OMAP24XX_AUTO_DPLL_MASK;
> + v |= m << OMAP24XX_AUTO_DPLL_SHIFT;
> + omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
> +}
> +
> +void omap2xxx_cm_set_dpll_disable_autoidle(void)
> +{
> + _omap2xxx_set_dpll_autoidle(OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP);
> +}
> +
> +void omap2xxx_cm_set_dpll_auto_low_power_stop(void)
> +{
> + _omap2xxx_set_dpll_autoidle(DPLL_AUTOIDLE_DISABLE);
> +}
> +
> +/*
> + * APLL autoidle control
> + */
> +
> +static void _omap2xxx_set_apll_autoidle(u8 m, u32 mask)
> +{
> + u32 v;
> +
> + v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
> + v &= ~mask;
> + v |= m << __ffs(mask);
> + omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
> +}
> +
> +void omap2xxx_cm_set_apll54_disable_autoidle(void)
> +{
> + _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP,
> + OMAP24XX_AUTO_54M_MASK);
> +}
> +
> +void omap2xxx_cm_set_apll54_auto_low_power_stop(void)
> +{
> + _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE,
> + OMAP24XX_AUTO_54M_MASK);
> +}
> +
> +void omap2xxx_cm_set_apll96_disable_autoidle(void)
> +{
> + _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP,
> + OMAP24XX_AUTO_96M_MASK);
> +}
> +
> +void omap2xxx_cm_set_apll96_auto_low_power_stop(void)
> +{
> + _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE,
> + OMAP24XX_AUTO_96M_MASK);
> +}
> +
> +/*
> + *
> + */
???
> +/**
> + * omap2xxx_cm_wait_module_ready - wait for a module to leave idle or standby
> + * @prcm_mod: PRCM module offset
> + * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3)
> + * @idlest_shift: shift of the bit in the CM_IDLEST* register to check
> + *
> + * Wait for the PRCM to indicate that the module identified by
> + * (@prcm_mod, @idlest_id, @idlest_shift) is clocked. Return 0 upon
> + * success or -EBUSY if the module doesn't enable in time.
> + */
> +int omap2xxx_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift)
> +{
> + int ena = 0, i = 0;
> + u8 cm_idlest_reg;
> + u32 mask;
> +
> + if (!idlest_id || (idlest_id > ARRAY_SIZE(omap2xxx_cm_idlest_offs)))
> + return -EINVAL;
> +
> + cm_idlest_reg = omap2xxx_cm_idlest_offs[idlest_id - 1];
> +
> + mask = 1 << idlest_shift;
> + ena = mask;
> +
> + omap_test_timeout(((omap2_cm_read_mod_reg(prcm_mod, cm_idlest_reg) &
> + mask) == ena), MAX_MODULE_READY_TIME, i);
> +
> + return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
> +}
> diff --git a/arch/arm/mach-omap2/cm2xxx.h b/arch/arm/mach-omap2/cm2xxx.h
> new file mode 100644
> index 0000000..99e8557
> --- /dev/null
> +++ b/arch/arm/mach-omap2/cm2xxx.h
> @@ -0,0 +1,68 @@
> +/*
> + * OMAP2/3 Clock Management (CM) register definitions
> + *
probably just omap2 in this case
> + * Copyright (C) 2007-2009 Texas Instruments, Inc.
> + * Copyright (C) 2007-2010 Nokia Corporation
> + * Paul Walmsley
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * The CM hardware modules on the OMAP2/3 are quite similar to each
> + * other. The CM modules/instances on OMAP4 are quite different, so
> + * they are handled in a separate file.
> + */
> +#ifndef __ARCH_ASM_MACH_OMAP2_CM2XXX_H
> +#define __ARCH_ASM_MACH_OMAP2_CM2XXX_H
> +
> +#include "prcm-common.h"
> +#include "cm2xxx_3xxx.h"
> +
> +#define OMAP2420_CM_REGADDR(module, reg) \
> + OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg))
> +#define OMAP2430_CM_REGADDR(module, reg) \
> + OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
> +
> +/*
> + * Module specific CM register offsets from CM_BASE + domain offset
> + * Use cm_{read,write}_mod_reg() with these registers.
> + * These register offsets generally appear in more than one PRCM submodule.
> + */
> +
> +/* OMAP2-specific register offsets */
> +
> +#define OMAP24XX_CM_FCLKEN2 0x0004
> +#define OMAP24XX_CM_ICLKEN4 0x001c
> +#define OMAP24XX_CM_AUTOIDLE4 0x003c
> +#define OMAP24XX_CM_IDLEST4 0x002c
> +
> +#define OMAP2430_CM_IDLEST3 0x0028
> +
> +/* CM_IDLEST bit field values to indicate deasserted IdleReq */
> +
> +#define OMAP24XX_CM_IDLEST_VAL 0
> +
> +
> +/* Clock management domain register get/set */
> +
> +#ifndef __ASSEMBLER__
> +
> +extern void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask);
> +extern void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask);
> +
> +extern void omap2xxx_cm_set_dpll_disable_autoidle(void);
> +extern void omap2xxx_cm_set_dpll_auto_low_power_stop(void);
> +
> +extern void omap2xxx_cm_set_apll54_disable_autoidle(void);
> +extern void omap2xxx_cm_set_apll54_auto_low_power_stop(void);
> +extern void omap2xxx_cm_set_apll96_disable_autoidle(void);
> +extern void omap2xxx_cm_set_apll96_auto_low_power_stop(void);
> +
> +extern bool omap2xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask);
> +extern int omap2xxx_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id,
> + u8 idlest_shift);
> +
> +#endif
> +
> +#endif
> diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.h b/arch/arm/mach-omap2/cm2xxx_3xxx.h
> index 57b2f3c..64df725 100644
> --- a/arch/arm/mach-omap2/cm2xxx_3xxx.h
> +++ b/arch/arm/mach-omap2/cm2xxx_3xxx.h
> @@ -18,27 +18,6 @@
>
> #include "prcm-common.h"
>
> -#define OMAP2420_CM_REGADDR(module, reg) \
> - OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg))
> -#define OMAP2430_CM_REGADDR(module, reg) \
> - OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
> -#define OMAP34XX_CM_REGADDR(module, reg) \
> - OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
> -
> -
> -/*
> - * OMAP3-specific global CM registers
> - * Use cm_{read,write}_reg() with these registers.
> - * These registers appear once per CM module.
> - */
> -
> -#define OMAP3430_CM_REVISION OMAP34XX_CM_REGADDR(OCP_MOD, 0x0000)
> -#define OMAP3430_CM_SYSCONFIG OMAP34XX_CM_REGADDR(OCP_MOD, 0x0010)
> -#define OMAP3430_CM_POLCTRL OMAP34XX_CM_REGADDR(OCP_MOD, 0x009c)
> -
> -#define OMAP3_CM_CLKOUT_CTRL_OFFSET 0x0070
> -#define OMAP3430_CM_CLKOUT_CTRL OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
> -
> /*
> * Module specific CM register offsets from CM_BASE + domain offset
> * Use cm_{read,write}_mod_reg() with these registers.
> @@ -66,70 +45,43 @@
> #define CM_CLKSEL2 0x0044
> #define OMAP2_CM_CLKSTCTRL 0x0048
>
> -/* OMAP2-specific register offsets */
> -
> -#define OMAP24XX_CM_FCLKEN2 0x0004
> -#define OMAP24XX_CM_ICLKEN4 0x001c
> -#define OMAP24XX_CM_AUTOIDLE4 0x003c
> -#define OMAP24XX_CM_IDLEST4 0x002c
> -
> -#define OMAP2430_CM_IDLEST3 0x0028
> -
> -/* OMAP3-specific register offsets */
> -
> -#define OMAP3430_CM_CLKEN_PLL 0x0004
> -#define OMAP3430ES2_CM_CLKEN2 0x0004
> -#define OMAP3430ES2_CM_FCLKEN3 0x0008
> -#define OMAP3430_CM_IDLEST_PLL CM_IDLEST2
> -#define OMAP3430_CM_AUTOIDLE_PLL CM_AUTOIDLE2
> -#define OMAP3430ES2_CM_AUTOIDLE2_PLL CM_AUTOIDLE2
> -#define OMAP3430_CM_CLKSEL1 CM_CLKSEL
> -#define OMAP3430_CM_CLKSEL1_PLL CM_CLKSEL
> -#define OMAP3430_CM_CLKSEL2_PLL CM_CLKSEL2
> -#define OMAP3430_CM_SLEEPDEP CM_CLKSEL2
> -#define OMAP3430_CM_CLKSEL3 OMAP2_CM_CLKSTCTRL
> -#define OMAP3430_CM_CLKSTST 0x004c
> -#define OMAP3430ES2_CM_CLKSEL4 0x004c
> -#define OMAP3430ES2_CM_CLKSEL5 0x0050
> -#define OMAP3430_CM_CLKSEL2_EMU 0x0050
> -#define OMAP3430_CM_CLKSEL3_EMU 0x0054
> -
> -
> -/* CM_IDLEST bit field values to indicate deasserted IdleReq */
> -
> -#define OMAP24XX_CM_IDLEST_VAL 0
> -#define OMAP34XX_CM_IDLEST_VAL 1
> -
> +#ifndef __ASSEMBLER__
>
> -/* Clock management domain register get/set */
> +#include <linux/io.h>
>
> -#ifndef __ASSEMBLER__
> +static inline u32 omap2_cm_read_mod_reg(s16 module, u16 idx)
> +{
> + return __raw_readl(cm_base + module + idx);
> +}
>
> -extern u32 omap2_cm_read_mod_reg(s16 module, u16 idx);
> -extern void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx);
> -extern u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
> +static inline void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx)
> +{
> + __raw_writel(val, cm_base + module + idx);
> +}
>
> -extern int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id,
> - u8 idlest_shift);
> -extern u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx);
> -extern u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx);
> +/* Read-modify-write a register in a CM module. Caller must lock */
> +static inline u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module,
> + s16 idx)
> +{
> + u32 v;
>
> -extern bool omap2_cm_is_clkdm_in_hwsup(s16 module, u32 mask);
> -extern void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask);
> -extern void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask);
> + v = omap2_cm_read_mod_reg(module, idx);
> + v &= ~mask;
> + v |= bits;
> + omap2_cm_write_mod_reg(v, module, idx);
>
> -extern void omap3xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask);
> -extern void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask);
> -extern void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask);
> -extern void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask);
> + return v;
> +}
>
> -extern void omap2xxx_cm_set_dpll_disable_autoidle(void);
> -extern void omap2xxx_cm_set_dpll_auto_low_power_stop(void);
> +static inline u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
> +{
> + return omap2_cm_rmw_mod_reg_bits(bits, bits, module, idx);
> +}
>
> -extern void omap2xxx_cm_set_apll54_disable_autoidle(void);
> -extern void omap2xxx_cm_set_apll54_auto_low_power_stop(void);
> -extern void omap2xxx_cm_set_apll96_disable_autoidle(void);
> -extern void omap2xxx_cm_set_apll96_auto_low_power_stop(void);
> +static inline u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
> +{
> + return omap2_cm_rmw_mod_reg_bits(bits, 0x0, module, idx);
> +}
>
> #endif
>
> @@ -147,10 +99,4 @@ extern void omap2xxx_cm_set_apll96_auto_low_power_stop(void);
> #define OMAP_ST_GFX_MASK (1 << 0)
>
>
> -/* Function prototypes */
> -# ifndef __ASSEMBLER__
> -extern void omap3_cm_save_context(void);
> -extern void omap3_cm_restore_context(void);
> -# endif
> -
> #endif
> diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.c b/arch/arm/mach-omap2/cm3xxx.c
> similarity index 80%
> rename from arch/arm/mach-omap2/cm2xxx_3xxx.c
> rename to arch/arm/mach-omap2/cm3xxx.c
> index 7f07ab0..075cabe 100644
> --- a/arch/arm/mach-omap2/cm2xxx_3xxx.c
> +++ b/arch/arm/mach-omap2/cm3xxx.c
> @@ -12,8 +12,6 @@
> #include <linux/kernel.h>
> #include <linux/types.h>
> #include <linux/delay.h>
> -#include <linux/spinlock.h>
> -#include <linux/list.h>
> #include <linux/errno.h>
> #include <linux/err.h>
> #include <linux/io.h>
> @@ -22,54 +20,10 @@
> #include "iomap.h"
> #include "common.h"
> #include "cm.h"
> -#include "cm2xxx_3xxx.h"
> -#include "cm-regbits-24xx.h"
> +#include "cm3xxx.h"
> #include "cm-regbits-34xx.h"
>
> -/* CM_AUTOIDLE_PLL.AUTO_* bit values for DPLLs */
> -#define DPLL_AUTOIDLE_DISABLE 0x0
> -#define OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP 0x3
> -
> -/* CM_AUTOIDLE_PLL.AUTO_* bit values for APLLs (OMAP2xxx only) */
> -#define OMAP2XXX_APLL_AUTOIDLE_DISABLE 0x0
> -#define OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP 0x3
> -
> -static const u8 cm_idlest_offs[] = {
> - CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3, OMAP24XX_CM_IDLEST4
> -};
> -
> -u32 omap2_cm_read_mod_reg(s16 module, u16 idx)
> -{
> - return __raw_readl(cm_base + module + idx);
> -}
> -
> -void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx)
> -{
> - __raw_writel(val, cm_base + module + idx);
> -}
> -
> -/* Read-modify-write a register in a CM module. Caller must lock */
> -u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
> -{
> - u32 v;
> -
> - v = omap2_cm_read_mod_reg(module, idx);
> - v &= ~mask;
> - v |= bits;
> - omap2_cm_write_mod_reg(v, module, idx);
> -
> - return v;
> -}
> -
> -u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
> -{
> - return omap2_cm_rmw_mod_reg_bits(bits, bits, module, idx);
> -}
> -
> -u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
> -{
> - return omap2_cm_rmw_mod_reg_bits(bits, 0x0, module, idx);
> -}
> +static const u8 omap3xxx_cm_idlest_offs[] = { CM_IDLEST1, CM_IDLEST2 };
>
> /*
> *
> @@ -85,33 +39,15 @@ static void _write_clktrctrl(u8 c, s16 module, u32 mask)
> omap2_cm_write_mod_reg(v, module, OMAP2_CM_CLKSTCTRL);
> }
>
> -bool omap2_cm_is_clkdm_in_hwsup(s16 module, u32 mask)
> +bool omap3xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask)
> {
> u32 v;
> - bool ret = 0;
> -
> - BUG_ON(!cpu_is_omap24xx() && !cpu_is_omap34xx());
>
> v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
> v &= mask;
> v >>= __ffs(mask);
>
> - if (cpu_is_omap24xx())
> - ret = (v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
> - else
> - ret = (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
> -
> - return ret;
> -}
> -
> -void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask)
> -{
> - _write_clktrctrl(OMAP24XX_CLKSTCTRL_ENABLE_AUTO, module, mask);
> -}
> -
> -void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask)
> -{
> - _write_clktrctrl(OMAP24XX_CLKSTCTRL_DISABLE_AUTO, module, mask);
> + return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
> }
>
> void omap3xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask)
> @@ -135,101 +71,35 @@ void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask)
> }
>
> /*
> - * DPLL autoidle control
> - */
> -
> -static void _omap2xxx_set_dpll_autoidle(u8 m)
> -{
> - u32 v;
> -
> - v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
> - v &= ~OMAP24XX_AUTO_DPLL_MASK;
> - v |= m << OMAP24XX_AUTO_DPLL_SHIFT;
> - omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
> -}
> -
> -void omap2xxx_cm_set_dpll_disable_autoidle(void)
> -{
> - _omap2xxx_set_dpll_autoidle(OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP);
> -}
> -
> -void omap2xxx_cm_set_dpll_auto_low_power_stop(void)
> -{
> - _omap2xxx_set_dpll_autoidle(DPLL_AUTOIDLE_DISABLE);
> -}
> -
> -/*
> - * APLL autoidle control
> - */
> -
> -static void _omap2xxx_set_apll_autoidle(u8 m, u32 mask)
> -{
> - u32 v;
> -
> - v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
> - v &= ~mask;
> - v |= m << __ffs(mask);
> - omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
> -}
> -
> -void omap2xxx_cm_set_apll54_disable_autoidle(void)
> -{
> - _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP,
> - OMAP24XX_AUTO_54M_MASK);
> -}
> -
> -void omap2xxx_cm_set_apll54_auto_low_power_stop(void)
> -{
> - _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE,
> - OMAP24XX_AUTO_54M_MASK);
> -}
> -
> -void omap2xxx_cm_set_apll96_disable_autoidle(void)
> -{
> - _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP,
> - OMAP24XX_AUTO_96M_MASK);
> -}
> -
> -void omap2xxx_cm_set_apll96_auto_low_power_stop(void)
> -{
> - _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE,
> - OMAP24XX_AUTO_96M_MASK);
> -}
> -
> -/*
> *
> */
>
> /**
> - * omap2_cm_wait_idlest_ready - wait for a module to leave idle or standby
> + * omap3xxx_cm_wait_module_ready - wait for a module to leave idle or standby
> * @prcm_mod: PRCM module offset
> * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3)
> * @idlest_shift: shift of the bit in the CM_IDLEST* register to check
> *
> - * XXX document
> + * Wait for the PRCM to indicate that the module identified by
> + * (@prcm_mod, @idlest_id, @idlest_shift) is clocked. Return 0 upon
> + * success or -EBUSY if the module doesn't enable in time.
> */
> -int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift)
> +int omap3xxx_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift)
> {
> int ena = 0, i = 0;
> u8 cm_idlest_reg;
> u32 mask;
>
> - if (!idlest_id || (idlest_id > ARRAY_SIZE(cm_idlest_offs)))
> + if (!idlest_id || (idlest_id > ARRAY_SIZE(omap3xxx_cm_idlest_offs)))
> return -EINVAL;
>
> - cm_idlest_reg = cm_idlest_offs[idlest_id - 1];
> + cm_idlest_reg = omap3xxx_cm_idlest_offs[idlest_id - 1];
>
> mask = 1 << idlest_shift;
> + ena = 0;
>
> - if (cpu_is_omap24xx())
> - ena = mask;
> - else if (cpu_is_omap34xx())
> - ena = 0;
> - else
> - BUG();
> -
> - omap_test_timeout(((omap2_cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) == ena),
> - MAX_MODULE_READY_TIME, i);
> + omap_test_timeout(((omap2_cm_read_mod_reg(prcm_mod, cm_idlest_reg) &
> + mask) == ena), MAX_MODULE_READY_TIME, i);
>
> return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
> }
> @@ -237,7 +107,6 @@ int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift)
> /*
> * Context save/restore code - OMAP3 only
> */
> -#ifdef CONFIG_ARCH_OMAP3
> struct omap3_cm_regs {
> u32 iva2_cm_clksel1;
> u32 iva2_cm_clksel2;
> @@ -555,4 +424,3 @@ void omap3_cm_restore_context(void)
> omap2_cm_write_mod_reg(cm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD,
> OMAP3_CM_CLKOUT_CTRL_OFFSET);
> }
> -#endif
> diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.h b/arch/arm/mach-omap2/cm3xxx.h
> similarity index 50%
> copy from arch/arm/mach-omap2/cm2xxx_3xxx.h
> copy to arch/arm/mach-omap2/cm3xxx.h
> index 57b2f3c..4a6ac81 100644
> --- a/arch/arm/mach-omap2/cm2xxx_3xxx.h
> +++ b/arch/arm/mach-omap2/cm3xxx.h
> @@ -13,15 +13,12 @@
> * other. The CM modules/instances on OMAP4 are quite different, so
> * they are handled in a separate file.
> */
> -#ifndef __ARCH_ASM_MACH_OMAP2_CM2XXX_3XXX_H
> -#define __ARCH_ASM_MACH_OMAP2_CM2XXX_3XXX_H
> +#ifndef __ARCH_ASM_MACH_OMAP2_CM3XXX_H
> +#define __ARCH_ASM_MACH_OMAP2_CM3XXX_H
>
> #include "prcm-common.h"
> +#include "cm2xxx_3xxx.h"
>
> -#define OMAP2420_CM_REGADDR(module, reg) \
> - OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg))
> -#define OMAP2430_CM_REGADDR(module, reg) \
> - OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
> #define OMAP34XX_CM_REGADDR(module, reg) \
> OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
>
> @@ -45,36 +42,6 @@
> * These register offsets generally appear in more than one PRCM submodule.
> */
>
> -/* Common between OMAP2 and OMAP3 */
> -
> -#define CM_FCLKEN 0x0000
> -#define CM_FCLKEN1 CM_FCLKEN
> -#define CM_CLKEN CM_FCLKEN
> -#define CM_ICLKEN 0x0010
> -#define CM_ICLKEN1 CM_ICLKEN
> -#define CM_ICLKEN2 0x0014
> -#define CM_ICLKEN3 0x0018
> -#define CM_IDLEST 0x0020
> -#define CM_IDLEST1 CM_IDLEST
> -#define CM_IDLEST2 0x0024
> -#define CM_AUTOIDLE 0x0030
> -#define CM_AUTOIDLE1 CM_AUTOIDLE
> -#define CM_AUTOIDLE2 0x0034
> -#define CM_AUTOIDLE3 0x0038
> -#define CM_CLKSEL 0x0040
> -#define CM_CLKSEL1 CM_CLKSEL
> -#define CM_CLKSEL2 0x0044
> -#define OMAP2_CM_CLKSTCTRL 0x0048
> -
> -/* OMAP2-specific register offsets */
> -
> -#define OMAP24XX_CM_FCLKEN2 0x0004
> -#define OMAP24XX_CM_ICLKEN4 0x001c
> -#define OMAP24XX_CM_AUTOIDLE4 0x003c
> -#define OMAP24XX_CM_IDLEST4 0x002c
> -
> -#define OMAP2430_CM_IDLEST3 0x0028
> -
> /* OMAP3-specific register offsets */
>
> #define OMAP3430_CM_CLKEN_PLL 0x0004
> @@ -97,60 +64,23 @@
>
> /* CM_IDLEST bit field values to indicate deasserted IdleReq */
>
> -#define OMAP24XX_CM_IDLEST_VAL 0
> #define OMAP34XX_CM_IDLEST_VAL 1
>
>
> -/* Clock management domain register get/set */
> -
> #ifndef __ASSEMBLER__
>
> -extern u32 omap2_cm_read_mod_reg(s16 module, u16 idx);
> -extern void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx);
> -extern u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
> -
> -extern int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id,
> - u8 idlest_shift);
> -extern u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx);
> -extern u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx);
> -
> -extern bool omap2_cm_is_clkdm_in_hwsup(s16 module, u32 mask);
> -extern void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask);
> -extern void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask);
> -
> extern void omap3xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask);
> extern void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask);
> extern void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask);
> extern void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask);
>
> -extern void omap2xxx_cm_set_dpll_disable_autoidle(void);
> -extern void omap2xxx_cm_set_dpll_auto_low_power_stop(void);
> -
> -extern void omap2xxx_cm_set_apll54_disable_autoidle(void);
> -extern void omap2xxx_cm_set_apll54_auto_low_power_stop(void);
> -extern void omap2xxx_cm_set_apll96_disable_autoidle(void);
> -extern void omap2xxx_cm_set_apll96_auto_low_power_stop(void);
> -
> -#endif
> +extern bool omap3xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask);
> +extern int omap3xxx_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id,
> + u8 idlest_shift);
>
> -/* CM register bits shared between 24XX and 3430 */
> -
> -/* CM_CLKSEL_GFX */
> -#define OMAP_CLKSEL_GFX_SHIFT 0
> -#define OMAP_CLKSEL_GFX_MASK (0x7 << 0)
> -
> -/* CM_ICLKEN_GFX */
> -#define OMAP_EN_GFX_SHIFT 0
> -#define OMAP_EN_GFX_MASK (1 << 0)
> -
> -/* CM_IDLEST_GFX */
> -#define OMAP_ST_GFX_MASK (1 << 0)
> -
> -
> -/* Function prototypes */
> -# ifndef __ASSEMBLER__
> extern void omap3_cm_save_context(void);
> extern void omap3_cm_restore_context(void);
> -# endif
> +
> +#endif
>
> #endif
> diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
> index 1220e0e..a7d1eb8 100644
> --- a/arch/arm/mach-omap2/control.c
> +++ b/arch/arm/mach-omap2/control.c
> @@ -23,7 +23,7 @@
> #include "cm-regbits-34xx.h"
> #include "prm-regbits-34xx.h"
> #include "prm3xxx.h"
> -#include "cm2xxx_3xxx.h"
> +#include "cm3xxx.h"
> #include "sdrc.h"
> #include "pm.h"
> #include "control.h"
> diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
> index 525c58d..504e0e0 100644
> --- a/arch/arm/mach-omap2/omap_hwmod.c
> +++ b/arch/arm/mach-omap2/omap_hwmod.c
> @@ -147,7 +147,8 @@
> #include "common.h"
> #include "clockdomain.h"
> #include "powerdomain.h"
> -#include "cm2xxx_3xxx.h"
> +#include "cm2xxx.h"
> +#include "cm3xxx.h"
> #include "cminst44xx.h"
> #include "cm33xx.h"
> #include "prm3xxx.h"
> @@ -2668,7 +2669,7 @@ static int __init _alloc_linkspace(struct omap_hwmod_ocp_if **ois)
> /* Static functions intended only for use in soc_ops field function pointers */
>
> /**
> - * _omap2_wait_target_ready - wait for a module to leave slave idle
> + * _omap2xxx_wait_target_ready - wait for a module to leave slave idle
> * @oh: struct omap_hwmod *
> *
> * Wait for a module @oh to leave slave idle. Returns 0 if the module
> @@ -2676,7 +2677,7 @@ static int __init _alloc_linkspace(struct omap_hwmod_ocp_if **ois)
> * slave idle; otherwise, pass along the return value of the
> * appropriate *_cm*_wait_module_ready() function.
> */
> -static int _omap2_wait_target_ready(struct omap_hwmod *oh)
> +static int _omap2xxx_wait_target_ready(struct omap_hwmod *oh)
> {
> if (!oh)
> return -EINVAL;
> @@ -2689,9 +2690,36 @@ static int _omap2_wait_target_ready(struct omap_hwmod *oh)
>
> /* XXX check module SIDLEMODE, hardreset status, enabled clocks */
>
> - return omap2_cm_wait_module_ready(oh->prcm.omap2.module_offs,
> - oh->prcm.omap2.idlest_reg_id,
> - oh->prcm.omap2.idlest_idle_bit);
> + return omap2xxx_cm_wait_module_ready(oh->prcm.omap2.module_offs,
> + oh->prcm.omap2.idlest_reg_id,
> + oh->prcm.omap2.idlest_idle_bit);
> +}
> +
> +/**
> + * _omap3xxx_wait_target_ready - wait for a module to leave slave idle
> + * @oh: struct omap_hwmod *
> + *
> + * Wait for a module @oh to leave slave idle. Returns 0 if the module
> + * does not have an IDLEST bit or if the module successfully leaves
> + * slave idle; otherwise, pass along the return value of the
> + * appropriate *_cm*_wait_module_ready() function.
> + */
> +static int _omap3xxx_wait_target_ready(struct omap_hwmod *oh)
> +{
> + if (!oh)
> + return -EINVAL;
> +
> + if (oh->flags & HWMOD_NO_IDLEST)
> + return 0;
> +
> + if (!_find_mpu_rt_port(oh))
> + return 0;
> +
> + /* XXX check module SIDLEMODE, hardreset status, enabled clocks */
> +
> + return omap3xxx_cm_wait_module_ready(oh->prcm.omap2.module_offs,
> + oh->prcm.omap2.idlest_reg_id,
> + oh->prcm.omap2.idlest_idle_bit);
> }
>
> /**
> @@ -3959,8 +3987,13 @@ int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx)
> */
> void __init omap_hwmod_init(void)
> {
> - if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
> - soc_ops.wait_target_ready = _omap2_wait_target_ready;
> + if (cpu_is_omap24xx()) {
> + soc_ops.wait_target_ready = _omap2xxx_wait_target_ready;
> + soc_ops.assert_hardreset = _omap2_assert_hardreset;
> + soc_ops.deassert_hardreset = _omap2_deassert_hardreset;
> + soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted;
> + } else if (cpu_is_omap34xx()) {
> + soc_ops.wait_target_ready = _omap3xxx_wait_target_ready;
> soc_ops.assert_hardreset = _omap2_assert_hardreset;
> soc_ops.deassert_hardreset = _omap2_deassert_hardreset;
> soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted;
> diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
> index 78405a7..02dca24 100644
> --- a/arch/arm/mach-omap2/pm24xx.c
> +++ b/arch/arm/mach-omap2/pm24xx.c
> @@ -43,7 +43,7 @@
> #include "common.h"
> #include "prm2xxx.h"
> #include "prm-regbits-24xx.h"
> -#include "cm2xxx_3xxx.h"
> +#include "cm2xxx.h"
> #include "cm-regbits-24xx.h"
> #include "sdrc.h"
> #include "pm.h"
> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
> index c02c9ca..c0f8a78 100644
> --- a/arch/arm/mach-omap2/pm34xx.c
> +++ b/arch/arm/mach-omap2/pm34xx.c
> @@ -44,10 +44,9 @@
> #include <plat/dma.h>
>
> #include "common.h"
> -#include "cm2xxx_3xxx.h"
> +#include "cm3xxx.h"
> #include "cm-regbits-34xx.h"
> #include "prm-regbits-34xx.h"
> -
> #include "prm3xxx.h"
> #include "pm.h"
> #include "sdrc.h"
> diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
> index d83b918..b5bc4b1 100644
> --- a/arch/arm/mach-omap2/sleep34xx.S
> +++ b/arch/arm/mach-omap2/sleep34xx.S
> @@ -30,7 +30,7 @@
>
> #include "omap34xx.h"
> #include "iomap.h"
> -#include "cm2xxx_3xxx.h"
> +#include "cm3xxx.h"
> #include "prm3xxx.h"
> #include "sdrc.h"
> #include "control.h"
> diff --git a/arch/arm/mach-omap2/sram242x.S b/arch/arm/mach-omap2/sram242x.S
> index c720443..680a7c5 100644
> --- a/arch/arm/mach-omap2/sram242x.S
> +++ b/arch/arm/mach-omap2/sram242x.S
> @@ -35,7 +35,7 @@
> #include "soc.h"
> #include "iomap.h"
> #include "prm2xxx.h"
> -#include "cm2xxx_3xxx.h"
> +#include "cm2xxx.h"
> #include "sdrc.h"
>
> .text
> diff --git a/arch/arm/mach-omap2/sram243x.S b/arch/arm/mach-omap2/sram243x.S
> index cfdc0bc..a1e9edd 100644
> --- a/arch/arm/mach-omap2/sram243x.S
> +++ b/arch/arm/mach-omap2/sram243x.S
> @@ -35,7 +35,7 @@
> #include "soc.h"
> #include "iomap.h"
> #include "prm2xxx.h"
> -#include "cm2xxx_3xxx.h"
> +#include "cm2xxx.h"
> #include "sdrc.h"
>
> .text
> diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
> index 2d0ceaa..1446331 100644
> --- a/arch/arm/mach-omap2/sram34xx.S
> +++ b/arch/arm/mach-omap2/sram34xx.S
> @@ -32,7 +32,7 @@
> #include "soc.h"
> #include "iomap.h"
> #include "sdrc.h"
> -#include "cm2xxx_3xxx.h"
> +#include "cm3xxx.h"
>
> /*
> * This file needs be built unconditionally as ARM to interoperate correctly
>
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* [PATCH] ARM: dts: AM33XX: Add tsl2550 ambient light sensor DT data
From: AnilKumar, Chimata @ 2012-10-18 11:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <507FB8FE.6010003@ti.com>
+Grant, DTML
On Thu, Oct 18, 2012 at 13:38:30, Cousson, Benoit wrote:
> Hi Anil,
>
> On 10/18/2012 07:46 AM, AnilKumar, Chimata wrote:
> > On Fri, Sep 21, 2012 at 21:19:11, AnilKumar, Chimata wrote:
> >> Add tsl2550 ambient light sensor DT data to am335x-evm.dts. In AM335x
> >> EVM tsl2550 ambient light sensor is connected to I2C2 bus. So this patch
> >> adds child node inside i2c2 node with i2c slave address.
> >>
> >> TAOS tsl2550 sensor with two-wire SMBus serial interface. This patch
> >> also reduces I2C2 clock frequency to 100KHz from 400KHz because the
> >> maximum clock frequency of SMBus is 100KHz.
> >>
> >> Signed-off-by: AnilKumar Ch <anilkumar@ti.com>
> >> ---
> >> arch/arm/boot/dts/am335x-evm.dts | 7 ++++++-
> >> 1 file changed, 6 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
> >> index 3b1f313..d99aa0f 100644
> >> --- a/arch/arm/boot/dts/am335x-evm.dts
> >> +++ b/arch/arm/boot/dts/am335x-evm.dts
> >> @@ -49,7 +49,7 @@
> >>
> >> i2c2: i2c at 4802a000 {
> >> status = "okay";
> >> - clock-frequency = <400000>;
> >> + clock-frequency = <100000>;
> >>
> >> lis331dlh: lis331dlh at 18 {
> >> compatible = "st,lis331dlh", "st,lis3lv02d";
> >> @@ -79,6 +79,11 @@
> >> st,max-limit-z = <750>;
> >> };
> >>
> >> + tsl2550: tsl2550 at 39 {
> >> + compatible = "taos,tsl2550";
> >> + reg = <0x39>;
> >> + };
> >> +
> >> tmp275: tmp275 at 48 {
> >> compatible = "ti,tmp275";
> >> reg = <0x48>;
> >
> > Hi Tony/Benoit,
> >
> > If there are no comments in this patch could you please take this in?
>
> Have you updated the binding documentation to list the device?
>
> It should be in:
> Documentation/devicetree/bindings/i2c/trivial-devices.txt
>
No I have not updated, I will send a separate patch by adding all the supported
devices, missed from earlier (this device, tmp275 and lis331dlh)
Thanks
AnilKumar
^ permalink raw reply
* [PATCH 3/5] ARM: OMAP2+: powerdomain/PRM: move the low-level powerdomain functions into PRM
From: Russ Dill @ 2012-10-18 11:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121015230542.18306.88940.stgit@dusk.lan>
On Mon, Oct 15, 2012 at 4:05 PM, Paul Walmsley <paul@pwsan.com> wrote:
> Move the low-level SoC-specific powerdomain control functions into
> prm*.c. For example, OMAP2xxx low-level powerdomain functions go into
> prm2xxx.c. Then remove the unnecessary powerdomain*xxx*.c files.
>
> The objective is to centralize low-level PRM register accesses into
> the prm*.[ch] files, and then to export an OMAP SoC-independent API to
> higher-level OMAP power management code.
Looks good
Reviewed-by: Russ.Dill at ti.com
> Signed-off-by: Paul Walmsley <paul@pwsan.com>
> Cc: Rajendra Nayak <rnayak@ti.com>
> Cc: Vaibhav Hiremath <hvaibhav@ti.com>
> ---
> arch/arm/mach-omap2/Makefile | 1
> arch/arm/mach-omap2/powerdomain2xxx_3xxx.c | 242 ------------------------
> arch/arm/mach-omap2/powerdomain33xx.c | 229 ----------------------
> arch/arm/mach-omap2/powerdomain44xx.c | 285 ----------------------------
> arch/arm/mach-omap2/prm2xxx.c | 40 ++++
> arch/arm/mach-omap2/prm2xxx_3xxx.c | 112 +++++++++++
> arch/arm/mach-omap2/prm2xxx_3xxx.h | 13 +
> arch/arm/mach-omap2/prm33xx.c | 202 ++++++++++++++++++++
> arch/arm/mach-omap2/prm3xxx.c | 106 ++++++++++
> arch/arm/mach-omap2/prm44xx.c | 264 ++++++++++++++++++++++++++
> 10 files changed, 736 insertions(+), 758 deletions(-)
> delete mode 100644 arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
> delete mode 100644 arch/arm/mach-omap2/powerdomain33xx.c
> delete mode 100644 arch/arm/mach-omap2/powerdomain44xx.c
> create mode 100644 arch/arm/mach-omap2/prm2xxx.c
>
> diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
> index 20849604..7404e3d 100644
> --- a/arch/arm/mach-omap2/Makefile
> +++ b/arch/arm/mach-omap2/Makefile
> @@ -95,6 +95,7 @@ endif
> # PRCM
> obj-y += prcm.o prm_common.o
> obj-$(CONFIG_ARCH_OMAP2) += cm2xxx_3xxx.o prm2xxx_3xxx.o
> +obj-$(CONFIG_ARCH_OMAP2) += prm2xxx.o
> obj-$(CONFIG_ARCH_OMAP3) += cm2xxx_3xxx.o prm2xxx_3xxx.o
> obj-$(CONFIG_ARCH_OMAP3) += prm3xxx.o
> obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o
> diff --git a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
> deleted file mode 100644
> index 3950ccf..0000000
> --- a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
> +++ /dev/null
> @@ -1,242 +0,0 @@
> -/*
> - * OMAP2 and OMAP3 powerdomain control
> - *
> - * Copyright (C) 2009-2011 Texas Instruments, Inc.
> - * Copyright (C) 2007-2009 Nokia Corporation
> - *
> - * Derived from mach-omap2/powerdomain.c written by Paul Walmsley
> - * Rajendra Nayak <rnayak@ti.com>
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License version 2 as
> - * published by the Free Software Foundation.
> - */
> -
> -#include <linux/io.h>
> -#include <linux/errno.h>
> -#include <linux/delay.h>
> -#include <linux/bug.h>
> -
> -#include <plat/prcm.h>
> -
> -#include "powerdomain.h"
> -#include "prm.h"
> -#include "prm-regbits-24xx.h"
> -#include "prm-regbits-34xx.h"
> -
> -
> -/* Common functions across OMAP2 and OMAP3 */
> -static int omap2_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
> -{
> - omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK,
> - (pwrst << OMAP_POWERSTATE_SHIFT),
> - pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
> - return 0;
> -}
> -
> -static int omap2_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
> -{
> - return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
> - OMAP2_PM_PWSTCTRL,
> - OMAP_POWERSTATE_MASK);
> -}
> -
> -static int omap2_pwrdm_read_pwrst(struct powerdomain *pwrdm)
> -{
> - return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
> - OMAP2_PM_PWSTST,
> - OMAP_POWERSTATEST_MASK);
> -}
> -
> -static int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
> - u8 pwrst)
> -{
> - u32 m;
> -
> - m = omap2_pwrdm_get_mem_bank_onstate_mask(bank);
> -
> - omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs,
> - OMAP2_PM_PWSTCTRL);
> -
> - return 0;
> -}
> -
> -static int omap2_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
> - u8 pwrst)
> -{
> - u32 m;
> -
> - m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
> -
> - omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs,
> - OMAP2_PM_PWSTCTRL);
> -
> - return 0;
> -}
> -
> -static int omap2_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
> -{
> - u32 m;
> -
> - m = omap2_pwrdm_get_mem_bank_stst_mask(bank);
> -
> - return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTST,
> - m);
> -}
> -
> -static int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
> -{
> - u32 m;
> -
> - m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
> -
> - return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
> - OMAP2_PM_PWSTCTRL, m);
> -}
> -
> -static int omap2_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
> -{
> - u32 v;
> -
> - v = pwrst << __ffs(OMAP3430_LOGICL1CACHERETSTATE_MASK);
> - omap2_prm_rmw_mod_reg_bits(OMAP3430_LOGICL1CACHERETSTATE_MASK, v,
> - pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
> -
> - return 0;
> -}
> -
> -static int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm)
> -{
> - u32 c = 0;
> -
> - /*
> - * REVISIT: pwrdm_wait_transition() may be better implemented
> - * via a callback and a periodic timer check -- how long do we expect
> - * powerdomain transitions to take?
> - */
> -
> - /* XXX Is this udelay() value meaningful? */
> - while ((omap2_prm_read_mod_reg(pwrdm->prcm_offs, OMAP2_PM_PWSTST) &
> - OMAP_INTRANSITION_MASK) &&
> - (c++ < PWRDM_TRANSITION_BAILOUT))
> - udelay(1);
> -
> - if (c > PWRDM_TRANSITION_BAILOUT) {
> - pr_err("powerdomain: %s: waited too long to complete transition\n",
> - pwrdm->name);
> - return -EAGAIN;
> - }
> -
> - pr_debug("powerdomain: completed transition in %d loops\n", c);
> -
> - return 0;
> -}
> -
> -/* Applicable only for OMAP3. Not supported on OMAP2 */
> -static int omap3_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
> -{
> - return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
> - OMAP3430_PM_PREPWSTST,
> - OMAP3430_LASTPOWERSTATEENTERED_MASK);
> -}
> -
> -static int omap3_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
> -{
> - return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
> - OMAP2_PM_PWSTST,
> - OMAP3430_LOGICSTATEST_MASK);
> -}
> -
> -static int omap3_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
> -{
> - return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
> - OMAP2_PM_PWSTCTRL,
> - OMAP3430_LOGICSTATEST_MASK);
> -}
> -
> -static int omap3_pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm)
> -{
> - return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
> - OMAP3430_PM_PREPWSTST,
> - OMAP3430_LASTLOGICSTATEENTERED_MASK);
> -}
> -
> -static int omap3_get_mem_bank_lastmemst_mask(u8 bank)
> -{
> - switch (bank) {
> - case 0:
> - return OMAP3430_LASTMEM1STATEENTERED_MASK;
> - case 1:
> - return OMAP3430_LASTMEM2STATEENTERED_MASK;
> - case 2:
> - return OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK;
> - case 3:
> - return OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK;
> - default:
> - WARN_ON(1); /* should never happen */
> - return -EEXIST;
> - }
> - return 0;
> -}
> -
> -static int omap3_pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
> -{
> - u32 m;
> -
> - m = omap3_get_mem_bank_lastmemst_mask(bank);
> -
> - return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
> - OMAP3430_PM_PREPWSTST, m);
> -}
> -
> -static int omap3_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
> -{
> - omap2_prm_write_mod_reg(0, pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST);
> - return 0;
> -}
> -
> -static int omap3_pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm)
> -{
> - return omap2_prm_rmw_mod_reg_bits(0,
> - 1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT,
> - pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
> -}
> -
> -static int omap3_pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm)
> -{
> - return omap2_prm_rmw_mod_reg_bits(1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT,
> - 0, pwrdm->prcm_offs,
> - OMAP2_PM_PWSTCTRL);
> -}
> -
> -struct pwrdm_ops omap2_pwrdm_operations = {
> - .pwrdm_set_next_pwrst = omap2_pwrdm_set_next_pwrst,
> - .pwrdm_read_next_pwrst = omap2_pwrdm_read_next_pwrst,
> - .pwrdm_read_pwrst = omap2_pwrdm_read_pwrst,
> - .pwrdm_set_logic_retst = omap2_pwrdm_set_logic_retst,
> - .pwrdm_set_mem_onst = omap2_pwrdm_set_mem_onst,
> - .pwrdm_set_mem_retst = omap2_pwrdm_set_mem_retst,
> - .pwrdm_read_mem_pwrst = omap2_pwrdm_read_mem_pwrst,
> - .pwrdm_read_mem_retst = omap2_pwrdm_read_mem_retst,
> - .pwrdm_wait_transition = omap2_pwrdm_wait_transition,
> -};
> -
> -struct pwrdm_ops omap3_pwrdm_operations = {
> - .pwrdm_set_next_pwrst = omap2_pwrdm_set_next_pwrst,
> - .pwrdm_read_next_pwrst = omap2_pwrdm_read_next_pwrst,
> - .pwrdm_read_pwrst = omap2_pwrdm_read_pwrst,
> - .pwrdm_read_prev_pwrst = omap3_pwrdm_read_prev_pwrst,
> - .pwrdm_set_logic_retst = omap2_pwrdm_set_logic_retst,
> - .pwrdm_read_logic_pwrst = omap3_pwrdm_read_logic_pwrst,
> - .pwrdm_read_logic_retst = omap3_pwrdm_read_logic_retst,
> - .pwrdm_read_prev_logic_pwrst = omap3_pwrdm_read_prev_logic_pwrst,
> - .pwrdm_set_mem_onst = omap2_pwrdm_set_mem_onst,
> - .pwrdm_set_mem_retst = omap2_pwrdm_set_mem_retst,
> - .pwrdm_read_mem_pwrst = omap2_pwrdm_read_mem_pwrst,
> - .pwrdm_read_mem_retst = omap2_pwrdm_read_mem_retst,
> - .pwrdm_read_prev_mem_pwrst = omap3_pwrdm_read_prev_mem_pwrst,
> - .pwrdm_clear_all_prev_pwrst = omap3_pwrdm_clear_all_prev_pwrst,
> - .pwrdm_enable_hdwr_sar = omap3_pwrdm_enable_hdwr_sar,
> - .pwrdm_disable_hdwr_sar = omap3_pwrdm_disable_hdwr_sar,
> - .pwrdm_wait_transition = omap2_pwrdm_wait_transition,
> -};
> diff --git a/arch/arm/mach-omap2/powerdomain33xx.c b/arch/arm/mach-omap2/powerdomain33xx.c
> deleted file mode 100644
> index 67c5663..0000000
> --- a/arch/arm/mach-omap2/powerdomain33xx.c
> +++ /dev/null
> @@ -1,229 +0,0 @@
> -/*
> - * AM33XX Powerdomain control
> - *
> - * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
> - *
> - * Derived from mach-omap2/powerdomain44xx.c written by Rajendra Nayak
> - * <rnayak@ti.com>
> - *
> - * This program is free software; you can redistribute it and/or
> - * modify it under the terms of the GNU General Public License as
> - * published by the Free Software Foundation version 2.
> - *
> - * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> - * kind, whether express or implied; without even the implied warranty
> - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> - * GNU General Public License for more details.
> - */
> -
> -#include <linux/io.h>
> -#include <linux/errno.h>
> -#include <linux/delay.h>
> -
> -#include <plat/prcm.h>
> -
> -#include "powerdomain.h"
> -#include "prm33xx.h"
> -#include "prm-regbits-33xx.h"
> -
> -
> -static int am33xx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
> -{
> - am33xx_prm_rmw_reg_bits(OMAP_POWERSTATE_MASK,
> - (pwrst << OMAP_POWERSTATE_SHIFT),
> - pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
> - return 0;
> -}
> -
> -static int am33xx_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
> -{
> - u32 v;
> -
> - v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
> - v &= OMAP_POWERSTATE_MASK;
> - v >>= OMAP_POWERSTATE_SHIFT;
> -
> - return v;
> -}
> -
> -static int am33xx_pwrdm_read_pwrst(struct powerdomain *pwrdm)
> -{
> - u32 v;
> -
> - v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
> - v &= OMAP_POWERSTATEST_MASK;
> - v >>= OMAP_POWERSTATEST_SHIFT;
> -
> - return v;
> -}
> -
> -static int am33xx_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
> -{
> - u32 v;
> -
> - v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
> - v &= AM33XX_LASTPOWERSTATEENTERED_MASK;
> - v >>= AM33XX_LASTPOWERSTATEENTERED_SHIFT;
> -
> - return v;
> -}
> -
> -static int am33xx_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
> -{
> - am33xx_prm_rmw_reg_bits(AM33XX_LOWPOWERSTATECHANGE_MASK,
> - (1 << AM33XX_LOWPOWERSTATECHANGE_SHIFT),
> - pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
> - return 0;
> -}
> -
> -static int am33xx_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
> -{
> - am33xx_prm_rmw_reg_bits(AM33XX_LASTPOWERSTATEENTERED_MASK,
> - AM33XX_LASTPOWERSTATEENTERED_MASK,
> - pwrdm->prcm_offs, pwrdm->pwrstst_offs);
> - return 0;
> -}
> -
> -static int am33xx_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
> -{
> - u32 m;
> -
> - m = pwrdm->logicretstate_mask;
> - if (!m)
> - return -EINVAL;
> -
> - am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
> - pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
> -
> - return 0;
> -}
> -
> -static int am33xx_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
> -{
> - u32 v;
> -
> - v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
> - v &= AM33XX_LOGICSTATEST_MASK;
> - v >>= AM33XX_LOGICSTATEST_SHIFT;
> -
> - return v;
> -}
> -
> -static int am33xx_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
> -{
> - u32 v, m;
> -
> - m = pwrdm->logicretstate_mask;
> - if (!m)
> - return -EINVAL;
> -
> - v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
> - v &= m;
> - v >>= __ffs(m);
> -
> - return v;
> -}
> -
> -static int am33xx_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
> - u8 pwrst)
> -{
> - u32 m;
> -
> - m = pwrdm->mem_on_mask[bank];
> - if (!m)
> - return -EINVAL;
> -
> - am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
> - pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
> -
> - return 0;
> -}
> -
> -static int am33xx_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
> - u8 pwrst)
> -{
> - u32 m;
> -
> - m = pwrdm->mem_ret_mask[bank];
> - if (!m)
> - return -EINVAL;
> -
> - am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
> - pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
> -
> - return 0;
> -}
> -
> -static int am33xx_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
> -{
> - u32 m, v;
> -
> - m = pwrdm->mem_pwrst_mask[bank];
> - if (!m)
> - return -EINVAL;
> -
> - v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
> - v &= m;
> - v >>= __ffs(m);
> -
> - return v;
> -}
> -
> -static int am33xx_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
> -{
> - u32 m, v;
> -
> - m = pwrdm->mem_retst_mask[bank];
> - if (!m)
> - return -EINVAL;
> -
> - v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
> - v &= m;
> - v >>= __ffs(m);
> -
> - return v;
> -}
> -
> -static int am33xx_pwrdm_wait_transition(struct powerdomain *pwrdm)
> -{
> - u32 c = 0;
> -
> - /*
> - * REVISIT: pwrdm_wait_transition() may be better implemented
> - * via a callback and a periodic timer check -- how long do we expect
> - * powerdomain transitions to take?
> - */
> -
> - /* XXX Is this udelay() value meaningful? */
> - while ((am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs)
> - & OMAP_INTRANSITION_MASK) &&
> - (c++ < PWRDM_TRANSITION_BAILOUT))
> - udelay(1);
> -
> - if (c > PWRDM_TRANSITION_BAILOUT) {
> - pr_err("powerdomain: %s: waited too long to complete transition\n",
> - pwrdm->name);
> - return -EAGAIN;
> - }
> -
> - pr_debug("powerdomain: completed transition in %d loops\n", c);
> -
> - return 0;
> -}
> -
> -struct pwrdm_ops am33xx_pwrdm_operations = {
> - .pwrdm_set_next_pwrst = am33xx_pwrdm_set_next_pwrst,
> - .pwrdm_read_next_pwrst = am33xx_pwrdm_read_next_pwrst,
> - .pwrdm_read_pwrst = am33xx_pwrdm_read_pwrst,
> - .pwrdm_read_prev_pwrst = am33xx_pwrdm_read_prev_pwrst,
> - .pwrdm_set_logic_retst = am33xx_pwrdm_set_logic_retst,
> - .pwrdm_read_logic_pwrst = am33xx_pwrdm_read_logic_pwrst,
> - .pwrdm_read_logic_retst = am33xx_pwrdm_read_logic_retst,
> - .pwrdm_clear_all_prev_pwrst = am33xx_pwrdm_clear_all_prev_pwrst,
> - .pwrdm_set_lowpwrstchange = am33xx_pwrdm_set_lowpwrstchange,
> - .pwrdm_read_mem_pwrst = am33xx_pwrdm_read_mem_pwrst,
> - .pwrdm_read_mem_retst = am33xx_pwrdm_read_mem_retst,
> - .pwrdm_set_mem_onst = am33xx_pwrdm_set_mem_onst,
> - .pwrdm_set_mem_retst = am33xx_pwrdm_set_mem_retst,
> - .pwrdm_wait_transition = am33xx_pwrdm_wait_transition,
> -};
> diff --git a/arch/arm/mach-omap2/powerdomain44xx.c b/arch/arm/mach-omap2/powerdomain44xx.c
> deleted file mode 100644
> index aceb4f4..0000000
> --- a/arch/arm/mach-omap2/powerdomain44xx.c
> +++ /dev/null
> @@ -1,285 +0,0 @@
> -/*
> - * OMAP4 powerdomain control
> - *
> - * Copyright (C) 2009-2010, 2012 Texas Instruments, Inc.
> - * Copyright (C) 2007-2009 Nokia Corporation
> - *
> - * Derived from mach-omap2/powerdomain.c written by Paul Walmsley
> - * Rajendra Nayak <rnayak@ti.com>
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License version 2 as
> - * published by the Free Software Foundation.
> - */
> -
> -#include <linux/io.h>
> -#include <linux/errno.h>
> -#include <linux/delay.h>
> -#include <linux/bug.h>
> -
> -#include "powerdomain.h"
> -#include <plat/prcm.h>
> -#include "prm2xxx_3xxx.h"
> -#include "prm44xx.h"
> -#include "prminst44xx.h"
> -#include "prm-regbits-44xx.h"
> -
> -static int omap4_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
> -{
> - omap4_prminst_rmw_inst_reg_bits(OMAP_POWERSTATE_MASK,
> - (pwrst << OMAP_POWERSTATE_SHIFT),
> - pwrdm->prcm_partition,
> - pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL);
> - return 0;
> -}
> -
> -static int omap4_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
> -{
> - u32 v;
> -
> - v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
> - OMAP4_PM_PWSTCTRL);
> - v &= OMAP_POWERSTATE_MASK;
> - v >>= OMAP_POWERSTATE_SHIFT;
> -
> - return v;
> -}
> -
> -static int omap4_pwrdm_read_pwrst(struct powerdomain *pwrdm)
> -{
> - u32 v;
> -
> - v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
> - OMAP4_PM_PWSTST);
> - v &= OMAP_POWERSTATEST_MASK;
> - v >>= OMAP_POWERSTATEST_SHIFT;
> -
> - return v;
> -}
> -
> -static int omap4_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
> -{
> - u32 v;
> -
> - v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
> - OMAP4_PM_PWSTST);
> - v &= OMAP4430_LASTPOWERSTATEENTERED_MASK;
> - v >>= OMAP4430_LASTPOWERSTATEENTERED_SHIFT;
> -
> - return v;
> -}
> -
> -static int omap4_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
> -{
> - omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOWPOWERSTATECHANGE_MASK,
> - (1 << OMAP4430_LOWPOWERSTATECHANGE_SHIFT),
> - pwrdm->prcm_partition,
> - pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL);
> - return 0;
> -}
> -
> -static int omap4_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
> -{
> - omap4_prminst_rmw_inst_reg_bits(OMAP4430_LASTPOWERSTATEENTERED_MASK,
> - OMAP4430_LASTPOWERSTATEENTERED_MASK,
> - pwrdm->prcm_partition,
> - pwrdm->prcm_offs, OMAP4_PM_PWSTST);
> - return 0;
> -}
> -
> -static int omap4_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
> -{
> - u32 v;
> -
> - v = pwrst << __ffs(OMAP4430_LOGICRETSTATE_MASK);
> - omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOGICRETSTATE_MASK, v,
> - pwrdm->prcm_partition, pwrdm->prcm_offs,
> - OMAP4_PM_PWSTCTRL);
> -
> - return 0;
> -}
> -
> -static int omap4_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
> - u8 pwrst)
> -{
> - u32 m;
> -
> - m = omap2_pwrdm_get_mem_bank_onstate_mask(bank);
> -
> - omap4_prminst_rmw_inst_reg_bits(m, (pwrst << __ffs(m)),
> - pwrdm->prcm_partition, pwrdm->prcm_offs,
> - OMAP4_PM_PWSTCTRL);
> -
> - return 0;
> -}
> -
> -static int omap4_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
> - u8 pwrst)
> -{
> - u32 m;
> -
> - m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
> -
> - omap4_prminst_rmw_inst_reg_bits(m, (pwrst << __ffs(m)),
> - pwrdm->prcm_partition, pwrdm->prcm_offs,
> - OMAP4_PM_PWSTCTRL);
> -
> - return 0;
> -}
> -
> -static int omap4_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
> -{
> - u32 v;
> -
> - v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
> - OMAP4_PM_PWSTST);
> - v &= OMAP4430_LOGICSTATEST_MASK;
> - v >>= OMAP4430_LOGICSTATEST_SHIFT;
> -
> - return v;
> -}
> -
> -static int omap4_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
> -{
> - u32 v;
> -
> - v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
> - OMAP4_PM_PWSTCTRL);
> - v &= OMAP4430_LOGICRETSTATE_MASK;
> - v >>= OMAP4430_LOGICRETSTATE_SHIFT;
> -
> - return v;
> -}
> -
> -/**
> - * omap4_pwrdm_read_prev_logic_pwrst - read the previous logic powerstate
> - * @pwrdm: struct powerdomain * to read the state for
> - *
> - * Reads the previous logic powerstate for a powerdomain. This
> - * function must determine the previous logic powerstate by first
> - * checking the previous powerstate for the domain. If that was OFF,
> - * then logic has been lost. If previous state was RETENTION, the
> - * function reads the setting for the next retention logic state to
> - * see the actual value. In every other case, the logic is
> - * retained. Returns either PWRDM_POWER_OFF or PWRDM_POWER_RET
> - * depending whether the logic was retained or not.
> - */
> -static int omap4_pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm)
> -{
> - int state;
> -
> - state = omap4_pwrdm_read_prev_pwrst(pwrdm);
> -
> - if (state == PWRDM_POWER_OFF)
> - return PWRDM_POWER_OFF;
> -
> - if (state != PWRDM_POWER_RET)
> - return PWRDM_POWER_RET;
> -
> - return omap4_pwrdm_read_logic_retst(pwrdm);
> -}
> -
> -static int omap4_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
> -{
> - u32 m, v;
> -
> - m = omap2_pwrdm_get_mem_bank_stst_mask(bank);
> -
> - v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
> - OMAP4_PM_PWSTST);
> - v &= m;
> - v >>= __ffs(m);
> -
> - return v;
> -}
> -
> -static int omap4_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
> -{
> - u32 m, v;
> -
> - m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
> -
> - v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
> - OMAP4_PM_PWSTCTRL);
> - v &= m;
> - v >>= __ffs(m);
> -
> - return v;
> -}
> -
> -/**
> - * omap4_pwrdm_read_prev_mem_pwrst - reads the previous memory powerstate
> - * @pwrdm: struct powerdomain * to read mem powerstate for
> - * @bank: memory bank index
> - *
> - * Reads the previous memory powerstate for a powerdomain. This
> - * function must determine the previous memory powerstate by first
> - * checking the previous powerstate for the domain. If that was OFF,
> - * then logic has been lost. If previous state was RETENTION, the
> - * function reads the setting for the next memory retention state to
> - * see the actual value. In every other case, the logic is
> - * retained. Returns either PWRDM_POWER_OFF or PWRDM_POWER_RET
> - * depending whether logic was retained or not.
> - */
> -static int omap4_pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
> -{
> - int state;
> -
> - state = omap4_pwrdm_read_prev_pwrst(pwrdm);
> -
> - if (state == PWRDM_POWER_OFF)
> - return PWRDM_POWER_OFF;
> -
> - if (state != PWRDM_POWER_RET)
> - return PWRDM_POWER_RET;
> -
> - return omap4_pwrdm_read_mem_retst(pwrdm, bank);
> -}
> -
> -static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm)
> -{
> - u32 c = 0;
> -
> - /*
> - * REVISIT: pwrdm_wait_transition() may be better implemented
> - * via a callback and a periodic timer check -- how long do we expect
> - * powerdomain transitions to take?
> - */
> -
> - /* XXX Is this udelay() value meaningful? */
> - while ((omap4_prminst_read_inst_reg(pwrdm->prcm_partition,
> - pwrdm->prcm_offs,
> - OMAP4_PM_PWSTST) &
> - OMAP_INTRANSITION_MASK) &&
> - (c++ < PWRDM_TRANSITION_BAILOUT))
> - udelay(1);
> -
> - if (c > PWRDM_TRANSITION_BAILOUT) {
> - pr_err("powerdomain: %s: waited too long to complete transition\n",
> - pwrdm->name);
> - return -EAGAIN;
> - }
> -
> - pr_debug("powerdomain: completed transition in %d loops\n", c);
> -
> - return 0;
> -}
> -
> -struct pwrdm_ops omap4_pwrdm_operations = {
> - .pwrdm_set_next_pwrst = omap4_pwrdm_set_next_pwrst,
> - .pwrdm_read_next_pwrst = omap4_pwrdm_read_next_pwrst,
> - .pwrdm_read_pwrst = omap4_pwrdm_read_pwrst,
> - .pwrdm_read_prev_pwrst = omap4_pwrdm_read_prev_pwrst,
> - .pwrdm_set_lowpwrstchange = omap4_pwrdm_set_lowpwrstchange,
> - .pwrdm_clear_all_prev_pwrst = omap4_pwrdm_clear_all_prev_pwrst,
> - .pwrdm_set_logic_retst = omap4_pwrdm_set_logic_retst,
> - .pwrdm_read_logic_pwrst = omap4_pwrdm_read_logic_pwrst,
> - .pwrdm_read_prev_logic_pwrst = omap4_pwrdm_read_prev_logic_pwrst,
> - .pwrdm_read_logic_retst = omap4_pwrdm_read_logic_retst,
> - .pwrdm_read_mem_pwrst = omap4_pwrdm_read_mem_pwrst,
> - .pwrdm_read_mem_retst = omap4_pwrdm_read_mem_retst,
> - .pwrdm_read_prev_mem_pwrst = omap4_pwrdm_read_prev_mem_pwrst,
> - .pwrdm_set_mem_onst = omap4_pwrdm_set_mem_onst,
> - .pwrdm_set_mem_retst = omap4_pwrdm_set_mem_retst,
> - .pwrdm_wait_transition = omap4_pwrdm_wait_transition,
> -};
> diff --git a/arch/arm/mach-omap2/prm2xxx.c b/arch/arm/mach-omap2/prm2xxx.c
> new file mode 100644
> index 0000000..14940c4
> --- /dev/null
> +++ b/arch/arm/mach-omap2/prm2xxx.c
> @@ -0,0 +1,40 @@
> +/*
> + * OMAP2xxx PRM module functions
> + *
> + * Copyright (C) 2010-2012 Texas Instruments, Inc.
> + * Copyright (C) 2010 Nokia Corporation
> + * Beno?t Cousson
> + * Paul Walmsley
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/errno.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/irq.h>
> +
> +#include "common.h"
> +#include <plat/cpu.h>
> +#include <plat/prcm.h>
> +
> +#include "vp.h"
> +#include "powerdomain.h"
> +#include "prm2xxx.h"
> +#include "cm2xxx_3xxx.h"
> +#include "prm-regbits-24xx.h"
> +
> +struct pwrdm_ops omap2_pwrdm_operations = {
> + .pwrdm_set_next_pwrst = omap2_pwrdm_set_next_pwrst,
> + .pwrdm_read_next_pwrst = omap2_pwrdm_read_next_pwrst,
> + .pwrdm_read_pwrst = omap2_pwrdm_read_pwrst,
> + .pwrdm_set_logic_retst = omap2_pwrdm_set_logic_retst,
> + .pwrdm_set_mem_onst = omap2_pwrdm_set_mem_onst,
> + .pwrdm_set_mem_retst = omap2_pwrdm_set_mem_retst,
> + .pwrdm_read_mem_pwrst = omap2_pwrdm_read_mem_pwrst,
> + .pwrdm_read_mem_retst = omap2_pwrdm_read_mem_retst,
> + .pwrdm_wait_transition = omap2_pwrdm_wait_transition,
> +};
> diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
> index 0d6cc54..bdddf5c 100644
> --- a/arch/arm/mach-omap2/prm2xxx_3xxx.c
> +++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
> @@ -17,7 +17,7 @@
> #include <linux/io.h>
>
> #include "common.h"
> -
> +#include "powerdomain.h"
> #include "prm2xxx_3xxx.h"
> #include "prm-regbits-24xx.h"
>
> @@ -98,3 +98,113 @@ int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift)
> return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
> }
>
> +
> +/* Powerdomain low-level functions */
> +
> +/* Common functions across OMAP2 and OMAP3 */
> +int omap2_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
> +{
> + omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK,
> + (pwrst << OMAP_POWERSTATE_SHIFT),
> + pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
> + return 0;
> +}
> +
> +int omap2_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
> +{
> + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
> + OMAP2_PM_PWSTCTRL,
> + OMAP_POWERSTATE_MASK);
> +}
> +
> +int omap2_pwrdm_read_pwrst(struct powerdomain *pwrdm)
> +{
> + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
> + OMAP2_PM_PWSTST,
> + OMAP_POWERSTATEST_MASK);
> +}
> +
> +int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
> + u8 pwrst)
> +{
> + u32 m;
> +
> + m = omap2_pwrdm_get_mem_bank_onstate_mask(bank);
> +
> + omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs,
> + OMAP2_PM_PWSTCTRL);
> +
> + return 0;
> +}
> +
> +int omap2_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
> + u8 pwrst)
> +{
> + u32 m;
> +
> + m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
> +
> + omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs,
> + OMAP2_PM_PWSTCTRL);
> +
> + return 0;
> +}
> +
> +int omap2_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
> +{
> + u32 m;
> +
> + m = omap2_pwrdm_get_mem_bank_stst_mask(bank);
> +
> + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTST,
> + m);
> +}
> +
> +int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
> +{
> + u32 m;
> +
> + m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
> +
> + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
> + OMAP2_PM_PWSTCTRL, m);
> +}
> +
> +int omap2_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
> +{
> + u32 v;
> +
> + v = pwrst << __ffs(OMAP_LOGICRETSTATE_MASK);
> + omap2_prm_rmw_mod_reg_bits(OMAP_LOGICRETSTATE_MASK, v, pwrdm->prcm_offs,
> + OMAP2_PM_PWSTCTRL);
> +
> + return 0;
> +}
> +
> +int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm)
> +{
> + u32 c = 0;
> +
> + /*
> + * REVISIT: pwrdm_wait_transition() may be better implemented
> + * via a callback and a periodic timer check -- how long do we expect
> + * powerdomain transitions to take?
> + */
> +
> + /* XXX Is this udelay() value meaningful? */
> + while ((omap2_prm_read_mod_reg(pwrdm->prcm_offs, OMAP2_PM_PWSTST) &
> + OMAP_INTRANSITION_MASK) &&
> + (c++ < PWRDM_TRANSITION_BAILOUT))
> + udelay(1);
> +
> + if (c > PWRDM_TRANSITION_BAILOUT) {
> + pr_err("powerdomain: %s: waited too long to complete transition\n",
> + pwrdm->name);
> + return -EAGAIN;
> + }
> +
> + pr_debug("powerdomain: completed transition in %d loops\n", c);
> +
> + return 0;
> +}
> +
> diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h
> index 8d09a1a..706b026 100644
> --- a/arch/arm/mach-omap2/prm2xxx_3xxx.h
> +++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h
> @@ -50,6 +50,7 @@
> #ifndef __ASSEMBLER__
>
> #include <linux/io.h>
> +#include "powerdomain.h"
>
> /* Power/reset management domain register get/set */
> static inline u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
> @@ -103,6 +104,18 @@ extern int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift);
> extern int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift);
> extern int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift);
>
> +extern int omap2_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
> +extern int omap2_pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
> +extern int omap2_pwrdm_read_pwrst(struct powerdomain *pwrdm);
> +extern int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
> + u8 pwrst);
> +extern int omap2_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
> + u8 pwrst);
> +extern int omap2_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
> +extern int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank);
> +extern int omap2_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst);
> +extern int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm);
> +
> #endif /* __ASSEMBLER */
>
> /*
> diff --git a/arch/arm/mach-omap2/prm33xx.c b/arch/arm/mach-omap2/prm33xx.c
> index e7dbb6c..3417dd3 100644
> --- a/arch/arm/mach-omap2/prm33xx.c
> +++ b/arch/arm/mach-omap2/prm33xx.c
> @@ -22,6 +22,7 @@
> #include <plat/common.h>
>
> #include "common.h"
> +#include "powerdomain.h"
> #include "prm33xx.h"
> #include "prm-regbits-33xx.h"
>
> @@ -133,3 +134,204 @@ int am33xx_prm_deassert_hardreset(u8 shift, s16 inst,
>
> return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
> }
> +
> +static int am33xx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
> +{
> + am33xx_prm_rmw_reg_bits(OMAP_POWERSTATE_MASK,
> + (pwrst << OMAP_POWERSTATE_SHIFT),
> + pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
> + return 0;
> +}
> +
> +static int am33xx_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
> +{
> + u32 v;
> +
> + v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
> + v &= OMAP_POWERSTATE_MASK;
> + v >>= OMAP_POWERSTATE_SHIFT;
> +
> + return v;
> +}
> +
> +static int am33xx_pwrdm_read_pwrst(struct powerdomain *pwrdm)
> +{
> + u32 v;
> +
> + v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
> + v &= OMAP_POWERSTATEST_MASK;
> + v >>= OMAP_POWERSTATEST_SHIFT;
> +
> + return v;
> +}
> +
> +static int am33xx_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
> +{
> + u32 v;
> +
> + v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
> + v &= AM33XX_LASTPOWERSTATEENTERED_MASK;
> + v >>= AM33XX_LASTPOWERSTATEENTERED_SHIFT;
> +
> + return v;
> +}
> +
> +static int am33xx_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
> +{
> + am33xx_prm_rmw_reg_bits(AM33XX_LOWPOWERSTATECHANGE_MASK,
> + (1 << AM33XX_LOWPOWERSTATECHANGE_SHIFT),
> + pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
> + return 0;
> +}
> +
> +static int am33xx_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
> +{
> + am33xx_prm_rmw_reg_bits(AM33XX_LASTPOWERSTATEENTERED_MASK,
> + AM33XX_LASTPOWERSTATEENTERED_MASK,
> + pwrdm->prcm_offs, pwrdm->pwrstst_offs);
> + return 0;
> +}
> +
> +static int am33xx_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
> +{
> + u32 m;
> +
> + m = pwrdm->logicretstate_mask;
> + if (!m)
> + return -EINVAL;
> +
> + am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
> + pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
> +
> + return 0;
> +}
> +
> +static int am33xx_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
> +{
> + u32 v;
> +
> + v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
> + v &= AM33XX_LOGICSTATEST_MASK;
> + v >>= AM33XX_LOGICSTATEST_SHIFT;
> +
> + return v;
> +}
> +
> +static int am33xx_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
> +{
> + u32 v, m;
> +
> + m = pwrdm->logicretstate_mask;
> + if (!m)
> + return -EINVAL;
> +
> + v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
> + v &= m;
> + v >>= __ffs(m);
> +
> + return v;
> +}
> +
> +static int am33xx_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
> + u8 pwrst)
> +{
> + u32 m;
> +
> + m = pwrdm->mem_on_mask[bank];
> + if (!m)
> + return -EINVAL;
> +
> + am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
> + pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
> +
> + return 0;
> +}
> +
> +static int am33xx_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
> + u8 pwrst)
> +{
> + u32 m;
> +
> + m = pwrdm->mem_ret_mask[bank];
> + if (!m)
> + return -EINVAL;
> +
> + am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
> + pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
> +
> + return 0;
> +}
> +
> +static int am33xx_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
> +{
> + u32 m, v;
> +
> + m = pwrdm->mem_pwrst_mask[bank];
> + if (!m)
> + return -EINVAL;
> +
> + v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
> + v &= m;
> + v >>= __ffs(m);
> +
> + return v;
> +}
> +
> +static int am33xx_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
> +{
> + u32 m, v;
> +
> + m = pwrdm->mem_retst_mask[bank];
> + if (!m)
> + return -EINVAL;
> +
> + v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
> + v &= m;
> + v >>= __ffs(m);
> +
> + return v;
> +}
> +
> +static int am33xx_pwrdm_wait_transition(struct powerdomain *pwrdm)
> +{
> + u32 c = 0;
> +
> + /*
> + * REVISIT: pwrdm_wait_transition() may be better implemented
> + * via a callback and a periodic timer check -- how long do we expect
> + * powerdomain transitions to take?
> + */
> +
> + /* XXX Is this udelay() value meaningful? */
> + while ((am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs)
> + & OMAP_INTRANSITION_MASK) &&
> + (c++ < PWRDM_TRANSITION_BAILOUT))
> + udelay(1);
> +
> + if (c > PWRDM_TRANSITION_BAILOUT) {
> + pr_err("powerdomain: %s: waited too long to complete transition\n",
> + pwrdm->name);
> + return -EAGAIN;
> + }
> +
> + pr_debug("powerdomain: completed transition in %d loops\n", c);
> +
> + return 0;
> +}
> +
> +struct pwrdm_ops am33xx_pwrdm_operations = {
> + .pwrdm_set_next_pwrst = am33xx_pwrdm_set_next_pwrst,
> + .pwrdm_read_next_pwrst = am33xx_pwrdm_read_next_pwrst,
> + .pwrdm_read_pwrst = am33xx_pwrdm_read_pwrst,
> + .pwrdm_read_prev_pwrst = am33xx_pwrdm_read_prev_pwrst,
> + .pwrdm_set_logic_retst = am33xx_pwrdm_set_logic_retst,
> + .pwrdm_read_logic_pwrst = am33xx_pwrdm_read_logic_pwrst,
> + .pwrdm_read_logic_retst = am33xx_pwrdm_read_logic_retst,
> + .pwrdm_clear_all_prev_pwrst = am33xx_pwrdm_clear_all_prev_pwrst,
> + .pwrdm_set_lowpwrstchange = am33xx_pwrdm_set_lowpwrstchange,
> + .pwrdm_read_mem_pwrst = am33xx_pwrdm_read_mem_pwrst,
> + .pwrdm_read_mem_retst = am33xx_pwrdm_read_mem_retst,
> + .pwrdm_set_mem_onst = am33xx_pwrdm_set_mem_onst,
> + .pwrdm_set_mem_retst = am33xx_pwrdm_set_mem_retst,
> + .pwrdm_wait_transition = am33xx_pwrdm_wait_transition,
> +};
> diff --git a/arch/arm/mach-omap2/prm3xxx.c b/arch/arm/mach-omap2/prm3xxx.c
> index 88f7d8d..b2c5fd9 100644
> --- a/arch/arm/mach-omap2/prm3xxx.c
> +++ b/arch/arm/mach-omap2/prm3xxx.c
> @@ -22,8 +22,9 @@
> #include <plat/prcm.h>
>
> #include "vp.h"
> -
> +#include "powerdomain.h"
> #include "prm3xxx.h"
> +#include "prm2xxx_3xxx.h"
> #include "cm2xxx_3xxx.h"
> #include "prm-regbits-34xx.h"
>
> @@ -215,6 +216,109 @@ static void __init omap3xxx_prm_enable_io_wakeup(void)
> PM_WKEN);
> }
>
> +/* Powerdomain low-level functions */
> +
> +/* Applicable only for OMAP3. Not supported on OMAP2 */
> +static int omap3_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
> +{
> + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
> + OMAP3430_PM_PREPWSTST,
> + OMAP3430_LASTPOWERSTATEENTERED_MASK);
> +}
> +
> +static int omap3_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
> +{
> + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
> + OMAP2_PM_PWSTST,
> + OMAP3430_LOGICSTATEST_MASK);
> +}
> +
> +static int omap3_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
> +{
> + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
> + OMAP2_PM_PWSTCTRL,
> + OMAP3430_LOGICSTATEST_MASK);
> +}
> +
> +static int omap3_pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm)
> +{
> + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
> + OMAP3430_PM_PREPWSTST,
> + OMAP3430_LASTLOGICSTATEENTERED_MASK);
> +}
> +
> +static int omap3_get_mem_bank_lastmemst_mask(u8 bank)
> +{
> + switch (bank) {
> + case 0:
> + return OMAP3430_LASTMEM1STATEENTERED_MASK;
> + case 1:
> + return OMAP3430_LASTMEM2STATEENTERED_MASK;
> + case 2:
> + return OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK;
> + case 3:
> + return OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK;
> + default:
> + WARN_ON(1); /* should never happen */
> + return -EEXIST;
> + }
> + return 0;
> +}
> +
> +static int omap3_pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
> +{
> + u32 m;
> +
> + m = omap3_get_mem_bank_lastmemst_mask(bank);
> +
> + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
> + OMAP3430_PM_PREPWSTST, m);
> +}
> +
> +static int omap3_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
> +{
> + omap2_prm_write_mod_reg(0, pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST);
> + return 0;
> +}
> +
> +static int omap3_pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm)
> +{
> + return omap2_prm_rmw_mod_reg_bits(0,
> + 1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT,
> + pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
> +}
> +
> +static int omap3_pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm)
> +{
> + return omap2_prm_rmw_mod_reg_bits(1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT,
> + 0, pwrdm->prcm_offs,
> + OMAP2_PM_PWSTCTRL);
> +}
> +
> +struct pwrdm_ops omap3_pwrdm_operations = {
> + .pwrdm_set_next_pwrst = omap2_pwrdm_set_next_pwrst,
> + .pwrdm_read_next_pwrst = omap2_pwrdm_read_next_pwrst,
> + .pwrdm_read_pwrst = omap2_pwrdm_read_pwrst,
> + .pwrdm_read_prev_pwrst = omap3_pwrdm_read_prev_pwrst,
> + .pwrdm_set_logic_retst = omap2_pwrdm_set_logic_retst,
> + .pwrdm_read_logic_pwrst = omap3_pwrdm_read_logic_pwrst,
> + .pwrdm_read_logic_retst = omap3_pwrdm_read_logic_retst,
> + .pwrdm_read_prev_logic_pwrst = omap3_pwrdm_read_prev_logic_pwrst,
> + .pwrdm_set_mem_onst = omap2_pwrdm_set_mem_onst,
> + .pwrdm_set_mem_retst = omap2_pwrdm_set_mem_retst,
> + .pwrdm_read_mem_pwrst = omap2_pwrdm_read_mem_pwrst,
> + .pwrdm_read_mem_retst = omap2_pwrdm_read_mem_retst,
> + .pwrdm_read_prev_mem_pwrst = omap3_pwrdm_read_prev_mem_pwrst,
> + .pwrdm_clear_all_prev_pwrst = omap3_pwrdm_clear_all_prev_pwrst,
> + .pwrdm_enable_hdwr_sar = omap3_pwrdm_enable_hdwr_sar,
> + .pwrdm_disable_hdwr_sar = omap3_pwrdm_disable_hdwr_sar,
> + .pwrdm_wait_transition = omap2_pwrdm_wait_transition,
> +};
> +
> +/*
> + *
> + */
> +
> static int __init omap3xxx_prm_init(void)
> {
> int ret;
> diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
> index 06bb679..9231fe5 100644
> --- a/arch/arm/mach-omap2/prm44xx.c
> +++ b/arch/arm/mach-omap2/prm44xx.c
> @@ -27,6 +27,7 @@
> #include "prm-regbits-44xx.h"
> #include "prcm44xx.h"
> #include "prminst44xx.h"
> +#include "powerdomain.h"
>
> static const struct omap_prcm_irq omap4_prcm_irqs[] = {
> OMAP_PRCM_IRQ("wkup", 0, 0),
> @@ -291,6 +292,269 @@ static void __init omap44xx_prm_enable_io_wakeup(void)
> OMAP4_PRM_IO_PMCTRL_OFFSET);
> }
>
> +/* Powerdomain low-level functions */
> +
> +static int omap4_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
> +{
> + omap4_prminst_rmw_inst_reg_bits(OMAP_POWERSTATE_MASK,
> + (pwrst << OMAP_POWERSTATE_SHIFT),
> + pwrdm->prcm_partition,
> + pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL);
> + return 0;
> +}
> +
> +static int omap4_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
> +{
> + u32 v;
> +
> + v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
> + OMAP4_PM_PWSTCTRL);
> + v &= OMAP_POWERSTATE_MASK;
> + v >>= OMAP_POWERSTATE_SHIFT;
> +
> + return v;
> +}
> +
> +static int omap4_pwrdm_read_pwrst(struct powerdomain *pwrdm)
> +{
> + u32 v;
> +
> + v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
> + OMAP4_PM_PWSTST);
> + v &= OMAP_POWERSTATEST_MASK;
> + v >>= OMAP_POWERSTATEST_SHIFT;
> +
> + return v;
> +}
> +
> +static int omap4_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
> +{
> + u32 v;
> +
> + v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
> + OMAP4_PM_PWSTST);
> + v &= OMAP4430_LASTPOWERSTATEENTERED_MASK;
> + v >>= OMAP4430_LASTPOWERSTATEENTERED_SHIFT;
> +
> + return v;
> +}
> +
> +static int omap4_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
> +{
> + omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOWPOWERSTATECHANGE_MASK,
> + (1 << OMAP4430_LOWPOWERSTATECHANGE_SHIFT),
> + pwrdm->prcm_partition,
> + pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL);
> + return 0;
> +}
> +
> +static int omap4_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
> +{
> + omap4_prminst_rmw_inst_reg_bits(OMAP4430_LASTPOWERSTATEENTERED_MASK,
> + OMAP4430_LASTPOWERSTATEENTERED_MASK,
> + pwrdm->prcm_partition,
> + pwrdm->prcm_offs, OMAP4_PM_PWSTST);
> + return 0;
> +}
> +
> +static int omap4_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
> +{
> + u32 v;
> +
> + v = pwrst << __ffs(OMAP4430_LOGICRETSTATE_MASK);
> + omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOGICRETSTATE_MASK, v,
> + pwrdm->prcm_partition, pwrdm->prcm_offs,
> + OMAP4_PM_PWSTCTRL);
> +
> + return 0;
> +}
> +
> +static int omap4_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
> + u8 pwrst)
> +{
> + u32 m;
> +
> + m = omap2_pwrdm_get_mem_bank_onstate_mask(bank);
> +
> + omap4_prminst_rmw_inst_reg_bits(m, (pwrst << __ffs(m)),
> + pwrdm->prcm_partition, pwrdm->prcm_offs,
> + OMAP4_PM_PWSTCTRL);
> +
> + return 0;
> +}
> +
> +static int omap4_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
> + u8 pwrst)
> +{
> + u32 m;
> +
> + m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
> +
> + omap4_prminst_rmw_inst_reg_bits(m, (pwrst << __ffs(m)),
> + pwrdm->prcm_partition, pwrdm->prcm_offs,
> + OMAP4_PM_PWSTCTRL);
> +
> + return 0;
> +}
> +
> +static int omap4_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
> +{
> + u32 v;
> +
> + v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
> + OMAP4_PM_PWSTST);
> + v &= OMAP4430_LOGICSTATEST_MASK;
> + v >>= OMAP4430_LOGICSTATEST_SHIFT;
> +
> + return v;
> +}
> +
> +static int omap4_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
> +{
> + u32 v;
> +
> + v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
> + OMAP4_PM_PWSTCTRL);
> + v &= OMAP4430_LOGICRETSTATE_MASK;
> + v >>= OMAP4430_LOGICRETSTATE_SHIFT;
> +
> + return v;
> +}
> +
> +/**
> + * omap4_pwrdm_read_prev_logic_pwrst - read the previous logic powerstate
> + * @pwrdm: struct powerdomain * to read the state for
> + *
> + * Reads the previous logic powerstate for a powerdomain. This
> + * function must determine the previous logic powerstate by first
> + * checking the previous powerstate for the domain. If that was OFF,
> + * then logic has been lost. If previous state was RETENTION, the
> + * function reads the setting for the next retention logic state to
> + * see the actual value. In every other case, the logic is
> + * retained. Returns either PWRDM_POWER_OFF or PWRDM_POWER_RET
> + * depending whether the logic was retained or not.
> + */
> +static int omap4_pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm)
> +{
> + int state;
> +
> + state = omap4_pwrdm_read_prev_pwrst(pwrdm);
> +
> + if (state == PWRDM_POWER_OFF)
> + return PWRDM_POWER_OFF;
> +
> + if (state != PWRDM_POWER_RET)
> + return PWRDM_POWER_RET;
> +
> + return omap4_pwrdm_read_logic_retst(pwrdm);
> +}
> +
> +static int omap4_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
> +{
> + u32 m, v;
> +
> + m = omap2_pwrdm_get_mem_bank_stst_mask(bank);
> +
> + v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
> + OMAP4_PM_PWSTST);
> + v &= m;
> + v >>= __ffs(m);
> +
> + return v;
> +}
> +
> +static int omap4_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
> +{
> + u32 m, v;
> +
> + m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
> +
> + v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
> + OMAP4_PM_PWSTCTRL);
> + v &= m;
> + v >>= __ffs(m);
> +
> + return v;
> +}
> +
> +/**
> + * omap4_pwrdm_read_prev_mem_pwrst - reads the previous memory powerstate
> + * @pwrdm: struct powerdomain * to read mem powerstate for
> + * @bank: memory bank index
> + *
> + * Reads the previous memory powerstate for a powerdomain. This
> + * function must determine the previous memory powerstate by first
> + * checking the previous powerstate for the domain. If that was OFF,
> + * then logic has been lost. If previous state was RETENTION, the
> + * function reads the setting for the next memory retention state to
> + * see the actual value. In every other case, the logic is
> + * retained. Returns either PWRDM_POWER_OFF or PWRDM_POWER_RET
> + * depending whether logic was retained or not.
> + */
> +static int omap4_pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
> +{
> + int state;
> +
> + state = omap4_pwrdm_read_prev_pwrst(pwrdm);
> +
> + if (state == PWRDM_POWER_OFF)
> + return PWRDM_POWER_OFF;
> +
> + if (state != PWRDM_POWER_RET)
> + return PWRDM_POWER_RET;
> +
> + return omap4_pwrdm_read_mem_retst(pwrdm, bank);
> +}
> +
> +static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm)
> +{
> + u32 c = 0;
> +
> + /*
> + * REVISIT: pwrdm_wait_transition() may be better implemented
> + * via a callback and a periodic timer check -- how long do we expect
> + * powerdomain transitions to take?
> + */
> +
> + /* XXX Is this udelay() value meaningful? */
> + while ((omap4_prminst_read_inst_reg(pwrdm->prcm_partition,
> + pwrdm->prcm_offs,
> + OMAP4_PM_PWSTST) &
> + OMAP_INTRANSITION_MASK) &&
> + (c++ < PWRDM_TRANSITION_BAILOUT))
> + udelay(1);
> +
> + if (c > PWRDM_TRANSITION_BAILOUT) {
> + pr_err("powerdomain: %s: waited too long to complete transition\n",
> + pwrdm->name);
> + return -EAGAIN;
> + }
> +
> + pr_debug("powerdomain: completed transition in %d loops\n", c);
> +
> + return 0;
> +}
> +
> +struct pwrdm_ops omap4_pwrdm_operations = {
> + .pwrdm_set_next_pwrst = omap4_pwrdm_set_next_pwrst,
> + .pwrdm_read_next_pwrst = omap4_pwrdm_read_next_pwrst,
> + .pwrdm_read_pwrst = omap4_pwrdm_read_pwrst,
> + .pwrdm_read_prev_pwrst = omap4_pwrdm_read_prev_pwrst,
> + .pwrdm_set_lowpwrstchange = omap4_pwrdm_set_lowpwrstchange,
> + .pwrdm_clear_all_prev_pwrst = omap4_pwrdm_clear_all_prev_pwrst,
> + .pwrdm_set_logic_retst = omap4_pwrdm_set_logic_retst,
> + .pwrdm_read_logic_pwrst = omap4_pwrdm_read_logic_pwrst,
> + .pwrdm_read_prev_logic_pwrst = omap4_pwrdm_read_prev_logic_pwrst,
> + .pwrdm_read_logic_retst = omap4_pwrdm_read_logic_retst,
> + .pwrdm_read_mem_pwrst = omap4_pwrdm_read_mem_pwrst,
> + .pwrdm_read_mem_retst = omap4_pwrdm_read_mem_retst,
> + .pwrdm_read_prev_mem_pwrst = omap4_pwrdm_read_prev_mem_pwrst,
> + .pwrdm_set_mem_onst = omap4_pwrdm_set_mem_onst,
> + .pwrdm_set_mem_retst = omap4_pwrdm_set_mem_retst,
> + .pwrdm_wait_transition = omap4_pwrdm_wait_transition,
> +};
> +
> +
> static int __init omap4xxx_prm_init(void)
> {
> if (!cpu_is_omap44xx())
>
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* [PATCH 5/5] ARM: tegra: config: enable spi driver for Tegra SLINK controller
From: Laxman Dewangan @ 2012-10-18 10:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350557795-31487-1-git-send-email-ldewangan@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
---
arch/arm/configs/tegra_defconfig | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index fb29680..60e1b2e 100644
--- a/arch/arm/configs/tegra_defconfig
+++ b/arch/arm/configs/tegra_defconfig
@@ -117,7 +117,7 @@ CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PINCTRL=y
CONFIG_I2C_TEGRA=y
CONFIG_SPI=y
-CONFIG_SPI_TEGRA=y
+CONFIG_SPI_TEGRA20_SLINK=y
CONFIG_GPIO_PCA953X_IRQ=y
CONFIG_GPIO_TPS6586X=y
CONFIG_GPIO_TPS65910=y
--
1.7.1.1
^ permalink raw reply related
* [PATCH 4/5] ARM: tegra: dts: cardhu: enable SLINK4
From: Laxman Dewangan @ 2012-10-18 10:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350557795-31487-1-git-send-email-ldewangan@nvidia.com>
Enable SLINK4 in Tegra30 based platform Cardhu.
Setting maximum spi frequency to 25MHz.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
---
arch/arm/boot/dts/tegra30-cardhu.dtsi | 5 +++++
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index b245e6c..1bd73ea 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -275,6 +275,11 @@
};
};
+ slink at 7000da00 {
+ status = "okay";
+ spi-max-frequency = <25000000>;
+ };
+
ahub {
i2s at 70080400 {
status = "okay";
--
1.7.1.1
^ permalink raw reply related
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