* 3.7-rc-1 Release Causing application failure for compilation
From: Baruch Siach @ 2012-10-18 18:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CA+V-a8uj4wSz60Ov8S3MpSrUe-D5+OcpVsFjURzSEcE6VdvGGQ@mail.gmail.com>
Hello Prabhakar Lad,
On Thu, Oct 18, 2012 at 09:49:34PM +0530, Prabhakar Lad wrote:
> I have updated to 3.7-rc1 kernel version with latest head with
> commit-id 43c422eda99b894f18d1cca17bcd2401efaf7bd0
> but when I try to cross compile the Application I am getting following errors.
>
> /home/plad/ti/linus/linus/include/linux/types.h:14:26: error:
> conflicting types for 'fd_set'
> /home/plad/CodeSourcery/Sourcery_G++_Lite/bin/../arm-none-linux-gnueabi/libc/usr/include/sys/select.h:78:5:
> note: previous declaration of 'fd_set' was here
> /home/plad/ti/linus/linus/include/linux/types.h:15:25: error:
[snip]
> I use the codesourcery toolchain for cross compiling the applications
> for ARM. The same compiler is used to build the uImage for ARM, but
> when I try building the apps I see this issue. Can any help me out in
> fixing this.
It seems that you are including kernel headers directly in your userspace
code. Don't do that. Types defined in kernel headers conflict with types
defined in your toolchain's kernel headers. Instead, just use the headers that
are part of your toolchain, which in turn include kernel headers that your
toolchain was built with.
baruch
--
http://baruch.siach.name/blog/ ~. .~ Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
- baruch at tkos.co.il - tel: +972.2.679.5364, http://www.tkos.co.il -
^ permalink raw reply
* [PATCH 1/5] ARM: OMAP2+: gpmc: Fix kernel BUG for DT boot mode
From: Hiremath, Vaibhav @ 2012-10-18 18:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50804AC7.3000309@ti.com>
On Fri, Oct 19, 2012 at 00:00:31, Hunter, Jon wrote:
>
> On 10/18/2012 01:04 PM, Hiremath, Vaibhav wrote:
> > On Thu, Oct 18, 2012 at 22:12:07, Hunter, Jon wrote:
>
> ...
>
> >> Yes, but do you also see the bug that is hiding in gpmc_mem_init()?
> >>
> >> My point is to highlight this and not hide it, so that we can fix it
> >> now. Otherwise if we wait until we enable the gpmc driver with DT and
> >> this could hinder the DT migration later.
> >>
> >
> > As I already mentioned in my previous response, your patch is required
> > irrespective of this patch. I would consider your patch as a cleanup patch.
> >
> >
> > Both the patches are independent, your patch is handling the error path
> > properly, whereas, my patch makes sure that you don't unnecessarily probe
> > GPMC if you are booting from DT and GPMC node is not present, as described
> > above.
>
> Your patch hides a bug. That's my point. How do you expect am335x ever
> to support gpmc devices if this bug is not addressed?
>
Jon,
May be my commit description was mis-leading to you.
I am not commenting anything on your bug-fix, but do not agree that it is
anything to do with hiding a bug.
I only agree with you on one point, if someone wants to change the board-
file to use GPMC with DT boot mode, then he will not be able to use it.
> So I think that you are over-simplifying it when you say that my patch
> is just a clean-up patch. I agree that it is adding appropriate error
> handling, but it also highlights the presence of a bug by allowing the
> probe to fail.
>
> Anyway, I don't care to debate this any further,
Me neither...
> we just need to fix
> gpmc_mem_init().
>
Agreed, and that's what your patch rightly doing it.
Thanks,
Vaibhav
> Jon
>
^ permalink raw reply
* [PATCH] ARM: kirkwood: fix buttons on lsxl boards
From: Jason Cooper @ 2012-10-18 18:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1348782877-857-1-git-send-email-michael@walle.cc>
On Thu, Sep 27, 2012 at 11:54:37PM +0200, Michael Walle wrote:
> Change event type to switch for the power and autopower switches.
> Additionally, this patch aligns the keycodes with the other linkstation
> boards already supported by linux.
>
> Signed-off-by: Michael Walle <michael@walle.cc>
> ---
> arch/arm/boot/dts/kirkwood-lsxl.dtsi | 8 +++++---
> 1 files changed, 5 insertions(+), 3 deletions(-)
Applied to:
git://git.infradead.org/users/jcooper/linux.git kirkwood/fixes
thx,
Jason.
^ permalink raw reply
* [PATCH] ARM: kirkwood: fix LEDs names for lsxl boards
From: Jason Cooper @ 2012-10-18 18:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1348519742-20126-1-git-send-email-michael@walle.cc>
On Mon, Sep 24, 2012 at 10:49:02PM +0200, Michael Walle wrote:
> Don't use the specific board name in a the common device tree include file.
> Instead use the common name 'lsxl'.
>
> Signed-off-by: Michael Walle <michael@walle.cc>
> ---
> arch/arm/boot/dts/kirkwood-lsxl.dtsi | 10 +++++-----
> 1 files changed, 5 insertions(+), 5 deletions(-)
Applied to:
git://git.infradead.org/users/jcooper/linux.git kirkwood/fixes
thx,
Jason.
^ permalink raw reply
* [PATCH 08/10] pinctrl: single: support pinconf generic
From: Linus Walleij @ 2012-10-18 18:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350551224-12857-8-git-send-email-haojian.zhuang@gmail.com>
On Thu, Oct 18, 2012 at 11:07 AM, Haojian Zhuang
<haojian.zhuang@gmail.com> wrote:
> Add pinconf generic support with POWER SOURCE, BIAS PULL.
>
> Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
I really like the looks of this, good job Haojian!
Now we just need to hear what Tony says about it...
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH 1/5] ARM: OMAP2+: gpmc: Fix kernel BUG for DT boot mode
From: Jon Hunter @ 2012-10-18 18:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <79CD15C6BA57404B839C016229A409A83EB43D0F@DBDE01.ent.ti.com>
On 10/18/2012 01:04 PM, Hiremath, Vaibhav wrote:
> On Thu, Oct 18, 2012 at 22:12:07, Hunter, Jon wrote:
...
>> Yes, but do you also see the bug that is hiding in gpmc_mem_init()?
>>
>> My point is to highlight this and not hide it, so that we can fix it
>> now. Otherwise if we wait until we enable the gpmc driver with DT and
>> this could hinder the DT migration later.
>>
>
> As I already mentioned in my previous response, your patch is required
> irrespective of this patch. I would consider your patch as a cleanup patch.
>
>
> Both the patches are independent, your patch is handling the error path
> properly, whereas, my patch makes sure that you don't unnecessarily probe
> GPMC if you are booting from DT and GPMC node is not present, as described
> above.
Your patch hides a bug. That's my point. How do you expect am335x ever
to support gpmc devices if this bug is not addressed?
So I think that you are over-simplifying it when you say that my patch
is just a clean-up patch. I agree that it is adding appropriate error
handling, but it also highlights the presence of a bug by allowing the
probe to fail.
Anyway, I don't care to debate this any further, we just need to fix
gpmc_mem_init().
Jon
^ permalink raw reply
* [PATCH 07/10] pinctrl: remove mutex lock in groups show
From: Linus Walleij @ 2012-10-18 18:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350551224-12857-7-git-send-email-haojian.zhuang@gmail.com>
On Thu, Oct 18, 2012 at 11:07 AM, Haojian Zhuang
<haojian.zhuang@gmail.com> wrote:
> Mutex is locked duplicatly by pinconf_groups_show() and
> pin_config_group_get(). It results dead lock. So avoid to lock mutex
> in pinconf_groups_show().
>
> Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Thanks! Applied to my fixes branch with a Cc: stable tag.
Yours,
Linus Walleij
^ permalink raw reply
* SD Card: how to change data bits on the clock falling edge?
From: Marco Lazzaroni @ 2012-10-18 18:29 UTC (permalink / raw)
To: linux-arm-kernel
Hello,
I'm using kernel 3.6 on a i.MX23 processor.
I was able to enable and use a second SD Card by using interface SSP2 (I
boot from a SD Card on SSP1).
The short story is, I need to keep BM_SSP_CTRL1_POLARITY bit in
HW_SSP_CTRL1 register to a 1 value, while now it is initialized at 1, but
after that it changes to 0.
How do I accomplish this?
Here I explain why I need this behaviour.
The SD Card is correctly recognised, (kern.log tells that I have a 1.84GB
card in it is correct), but then I'm having some communication errors
[...]
Oct 18 19:19:30 debian kernel: [ 527.800000] mmcblk1: error -84
transferring data, sector 0, nr 8, cmd response 0x900, card status 0x800b00
Oct 18 19:19:30 debian kernel: [ 527.810000] mmcblk1: retrying using
single block read
Oct 18 19:19:30 debian kernel: [ 527.820000] mmcblk1: error -84
transferring data, sector 0, nr 8, cmd response 0x900, card status 0x0
Oct 18 19:19:30 debian kernel: [ 527.830000] end_request: I/O error, dev
mmcblk1, sector 0
Oct 18 19:19:30 debian kernel: [ 527.840000] mmcblk1: error -84
transferring data, sector 1, nr 7, cmd response 0x900, card status 0x0
Oct 18 19:19:30 debian kernel: [ 527.840000] end_request: I/O error, dev
mmcblk1, sector 1
Oct 18 19:19:30 debian kernel: [ 527.850000] mmcblk1: error -84
transferring data, sector 2, nr 6, cmd response 0x900, card status 0x0
Oct 18 19:19:30 debian kernel: [ 527.860000] end_request: I/O error, dev
mmcblk1, sector 2
Oct 18 19:19:30 debian kernel: [ 527.870000] mmcblk1: error -84
transferring data, sector 3, nr 5, cmd response 0x900, card status 0x0
Oct 18 19:19:30 debian kernel: [ 527.880000] end_request: I/O error, dev
mmcblk1, sector 3
Oct 18 19:19:30 debian kernel: [ 527.900000] mmcblk1: error -84
transferring data, sector 4, nr 4, cmd response 0x900, card status 0x0
Oct 18 19:19:30 debian kernel: [ 527.910000] end_request: I/O error, dev
mmcblk1, sector 4
Oct 18 19:19:30 debian kernel: [ 527.940000] mmcblk1: error -84
transferring data, sector 5, nr 3, cmd response 0x900, card status 0x0
Oct 18 19:19:30 debian kernel: [ 527.950000] end_request: I/O error, dev
mmcblk1, sector 5
Oct 18 19:19:30 debian kernel: [ 527.960000] mmcblk1: error -84
transferring data, sector 6, nr 2, cmd response 0x900, card status 0x0
Oct 18 19:19:30 debian kernel: [ 527.960000] end_request: I/O error, dev
mmcblk1, sector 6
Oct 18 19:19:30 debian kernel: [ 527.980000] mmcblk1: error -84
transferring data, sector 7, nr 1, cmd response 0x900, card status 0x0
Oct 18 19:19:30 debian kernel: [ 527.990000] end_request: I/O error, dev
mmcblk1, sector 7
Oct 18 19:19:30 debian kernel: [ 527.990000] quiet_error: 13 callbacks
suppressed
Oct 18 19:19:30 debian kernel: [ 528.000000] Buffer I/O error on device
mmcblk1, logical block 0
Oct 18 19:19:30 debian kernel: [ 528.020000] mmcblk1: error -110 sending
stop command, original cmd response 0x900, card status 0x800b00
[...]
Here is some facts:
- if I'm right, SD standard says that data bits are sampled on the rising
edge of the clock signal, and must be valid for at least 2.5ns after that.
- in mxs-mmc.c, I see that BM_SSP_CTRL1_POLARITY bit in HW_SSP_CTRL1
register is set in function mxs_mmc_reset -> this means data changes after
falling edge (this information is contained in the imx23 datasheet p1042 ->
http://www.freescale.com/files/dsp/doc/ref_manual/IMX23RM.pdf )
- with an oscilloscope I see that data bits correctly change after falling
in edge during the first communications (the phase at 400 kHz clock)
- I see also that after this, when clock switches to high speed (default is
50MHz, but I slowed down because of hardware problems to 1 MHz), data bits
change after rising edge
- in fact if I printk out HW_SSP_CTRL1, I see that BM_SSP_CTRL1_POLARITY is
reset (-> data changes after rising edge).
The outcome is that even if I slow down to 1 MHz, I can't correctly read
the content of the SD card. Looking at the oscilloscope if I measure
signals near the SD Card I see that the clock rising edge is a little late,
so the SD Card sees that bits changing when they're sampled.
I think that doing changes after the rising edge while in high speed is the
correct thing, so there's enough time for data bits to settle.
Anyway, because of my hardware problems (SD Card is 50 cm away from the
CPU), slowing down the card to 1MHz does not improve things because data
are changed so close to the time at which they're sampled. Signals and good
and squared, with no ringings, but that little time shift throws me in
trouble).
I would need to keep the BM_SSP_CTRL1_POLARITY bit to 1 even in high
speed, so data bits change on the falling edge; data bits have all the time
to settle before the arriving of the rising edge since the clock is as slow
as 1MHz.
But I don't know how to keep this bit at 1.
There's only a reference in mxs-mmc.c to BM_SSP_CTRL1_POLARITY, when it is
set to 1, so I can't figure where it gets changed and set to 0.
Any help is appreciated. Thank you very much in advance.
Best regards,
Marco Lazzaroni
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^ permalink raw reply
* Fwd: [PATCH 2/5] ARM: OMAP3+: hwmod: Add AM33XX HWMOD data for davinci_mdio
From: Richard Cochran @ 2012-10-18 18:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.DEB.2.00.1210180313360.6893@utopia.booyaka.com>
On Thu, Oct 18, 2012 at 03:46:15AM +0000, Paul Walmsley wrote:
>
> It doesn't necessarily mean that the driver is usable in that kernel
> release.
Well, it should. We have staging for half-baked stuff.
> Either way, the patch is likely to make it into the mainline kernel.
> It's just that it will probably take a few weeks longer than you might
> like.
I don't mind waiting for a driver that is held off because of missing
background support.
I *do* mind if y'all go merging all kinds of code that has never been
tested. Those who submit and their reviewers should ensure that the
code is actually working. Before buying hardware or starting projects,
I often check what is in mainline. I expect that mainline has been at
least minimally tested.
Maybe that is just me, or maybe people working on the ARM tree have
different expectations.
Thanks,
Richard
^ permalink raw reply
* [PATCH 04/10] i2c: pxa: configure pins
From: Linus Walleij @ 2012-10-18 18:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350551224-12857-4-git-send-email-haojian.zhuang@gmail.com>
On Thu, Oct 18, 2012 at 11:06 AM, Haojian Zhuang
<haojian.zhuang@gmail.com> wrote:
> Configure pins by pinctrl driver.
>
> Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH 03/10] tty: pxa: configure pin
From: Linus Walleij @ 2012-10-18 18:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350551224-12857-3-git-send-email-haojian.zhuang@gmail.com>
On Thu, Oct 18, 2012 at 11:06 AM, Haojian Zhuang
<haojian.zhuang@gmail.com> wrote:
> Configure pins by pinctrl driver.
>
> Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH 01/10] pinctrl: use postcore_initcall
From: Linus Walleij @ 2012-10-18 18:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350551224-12857-1-git-send-email-haojian.zhuang@gmail.com>
This patch has the wrong subject, should be pinctrl: single: or
pinctrl/single: ...
Anyway, I need Tony to ACK them before merging.
Yours,
Linus Walleij
^ permalink raw reply
* [GIT PULL V2] ARM: Kirkwood: fixes for v3.7
From: Jason Cooper @ 2012-10-18 18:18 UTC (permalink / raw)
To: linux-arm-kernel
The following changes since commit ddffeb8c4d0331609ef2581d84de4d763607bd37:
Linux 3.7-rc1 (2012-10-14 14:41:04 -0700)
are available in the git repository at:
git://git.infradead.org/users/jcooper/linux.git tags/kirkwood_fixes_for_v3.7
for you to fetch changes up to 12431634947f4c34015561104c4f8a305bfe6b48:
ARM: kirkwood: fix buttons on lsxl boards (2012-10-18 17:07:23 +0000)
----------------------------------------------------------------
- improve #ifdef logic to prevent linker errors with CACHE_FEROCEON_L2
- lsxl board dts fixes
----------------------------------------------------------------
Jason Gunthorpe (1):
ARM: Kirkwood: fix disabling CACHE_FEROCEON_L2
Michael Walle (2):
ARM: kirkwood: fix LEDs names for lsxl boards
ARM: kirkwood: fix buttons on lsxl boards
arch/arm/boot/dts/kirkwood-lsxl.dtsi | 18 ++++++++++--------
arch/arm/mach-kirkwood/board-dt.c | 2 --
arch/arm/mach-kirkwood/common.c | 4 ++--
3 files changed, 12 insertions(+), 12 deletions(-)
^ permalink raw reply
* [PATCH] ARM: multi_v7_defconfig: Add ARCH_MXC
From: Fabio Estevam @ 2012-10-18 18:06 UTC (permalink / raw)
To: linux-arm-kernel
Let ARCH_MXC be covered by multi_v7_defconfig.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
arch/arm/configs/multi_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 159f75f..c8cbd6a 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -5,6 +5,7 @@ CONFIG_ARCH_MVEBU=y
CONFIG_MACH_ARMADA_370=y
CONFIG_MACH_ARMADA_XP=y
CONFIG_ARCH_HIGHBANK=y
+CONFIG_ARCH_MXC=y
CONFIG_ARCH_SOCFPGA=y
# CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA is not set
CONFIG_ARM_ERRATA_754322=y
--
1.7.9.5
^ permalink raw reply related
* [PATCH v3] ARM: mach-imx: Fix selection of ARCH_MXC
From: Fabio Estevam @ 2012-10-18 18:04 UTC (permalink / raw)
To: linux-arm-kernel
Since commit c5a0d497(ARM: imx: enable multi-platform build),
ARCH_MXC is selected by the following logic:
config ARCH_MXC
def_bool y if ARCH_MULTI_V4_V5 || ARCH_MULTI_V6_V7
, which causes build error on vexpress_defconfig:
arch/arm/mach-imx/hotplug.c:49: undefined reference to `imx_enable_cpu'
arch/arm/mach-imx/platsmp.c:57: undefined reference to `imx_set_cpu_jump'
arch/arm/mach-imx/platsmp.c:58: undefined reference to `imx_enable_cpu'
Make ARCH_MXC a user selectable option, so that it does not get built
by default on other defconfigs that select ARCH_MULTI_V4_V5 or ARCH_MULTI_V6_V7.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
Changes since v2:
- Make ARCH_MXC a user selectable option
Changes since v1:
- Fix typo in commit message and improve it a bit
arch/arm/configs/imx_v4_v5_defconfig | 1 +
arch/arm/configs/imx_v6_v7_defconfig | 1 +
arch/arm/mach-imx/Kconfig | 2 +-
3 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig
index bd01244..f71302c 100644
--- a/arch/arm/configs/imx_v4_v5_defconfig
+++ b/arch/arm/configs/imx_v4_v5_defconfig
@@ -17,6 +17,7 @@ CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
+CONFIG_ARCH_MXC=y
CONFIG_ARCH_MULTI_V4T=y
CONFIG_ARCH_MULTI_V5=y
# CONFIG_ARCH_MULTI_V7 is not set
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index a4965f3..5dfadfb 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -16,6 +16,7 @@ CONFIG_MODULE_UNLOAD=y
CONFIG_MODVERSIONS=y
CONFIG_MODULE_SRCVERSION_ALL=y
# CONFIG_BLK_DEV_BSG is not set
+CONFIG_ARCH_MXC=y
CONFIG_ARCH_MULTI_V6=y
CONFIG_ARCH_MULTI_V7=y
CONFIG_MACH_MX31LILLY=y
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 856482d..cbbef1a 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -1,5 +1,5 @@
config ARCH_MXC
- def_bool y if ARCH_MULTI_V4_V5 || ARCH_MULTI_V6_V7
+ bool "Freescale i.MX family" if ARCH_MULTI_V4_V5 || ARCH_MULTI_V6_V7
select ARCH_REQUIRE_GPIOLIB
select ARM_PATCH_PHYS_VIRT
select AUTO_ZRELADDR if !ZBOOT_ROM
--
1.7.9.5
^ permalink raw reply related
* [PATCH 1/5] ARM: OMAP2+: gpmc: Fix kernel BUG for DT boot mode
From: Hiremath, Vaibhav @ 2012-10-18 18:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5080315F.8090802@ti.com>
On Thu, Oct 18, 2012 at 22:12:07, Hunter, Jon wrote:
>
> On 10/18/2012 11:16 AM, Hiremath, Vaibhav wrote:
> > On Wed, Oct 17, 2012 at 01:17:56, Hunter, Jon wrote:
> >>
> >> On 10/15/2012 02:16 PM, Richard Cochran wrote:
> >>> From: hvaibhav at ti.com <hvaibhav@ti.com>
> >>>
> >>> With recent changes in omap gpmc driver code, in case of DT
> >>> boot mode, where bootloader does not configure gpmc cs space
> >>> will result into kernel BUG() inside gpmc_mem_init() function,
> >>> as gpmc cs0 gpmc_config7[0].csvalid bit is set to '1' and
> >>> gpmc_config7[0].baseaddress is set to '0' on reset.
> >>
> >> I am not sure I completely follow the logic here.
> >>
> >> Won't this problem occur if the bootloader does not configure the gpmc
> >> cs space AND we are not using DT?
> >>
> >
> > That's what exactly the above comment describes.
>
> Hmm ... you said "in the case of DT", but I am saying even "in the case
> WITHOUT DT" this can happen. So I think the subject is mis-leading.
>
Ok, may be my above statement was confusing. But the bottom line is,
We should GPMC without any pre-configuration (either at u-boot or ROM) will
have this issue.
> >> Is the csvalid bit set because we are booting from the internal ROM?
> >>
> >
> > As per TRM, the reset value of the CS0_valis bit is set to 0. I have pasted
> > TRM statement below -
> >
> > "Chip-select enable (reset value is 1 for CS[0] and 0 for CS[1-5])."
>
> The above two sentences don't see to agree ...
Oops, it was typo mistake. I meant "is set to '1'"
>
> > And same applies to OMAP3 family of devices.
>
> For which boot-modes? All or just the gpmc boot-modes?
>
That's reset value, and I believe it is applicable for all boot modes.
> My omap3430 beagle has been booting with DT fine for some time and I
> have not encountered this problem even on the latest kernel with the
> gpmc driver present.
>
OMAp3430 beagle board has NAND flash available over GPMC-CS0 interface.
> >> I guess I don't see why csvalid bit being set and a base-address of 0x0
> >> should not be allowed. That should be a valid combination.
> >>
> >
> > Yes, agreed.
> >
> >> One problem I see with gpmc_mem_init() is that it assumes that
> >> BOOT_ROM_SPACE is 1MB for all devices starting at 0x0 apart from the
> >> apollon board. For newer devices such as OMAP4, there is only 48KB of
> >> internal ROM and only mapped to 0x0 when booting from internal ROM. So
> >> this needs to be fixed.
> >>
> >> How much internal ROM does the AM335x have and where is it mapped?
> >>
> >
> > AM33xx memory map is something like,
> >
> > Boot ROM 0x4000_0000 0x4001_FFFF 128KB
> > 0x4002_0000 0x4002_BFFF 48KB 32-bit Ex/R(1) - Public
> > Reserved 0x4002_C000 0x400F_FFFF 848KB Reserved
> > Reserved 0x4010_0000 0x401F_FFFF 1MB Reserved
> > Reserved 0x4020_0000 0x402E_FFFF 960KB Reserved
> > Reserved 0x402f_0000 0x4020_03FF 64KB Reserved
> > SRAM internal 0x402F_0400 0x402F_FFFF 32-bit Ex/R/W(1)
>
> Does the boot ROM get mapped to 0x0, when booting from ROM?
>
I expect, it should be same as OMAP4.
> >>> This use-case is applicable for any board/EVM which doesn't have
> >>> any peripheral connected to gpmc cs0, for example BeagleXM and
> >>> BeagleBone, so DT boot mode fails.
> >>>
> >>> This patch adds of_have_populated_dt() check before creating
> >>> device, so that for DT boot mode, gpmc probe will not be called
> >>> which is expected behavior, as gpmc is not supported yet from DT.
> >>
> >> Yes, but we do actually still allow some platform devices to be probed
> >> (such as dmtimers) when booting with DT that don't support DT yet. So
> >> this change prevents us from using the gpmc on boards when booting with DT.
> >>
> >
> > The idea here was,
> >
> > In order to use GPMC in meaningful way, where some peripheral is connected
> > to the GPMC, you must create platform_device for the probe to happen
> > properly. Now all the devices I know so far, we have gpmc_smsc911x_init(),
> > omap_nand_flash_init(), etc...
> > These api's are getting called only through machine_desc.init_xxx callbacks,
> > And in case of DT, we have centralized machine_desc definition for all
> > platforms (board-generic.c). So even though you want to use GPMC for DT boot
> > mode, you can not make use of peripheral without changing board-files to
> > change to create platform_device.
> >
> > Does it make sense?
>
> Sure, if you are using one of the generic machine configurations for DT.
> However, while this migration happens people may create their own custom
> machine configurations for DT for testing things like smsc911x.
>
If we want to think about all such use-cases, then yes, this patch is not
required.
> >> I am not convinced that this is addressing the underlying problem with
> >> gpmc_mem_init().
> >>
> >
> > The patch you submitted is cleanup patch and is required irrespective of
> > this patch. I believe this patch is just makes sure that, if you are booting
> > from DT and you do not have meaningful DT node for GPMC and peripheral
> > interfaced to it, no point in probing it.
> >
> > Does it make any sense???
>
> Yes, but do you also see the bug that is hiding in gpmc_mem_init()?
>
> My point is to highlight this and not hide it, so that we can fix it
> now. Otherwise if we wait until we enable the gpmc driver with DT and
> this could hinder the DT migration later.
>
As I already mentioned in my previous response, your patch is required
irrespective of this patch. I would consider your patch as a cleanup patch.
Both the patches are independent, your patch is handling the error path
properly, whereas, my patch makes sure that you don't unnecessarily probe
GPMC if you are booting from DT and GPMC node is not present, as described
above.
Thanks,
Vaibhav
> Jon
>
>
^ permalink raw reply
* [RFC PATCH 2/2] ARM: OMAP4: clock: use omap4_clks_register API
From: Mike Turquette @ 2012-10-18 17:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350578297-22572-3-git-send-email-grygorii.strashko@ti.com>
Quoting Grygorii Strashko (2012-10-18 09:38:17)
> Remove OMAP443x and OMAP446x specific clocks from omap44xx_clks
> array and add corresponding set of clocks per each SoC:
> - struct omap_clk omap44xx_clks[]; - common clocks set for all OMAP4
> - struct omap_clk omap443x_clks[]; - specific clocks set for OMAP443x
> - struct omap_clk omap446x_clks[]; - specific clocks set for OMAP446x
> and don't rely on platform specific flags any more.
>
> Use omap4_clks_register() API to register and init OMAP4 set of
> clocks.
>
> With this change, we can now safely remove CK_443X/CK_446X etc macro
> usage. It has not been done in this patch, but if the approach is OK,
> then, it is possible to do the same.
>
In addition to removing CK_443X/CK_446X you could also get rid of struct
omap_clk completely (arch/arm/plat-omap/include/plat/clkdev_omap.h) and
the CLK macro by changing the clk array to be of type struct clk_lookup
and using the CLKDEV_INIT macro.
> One additional benefit seen is that the match logic can entirely be
> skipped.
>
I wonder if splitting the tables would make initdata any easier. It
would be nice to get more functional changes out of this series
alongside the data reorganization.
Also have you looked at splitting the tables for OMAP2/3?
Regards,
Mike
> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
> ---
> arch/arm/mach-omap2/clock44xx_data.c | 40 ++++++++++++++++++----------------
> 1 file changed, 21 insertions(+), 19 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
> index 6efc30c..4060c9c 100644
> --- a/arch/arm/mach-omap2/clock44xx_data.c
> +++ b/arch/arm/mach-omap2/clock44xx_data.c
> @@ -3145,10 +3145,7 @@ static struct omap_clk omap44xx_clks[] = {
> CLK(NULL, "aes1_fck", &aes1_fck, CK_443X),
> CLK(NULL, "aes2_fck", &aes2_fck, CK_443X),
> CLK(NULL, "aess_fck", &aess_fck, CK_443X),
> - CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X),
> - CLK(NULL, "bandgap_ts_fclk", &bandgap_ts_fclk, CK_446X),
> CLK(NULL, "des3des_fck", &des3des_fck, CK_443X),
> - CLK(NULL, "div_ts_ck", &div_ts_ck, CK_446X),
> CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X),
> CLK(NULL, "dmic_fck", &dmic_fck, CK_443X),
> CLK(NULL, "dsp_fck", &dsp_fck, CK_443X),
> @@ -3346,19 +3343,27 @@ static struct omap_clk omap44xx_clks[] = {
> CLK("4903c000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
> CLK("4903e000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
> CLK(NULL, "cpufreq_ck", &dpll_mpu_ck, CK_443X),
> + CLK(NULL, NULL, NULL, CK_443X),
> +};
> +
> +static struct omap_clk omap443x_clks[] = {
> + CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X),
> + CLK(NULL, NULL, NULL, CK_443X),
> +};
> +
> +
> +static struct omap_clk omap446x_clks[] = {
> + CLK(NULL, "div_ts_ck", &div_ts_ck, CK_446X),
> + CLK(NULL, "bandgap_ts_fclk", &bandgap_ts_fclk, CK_446X),
> + CLK(NULL, NULL, NULL, CK_446X),
> };
>
> int __init omap4xxx_clk_init(void)
> {
> - struct omap_clk *c;
> - u32 cpu_clkflg;
> -
> if (cpu_is_omap443x()) {
> cpu_mask = RATE_IN_4430;
> - cpu_clkflg = CK_443X;
> } else if (cpu_is_omap446x() || cpu_is_omap447x()) {
> cpu_mask = RATE_IN_4460 | RATE_IN_4430;
> - cpu_clkflg = CK_446X | CK_443X;
>
> if (cpu_is_omap447x())
> pr_warn("WARNING: OMAP4470 clock data incomplete!\n");
> @@ -3375,17 +3380,14 @@ int __init omap4xxx_clk_init(void)
> * omap2_clk_disable_clkdm_control();
> */
>
> - for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
> - c++)
> - clk_preinit(c->lk.clk);
> -
> - for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
> - c++)
> - if (c->cpu & cpu_clkflg) {
> - clkdev_add(&c->lk);
> - clk_register(c->lk.clk);
> - omap2_init_clk_clkdm(c->lk.clk);
> - }
> + omap2_clks_register(omap44xx_clks);
> +
> + if (cpu_is_omap443x())
> + omap2_clks_register(omap443x_clks);
> + else if (cpu_is_omap446x() || cpu_is_omap447x())
> + omap2_clks_register(omap446x_clks);
> + else
> + return 0;
>
> /* Disable autoidle on all clocks; let the PM code enable it later */
> omap_clk_disable_autoidle_all();
> --
> 1.7.9.5
^ permalink raw reply
* [RFC/NOT FOR MERGING 1/5] arm: omap: fix up _od_suspend_noirq and _od_resume_noirq
From: Felipe Balbi @ 2012-10-18 17:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <87ipa7d6cy.fsf@deeprootsystems.com>
Hi,
On Thu, Oct 18, 2012 at 10:42:37AM -0700, Kevin Hilman wrote:
> Felipe Balbi <balbi@ti.com> writes:
>
> > Hi,
> >
> > On Thu, Oct 18, 2012 at 09:34:15AM -0700, Kevin Hilman wrote:
> >> Felipe Balbi <balbi@ti.com> writes:
> >>
> >> > current implementation doesn't take care about
> >> > drivers which don't provide *_noirq methods
> >>
> >> The generic ops handle this. See below.
> >>
> >> > and we could fall into a situation where we would suspend/resume
> >> > devices even though they haven't asked for it.
> >>
> >> The following explanation doesn't explain this, so I dont' follow
> >> the "even though they haven't asked for it" part.
> >>
> >> > One such case happened with the I2C driver which
> >> > was getting suspended during suspend_noirq() just
> >> > to be resume right after by any other device doing
> >> > an I2C transfer on its suspend method.
> >>
> >> In order to be I2C to be runtime resumed after its noirq method has been
> >> called, that means the other device is doing an I2C xfer in its noirq
> >> method. That is a bug.
> >>
> >> > Signed-off-by: Felipe Balbi <balbi@ti.com>
> >> > ---
> >> > arch/arm/plat-omap/omap_device.c | 8 ++++++++
> >> > 1 file changed, 8 insertions(+)
> >> >
> >> > diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
> >> > index 7a7d1f2..935f416 100644
> >> > --- a/arch/arm/plat-omap/omap_device.c
> >> > +++ b/arch/arm/plat-omap/omap_device.c
> >> > @@ -804,8 +804,12 @@ static int _od_suspend_noirq(struct device *dev)
> >> > {
> >> > struct platform_device *pdev = to_platform_device(dev);
> >> > struct omap_device *od = to_omap_device(pdev);
> >> > + const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL;
> >> > int ret;
> >> >
> >> > + if (!pm || !pm->suspend_noirq)
> >> > + return 0;
> >> > +
> >>
> >> you just re implemented pm_generic_suspend_noirq() (c.f. drivers/base/power/generic_ops.c)
> >>
> >> > /* Don't attempt late suspend on a driver that is not bound */
> >> > if (od->_driver_status != BUS_NOTIFY_BOUND_DRIVER)
> >> > return 0;
> >> > @@ -827,6 +831,10 @@ static int _od_resume_noirq(struct device *dev)
> >> > {
> >> > struct platform_device *pdev = to_platform_device(dev);
> >> > struct omap_device *od = to_omap_device(pdev);
> >> > + const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL;
> >> > +
> >> > + if (!pm || !pm->resume_noirq)
> >> > + return 0;
> >>
> >> and this is basically pm_generic_resume_noirq()
> >
> > not true, there is a slight different. Note that you only call
> > pm_generic_resume_noirq() after calling pm_runtime_resume()ing the
> > device:
>
> >> static int _od_resume_noirq(struct device *dev)
> >> {
> >> struct platform_device *pdev = to_platform_device(dev);
> >> struct omap_device *od = to_omap_device(pdev);
> >>
> >> if ((od->flags & OMAP_DEVICE_SUSPENDED) &&
> >> !pm_runtime_status_suspended(dev)) {
> >> od->flags &= ~OMAP_DEVICE_SUSPENDED;
> >> if (!(od->flags & OMAP_DEVICE_NO_IDLE_ON_SUSPEND))
> >> omap_device_enable(pdev);
> >> pm_generic_runtime_resume(dev);
> >
> > right here. IMHO this is a bug, if the define doesn't implement
> > resume_noirq, it's telling you that it has nothing to do at that time,
>
> This is where the misunderstanding is. I suggest you have a look
> at commit c03f007a8bf0e092caeb6856a5c8a850df10b974 where this feature
> was added, but I'll try to summarize:
>
> The goal is simply this:
>
> If, by the time .suspend_noirq has run, the driver is not already
> runtime suspended, then forcefully runtime suspend it.
>
> That's it.
Yes, I got the intention, but to me it looks wrong.
> Again, this is required because system suspend disables runtime PM
> transitions at a certain point, if the device is used after that point,
> there is *no other way* for the driver to properly manage the idle
> transition (or, if there is, please explain it to me.)
Can you please let me know of any situation where e.g. I2C/SPI would be
needed after all its children are suspended ?
> > so you shouldn't forcefully resume the device.
>
> Note it's only forcefully resumed *if* it was forcefully suspended by
> suspend_noirq.
likewise, you shouldn't forcefully runtime suspend a device. The device
driver needs to be required to provide suspend/resume functions if it
cares.
> > If the device dies, then it means that it needs to implement
> > resume_noirq. What you have here, is a "workaround" for badly written
> > device drivers IMHO.
>
> That's one way of looking at it. The other way of looking at it is that
> by handling this at the PM domain level, the drivers can be much simpler,
> and thus less likely to get wrong.
You're still bypassing what the PM framework wants us to do, no ? What
if Rafael decides to drastically change the way system and runtime PM is
done and it ends up breaking what we have on OMAP ? If we stick to the
standard, the it's less likely to brea.
> But even then, with your proposed changes, I don't think the device will
> be properly idled (including the omap_device_idle) in these important cases:
>
> 1) I2C is used by some other device *after* its ->suspend method has
> been called.
how can that happen ? I2C's ->suspend method will only be called after
all its children are suspended.
> 2) I2C runtime PM is disabled from userspace
> (echo off > /sys/devices/.../power/control)
that should not make a difference if you omap_device_idle() is written
as it should. Maybe what you need is a refactor to provide
omap_device_idle() and omap_device_runtime_idle(), the latter taking
care of the case where runtime pm can be disabled from userspace while
the former idling whenever it's called.
> but I'll take this up in the I2C driver patch itself.
sure :-)
> > Note also, that you could runtime resume devices which don't implement
> > resume_noirq().
>
> Again, this is by design.
a very weird design IMHO. Either that or I'm really missing something
here.
> It doesn't matter if the driver has noirq methods. If it is not yet
> runtime suspended, it is forceably runtime suspended. The generic
if it's not yet runtime suspended, you need to call the driver's
->suspend_* method (depending on the suspend phase you are right now),
but "reusing" the runtime_suspend method sounds to me like another
"special OMAP requirement".
> noirq calls are just there in case the driver has noirq callbacks.
I get that, but why would you suspend a device which doesn't want to be
suspended in suspend_noirq(), but using its runtime_suspend method ?
If I2C dies on a suspend/resume transition, it's a bug in the I2C
driver, no ?
--
balbi
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^ permalink raw reply
* [RFC/NOT FOR MERGING 1/5] arm: omap: fix up _od_suspend_noirq and _od_resume_noirq
From: Kevin Hilman @ 2012-10-18 17:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121018165525.GA6385@arwen.pp.htv.fi>
Felipe Balbi <balbi@ti.com> writes:
> Hi,
>
> On Thu, Oct 18, 2012 at 09:34:15AM -0700, Kevin Hilman wrote:
>> Felipe Balbi <balbi@ti.com> writes:
>>
>> > current implementation doesn't take care about
>> > drivers which don't provide *_noirq methods
>>
>> The generic ops handle this. See below.
>>
>> > and we could fall into a situation where we would suspend/resume
>> > devices even though they haven't asked for it.
>>
>> The following explanation doesn't explain this, so I dont' follow
>> the "even though they haven't asked for it" part.
>>
>> > One such case happened with the I2C driver which
>> > was getting suspended during suspend_noirq() just
>> > to be resume right after by any other device doing
>> > an I2C transfer on its suspend method.
>>
>> In order to be I2C to be runtime resumed after its noirq method has been
>> called, that means the other device is doing an I2C xfer in its noirq
>> method. That is a bug.
>>
>> > Signed-off-by: Felipe Balbi <balbi@ti.com>
>> > ---
>> > arch/arm/plat-omap/omap_device.c | 8 ++++++++
>> > 1 file changed, 8 insertions(+)
>> >
>> > diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
>> > index 7a7d1f2..935f416 100644
>> > --- a/arch/arm/plat-omap/omap_device.c
>> > +++ b/arch/arm/plat-omap/omap_device.c
>> > @@ -804,8 +804,12 @@ static int _od_suspend_noirq(struct device *dev)
>> > {
>> > struct platform_device *pdev = to_platform_device(dev);
>> > struct omap_device *od = to_omap_device(pdev);
>> > + const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL;
>> > int ret;
>> >
>> > + if (!pm || !pm->suspend_noirq)
>> > + return 0;
>> > +
>>
>> you just re implemented pm_generic_suspend_noirq() (c.f. drivers/base/power/generic_ops.c)
>>
>> > /* Don't attempt late suspend on a driver that is not bound */
>> > if (od->_driver_status != BUS_NOTIFY_BOUND_DRIVER)
>> > return 0;
>> > @@ -827,6 +831,10 @@ static int _od_resume_noirq(struct device *dev)
>> > {
>> > struct platform_device *pdev = to_platform_device(dev);
>> > struct omap_device *od = to_omap_device(pdev);
>> > + const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL;
>> > +
>> > + if (!pm || !pm->resume_noirq)
>> > + return 0;
>>
>> and this is basically pm_generic_resume_noirq()
>
> not true, there is a slight different. Note that you only call
> pm_generic_resume_noirq() after calling pm_runtime_resume()ing the
> device:
>> static int _od_resume_noirq(struct device *dev)
>> {
>> struct platform_device *pdev = to_platform_device(dev);
>> struct omap_device *od = to_omap_device(pdev);
>>
>> if ((od->flags & OMAP_DEVICE_SUSPENDED) &&
>> !pm_runtime_status_suspended(dev)) {
>> od->flags &= ~OMAP_DEVICE_SUSPENDED;
>> if (!(od->flags & OMAP_DEVICE_NO_IDLE_ON_SUSPEND))
>> omap_device_enable(pdev);
>> pm_generic_runtime_resume(dev);
>
> right here. IMHO this is a bug, if the define doesn't implement
> resume_noirq, it's telling you that it has nothing to do at that time,
This is where the misunderstanding is. I suggest you have a look
at commit c03f007a8bf0e092caeb6856a5c8a850df10b974 where this feature
was added, but I'll try to summarize:
The goal is simply this:
If, by the time .suspend_noirq has run, the driver is not already
runtime suspended, then forcefully runtime suspend it.
That's it.
Again, this is required because system suspend disables runtime PM
transitions at a certain point, if the device is used after that point,
there is *no other way* for the driver to properly manage the idle
transition (or, if there is, please explain it to me.)
> so you shouldn't forcefully resume the device.
Note it's only forcefully resumed *if* it was forcefully suspended by
suspend_noirq.
> If the device dies, then it means that it needs to implement
> resume_noirq. What you have here, is a "workaround" for badly written
> device drivers IMHO.
That's one way of looking at it. The other way of looking at it is that
by handling this at the PM domain level, the drivers can be much simpler,
and thus less likely to get wrong.
But even then, with your proposed changes, I don't think the device will
be properly idled (including the omap_device_idle) in these important cases:
1) I2C is used by some other device *after* its ->suspend method has
been called.
2) I2C runtime PM is disabled from userspace
(echo off > /sys/devices/.../power/control)
but I'll take this up in the I2C driver patch itself.
> Note also, that you could runtime resume devices which don't implement
> resume_noirq().
Again, this is by design.
It doesn't matter if the driver has noirq methods. If it is not yet
runtime suspended, it is forceably runtime suspended. The generic
noirq calls are just there in case the driver has noirq callbacks.
Kevin
> the same is valid for suspend_noirq.
>
>> }
>>
>> return pm_generic_resume_noirq(dev);
>> }
^ permalink raw reply
* [PATCHv2] arm:socfpga: Enable SMP for socfpga
From: dinguyen at altera.com @ 2012-10-18 17:32 UTC (permalink / raw)
To: linux-arm-kernel
From: Dinh Nguyen <dinguyen@altera.com>
Enable SMP for the SOCFPGA platform.
Signed-off-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
---
v2:
-Remove pen_release code
-Remove code that was already done by v7_setup
-Add bindings document for reset and system manager
-Move socfpga_sysmgr_init from platsmp.c to socfpga.c, because
we will need to use the reset and system manager for more than SMP.
-Move core.h to mach-socfpga from mach-socfpga/include/mach
---
.../bindings/arm/altera/socfpga-reset.txt | 11 ++
.../bindings/arm/altera/socfpga-system.txt | 11 ++
arch/arm/boot/dts/socfpga.dtsi | 10 ++
arch/arm/configs/socfpga_defconfig | 9 +-
arch/arm/mach-socfpga/Kconfig | 1 +
arch/arm/mach-socfpga/Makefile | 1 +
arch/arm/mach-socfpga/core.h | 34 ++++++
arch/arm/mach-socfpga/headsmp.S | 24 ++++
arch/arm/mach-socfpga/platsmp.c | 117 ++++++++++++++++++++
arch/arm/mach-socfpga/socfpga.c | 45 +++++++-
10 files changed, 259 insertions(+), 4 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/altera/socfpga-reset.txt
create mode 100644 Documentation/devicetree/bindings/arm/altera/socfpga-system.txt
create mode 100644 arch/arm/mach-socfpga/core.h
create mode 100644 arch/arm/mach-socfpga/headsmp.S
create mode 100644 arch/arm/mach-socfpga/platsmp.c
diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-reset.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-reset.txt
new file mode 100644
index 0000000..ecdb57d
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-reset.txt
@@ -0,0 +1,11 @@
+Altera SOCFPGA Reset Manager
+
+Required properties:
+- compatible : "altr,rst-mgr"
+- reg : Should contain 1 register ranges(address and length)
+
+Example:
+ rstmgr at ffd05000 {
+ compatible = "altr,rst-mgr";
+ reg = <0xffd05000 0x1000>;
+ };
diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-system.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-system.txt
new file mode 100644
index 0000000..07c65e3
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-system.txt
@@ -0,0 +1,11 @@
+Altera SOCFPGA System Manager
+
+Required properties:
+- compatible : "altr,sys-mgr"
+- reg : Should contain 1 register ranges(address and length)
+
+Example:
+ sysmgr at ffd08000 {
+ compatible = "altr,sys-mgr";
+ reg = <0xffd08000 0x1000>;
+ };
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 0772f57..19aec42 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -143,5 +143,15 @@
reg-shift = <2>;
reg-io-width = <4>;
};
+
+ rstmgr at ffd05000 {
+ compatible = "altr,rst-mgr";
+ reg = <0xffd05000 0x1000>;
+ };
+
+ sysmgr at ffd08000 {
+ compatible = "altr,sys-mgr";
+ reg = <0xffd08000 0x4000>;
+ };
};
};
diff --git a/arch/arm/configs/socfpga_defconfig b/arch/arm/configs/socfpga_defconfig
index 0ac1293..349ac22 100644
--- a/arch/arm/configs/socfpga_defconfig
+++ b/arch/arm/configs/socfpga_defconfig
@@ -1,5 +1,5 @@
CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
+CONFIG_NO_HZ=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
@@ -16,10 +16,13 @@ CONFIG_MODULE_UNLOAD=y
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_SOCFPGA=y
-CONFIG_MACH_SOCFPGA_CYCLONE5=y
-CONFIG_ARM_THUMBEE=y
+# CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA is not set
# CONFIG_CACHE_L2X0 is not set
CONFIG_HIGH_RES_TIMERS=y
+CONFIG_SMP=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_HIGHMEM=y
+CONFIG_HIGHPTE=y
CONFIG_VMSPLIT_2G=y
CONFIG_NR_CPUS=2
CONFIG_AEABI=y
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 803a328..566e804 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -12,5 +12,6 @@ config ARCH_SOCFPGA
select GENERIC_CLOCKEVENTS
select GPIO_PL061 if GPIOLIB
select HAVE_ARM_SCU
+ select HAVE_SMP
select SPARSE_IRQ
select USE_OF
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 4fb9324..6dd7a93 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -3,3 +3,4 @@
#
obj-y := socfpga.o
+obj-$(CONFIG_SMP) += headsmp.o platsmp.o
diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h
new file mode 100644
index 0000000..9941caa
--- /dev/null
+++ b/arch/arm/mach-socfpga/core.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2012 Pavel Machek <pavel@denx.de>
+ * Copyright (C) 2012 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __MACH_CORE_H
+#define __MACH_CORE_H
+
+extern void secondary_startup(void);
+extern void __iomem *socfpga_scu_base_addr;
+
+extern void socfpga_init_clocks(void);
+extern void socfpga_sysmgr_init(void);
+
+extern struct smp_operations socfpga_smp_ops;
+extern char secondary_trampoline, secondary_trampoline_end;
+
+#define SOCFPGA_SCU_VIRT_BASE 0xfffec000
+
+#endif
diff --git a/arch/arm/mach-socfpga/headsmp.S b/arch/arm/mach-socfpga/headsmp.S
new file mode 100644
index 0000000..17d6eaf
--- /dev/null
+++ b/arch/arm/mach-socfpga/headsmp.S
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2003 ARM Limited
+ * Copyright (c) u-boot contributors
+ * Copyright (c) 2012 Pavel Machek <pavel@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+ __INIT
+
+#define CPU1_START_ADDR 0xffd08010
+
+ENTRY(secondary_trampoline)
+ movw r0, #:lower16:CPU1_START_ADDR
+ movt r0, #:upper16:CPU1_START_ADDR
+
+ ldr r1, [r0]
+ bx r1
+
+ENTRY(secondary_trampoline_end)
diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c
new file mode 100644
index 0000000..7fce9a3
--- /dev/null
+++ b/arch/arm/mach-socfpga/platsmp.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright 2010-2011 Calxeda, Inc.
+ * Copyright 2012 Pavel Machek <pavel@denx.de>
+ * Based on platsmp.c, Copyright (C) 2002 ARM Ltd.
+ * Copyright (C) 2012 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/smp.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#include <asm/cacheflush.h>
+#include <asm/hardware/gic.h>
+#include <asm/smp_scu.h>
+#include <asm/smp_plat.h>
+
+#include "core.h"
+
+extern void __iomem *sys_manager_base_addr;
+extern void __iomem *rst_manager_base_addr;
+
+static void __cpuinit socfpga_secondary_init(unsigned int cpu)
+{
+ /*
+ * if any interrupts are already enabled for the primary
+ * core (e.g. timer irq), then they will not have been enabled
+ * for us: do so
+ */
+ gic_secondary_init(0);
+}
+
+static int __cpuinit socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+ int trampoline_size = &secondary_trampoline_end - &secondary_trampoline;
+
+ memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
+
+ __raw_writel(virt_to_phys(secondary_startup), (sys_manager_base_addr+0x10));
+
+ pen_release = 0;
+ flush_cache_all();
+ smp_wmb();
+ outer_clean_range(0, trampoline_size);
+
+ /* This will release CPU #1 out of reset.*/
+ __raw_writel(0, rst_manager_base_addr + 0x10);
+
+ return 0;
+}
+
+/*
+ * Initialise the CPU possible map early - this describes the CPUs
+ * which may be present or become present in the system.
+ */
+static void __init socfpga_smp_init_cpus(void)
+{
+ unsigned int i, ncores;
+
+ ncores = scu_get_core_count(socfpga_scu_base_addr);
+
+ for (i = 0; i < ncores; i++)
+ set_cpu_possible(i, true);
+
+ /* sanity check */
+ if (ncores > num_possible_cpus()) {
+ pr_warn("socfpga: no. of cores (%d) greater than configured"
+ "maximum of %d - clipping\n", ncores, num_possible_cpus());
+ ncores = num_possible_cpus();
+ }
+
+ for (i = 0; i < ncores; i++)
+ set_cpu_possible(i, true);
+
+ set_smp_cross_call(gic_raise_softirq);
+}
+
+static void __init socfpga_smp_prepare_cpus(unsigned int max_cpus)
+{
+ scu_enable(socfpga_scu_base_addr);
+}
+
+/*
+ * platform-specific code to shutdown a CPU
+ *
+ * Called with IRQs disabled
+ */
+static void socfpga_cpu_die(unsigned int cpu)
+{
+ cpu_do_idle();
+
+ /* We should have never returned from idle */
+ panic("cpu %d unexpectedly exit from shutdown\n", cpu);
+}
+
+struct smp_operations socfpga_smp_ops __initdata = {
+ .smp_init_cpus = socfpga_smp_init_cpus,
+ .smp_prepare_cpus = socfpga_smp_prepare_cpus,
+ .smp_secondary_init = socfpga_secondary_init,
+ .smp_boot_secondary = socfpga_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+ .cpu_die = socfpga_cpu_die,
+#endif
+};
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index f01e1eb..ab81ea9 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -15,23 +15,64 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <linux/dw_apb_timer.h>
+#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/hardware/gic.h>
#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
-extern void socfpga_init_clocks(void);
+#include "core.h"
+
+void __iomem *socfpga_scu_base_addr = ((void __iomem *)(SOCFPGA_SCU_VIRT_BASE));
+void __iomem *sys_manager_base_addr;
+void __iomem *rst_manager_base_addr;
+
+static struct map_desc scu_io_desc __initdata = {
+ .virtual = SOCFPGA_SCU_VIRT_BASE,
+ .pfn = 0, /* run-time */
+ .length = SZ_8K,
+ .type = MT_DEVICE,
+};
+
+static void __init socfpga_scu_map_io(void)
+{
+ unsigned long base;
+
+ /* Get SCU base */
+ asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
+
+ scu_io_desc.pfn = __phys_to_pfn(base);
+ iotable_init(&scu_io_desc, 1);
+}
+
+static void __init socfpga_map_io(void)
+{
+ socfpga_scu_map_io();
+}
const static struct of_device_id irq_match[] = {
{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
{}
};
+void __init socfpga_sysmgr_init(void)
+{
+ struct device_node *np;
+
+ np = of_find_compatible_node(NULL, NULL, "altr,sys-mgr");
+ sys_manager_base_addr = of_iomap(np, 0);
+
+ np = of_find_compatible_node(NULL, NULL, "altr,rst-mgr");
+ rst_manager_base_addr = of_iomap(np, 0);
+}
+
static void __init gic_init_irq(void)
{
of_irq_init(irq_match);
+ socfpga_sysmgr_init();
}
static void socfpga_cyclone5_restart(char mode, const char *cmd)
@@ -53,6 +94,8 @@ static const char *altera_dt_match[] = {
};
DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA")
+ .smp = smp_ops(socfpga_smp_ops),
+ .map_io = socfpga_map_io,
.init_irq = gic_init_irq,
.handle_irq = gic_handle_irq,
.timer = &dw_apb_timer,
--
1.7.9.5
^ permalink raw reply related
* [RFC/NOT FOR MERGING 3/5] arm: omap: introduce other PM methods
From: Felipe Balbi @ 2012-10-18 17:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121018170640.GB6641@arwen.pp.htv.fi>
Hi,
On Thu, Oct 18, 2012 at 08:06:40PM +0300, Felipe Balbi wrote:
> Hi,
>
> On Thu, Oct 18, 2012 at 10:07:31AM -0700, Kevin Hilman wrote:
> > Felipe Balbi <balbi@ti.com> writes:
> >
> > > current omap_device PM implementation defines
> > > omap-specific *_noirq methods but uses the
> > > generic versions for all other PM methods.
> > >
> > > As it turns out, if a device decides to implement
> > > non-runtime PM callbacks, we might fall into a
> > > situation where the hwmod is still idled which
> > > will generate an abort exception when we try
> > > to access device's address space while clocks
> > > are still gated.
> >
> > Please explain in more detail how this could happen.
>
> just follow the patchset. If I implement system suspend and I'm not
> focefully calling runtime_* methods, who will be there to call
> omap_device_enable() ?
let me rephrase this. If we exit _noirq right in the beginning with the
extra check I've added, who will call omap_device_enable() ?
--
balbi
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^ permalink raw reply
* [PATCH 8/8] ARM: plat-nomadik: convert platforms to SPARSE_IRQ
From: Linus Walleij @ 2012-10-18 17:19 UTC (permalink / raw)
To: linux-arm-kernel
From: Linus Walleij <linus.walleij@linaro.org>
This converts the Nomadik and Ux500 platforms to use SPARSE_IRQ.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/Kconfig | 2 ++
arch/arm/mach-nomadik/include/mach/irqs.h | 2 +-
arch/arm/mach-ux500/board-mop500.c | 1 -
arch/arm/mach-ux500/cpu-db8500.c | 1 +
arch/arm/mach-ux500/devices-common.c | 1 +
arch/arm/mach-ux500/devices-db8500.c | 1 +
arch/arm/mach-ux500/devices-db8500.h | 1 +
arch/arm/mach-ux500/include/mach/irqs.h | 2 +-
drivers/pinctrl/pinctrl-nomadik.c | 3 +--
9 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index c5f2c18..8d7fcd3 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -885,6 +885,7 @@ config ARCH_U8500
select GENERIC_CLOCKEVENTS
select HAVE_SMP
select MIGHT_HAVE_CACHE_L2X0
+ select SPARSE_IRQ
help
Support for ST-Ericsson's Ux500 architecture
@@ -899,6 +900,7 @@ config ARCH_NOMADIK
select MIGHT_HAVE_CACHE_L2X0
select PINCTRL
select PINCTRL_STN8815
+ select SPARSE_IRQ
help
Support for the Nomadik platform by ST-Ericsson
diff --git a/arch/arm/mach-nomadik/include/mach/irqs.h b/arch/arm/mach-nomadik/include/mach/irqs.h
index a118e61..b549d05 100644
--- a/arch/arm/mach-nomadik/include/mach/irqs.h
+++ b/arch/arm/mach-nomadik/include/mach/irqs.h
@@ -72,7 +72,7 @@
#define NOMADIK_NR_GPIO 128 /* last 4 not wired to pins */
#define NOMADIK_GPIO_TO_IRQ(gpio) ((gpio) + NOMADIK_GPIO_OFFSET)
#define NOMADIK_IRQ_TO_GPIO(irq) ((irq) - NOMADIK_GPIO_OFFSET)
-#define NR_IRQS NOMADIK_GPIO_TO_IRQ(NOMADIK_NR_GPIO)
+#define NOMADIK_NR_IRQS NOMADIK_GPIO_TO_IRQ(NOMADIK_NR_GPIO)
/* Following two are used by entry_macro.S, to access our dual-vic */
#define VIC_REG_IRQSR0 0
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 0213e89..9268056 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -1,4 +1,3 @@
-
/*
* Copyright (C) 2008-2009 ST-Ericsson
*
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 87a8f9f..8bff078 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -26,6 +26,7 @@
#include <mach/setup.h>
#include <mach/devices.h>
#include <mach/db8500-regs.h>
+#include <mach/irqs.h>
#include "devices-db8500.h"
#include "ste-dma40-db8500.h"
diff --git a/arch/arm/mach-ux500/devices-common.c b/arch/arm/mach-ux500/devices-common.c
index 692a77a..16b5f71 100644
--- a/arch/arm/mach-ux500/devices-common.c
+++ b/arch/arm/mach-ux500/devices-common.c
@@ -14,6 +14,7 @@
#include <linux/platform_data/pinctrl-nomadik.h>
#include <mach/hardware.h>
+#include <mach/irqs.h>
#include "devices-common.h"
diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c
index bdc963c..318d490 100644
--- a/arch/arm/mach-ux500/devices-db8500.c
+++ b/arch/arm/mach-ux500/devices-db8500.c
@@ -16,6 +16,7 @@
#include <mach/hardware.h>
#include <mach/setup.h>
+#include <mach/irqs.h>
#include "ste-dma40-db8500.h"
diff --git a/arch/arm/mach-ux500/devices-db8500.h b/arch/arm/mach-ux500/devices-db8500.h
index 3c8010f..4b24c99 100644
--- a/arch/arm/mach-ux500/devices-db8500.h
+++ b/arch/arm/mach-ux500/devices-db8500.h
@@ -8,6 +8,7 @@
#ifndef __DEVICES_DB8500_H
#define __DEVICES_DB8500_H
+#include <mach/irqs.h>
#include "devices-common.h"
struct ske_keypad_platform_data;
diff --git a/arch/arm/mach-ux500/include/mach/irqs.h b/arch/arm/mach-ux500/include/mach/irqs.h
index e892854..fc77b42 100644
--- a/arch/arm/mach-ux500/include/mach/irqs.h
+++ b/arch/arm/mach-ux500/include/mach/irqs.h
@@ -46,6 +46,6 @@
#include <mach/irqs-board-mop500.h>
#endif
-#define NR_IRQS IRQ_BOARD_END
+#define UX500_NR_IRQS IRQ_BOARD_END
#endif /* ASM_ARCH_IRQS_H */
diff --git a/drivers/pinctrl/pinctrl-nomadik.c b/drivers/pinctrl/pinctrl-nomadik.c
index 0a712c2..abf9dea 100644
--- a/drivers/pinctrl/pinctrl-nomadik.c
+++ b/drivers/pinctrl/pinctrl-nomadik.c
@@ -32,9 +32,8 @@
#include <linux/pinctrl/consumer.h>
#include <linux/mfd/dbx500-prcmu.h>
#include <linux/platform_data/pinctrl-nomadik.h>
-
#include <asm/mach/irq.h>
-
+#include <mach/irqs.h>
#include "pinctrl-nomadik.h"
/*
--
1.7.11.3
^ permalink raw reply related
* [PATCH 7/8] mfd/db8500-prcmu: use the irq_domain_add_simple()
From: Linus Walleij @ 2012-10-18 17:19 UTC (permalink / raw)
To: linux-arm-kernel
From: Linus Walleij <linus.walleij@linaro.org>
To be able to use SPARSE_IRQ while yet not using device tree,
we need to use irq_domain_add_simple() that will allocate
descriptors for the IRQs in the non-DT case, and fall back
to using the linear irqdomain in the DT case.
Cc: Lee Jones <lee.jones@linaro.org>
Cc: Samuel Ortiz <sameo@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
Sam, requesting you ACK on this patch so we can merge them
all together.
Lee, requesting your testing with Device Tree to see that this
actually can fly as I wanted it.
---
drivers/mfd/db8500-prcmu.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/mfd/db8500-prcmu.c b/drivers/mfd/db8500-prcmu.c
index 00b8b0f..cea29ba 100644
--- a/drivers/mfd/db8500-prcmu.c
+++ b/drivers/mfd/db8500-prcmu.c
@@ -2697,9 +2697,15 @@ static struct irq_domain_ops db8500_irq_ops = {
static int db8500_irq_init(struct device_node *np)
{
- db8500_irq_domain = irq_domain_add_legacy(
- np, NUM_PRCMU_WAKEUPS, IRQ_PRCMU_BASE,
- 0, &db8500_irq_ops, NULL);
+ int irq_base = -1;
+
+ /* In the device tree case, just take some IRQs */
+ if (!np)
+ irq_base = IRQ_PRCMU_BASE;
+
+ db8500_irq_domain = irq_domain_add_simple(
+ np, NUM_PRCMU_WAKEUPS, irq_base,
+ &db8500_irq_ops, NULL);
if (!db8500_irq_domain) {
pr_err("Failed to create irqdomain\n");
--
1.7.11.3
^ permalink raw reply related
* [PATCH 6/8] mfd/ab8500-core: use irq_domain_add_simple()
From: Linus Walleij @ 2012-10-18 17:19 UTC (permalink / raw)
To: linux-arm-kernel
From: Linus Walleij <linus.walleij@linaro.org>
To be able to use SPARSE_IRQ while yet not using device tree,
we need to use irq_domain_add_simple() that will allocate
descriptors for the IRQs in the non-DT case, and fall back
to using the linear irqdomain in the DT case.
Cc: Lee Jones <lee.jones@linaro.org>
Cc: Samuel Ortiz <sameo@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
Sam, requesting you ACK on this patch so we can merge them
all together.
Lee, requesting your testing with Device Tree to see that this
actually can fly as I wanted it.
---
drivers/mfd/ab8500-core.c | 13 ++++---------
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/drivers/mfd/ab8500-core.c b/drivers/mfd/ab8500-core.c
index 1667c77..547fff4 100644
--- a/drivers/mfd/ab8500-core.c
+++ b/drivers/mfd/ab8500-core.c
@@ -565,15 +565,10 @@ static int ab8500_irq_init(struct ab8500 *ab8500, struct device_node *np)
else
num_irqs = AB8500_NR_IRQS;
- if (ab8500->irq_base) {
- ab8500->domain = irq_domain_add_legacy(
- NULL, num_irqs, ab8500->irq_base,
- 0, &ab8500_irq_ops, ab8500);
- }
- else {
- ab8500->domain = irq_domain_add_linear(
- np, num_irqs, &ab8500_irq_ops, ab8500);
- }
+ /* If ->irq_base is zero this will give a linear mapping */
+ ab8500->domain = irq_domain_add_simple(NULL,
+ num_irqs, ab8500->irq_base,
+ &ab8500_irq_ops, ab8500);
if (!ab8500->domain) {
dev_err(ab8500->dev, "Failed to create irqdomain\n");
--
1.7.11.3
^ permalink raw reply related
* [PATCH 5/8] ARM: plat-nomadik: move MTU, kill plat-nomadik
From: Linus Walleij @ 2012-10-18 17:19 UTC (permalink / raw)
To: linux-arm-kernel
From: Linus Walleij <linus.walleij@linaro.org>
This moves the MTU timer driver from arch/arm/plat-nomadik
to drivers/clocksource and moves the header file to the
platform_data directory.
As this moves the last file being compiled to an object out
of arch/arm/plat-nomadik, we have to "turn off the light"
and delete the plat-nomadik directory, because it is not
allowed to have an empty Makefile in a plat-* directory.
This is probably also a desired side effect of depopulating
the arch/arm directory of drivers. Luckily we have just
deleted all the <plat/*> include files prior to this so
by moving the last one we may delete the directory.
After this all the Ux500 and Nomadik device drivers live
outside of the arch/arm hierarchy.
Cc: Alessandro Rubini <rubini@unipv.it>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/Kconfig | 1 -
arch/arm/Makefile | 1 -
arch/arm/mach-nomadik/Kconfig | 2 +-
arch/arm/mach-nomadik/board-nhk8815.c | 6 +-
arch/arm/mach-ux500/Kconfig | 2 +-
arch/arm/mach-ux500/timer.c | 3 +-
arch/arm/plat-nomadik/Kconfig | 29 ---
arch/arm/plat-nomadik/Makefile | 5 -
arch/arm/plat-nomadik/include/plat/mtu.h | 9 -
arch/arm/plat-nomadik/timer.c | 224 ---------------------
drivers/char/hw_random/Kconfig | 2 +-
drivers/clocksource/Kconfig | 17 +-
drivers/clocksource/Makefile | 1 +
drivers/clocksource/nomadik-mtu.c | 224 +++++++++++++++++++++
drivers/input/keyboard/Kconfig | 2 +-
drivers/mtd/nand/Kconfig | 2 +-
.../linux/platform_data/clocksource-nomadik-mtu.h | 9 +
17 files changed, 258 insertions(+), 281 deletions(-)
delete mode 100644 arch/arm/plat-nomadik/Kconfig
delete mode 100644 arch/arm/plat-nomadik/Makefile
delete mode 100644 arch/arm/plat-nomadik/include/plat/mtu.h
delete mode 100644 arch/arm/plat-nomadik/timer.c
create mode 100644 drivers/clocksource/nomadik-mtu.c
create mode 100644 include/linux/platform_data/clocksource-nomadik-mtu.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 73067ef..c5f2c18 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1065,7 +1065,6 @@ source "arch/arm/mach-mxs/Kconfig"
source "arch/arm/mach-netx/Kconfig"
source "arch/arm/mach-nomadik/Kconfig"
-source "arch/arm/plat-nomadik/Kconfig"
source "arch/arm/plat-omap/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index f023e3a..ed6a304 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -200,7 +200,6 @@ plat-$(CONFIG_ARCH_OMAP) += omap
plat-$(CONFIG_ARCH_S3C64XX) += samsung
plat-$(CONFIG_ARCH_ZYNQ) += versatile
plat-$(CONFIG_PLAT_IOP) += iop
-plat-$(CONFIG_PLAT_NOMADIK) += nomadik
plat-$(CONFIG_PLAT_ORION) += orion
plat-$(CONFIG_PLAT_PXA) += pxa
plat-$(CONFIG_PLAT_S3C24XX) += s3c24xx samsung
diff --git a/arch/arm/mach-nomadik/Kconfig b/arch/arm/mach-nomadik/Kconfig
index c744946..706dc57 100644
--- a/arch/arm/mach-nomadik/Kconfig
+++ b/arch/arm/mach-nomadik/Kconfig
@@ -4,7 +4,7 @@ menu "Nomadik boards"
config MACH_NOMADIK_8815NHK
bool "ST 8815 Nomadik Hardware Kit (evaluation board)"
- select HAS_MTU
+ select CLKSRC_NOMADIK_MTU
select NOMADIK_8815
endmenu
diff --git a/arch/arm/mach-nomadik/board-nhk8815.c b/arch/arm/mach-nomadik/board-nhk8815.c
index 16f10e0..5ccdf53 100644
--- a/arch/arm/mach-nomadik/board-nhk8815.c
+++ b/arch/arm/mach-nomadik/board-nhk8815.c
@@ -25,16 +25,14 @@
#include <linux/io.h>
#include <linux/pinctrl/machine.h>
#include <linux/platform_data/pinctrl-nomadik.h>
+#include <linux/platform_data/clocksource-nomadik-mtu.h>
+#include <linux/platform_data/mtd-nomadik-nand.h>
#include <asm/hardware/vic.h>
#include <asm/sizes.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include <asm/mach/time.h>
-
-#include <plat/mtu.h>
-
-#include <linux/platform_data/mtd-nomadik-nand.h>
#include <mach/fsmc.h>
#include <mach/irqs.h>
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index e8c3f0d..5dea906 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -7,8 +7,8 @@ config UX500_SOC_COMMON
select ARM_ERRATA_764369 if SMP
select ARM_GIC
select CACHE_L2X0
+ select CLKSRC_NOMADIK_MTU
select COMMON_CLK
- select HAS_MTU
select PINCTRL
select PINCTRL_NOMADIK
select PL310_ERRATA_753970 if CACHE_PL310
diff --git a/arch/arm/mach-ux500/timer.c b/arch/arm/mach-ux500/timer.c
index 20d02fa..875309a 100644
--- a/arch/arm/mach-ux500/timer.c
+++ b/arch/arm/mach-ux500/timer.c
@@ -9,11 +9,10 @@
#include <linux/clksrc-dbx500-prcmu.h>
#include <linux/of.h>
#include <linux/of_address.h>
+#include <linux/platform_data/clocksource-nomadik-mtu.h>
#include <asm/smp_twd.h>
-#include <plat/mtu.h>
-
#include <mach/setup.h>
#include <mach/hardware.h>
#include <mach/irqs.h>
diff --git a/arch/arm/plat-nomadik/Kconfig b/arch/arm/plat-nomadik/Kconfig
deleted file mode 100644
index 19f55ca..0000000
--- a/arch/arm/plat-nomadik/Kconfig
+++ /dev/null
@@ -1,29 +0,0 @@
-# We keep common IP's here for Nomadik and other similar
-# familiy of processors from ST-Ericsson. At the moment we have
-# just MTU, others to follow soon.
-
-config PLAT_NOMADIK
- bool
- depends on ARCH_NOMADIK || ARCH_U8500
- default y
- select CLKSRC_MMIO
- help
- Common platform code for Nomadik and other ST-Ericsson
- platforms.
-
-if PLAT_NOMADIK
-
-config HAS_MTU
- bool
- help
- Support for Multi Timer Unit. MTU provides access
- to multiple interrupt generating programmable
- 32-bit free running decrementing counters.
-
-config NOMADIK_MTU_SCHED_CLOCK
- bool
- depends on HAS_MTU
- help
- Use the Multi Timer Unit as the sched_clock.
-
-endif
diff --git a/arch/arm/plat-nomadik/Makefile b/arch/arm/plat-nomadik/Makefile
deleted file mode 100644
index 37c7cdd..0000000
--- a/arch/arm/plat-nomadik/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-# arch/arm/plat-nomadik/Makefile
-# Copyright 2009 ST-Ericsson
-# Licensed under GPLv2
-
-obj-$(CONFIG_HAS_MTU) += timer.o
diff --git a/arch/arm/plat-nomadik/include/plat/mtu.h b/arch/arm/plat-nomadik/include/plat/mtu.h
deleted file mode 100644
index 8008897..0000000
--- a/arch/arm/plat-nomadik/include/plat/mtu.h
+++ /dev/null
@@ -1,9 +0,0 @@
-#ifndef __PLAT_MTU_H
-#define __PLAT_MTU_H
-
-void nmdk_timer_init(void __iomem *base, int irq);
-void nmdk_clkevt_reset(void);
-void nmdk_clksrc_reset(void);
-
-#endif /* __PLAT_MTU_H */
-
diff --git a/arch/arm/plat-nomadik/timer.c b/arch/arm/plat-nomadik/timer.c
deleted file mode 100644
index f911430..0000000
--- a/arch/arm/plat-nomadik/timer.c
+++ /dev/null
@@ -1,224 +0,0 @@
-/*
- * linux/arch/arm/plat-nomadik/timer.c
- *
- * Copyright (C) 2008 STMicroelectronics
- * Copyright (C) 2010 Alessandro Rubini
- * Copyright (C) 2010 Linus Walleij for ST-Ericsson
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2, as
- * published by the Free Software Foundation.
- */
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <linux/clockchips.h>
-#include <linux/clk.h>
-#include <linux/jiffies.h>
-#include <linux/err.h>
-#include <asm/mach/time.h>
-#include <asm/sched_clock.h>
-
-/*
- * The MTU device hosts four different counters, with 4 set of
- * registers. These are register names.
- */
-
-#define MTU_IMSC 0x00 /* Interrupt mask set/clear */
-#define MTU_RIS 0x04 /* Raw interrupt status */
-#define MTU_MIS 0x08 /* Masked interrupt status */
-#define MTU_ICR 0x0C /* Interrupt clear register */
-
-/* per-timer registers take 0..3 as argument */
-#define MTU_LR(x) (0x10 + 0x10 * (x) + 0x00) /* Load value */
-#define MTU_VAL(x) (0x10 + 0x10 * (x) + 0x04) /* Current value */
-#define MTU_CR(x) (0x10 + 0x10 * (x) + 0x08) /* Control reg */
-#define MTU_BGLR(x) (0x10 + 0x10 * (x) + 0x0c) /* At next overflow */
-
-/* bits for the control register */
-#define MTU_CRn_ENA 0x80
-#define MTU_CRn_PERIODIC 0x40 /* if 0 = free-running */
-#define MTU_CRn_PRESCALE_MASK 0x0c
-#define MTU_CRn_PRESCALE_1 0x00
-#define MTU_CRn_PRESCALE_16 0x04
-#define MTU_CRn_PRESCALE_256 0x08
-#define MTU_CRn_32BITS 0x02
-#define MTU_CRn_ONESHOT 0x01 /* if 0 = wraps reloading from BGLR*/
-
-/* Other registers are usual amba/primecell registers, currently not used */
-#define MTU_ITCR 0xff0
-#define MTU_ITOP 0xff4
-
-#define MTU_PERIPH_ID0 0xfe0
-#define MTU_PERIPH_ID1 0xfe4
-#define MTU_PERIPH_ID2 0xfe8
-#define MTU_PERIPH_ID3 0xfeC
-
-#define MTU_PCELL0 0xff0
-#define MTU_PCELL1 0xff4
-#define MTU_PCELL2 0xff8
-#define MTU_PCELL3 0xffC
-
-static void __iomem *mtu_base;
-static bool clkevt_periodic;
-static u32 clk_prescale;
-static u32 nmdk_cycle; /* write-once */
-
-#ifdef CONFIG_NOMADIK_MTU_SCHED_CLOCK
-/*
- * Override the global weak sched_clock symbol with this
- * local implementation which uses the clocksource to get some
- * better resolution when scheduling the kernel.
- */
-static u32 notrace nomadik_read_sched_clock(void)
-{
- if (unlikely(!mtu_base))
- return 0;
-
- return -readl(mtu_base + MTU_VAL(0));
-}
-#endif
-
-/* Clockevent device: use one-shot mode */
-static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev)
-{
- writel(1 << 1, mtu_base + MTU_IMSC);
- writel(evt, mtu_base + MTU_LR(1));
- /* Load highest value, enable device, enable interrupts */
- writel(MTU_CRn_ONESHOT | clk_prescale |
- MTU_CRn_32BITS | MTU_CRn_ENA,
- mtu_base + MTU_CR(1));
-
- return 0;
-}
-
-void nmdk_clkevt_reset(void)
-{
- if (clkevt_periodic) {
- /* Timer: configure load and background-load, and fire it up */
- writel(nmdk_cycle, mtu_base + MTU_LR(1));
- writel(nmdk_cycle, mtu_base + MTU_BGLR(1));
-
- writel(MTU_CRn_PERIODIC | clk_prescale |
- MTU_CRn_32BITS | MTU_CRn_ENA,
- mtu_base + MTU_CR(1));
- writel(1 << 1, mtu_base + MTU_IMSC);
- } else {
- /* Generate an interrupt to start the clockevent again */
- (void) nmdk_clkevt_next(nmdk_cycle, NULL);
- }
-}
-
-static void nmdk_clkevt_mode(enum clock_event_mode mode,
- struct clock_event_device *dev)
-{
- switch (mode) {
- case CLOCK_EVT_MODE_PERIODIC:
- clkevt_periodic = true;
- nmdk_clkevt_reset();
- break;
- case CLOCK_EVT_MODE_ONESHOT:
- clkevt_periodic = false;
- break;
- case CLOCK_EVT_MODE_SHUTDOWN:
- case CLOCK_EVT_MODE_UNUSED:
- writel(0, mtu_base + MTU_IMSC);
- /* disable timer */
- writel(0, mtu_base + MTU_CR(1));
- /* load some high default value */
- writel(0xffffffff, mtu_base + MTU_LR(1));
- break;
- case CLOCK_EVT_MODE_RESUME:
- break;
- }
-}
-
-static struct clock_event_device nmdk_clkevt = {
- .name = "mtu_1",
- .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
- .rating = 200,
- .set_mode = nmdk_clkevt_mode,
- .set_next_event = nmdk_clkevt_next,
-};
-
-/*
- * IRQ Handler for timer 1 of the MTU block.
- */
-static irqreturn_t nmdk_timer_interrupt(int irq, void *dev_id)
-{
- struct clock_event_device *evdev = dev_id;
-
- writel(1 << 1, mtu_base + MTU_ICR); /* Interrupt clear reg */
- evdev->event_handler(evdev);
- return IRQ_HANDLED;
-}
-
-static struct irqaction nmdk_timer_irq = {
- .name = "Nomadik Timer Tick",
- .flags = IRQF_DISABLED | IRQF_TIMER,
- .handler = nmdk_timer_interrupt,
- .dev_id = &nmdk_clkevt,
-};
-
-void nmdk_clksrc_reset(void)
-{
- /* Disable */
- writel(0, mtu_base + MTU_CR(0));
-
- /* ClockSource: configure load and background-load, and fire it up */
- writel(nmdk_cycle, mtu_base + MTU_LR(0));
- writel(nmdk_cycle, mtu_base + MTU_BGLR(0));
-
- writel(clk_prescale | MTU_CRn_32BITS | MTU_CRn_ENA,
- mtu_base + MTU_CR(0));
-}
-
-void __init nmdk_timer_init(void __iomem *base, int irq)
-{
- unsigned long rate;
- struct clk *clk0;
-
- mtu_base = base;
- clk0 = clk_get_sys("mtu0", NULL);
- BUG_ON(IS_ERR(clk0));
- BUG_ON(clk_prepare(clk0) < 0);
- BUG_ON(clk_enable(clk0) < 0);
-
- /*
- * Tick rate is 2.4MHz for Nomadik and 2.4Mhz, 100MHz or 133 MHz
- * for ux500.
- * Use a divide-by-16 counter if the tick rate is more than 32MHz.
- * At 32 MHz, the timer (with 32 bit counter) can be programmed
- * to wake-up@a max 127s a head in time. Dividing a 2.4 MHz timer
- * with 16 gives too low timer resolution.
- */
- rate = clk_get_rate(clk0);
- if (rate > 32000000) {
- rate /= 16;
- clk_prescale = MTU_CRn_PRESCALE_16;
- } else {
- clk_prescale = MTU_CRn_PRESCALE_1;
- }
-
- /* Cycles for periodic mode */
- nmdk_cycle = DIV_ROUND_CLOSEST(rate, HZ);
-
-
- /* Timer 0 is the free running clocksource */
- nmdk_clksrc_reset();
-
- if (clocksource_mmio_init(mtu_base + MTU_VAL(0), "mtu_0",
- rate, 200, 32, clocksource_mmio_readl_down))
- pr_err("timer: failed to initialize clock source %s\n",
- "mtu_0");
-
-#ifdef CONFIG_NOMADIK_MTU_SCHED_CLOCK
- setup_sched_clock(nomadik_read_sched_clock, 32, rate);
-#endif
-
- /* Timer 1 is used for events, register irq and clockevents */
- setup_irq(irq, &nmdk_timer_irq);
- nmdk_clkevt.cpumask = cpumask_of(0);
- clockevents_config_and_register(&nmdk_clkevt, rate, 2, 0xffffffffU);
-}
diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig
index fbd9b2b..5bc09ee 100644
--- a/drivers/char/hw_random/Kconfig
+++ b/drivers/char/hw_random/Kconfig
@@ -216,7 +216,7 @@ config HW_RANDOM_MXC_RNGA
config HW_RANDOM_NOMADIK
tristate "ST-Ericsson Nomadik Random Number Generator support"
- depends on HW_RANDOM && PLAT_NOMADIK
+ depends on HW_RANDOM && ARCH_NOMADIK
---help---
This driver provides kernel-side support for the Random Number
Generator hardware found on ST-Ericsson SoCs (8815 and 8500).
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 6a78073..c9f67de 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -22,6 +22,21 @@ config DW_APB_TIMER_OF
config ARMADA_370_XP_TIMER
bool
+config CLKSRC_NOMADIK_MTU
+ bool
+ depends on (ARCH_NOMADIK || ARCH_U8500)
+ select CLKSRC_MMIO
+ help
+ Support for Multi Timer Unit. MTU provides access
+ to multiple interrupt generating programmable
+ 32-bit free running decrementing counters.
+
+config CLKSRC_NOMADIK_MTU_SCHED_CLOCK
+ bool
+ depends on CLKSRC_NOMADIK_MTU
+ help
+ Use the Multi Timer Unit as the sched_clock.
+
config CLKSRC_DBX500_PRCMU
bool "Clocksource PRCMU Timer"
depends on UX500_SOC_DB8500
@@ -31,7 +46,7 @@ config CLKSRC_DBX500_PRCMU
config CLKSRC_DBX500_PRCMU_SCHED_CLOCK
bool "Clocksource PRCMU Timer sched_clock"
- depends on (CLKSRC_DBX500_PRCMU && !NOMADIK_MTU_SCHED_CLOCK)
+ depends on (CLKSRC_DBX500_PRCMU && !CLKSRC_NOMADIK_MTU_SCHED_CLOCK)
default y
help
Use the always on PRCMU Timer as sched_clock
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 603be36..24fb888 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_CLKBLD_I8253) += i8253.o
obj-$(CONFIG_CLKSRC_MMIO) += mmio.o
obj-$(CONFIG_DW_APB_TIMER) += dw_apb_timer.o
obj-$(CONFIG_DW_APB_TIMER_OF) += dw_apb_timer_of.o
+obj-$(CONFIG_CLKSRC_NOMADIK_MTU) += nomadik-mtu.o
obj-$(CONFIG_CLKSRC_DBX500_PRCMU) += clksrc-dbx500-prcmu.o
obj-$(CONFIG_ARMADA_370_XP_TIMER) += time-armada-370-xp.o
obj-$(CONFIG_ARCH_BCM2835) += bcm2835_timer.o
diff --git a/drivers/clocksource/nomadik-mtu.c b/drivers/clocksource/nomadik-mtu.c
new file mode 100644
index 0000000..23c780b
--- /dev/null
+++ b/drivers/clocksource/nomadik-mtu.c
@@ -0,0 +1,224 @@
+/*
+ * Copyright (C) 2008 STMicroelectronics
+ * Copyright (C) 2010 Alessandro Rubini
+ * Copyright (C) 2010 Linus Walleij for ST-Ericsson
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/clockchips.h>
+#include <linux/clocksource.h>
+#include <linux/clk.h>
+#include <linux/jiffies.h>
+#include <linux/err.h>
+#include <linux/platform_data/clocksource-nomadik-mtu.h>
+#include <asm/mach/time.h>
+#include <asm/sched_clock.h>
+
+/*
+ * The MTU device hosts four different counters, with 4 set of
+ * registers. These are register names.
+ */
+
+#define MTU_IMSC 0x00 /* Interrupt mask set/clear */
+#define MTU_RIS 0x04 /* Raw interrupt status */
+#define MTU_MIS 0x08 /* Masked interrupt status */
+#define MTU_ICR 0x0C /* Interrupt clear register */
+
+/* per-timer registers take 0..3 as argument */
+#define MTU_LR(x) (0x10 + 0x10 * (x) + 0x00) /* Load value */
+#define MTU_VAL(x) (0x10 + 0x10 * (x) + 0x04) /* Current value */
+#define MTU_CR(x) (0x10 + 0x10 * (x) + 0x08) /* Control reg */
+#define MTU_BGLR(x) (0x10 + 0x10 * (x) + 0x0c) /* At next overflow */
+
+/* bits for the control register */
+#define MTU_CRn_ENA 0x80
+#define MTU_CRn_PERIODIC 0x40 /* if 0 = free-running */
+#define MTU_CRn_PRESCALE_MASK 0x0c
+#define MTU_CRn_PRESCALE_1 0x00
+#define MTU_CRn_PRESCALE_16 0x04
+#define MTU_CRn_PRESCALE_256 0x08
+#define MTU_CRn_32BITS 0x02
+#define MTU_CRn_ONESHOT 0x01 /* if 0 = wraps reloading from BGLR*/
+
+/* Other registers are usual amba/primecell registers, currently not used */
+#define MTU_ITCR 0xff0
+#define MTU_ITOP 0xff4
+
+#define MTU_PERIPH_ID0 0xfe0
+#define MTU_PERIPH_ID1 0xfe4
+#define MTU_PERIPH_ID2 0xfe8
+#define MTU_PERIPH_ID3 0xfeC
+
+#define MTU_PCELL0 0xff0
+#define MTU_PCELL1 0xff4
+#define MTU_PCELL2 0xff8
+#define MTU_PCELL3 0xffC
+
+static void __iomem *mtu_base;
+static bool clkevt_periodic;
+static u32 clk_prescale;
+static u32 nmdk_cycle; /* write-once */
+
+#ifdef CONFIG_NOMADIK_MTU_SCHED_CLOCK
+/*
+ * Override the global weak sched_clock symbol with this
+ * local implementation which uses the clocksource to get some
+ * better resolution when scheduling the kernel.
+ */
+static u32 notrace nomadik_read_sched_clock(void)
+{
+ if (unlikely(!mtu_base))
+ return 0;
+
+ return -readl(mtu_base + MTU_VAL(0));
+}
+#endif
+
+/* Clockevent device: use one-shot mode */
+static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev)
+{
+ writel(1 << 1, mtu_base + MTU_IMSC);
+ writel(evt, mtu_base + MTU_LR(1));
+ /* Load highest value, enable device, enable interrupts */
+ writel(MTU_CRn_ONESHOT | clk_prescale |
+ MTU_CRn_32BITS | MTU_CRn_ENA,
+ mtu_base + MTU_CR(1));
+
+ return 0;
+}
+
+void nmdk_clkevt_reset(void)
+{
+ if (clkevt_periodic) {
+ /* Timer: configure load and background-load, and fire it up */
+ writel(nmdk_cycle, mtu_base + MTU_LR(1));
+ writel(nmdk_cycle, mtu_base + MTU_BGLR(1));
+
+ writel(MTU_CRn_PERIODIC | clk_prescale |
+ MTU_CRn_32BITS | MTU_CRn_ENA,
+ mtu_base + MTU_CR(1));
+ writel(1 << 1, mtu_base + MTU_IMSC);
+ } else {
+ /* Generate an interrupt to start the clockevent again */
+ (void) nmdk_clkevt_next(nmdk_cycle, NULL);
+ }
+}
+
+static void nmdk_clkevt_mode(enum clock_event_mode mode,
+ struct clock_event_device *dev)
+{
+ switch (mode) {
+ case CLOCK_EVT_MODE_PERIODIC:
+ clkevt_periodic = true;
+ nmdk_clkevt_reset();
+ break;
+ case CLOCK_EVT_MODE_ONESHOT:
+ clkevt_periodic = false;
+ break;
+ case CLOCK_EVT_MODE_SHUTDOWN:
+ case CLOCK_EVT_MODE_UNUSED:
+ writel(0, mtu_base + MTU_IMSC);
+ /* disable timer */
+ writel(0, mtu_base + MTU_CR(1));
+ /* load some high default value */
+ writel(0xffffffff, mtu_base + MTU_LR(1));
+ break;
+ case CLOCK_EVT_MODE_RESUME:
+ break;
+ }
+}
+
+static struct clock_event_device nmdk_clkevt = {
+ .name = "mtu_1",
+ .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
+ .rating = 200,
+ .set_mode = nmdk_clkevt_mode,
+ .set_next_event = nmdk_clkevt_next,
+};
+
+/*
+ * IRQ Handler for timer 1 of the MTU block.
+ */
+static irqreturn_t nmdk_timer_interrupt(int irq, void *dev_id)
+{
+ struct clock_event_device *evdev = dev_id;
+
+ writel(1 << 1, mtu_base + MTU_ICR); /* Interrupt clear reg */
+ evdev->event_handler(evdev);
+ return IRQ_HANDLED;
+}
+
+static struct irqaction nmdk_timer_irq = {
+ .name = "Nomadik Timer Tick",
+ .flags = IRQF_DISABLED | IRQF_TIMER,
+ .handler = nmdk_timer_interrupt,
+ .dev_id = &nmdk_clkevt,
+};
+
+void nmdk_clksrc_reset(void)
+{
+ /* Disable */
+ writel(0, mtu_base + MTU_CR(0));
+
+ /* ClockSource: configure load and background-load, and fire it up */
+ writel(nmdk_cycle, mtu_base + MTU_LR(0));
+ writel(nmdk_cycle, mtu_base + MTU_BGLR(0));
+
+ writel(clk_prescale | MTU_CRn_32BITS | MTU_CRn_ENA,
+ mtu_base + MTU_CR(0));
+}
+
+void __init nmdk_timer_init(void __iomem *base, int irq)
+{
+ unsigned long rate;
+ struct clk *clk0;
+
+ mtu_base = base;
+ clk0 = clk_get_sys("mtu0", NULL);
+ BUG_ON(IS_ERR(clk0));
+ BUG_ON(clk_prepare(clk0) < 0);
+ BUG_ON(clk_enable(clk0) < 0);
+
+ /*
+ * Tick rate is 2.4MHz for Nomadik and 2.4Mhz, 100MHz or 133 MHz
+ * for ux500.
+ * Use a divide-by-16 counter if the tick rate is more than 32MHz.
+ * At 32 MHz, the timer (with 32 bit counter) can be programmed
+ * to wake-up@a max 127s a head in time. Dividing a 2.4 MHz timer
+ * with 16 gives too low timer resolution.
+ */
+ rate = clk_get_rate(clk0);
+ if (rate > 32000000) {
+ rate /= 16;
+ clk_prescale = MTU_CRn_PRESCALE_16;
+ } else {
+ clk_prescale = MTU_CRn_PRESCALE_1;
+ }
+
+ /* Cycles for periodic mode */
+ nmdk_cycle = DIV_ROUND_CLOSEST(rate, HZ);
+
+
+ /* Timer 0 is the free running clocksource */
+ nmdk_clksrc_reset();
+
+ if (clocksource_mmio_init(mtu_base + MTU_VAL(0), "mtu_0",
+ rate, 200, 32, clocksource_mmio_readl_down))
+ pr_err("timer: failed to initialize clock source %s\n",
+ "mtu_0");
+
+#ifdef CONFIG_NOMADIK_MTU_SCHED_CLOCK
+ setup_sched_clock(nomadik_read_sched_clock, 32, rate);
+#endif
+
+ /* Timer 1 is used for events, register irq and clockevents */
+ setup_irq(irq, &nmdk_timer_irq);
+ nmdk_clkevt.cpumask = cpumask_of(0);
+ clockevents_config_and_register(&nmdk_clkevt, rate, 2, 0xffffffffU);
+}
diff --git a/drivers/input/keyboard/Kconfig b/drivers/input/keyboard/Kconfig
index b4b65af..855fc52 100644
--- a/drivers/input/keyboard/Kconfig
+++ b/drivers/input/keyboard/Kconfig
@@ -408,7 +408,7 @@ config KEYBOARD_NEWTON
config KEYBOARD_NOMADIK
tristate "ST-Ericsson Nomadik SKE keyboard"
- depends on PLAT_NOMADIK
+ depends on (ARCH_NOMADIK || ARCH_U8500)
select INPUT_MATRIXKMAP
help
Say Y here if you want to use a keypad provided on the SKE controller
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 4883139..e4f5748 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -559,7 +559,7 @@ config MTD_NAND_JZ4740
config MTD_NAND_FSMC
tristate "Support for NAND on ST Micros FSMC"
- depends on PLAT_SPEAR || PLAT_NOMADIK || MACH_U300
+ depends on PLAT_SPEAR || ARCH_NOMADIK || ARCH_U8500 || MACH_U300
help
Enables support for NAND Flash chips on the ST Microelectronics
Flexible Static Memory Controller (FSMC)
diff --git a/include/linux/platform_data/clocksource-nomadik-mtu.h b/include/linux/platform_data/clocksource-nomadik-mtu.h
new file mode 100644
index 0000000..8008897
--- /dev/null
+++ b/include/linux/platform_data/clocksource-nomadik-mtu.h
@@ -0,0 +1,9 @@
+#ifndef __PLAT_MTU_H
+#define __PLAT_MTU_H
+
+void nmdk_timer_init(void __iomem *base, int irq);
+void nmdk_clkevt_reset(void);
+void nmdk_clksrc_reset(void);
+
+#endif /* __PLAT_MTU_H */
+
--
1.7.11.3
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