* [PATCHv4 1/2] i2c: omap: re-factor omap_i2c_init function
From: Felipe Balbi @ 2012-10-29 19:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351176199-6479-2-git-send-email-shubhrajyoti@ti.com>
On Thu, Oct 25, 2012 at 08:13:18PM +0530, Shubhrajyoti D wrote:
> re-factor omap_i2c_init() so that we can re-use it for resume.
> While at it also remove the bufstate variable as we write it
> in omap_i2c_resize_fifo for every transfer.
>
> Signed-off-by: Shubhrajyoti D <shubhrajyoti@ti.com>
FWIW:
Reviewed-by: Felipe Balbi <balbi@ti.com>
(if I have time I will test this tomorrow and reply with a Tested-by)
> ---
> v4: add spaces for readability
>
> drivers/i2c/busses/i2c-omap.c | 74 +++++++++++++++++++---------------------
> 1 files changed, 35 insertions(+), 39 deletions(-)
>
> diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
> index be329e9..38acf1a 100644
> --- a/drivers/i2c/busses/i2c-omap.c
> +++ b/drivers/i2c/busses/i2c-omap.c
> @@ -209,7 +209,6 @@ struct omap_i2c_dev {
> u16 pscstate;
> u16 scllstate;
> u16 sclhstate;
> - u16 bufstate;
> u16 syscstate;
> u16 westate;
> u16 errata;
> @@ -285,9 +284,34 @@ static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
> }
> }
>
> +static void __omap_i2c_init(struct omap_i2c_dev *dev)
> +{
> +
> + omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
> +
> + /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
> + omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev->pscstate);
> +
> + /* SCL low and high time values */
> + omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, dev->scllstate);
> + omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, dev->sclhstate);
> + if (dev->rev >= OMAP_I2C_REV_ON_3430_3530)
> + omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate);
> +
> + /* Take the I2C module out of reset: */
> + omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
> +
> + /*
> + * Don't write to this register if the IE state is 0 as it can
> + * cause deadlock.
> + */
> + if (dev->iestate)
> + omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
> +}
> +
> static int omap_i2c_init(struct omap_i2c_dev *dev)
> {
> - u16 psc = 0, scll = 0, sclh = 0, buf = 0;
> + u16 psc = 0, scll = 0, sclh = 0;
> u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
> unsigned long fclk_rate = 12000000;
> unsigned long timeout;
> @@ -337,11 +361,8 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
> * REVISIT: Some wkup sources might not be needed.
> */
> dev->westate = OMAP_I2C_WE_ALL;
> - omap_i2c_write_reg(dev, OMAP_I2C_WE_REG,
> - dev->westate);
> }
> }
> - omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
>
> if (dev->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) {
> /*
> @@ -426,28 +447,18 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
> sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
> }
>
> - /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
> - omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
> -
> - /* SCL low and high time values */
> - omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
> - omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
> -
> - /* Take the I2C module out of reset: */
> - omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
> -
> /* Enable interrupts */
> dev->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
> OMAP_I2C_IE_NACK | OMAP_I2C_IE_AL) |
> ((dev->fifo_size) ? (OMAP_I2C_IE_RDR |
> OMAP_I2C_IE_XDR) : 0);
> - omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
> - if (dev->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE) {
> - dev->pscstate = psc;
> - dev->scllstate = scll;
> - dev->sclhstate = sclh;
> - dev->bufstate = buf;
> - }
> +
> + dev->pscstate = psc;
> + dev->scllstate = scll;
> + dev->sclhstate = sclh;
> +
> + __omap_i2c_init(dev);
> +
> return 0;
> }
>
> @@ -1267,23 +1278,8 @@ static int omap_i2c_runtime_resume(struct device *dev)
> {
> struct omap_i2c_dev *_dev = dev_get_drvdata(dev);
>
> - if (_dev->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE) {
> - omap_i2c_write_reg(_dev, OMAP_I2C_CON_REG, 0);
> - omap_i2c_write_reg(_dev, OMAP_I2C_PSC_REG, _dev->pscstate);
> - omap_i2c_write_reg(_dev, OMAP_I2C_SCLL_REG, _dev->scllstate);
> - omap_i2c_write_reg(_dev, OMAP_I2C_SCLH_REG, _dev->sclhstate);
> - omap_i2c_write_reg(_dev, OMAP_I2C_BUF_REG, _dev->bufstate);
> - omap_i2c_write_reg(_dev, OMAP_I2C_SYSC_REG, _dev->syscstate);
> - omap_i2c_write_reg(_dev, OMAP_I2C_WE_REG, _dev->westate);
> - omap_i2c_write_reg(_dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
> - }
> -
> - /*
> - * Don't write to this register if the IE state is 0 as it can
> - * cause deadlock.
> - */
> - if (_dev->iestate)
> - omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, _dev->iestate);
> + if (_dev->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE)
> + __omap_i2c_init(_dev);
>
> return 0;
> }
> --
> 1.7.5.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
--
balbi
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* [PATCHv4 2/2] i2c: omap: make reset a seperate function
From: Felipe Balbi @ 2012-10-29 19:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351176199-6479-3-git-send-email-shubhrajyoti@ti.com>
On Thu, Oct 25, 2012 at 08:13:19PM +0530, Shubhrajyoti D wrote:
> Implement reset as a separate function.
> This will enable us to make sure that we don't do the
> calculation again on every transfer.
> Also at probe the reset is not added as the hwmod is doing that
> for us.
>
> Signed-off-by: Shubhrajyoti D <shubhrajyoti@ti.com>
Reviewed-by: Felipe Balbi <balbi@ti.com>
(again, will test tomorrow if I have time)
Next step would be to figure out if it is necessary to reset the IP in
case of error. I don't think so, but only testing will say...
> ---
> some of the errors may not need a reset.
> will check and post separate patch.
>
> drivers/i2c/busses/i2c-omap.c | 25 ++++++++++++++++---------
> 1 files changed, 16 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
> index 38acf1a..a25b7b0 100644
> --- a/drivers/i2c/busses/i2c-omap.c
> +++ b/drivers/i2c/busses/i2c-omap.c
> @@ -309,15 +309,9 @@ static void __omap_i2c_init(struct omap_i2c_dev *dev)
> omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
> }
>
> -static int omap_i2c_init(struct omap_i2c_dev *dev)
> +static int omap_i2c_reset(struct omap_i2c_dev *dev)
> {
> - u16 psc = 0, scll = 0, sclh = 0;
> - u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
> - unsigned long fclk_rate = 12000000;
> unsigned long timeout;
> - unsigned long internal_clk = 0;
> - struct clk *fclk;
> -
> if (dev->rev >= OMAP_I2C_OMAP1_REV_2) {
> /* Disable I2C controller before soft reset */
> omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
> @@ -363,6 +357,17 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
> dev->westate = OMAP_I2C_WE_ALL;
> }
> }
> + return 0;
> +}
> +
> +static int omap_i2c_init(struct omap_i2c_dev *dev)
> +{
> + u16 psc = 0, scll = 0, sclh = 0;
> + u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
> + unsigned long fclk_rate = 12000000;
> + unsigned long internal_clk = 0;
> + struct clk *fclk;
> +
>
> if (dev->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) {
> /*
> @@ -595,7 +600,8 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
> if (timeout == 0) {
> dev_err(dev->dev, "controller timed out\n");
> ret = -ETIMEDOUT;
> - omap_i2c_init(dev);
> + omap_i2c_reset(dev);
> + __omap_i2c_init(dev);
> goto out;
> }
>
> @@ -606,7 +612,8 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
> if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
> OMAP_I2C_STAT_XUDF)) {
> ret = -EIO;
> - omap_i2c_init(dev);
> + omap_i2c_reset(dev);
> + __omap_i2c_init(dev);
> goto out;
> }
>
> --
> 1.7.5.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
--
balbi
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* OMAP baseline test results for v3.7-rc1
From: Felipe Balbi @ 2012-10-29 20:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.DEB.2.00.1210262201500.11258@utopia.booyaka.com>
Hi,
On Fri, Oct 26, 2012 at 10:03:11PM +0000, Paul Walmsley wrote:
> Hi Felipe,
>
> On Fri, 26 Oct 2012, Felipe Balbi wrote:
>
> > On Thu, Oct 25, 2012 at 01:12:12PM +0300, Felipe Balbi wrote:
> > > On Tue, Oct 23, 2012 at 09:23:03PM +0200, Jean Pihet wrote:
> > > > On Tue, Oct 23, 2012 at 9:19 PM, Paul Walmsley <paul@pwsan.com> wrote:
> > > > > On Mon, 22 Oct 2012, Jean Pihet wrote:
> > > > >
> > > > >> On Mon, Oct 22, 2012 at 6:12 PM, Jean Pihet <jean.pihet@newoldbits.com> wrote:
> > > > >>
> > > > >> > Do you have CPU_IDLE enabled?
> > > > >> FYI the issue is not present with CPU_IDLE enabled.
> > > > >
> > > > > Hmm, how can you tell? I thought you weren't able to reproduce it with
> > > > > CPU_IDLE disabled either?
> > > > I could not reproduce the issue, with and without CPU_IDLE enabled.
> > > > What puzzles me is that the PM QoS code only has influence on the
> > > > states chosen by cpuidle, so the change should not have any impact
> > > > with CPU_IDLE enabled. I reallt need to reproduce the issue.
> > > > Let me try with the same setup as yours (bootloader images,
> > > > omap2pus_defconfig, angstrom roots).
> > >
> > > I just sent a patch to fix a bug I found on OMAP4 panda but while
> > > reading this thread again, I think it could be that it's the same bug
> > > which is just easier to reproduce on Paul's setup.
> > >
> > > Paul, Aaro, can you see if [1] makes the problem go away ? that would be
> > > another reason to push [1] during this -rc cycle.
> > >
> > > [1] http://marc.info/?l=linux-omap&m=135115602407925&w=2
>
> Thanks for mentioning it, but this patch doesn't fix the I2C timeout
> problem here. Log fragment below from the 3530ES3 Beagle.
that's too bad :-(
Can you compile with:
CONFIG_I2C_DEBUG_CORE=y
CONFIG_I2C_DEBUG_ALGO=y
CONFIG_I2C_DEBUG_BUS=y
CONFIG_DEFAULT_MESSAGE_LOGLEVEL=9
so that I can see all transfers ?
--
balbi
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* vexpress issues in next-20121029
From: Stephen Warren @ 2012-10-29 20:24 UTC (permalink / raw)
To: linux-arm-kernel
Pawel,
I see two issues on vexpress in next-20121029:
1) At compile-time: v2m_timer_init() and v2m_dt_timer_init() reference
functions vexpress_clk_init() and vexpress_clk_of_init() respectively,
which don't appear anywhere in the source tree.
2) With those calls commented out, I find that
vexpress_sysreg_init_leds() is device_initcall, and so executes even
when not running on vexpress HW. This crashes on Tegra (which I have
converted to single-zImage locally).
These appear to come from the following commits:
0891642 ARM: vexpress: Start using new Versatile Express infrastructure
568e5e4 mfd: Versatile Express system registers driver
^ permalink raw reply
* imx-sdma.c broken on imx53 for sound
From: Fabio Estevam @ 2012-10-29 20:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121029194505.DD38B1A1A4DB@amazonia.comcast.net>
On Mon, Oct 29, 2012 at 5:45 PM, Rick Bronson <rickbronson@gmail.com> wrote:
> Hi Fabio,
>
> Thanks for the help. Apparently the firmware moved from internal to
> /lib/firmware/imx/sdma/sdma-imx53.bin
You can generate the mx53 sdma firmware using this tool:
http://git.pengutronix.de/?p=imx/sdma-firmware.git;a=summary
Regards,
Fabio Estevam
^ permalink raw reply
* [PATCH 1/2] rtc-imxdi: Support for i.MX53
From: Sascha Hauer @ 2012-10-29 21:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350576370-29098-1-git-send-email-stigge@antcom.de>
On Thu, Oct 18, 2012 at 06:06:08PM +0200, Roland Stigge wrote:
> This patch enables support for i.MX53 in addition to i.MX25 by enabling the
> driver on ARCH_MXC generally.
>
> Signed-off-by: Roland Stigge <stigge@antcom.de>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
> drivers/rtc/Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> --- linux-2.6.orig/drivers/rtc/Kconfig
> +++ linux-2.6/drivers/rtc/Kconfig
> @@ -768,7 +768,7 @@ config RTC_DRV_DAVINCI
>
> config RTC_DRV_IMXDI
> tristate "Freescale IMX DryIce Real Time Clock"
> - depends on SOC_IMX25
> + depends on ARCH_MXC
> help
> Support for Freescale IMX DryIce RTC
>
>
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply
* [PATCH 2/2] rtc-imxdi: Add devicetree support
From: Sascha Hauer @ 2012-10-29 21:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350576370-29098-2-git-send-email-stigge@antcom.de>
On Thu, Oct 18, 2012 at 06:06:09PM +0200, Roland Stigge wrote:
> This patch adds device tree support to the rtc-imxdi driver.
>
> Signed-off-by: Roland Stigge <stigge@antcom.de>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
> Documentation/devicetree/bindings/rtc/imxdi-rtc.txt | 17 +++++++++++++++++
> drivers/rtc/rtc-imxdi.c | 11 +++++++++++
> 2 files changed, 28 insertions(+)
>
> --- /dev/null
> +++ linux-2.6/Documentation/devicetree/bindings/rtc/imxdi-rtc.txt
> @@ -0,0 +1,17 @@
> +* i.MX25 Real Time Clock controller
> +
> +This binding supports the following chips: i.MX25, i.MX53
> +
> +Required properties:
> +- compatible: should be: "fsl,imx25-rtc"
> +- reg: physical base address of the controller and length of memory mapped
> + region.
> +- interrupts: rtc alarm interrupt
> +
> +Example:
> +
> +rtc at 80056000 {
> + compatible = "fsl,imx53-rtc", "fsl,imx25-rtc";
> + reg = <0x80056000 2000>;
> + interrupts = <29>;
> +};
> --- linux-2.6.orig/drivers/rtc/rtc-imxdi.c
> +++ linux-2.6/drivers/rtc/rtc-imxdi.c
> @@ -37,6 +37,7 @@
> #include <linux/rtc.h>
> #include <linux/sched.h>
> #include <linux/workqueue.h>
> +#include <linux/of.h>
>
> /* DryIce Register Definitions */
>
> @@ -493,10 +494,20 @@ static int __devexit dryice_rtc_remove(s
> return 0;
> }
>
> +#ifdef CONFIG_OF
> +static const struct of_device_id dryice_dt_ids[] = {
> + { .compatible = "fsl,imx25-rtc" },
> + { /* sentinel */ }
> +};
> +
> +MODULE_DEVICE_TABLE(of, dryice_dt_ids);
> +#endif
> +
> static struct platform_driver dryice_rtc_driver = {
> .driver = {
> .name = "imxdi_rtc",
> .owner = THIS_MODULE,
> + .of_match_table = of_match_ptr(dryice_dt_ids),
> },
> .remove = __devexit_p(dryice_rtc_remove),
> };
>
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply
* [PATCH] ARM: mach-imx: Support for DryIce RTC in i.MX53
From: Sascha Hauer @ 2012-10-29 21:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350576370-29098-3-git-send-email-stigge@antcom.de>
On Thu, Oct 18, 2012 at 06:06:10PM +0200, Roland Stigge wrote:
> This patch enables support for i.MX53 in addition to i.MX25 by providing a
> dummy clock on i.MX53 since this one doesn't have a separate clock for internal
> RTC but the driver requests one.
>
> Signed-off-by: Roland Stigge <stigge@antcom.de>
Applied, thanks
Sascha
> ---
> arch/arm/mach-imx/clk-imx51-imx53.c | 1 +
> 1 file changed, 1 insertion(+)
>
> --- linux-2.6.orig/arch/arm/mach-imx/clk-imx51-imx53.c
> +++ linux-2.6/arch/arm/mach-imx/clk-imx51-imx53.c
> @@ -467,6 +467,7 @@ int __init mx53_clocks_init(unsigned lon
> clk_register_clkdev(clk[can1_serial_gate], "per", "53fc8000.can");
> clk_register_clkdev(clk[can2_ipg_gate], "ipg", "53fcc000.can");
> clk_register_clkdev(clk[can2_serial_gate], "per", "53fcc000.can");
> + clk_register_clkdev(clk[dummy], NULL, "53fa4000.rtc");
>
> /* set SDHC root clock to 200MHZ*/
> clk_set_rate(clk[esdhc_a_podf], 200000000);
>
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply
* [PATCH] Add device tree file for the armadeus apf27
From: Sascha Hauer @ 2012-10-29 21:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351268980-25347-1-git-send-email-tremyfr@yahoo.fr>
On Fri, Oct 26, 2012 at 06:29:40PM +0200, Philippe Reynes wrote:
> Signed-off-by: Philippe Reynes <tremyfr@yahoo.fr>
> Signed-off-by: Eric Jarrige <eric.jarrige@armadeus.org>
> ---
> arch/arm/boot/dts/imx27-apf27.dts | 96 +++++++++++++++++++++++++++++++++++++
> 1 files changed, 96 insertions(+), 0 deletions(-)
> create mode 100644 arch/arm/boot/dts/imx27-apf27.dts
>
> diff --git a/arch/arm/boot/dts/imx27-apf27.dts b/arch/arm/boot/dts/imx27-apf27.dts
> new file mode 100644
> index 0000000..b7d11e0
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx27-apf27.dts
> @@ -0,0 +1,96 @@
> +/*
> + * Copyright 2012 Philippe Reynes <tremyfr@yahoo.fr>
> + * Copyright 2012 Armadeus Systems <support@armadeus.com>
> + *
> + * Based on code which is: Copyright 2012 Sascha Hauer, Pengutronix
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +/dts-v1/;
> +/include/ "imx27.dtsi"
> +
> +/ {
> + model = "Armadeus apf27";
> + compatible = "armadeus,imx27-apf27", "fsl,imx27";
> +
> + memory {
> + reg = <0xa0000000 0x04000000>;
> + };
> +
> + clocks {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + osc26m {
> + compatible = "fsl,imx-osc26m", "fixed-clock";
> + clock-frequency = <33554432>;
Is this really correct? The Datasheet specificies 26MHz, some boards
have 27Mhz, but 33?
> + };
> + };
> +
> + soc {
> + aipi at 10000000 {
> + wdog at 10002000 {
> + status = "okay";
> + };
This node is not necessary. The watchdog is enabled already in the dtsi
file.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply
* [PATCH] MMC: fix sdhci-dove removal
From: Chris Ball @ 2012-10-29 21:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121015104456.GR21164@n2100.arm.linux.org.uk>
Hi Russell,
On Mon, Oct 15 2012, Russell King - ARM Linux wrote:
> Here's an updated patch which just about fixes the sdhci-dove driver.
> I would not be surprised given the idiotic sdhci-pltfm API if many
> other drivers suffered the same bug.
>
> 8<====
> From: Russell King <rmk+kernel@arm.linux.org.uk>
> Subject: [PATCH] MMC: fix sdhci-dove probe/removal
>
> 1. Never ever publish a device in the system before it has been setup
> to a usable state.
> 2. Unregister the device _BEFORE_ taking away any resources it may be
> using.
> 3. Don't check clks against NULL.
>
> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This version of the patch doesn't apply cleanly or compile -- maybe you
have a later revision?
/home/cjb/git/mmc/drivers/mmc/host/sdhci-dove.c: In function ?sdhci_dove_probe?:
/home/cjb/git/mmc/drivers/mmc/host/sdhci-dove.c:109:2: error: implicit declaration of function ?clk_unprepare_disable? [-Werror=implicit-function-declaration]
/home/cjb/git/mmc/drivers/mmc/host/sdhci-dove.c:111:1: warning: label ?sdhci_dove_allocate_fail? defined but not used [-Wunused-label]
Thanks,
- Chris.
--
Chris Ball <cjb@laptop.org> <http://printf.net/>
One Laptop Per Child
^ permalink raw reply
* [PATCH V2 0/5] SMP support for Armada XP
From: Gregory CLEMENT @ 2012-10-29 21:11 UTC (permalink / raw)
To: linux-arm-kernel
Hello,
The purpose of this patch set is to add the SMP support for the Armada
XP SoCs. Beside the SMP support itself brought by the last 3 patches,
this patch set also adds the support for the coherency fabric unit and
the power management service unit.
The coherency fabric is responsible for ensuring hardware coherency
between all CPUs and between CPUs and I/O masters. This unit is also
available for Armada 370 and will be used in an incoming patch set
for hardware I/O cache coherency.
The power management service unit is responsible for powering down and
waking up CPUs and other SOC units.
The original code is from Yehuda Yitschak, it was reworked by myself
and reviewed by Yehuda.
This patch set is based on 3.7-rc3 and depends one the framework clock
support (the last version was posted 2 weeks ago:
http://thread.gmane.org/gmane.linux.kernel/1375701). The git branch
called ArmadaXP-SMP-for-3.8-V2 is also available at
https://github.com/MISL-EBU-System-SW/mainline-public.git.
Arnd, Olof, as this code is SoC specific will you be able to pull it
through Jason tree? Or should I push the part added in
arch/arm/mm/proc-v7.S to support PJ4B CPU through Russell tree?
Changelog:
V1 -> V2:
- Rebased on to v3.7-rc3
- Fixed typos found by Alexandre Belloni
- Added clk_prepare_enable() before getting rate clk in
set_secondary_cpus_clock()
- Add explanation in the binding documentation about the per-CPU
interrupt registers: the address of the virtual register must be
used.
- Removed the armada_xp prefix in the coherency.c file to be more
compliant with the name convention of the other files.
- Coherency_init is now called from armada_370_xp_dt_init() and is no
more an early_init() call. As the device tree is not available from
an early_init(), it was useless to call coherency_init() so
early. The need to be able to call some function very early during
the boot were already resolved by using the hard code address of the
register.
Regards,
Yehuda Yitschak (5):
arm: mvebu: Added support for coherency fabric in mach-mvebu
arm: mvebu: Added initial support for power managmement service unit
arm: mvebu: Added IPI support via doorbells
arm: mm: Added support for PJ4B cpu and init routines
arm: mvebu: Added SMP support for Armada XP
.../devicetree/bindings/arm/armada-370-xp-mpic.txt | 12 +-
.../devicetree/bindings/arm/armada-370-xp-pmsu.txt | 20 ++++
.../devicetree/bindings/arm/coherency-fabric.txt | 16 +++
arch/arm/boot/dts/armada-370-xp.dtsi | 5 +
arch/arm/boot/dts/armada-xp.dtsi | 12 +-
arch/arm/configs/mvebu_defconfig | 3 +
arch/arm/mach-mvebu/Kconfig | 3 +-
arch/arm/mach-mvebu/Makefile | 4 +-
arch/arm/mach-mvebu/armada-370-xp.c | 3 +
arch/arm/mach-mvebu/armada-370-xp.h | 10 ++
arch/arm/mach-mvebu/coherency.c | 89 ++++++++++++++
arch/arm/mach-mvebu/coherency.h | 21 ++++
arch/arm/mach-mvebu/common.h | 6 +
arch/arm/mach-mvebu/headsmp.S | 66 +++++++++++
arch/arm/mach-mvebu/hotplug.c | 30 +++++
arch/arm/mach-mvebu/irq-armada-370-xp.c | 92 ++++++++++++++-
arch/arm/mach-mvebu/platsmp.c | 124 ++++++++++++++++++++
arch/arm/mach-mvebu/pmsu.c | 78 ++++++++++++
arch/arm/mach-mvebu/pmsu.h | 16 +++
arch/arm/mm/Kconfig | 4 +
arch/arm/mm/proc-v7.S | 46 ++++++++
21 files changed, 648 insertions(+), 12 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/armada-370-xp-pmsu.txt
create mode 100644 Documentation/devicetree/bindings/arm/coherency-fabric.txt
create mode 100644 arch/arm/mach-mvebu/coherency.c
create mode 100644 arch/arm/mach-mvebu/coherency.h
create mode 100644 arch/arm/mach-mvebu/headsmp.S
create mode 100644 arch/arm/mach-mvebu/hotplug.c
create mode 100644 arch/arm/mach-mvebu/platsmp.c
create mode 100644 arch/arm/mach-mvebu/pmsu.c
create mode 100644 arch/arm/mach-mvebu/pmsu.h
--
1.7.9.5
^ permalink raw reply
* [PATCH V2 1/5] arm: mvebu: Added support for coherency fabric in mach-mvebu
From: Gregory CLEMENT @ 2012-10-29 21:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351545108-18954-1-git-send-email-gregory.clement@free-electrons.com>
From: Yehuda Yitschak <yehuday@marvell.com>
Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
.../devicetree/bindings/arm/coherency-fabric.txt | 16 ++++
arch/arm/boot/dts/armada-370-xp.dtsi | 5 ++
arch/arm/mach-mvebu/Makefile | 2 +-
arch/arm/mach-mvebu/coherency.c | 89 ++++++++++++++++++++
arch/arm/mach-mvebu/coherency.h | 21 +++++
arch/arm/mach-mvebu/common.h | 2 +
6 files changed, 134 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/arm/coherency-fabric.txt
create mode 100644 arch/arm/mach-mvebu/coherency.c
create mode 100644 arch/arm/mach-mvebu/coherency.h
diff --git a/Documentation/devicetree/bindings/arm/coherency-fabric.txt b/Documentation/devicetree/bindings/arm/coherency-fabric.txt
new file mode 100644
index 0000000..2bfbf67
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/coherency-fabric.txt
@@ -0,0 +1,16 @@
+Coherency fabric
+----------------
+Available on Marvell SOCs: Armada 370 and Armada XP
+
+Required properties:
+
+- compatible: "marvell,coherency-fabric"
+- reg: Should contain,coherency fabric registers location and length.
+
+Example:
+
+coherency-fabric at d0020200 {
+ compatible = "marvell,coherency-fabric";
+ reg = <0xd0020200 0xb0>;
+};
+
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 94b4b9e..b0d075b 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -36,6 +36,11 @@
interrupt-controller;
};
+ coherency-fabric at d0020200 {
+ compatible = "marvell,coherency-fabric";
+ reg = <0xd0020200 0xb0>;
+ };
+
soc {
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index 57f996b..abd6d3b 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -2,4 +2,4 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
-I$(srctree)/arch/arm/plat-orion/include
obj-y += system-controller.o
-obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o addr-map.o
+obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o addr-map.o coherency.o
diff --git a/arch/arm/mach-mvebu/coherency.c b/arch/arm/mach-mvebu/coherency.c
new file mode 100644
index 0000000..69e130d
--- /dev/null
+++ b/arch/arm/mach-mvebu/coherency.c
@@ -0,0 +1,89 @@
+/*
+ * Coherency fabric (Aurora) support for Armada 370 and XP platforms.
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Yehuda Yitschak <yehuday@marvell.com>
+ * Gregory Clement <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * The Armada 370 and Armada XP SOCs have a coherency fabric which is
+ * responsible for ensuring hardware coherency between all CPUs and between
+ * CPUs and I/O masters. This file initializes the coherency fabric and
+ * supplies basic routines for configuring and controlling hardware coherency
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/of_address.h>
+#include <linux/io.h>
+#include <linux/smp.h>
+#include <asm/smp_plat.h>
+#include "armada-370-xp.h"
+
+/* Some functions in this file are called very early during SMP
+ * initialization. At that time the device tree framework is not yet
+ * ready, and it is not possible to get the register address to
+ * ioremap it. That's why the pointer below is given with an initial
+ * value matching its virtual mapping
+ */
+static void __iomem *coherency_base = ARMADA_370_XP_REGS_VIRT_BASE + 0x20200;
+
+/* Coherency fabric registers */
+#define COHERENCY_FABRIC_CTL_OFFSET 0x0
+#define COHERENCY_FABRIC_CFG_OFFSET 0x4
+
+static struct of_device_id of_coherency_table[] = {
+ {.compatible = "marvell,coherency-fabric"},
+ { /* end of list */ },
+};
+
+int coherency_get_cpu_count(void)
+{
+ int reg, cnt;
+
+ reg = readl(coherency_base + COHERENCY_FABRIC_CFG_OFFSET);
+ cnt = (reg & 0xF) + 1;
+
+ return cnt;
+}
+
+int set_cpu_coherent(unsigned int hw_cpu_id, int smp_group_id)
+{
+ int reg;
+
+ if (!coherency_base) {
+ pr_warn("Can't make CPU %d cache coherent.\n", hw_cpu_id);
+ pr_warn("Coherency fabric is not initialized\n");
+ return 1;
+ }
+
+ /* Enable the CPU in coherency fabric */
+ reg = readl(coherency_base + COHERENCY_FABRIC_CTL_OFFSET);
+ reg |= 1 << (24 + hw_cpu_id);
+ writel(reg, coherency_base + COHERENCY_FABRIC_CTL_OFFSET);
+
+ /* Add CPU to SMP group */
+ reg = readl(coherency_base + COHERENCY_FABRIC_CFG_OFFSET);
+ reg |= 1 << (16 + hw_cpu_id + (smp_group_id == 0 ? 8 : 0));
+ writel(reg, coherency_base + COHERENCY_FABRIC_CFG_OFFSET);
+
+ return 0;
+}
+
+int __init coherency_init(void)
+{
+ struct device_node *np;
+
+ np = of_find_matching_node(NULL, of_coherency_table);
+ if (np) {
+ pr_info("Initializing Coherency fabric\n");
+ coherency_base = of_iomap(np, 0);
+ }
+
+ return 0;
+}
diff --git a/arch/arm/mach-mvebu/coherency.h b/arch/arm/mach-mvebu/coherency.h
new file mode 100644
index 0000000..6182192
--- /dev/null
+++ b/arch/arm/mach-mvebu/coherency.h
@@ -0,0 +1,21 @@
+/*
+ * arch/arm/mach-mvebu/include/mach/coherency.h
+ *
+ *
+ * Coherency fabric (Aurora) support for Armada 370 and XP platforms.
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_370_XP_COHERENCY_H
+#define __MACH_370_XP_COHERENCY_H
+
+int set_cpu_coherent(int cpu_id, int smp_group_id);
+int coherency_get_cpu_count(void);
+int coherency_init(void);
+
+#endif /* __MACH_370_XP_COHERENCY_H */
diff --git a/arch/arm/mach-mvebu/common.h b/arch/arm/mach-mvebu/common.h
index 281fab3..ea08919 100644
--- a/arch/arm/mach-mvebu/common.h
+++ b/arch/arm/mach-mvebu/common.h
@@ -21,4 +21,6 @@ void mvebu_clocks_init(void);
void armada_370_xp_init_irq(void);
void armada_370_xp_handle_irq(struct pt_regs *regs);
+
+int armada_370_xp_coherency_init(void);
#endif
--
1.7.9.5
^ permalink raw reply related
* [PATCH V2 2/5] arm: mvebu: Added initial support for power managmement service unit
From: Gregory CLEMENT @ 2012-10-29 21:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351545108-18954-1-git-send-email-gregory.clement@free-electrons.com>
From: Yehuda Yitschak <yehuday@marvell.com>
Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
.../devicetree/bindings/arm/armada-370-xp-pmsu.txt | 20 +++++
arch/arm/boot/dts/armada-xp.dtsi | 6 ++
arch/arm/mach-mvebu/Makefile | 2 +-
arch/arm/mach-mvebu/common.h | 1 +
arch/arm/mach-mvebu/pmsu.c | 78 ++++++++++++++++++++
arch/arm/mach-mvebu/pmsu.h | 16 ++++
6 files changed, 122 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/arm/armada-370-xp-pmsu.txt
create mode 100644 arch/arm/mach-mvebu/pmsu.c
create mode 100644 arch/arm/mach-mvebu/pmsu.h
diff --git a/Documentation/devicetree/bindings/arm/armada-370-xp-pmsu.txt b/Documentation/devicetree/bindings/arm/armada-370-xp-pmsu.txt
new file mode 100644
index 0000000..926b4d6
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/armada-370-xp-pmsu.txt
@@ -0,0 +1,20 @@
+Power Management Service Unit(PMSU)
+-----------------------------------
+Available on Marvell SOCs: Armada 370 and Armada XP
+
+Required properties:
+
+- compatible: "marvell,armada-370-xp-pmsu"
+
+- reg: Should contain PMSU registers location and length. First pair
+ for the per-CPU SW Reset Control registers, second pair for the
+ Power Management Service Unit.
+
+Example:
+
+armada-370-xp-pmsu at d0022000 {
+ compatible = "marvell,armada-370-xp-pmsu";
+ reg = <0xd0022100 0x430>,
+ <0xd0020800 0x20>;
+};
+
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index a564b52..f521ed8 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -27,6 +27,12 @@
<0xd0021870 0x58>;
};
+ armada-370-xp-pmsu at d0022000 {
+ compatible = "marvell,armada-370-xp-pmsu";
+ reg = <0xd0022100 0x430>,
+ <0xd0020800 0x20>;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index abd6d3b..8e6e50b 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -2,4 +2,4 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
-I$(srctree)/arch/arm/plat-orion/include
obj-y += system-controller.o
-obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o addr-map.o coherency.o
+obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o addr-map.o coherency.o pmsu.o
diff --git a/arch/arm/mach-mvebu/common.h b/arch/arm/mach-mvebu/common.h
index ea08919..74ee0b2 100644
--- a/arch/arm/mach-mvebu/common.h
+++ b/arch/arm/mach-mvebu/common.h
@@ -23,4 +23,5 @@ void armada_370_xp_handle_irq(struct pt_regs *regs);
int armada_370_xp_coherency_init(void);
+int armada_370_xp_pmsu_init(void);
#endif
diff --git a/arch/arm/mach-mvebu/pmsu.c b/arch/arm/mach-mvebu/pmsu.c
new file mode 100644
index 0000000..cee020b
--- /dev/null
+++ b/arch/arm/mach-mvebu/pmsu.c
@@ -0,0 +1,78 @@
+/*
+ * Power Management Service Unit(PMSU) support for Armada 370/XP platforms.
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Yehuda Yitschak <yehuday@marvell.com>
+ * Gregory Clement <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * The Armada 370 and Armada XP SOCs have a power management service
+ * unit which is responsible for powering down and waking up CPUs and
+ * other SOC units
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/of_address.h>
+#include <linux/io.h>
+#include <linux/smp.h>
+#include <asm/smp_plat.h>
+
+static void __iomem *pmsu_mp_base;
+static void __iomem *pmsu_reset_base;
+
+#define PMSU_BOOT_ADDR_REDIRECT_OFFSET(cpu) ((cpu * 0x100) + 0x24)
+#define PMSU_RESET_CTL_OFFSET(cpu) (cpu * 0x8)
+
+static struct of_device_id of_pmsu_table[] = {
+ {.compatible = "marvell,armada-370-xp-pmsu"},
+ { /* end of list */ },
+};
+
+#ifdef CONFIG_SMP
+int armada_xp_boot_cpu(unsigned int cpu_id, void __iomem *boot_addr)
+{
+ int reg, hw_cpu;
+
+ if (!pmsu_mp_base || !pmsu_reset_base) {
+ pr_warn("Can't boot CPU. PMSU is uninitialized\n");
+ return 1;
+ }
+
+ hw_cpu = cpu_logical_map(cpu_id);
+
+ writel(virt_to_phys(boot_addr), pmsu_mp_base +
+ PMSU_BOOT_ADDR_REDIRECT_OFFSET(hw_cpu));
+
+ /* Make sure value hits memory before reset */
+ dsb();
+
+ /* Release CPU from reset by clearing reset bit*/
+ reg = readl(pmsu_reset_base + PMSU_RESET_CTL_OFFSET(hw_cpu));
+ reg &= (~0x1);
+ writel(reg, pmsu_reset_base + PMSU_RESET_CTL_OFFSET(hw_cpu));
+
+ return 0;
+}
+#endif
+
+int __init armada_370_xp_pmsu_init(void)
+{
+ struct device_node *np;
+
+ np = of_find_matching_node(NULL, of_pmsu_table);
+ if (np) {
+ pr_info("Initializing Power Management Service Unit\n");
+ pmsu_mp_base = of_iomap(np, 0);
+ pmsu_reset_base = of_iomap(np, 1);
+ }
+
+ return 0;
+}
+
+early_initcall(armada_370_xp_pmsu_init);
diff --git a/arch/arm/mach-mvebu/pmsu.h b/arch/arm/mach-mvebu/pmsu.h
new file mode 100644
index 0000000..bafac8e
--- /dev/null
+++ b/arch/arm/mach-mvebu/pmsu.h
@@ -0,0 +1,16 @@
+/*
+ * Power Management Service Unit (PMSU) support for Armada 370/XP platforms.
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_MVEBU_PMSU_H
+#define __MACH_MVEBU_PMSU_H
+
+int armada_xp_boot_cpu(unsigned int cpu_id, void __iomem *phys_addr);
+
+#endif /* __MACH_370_XP_PMSU_H */
--
1.7.9.5
^ permalink raw reply related
* [PATCH V2 3/5] arm: mvebu: Added IPI support via doorbells
From: Gregory CLEMENT @ 2012-10-29 21:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351545108-18954-1-git-send-email-gregory.clement@free-electrons.com>
From: Yehuda Yitschak <yehuday@marvell.com>
Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
.../devicetree/bindings/arm/armada-370-xp-mpic.txt | 12 ++-
arch/arm/boot/dts/armada-xp.dtsi | 2 +-
arch/arm/mach-mvebu/armada-370-xp.h | 10 +++
arch/arm/mach-mvebu/irq-armada-370-xp.c | 92 ++++++++++++++++++--
4 files changed, 106 insertions(+), 10 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt b/Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt
index 70c0dc5..61df564 100644
--- a/Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt
+++ b/Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt
@@ -6,9 +6,15 @@ Required properties:
- interrupt-controller: Identifies the node as an interrupt controller.
- #interrupt-cells: The number of cells to define the interrupts. Should be 1.
The cell is the IRQ number
+
- reg: Should contain PMIC registers location and length. First pair
for the main interrupt registers, second pair for the per-CPU
- interrupt registers
+ interrupt registers. For this last pair, to be compliant with SMP
+ support, the "virtual" must be use (For the record, these registers
+ automatically map to the interrupt controller registers of the
+ current CPU)
+
+
Example:
@@ -18,6 +24,6 @@ Example:
#address-cells = <1>;
#size-cells = <1>;
interrupt-controller;
- reg = <0xd0020000 0x1000>,
- <0xd0021000 0x1000>;
+ reg = <0xd0020a00 0x1d0>,
+ <0xd0021070 0x58>;
};
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index f521ed8..531619f 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -24,7 +24,7 @@
mpic: interrupt-controller at d0020000 {
reg = <0xd0020a00 0x1d0>,
- <0xd0021870 0x58>;
+ <0xd0021070 0x58>;
};
armada-370-xp-pmsu at d0022000 {
diff --git a/arch/arm/mach-mvebu/armada-370-xp.h b/arch/arm/mach-mvebu/armada-370-xp.h
index aac9beb..dce590d 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.h
+++ b/arch/arm/mach-mvebu/armada-370-xp.h
@@ -19,4 +19,14 @@
#define ARMADA_370_XP_REGS_VIRT_BASE IOMEM(0xfeb00000)
#define ARMADA_370_XP_REGS_SIZE SZ_1M
+#ifndef __ASSEMBLY__
+
+#ifdef CONFIG_SMP
+#include <linux/cpumask.h>
+
+void armada_mpic_send_doorbell(const struct cpumask *mask, unsigned int irq);
+void armada_xp_mpic_smp_cpu_init(void);
+#endif
+#endif
+
#endif /* __MACH_ARMADA_370_XP_H */
diff --git a/arch/arm/mach-mvebu/irq-armada-370-xp.c b/arch/arm/mach-mvebu/irq-armada-370-xp.c
index 5f5f939..549b684 100644
--- a/arch/arm/mach-mvebu/irq-armada-370-xp.c
+++ b/arch/arm/mach-mvebu/irq-armada-370-xp.c
@@ -24,6 +24,7 @@
#include <linux/irqdomain.h>
#include <asm/mach/arch.h>
#include <asm/exception.h>
+#include <asm/smp_plat.h>
/* Interrupt Controller Registers Map */
#define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48)
@@ -35,6 +36,12 @@
#define ARMADA_370_XP_CPU_INTACK_OFFS (0x44)
+#define ARMADA_370_XP_SW_TRIG_INT_OFFS (0x4)
+#define ARMADA_370_XP_IN_DRBEL_MSK_OFFS (0xc)
+#define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS (0x8)
+
+#define ACTIVE_DOORBELLS (8)
+
static void __iomem *per_cpu_int_base;
static void __iomem *main_int_base;
static struct irq_domain *armada_370_xp_mpic_domain;
@@ -51,11 +58,22 @@ static void armada_370_xp_irq_unmask(struct irq_data *d)
per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
}
+#ifdef CONFIG_SMP
+static int armada_xp_set_affinity(struct irq_data *d,
+ const struct cpumask *mask_val, bool force)
+{
+ return 0;
+}
+#endif
+
static struct irq_chip armada_370_xp_irq_chip = {
.name = "armada_370_xp_irq",
.irq_mask = armada_370_xp_irq_mask,
.irq_mask_ack = armada_370_xp_irq_mask,
.irq_unmask = armada_370_xp_irq_unmask,
+#ifdef CONFIG_SMP
+ .irq_set_affinity = armada_xp_set_affinity,
+#endif
};
static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
@@ -72,6 +90,41 @@ static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
return 0;
}
+#ifdef CONFIG_SMP
+void armada_mpic_send_doorbell(const struct cpumask *mask, unsigned int irq)
+{
+ int cpu;
+ unsigned long map = 0;
+
+ /* Convert our logical CPU mask into a physical one. */
+ for_each_cpu(cpu, mask)
+ map |= 1 << cpu_logical_map(cpu);
+
+ /*
+ * Ensure that stores to Normal memory are visible to the
+ * other CPUs before issuing the IPI.
+ */
+ dsb();
+
+ /* submit softirq */
+ writel((map << 8) | irq, main_int_base +
+ ARMADA_370_XP_SW_TRIG_INT_OFFS);
+}
+
+void armada_xp_mpic_smp_cpu_init(void)
+{
+ /* Clear pending IPIs */
+ writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
+
+ /* Enable first 8 IPIs */
+ writel((1 << ACTIVE_DOORBELLS) - 1, per_cpu_int_base +
+ ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
+
+ /* Unmask IPI interrupt */
+ writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
+}
+#endif /* CONFIG_SMP */
+
static struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
.map = armada_370_xp_mpic_irq_map,
.xlate = irq_domain_xlate_onecell,
@@ -91,13 +144,18 @@ static int __init armada_370_xp_mpic_of_init(struct device_node *node,
control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
armada_370_xp_mpic_domain =
- irq_domain_add_linear(node, (control >> 2) & 0x3ff,
- &armada_370_xp_mpic_irq_ops, NULL);
+ irq_domain_add_linear(node, (control >> 2) & 0x3ff,
+ &armada_370_xp_mpic_irq_ops, NULL);
if (!armada_370_xp_mpic_domain)
panic("Unable to add Armada_370_Xp MPIC irq domain (DT)\n");
irq_set_default_host(armada_370_xp_mpic_domain);
+
+#ifdef CONFIG_SMP
+ armada_xp_mpic_smp_cpu_init();
+#endif
+
return 0;
}
@@ -111,14 +169,36 @@ asmlinkage void __exception_irq_entry armada_370_xp_handle_irq(struct pt_regs
ARMADA_370_XP_CPU_INTACK_OFFS);
irqnr = irqstat & 0x3FF;
- if (irqnr < 1023) {
- irqnr =
- irq_find_mapping(armada_370_xp_mpic_domain, irqnr);
+ if (irqnr > 1022)
+ break;
+
+ if (irqnr >= 8) {
+ irqnr = irq_find_mapping(armada_370_xp_mpic_domain,
+ irqnr);
handle_IRQ(irqnr, regs);
continue;
}
+#ifdef CONFIG_SMP
+ /* IPI Handling */
+ if (irqnr == 0) {
+ u32 ipimask, ipinr;
+
+ ipimask = readl_relaxed(per_cpu_int_base +
+ ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
+ & 0xFF;
+
+ writel(0x0, per_cpu_int_base +
+ ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
+
+ /* Handle all pending doorbells */
+ for (ipinr = 0; ipinr < ACTIVE_DOORBELLS; ipinr++) {
+ if (ipimask & (0x1 << ipinr))
+ handle_IPI(ipinr, regs);
+ }
+ continue;
+ }
+#endif
- break;
} while (1);
}
--
1.7.9.5
^ permalink raw reply related
* [PATCH V2 4/5] arm: mm: Added support for PJ4B cpu and init routines
From: Gregory CLEMENT @ 2012-10-29 21:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351545108-18954-1-git-send-email-gregory.clement@free-electrons.com>
From: Yehuda Yitschak <yehuday@marvell.com>
Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
arch/arm/mach-mvebu/Kconfig | 2 +-
arch/arm/mm/Kconfig | 4 ++++
arch/arm/mm/proc-v7.S | 43 +++++++++++++++++++++++++++++++++++++++++++
3 files changed, 48 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 17d246b..9bfaa0c 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -22,7 +22,7 @@ config MVEBU_CLK_CPU
config MACH_ARMADA_370_XP
bool
select ARMADA_370_XP_TIMER
- select CPU_V7
+ select CPU_PJ4B
config MACH_ARMADA_370
bool "Marvell Armada 370 boards"
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 94186b6..3fd629d 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -352,6 +352,10 @@ config CPU_PJ4
select ARM_THUMBEE
select CPU_V7
+config CPU_PJ4B
+ bool
+ select CPU_V7
+
# ARMv6
config CPU_V6
bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 846d279..1a373c2 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -169,6 +169,39 @@ __v7_ca15mp_setup:
orreq r0, r0, r10 @ Enable CPU-specific SMP bits
mcreq p15, 0, r0, c1, c0, 1
#endif
+
+__v7_pj4b_setup:
+#ifdef CONFIG_CPU_PJ4B
+ /* Auxiliary Debug Modes Control 1 Register */
+ mrc p15, 1, r0, c15, c1, 1
+ orr r0, r0, #(1 << 16) @ Disable data transfer for clean line.
+ orr r0, r0, #(1 << 5) @ Enable the back off of STREX instr
+ orr r0, r0, #(1 << 8) @ Disable Internal Parity Handling
+ bic r0, r0, #(1 << 2) @ Disable Static BP
+ mcr p15, 1, r0, c15, c1, 1
+
+ /* Auxiliary Debug Modes Control 2 Register */
+ mrc p15, 1, r0, c15, c1, 2
+ bic r0, r0, #(1 << 23) @ Enable fast LDR.
+ orr r0, r0, #(1 << 25) @ Dont interleave write and snoop data.
+ orr r0, r0, #(1 << 27) @ Disable Critical Word First feature.
+ orr r0, r0, #(1 << 29) @ Disable outstanding non cacheable request
+ orr r0, r0, #(1 << 30) @ L1 replacement - Strict round robin
+ mcr p15, 1, r0, c15, c1, 2
+
+ /* Auxiliary Functional Modes Control Register 0 */
+ mrc p15, 1, r0, c15, c2, 0
+ orr r0, r0, #(1 << 2) @ Support L1 parity checking
+ orr r0, r0, #(1 << 8) @ Broadcast Cache and TLB maintenance
+ mcr p15, 1, r0, c15, c2, 0
+
+ /* Auxiliary Debug Modes Control 0 Register */
+ mrc p15, 1, r0, c15, c1, 0
+ orr r0, r0, #(1 << 22) @ WFI/WFE - serve the DVM and back to idle
+ mcr p15, 1, r0, c15, c1, 0
+
+#endif /* CONFIG_CPU_PJ4B */
+
__v7_setup:
adr r12, __v7_setup_stack @ the local stack
stmia r12, {r0-r5, r7, r9, r11, lr}
@@ -342,6 +375,16 @@ __v7_ca9mp_proc_info:
.long 0xff0ffff0
__v7_proc __v7_ca9mp_setup
.size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
+
+ /*
+ * Marvell PJ4B processor.
+ */
+ .type __v7_pj4b_proc_info, #object
+__v7_pj4b_proc_info:
+ .long 0x562f5842
+ .long 0xffffffff
+ __v7_proc __v7_pj4b_setup
+ .size __v7_pj4b_proc_info, . - __v7_pj4b_proc_info
#endif /* CONFIG_ARM_LPAE */
/*
--
1.7.9.5
^ permalink raw reply related
* [PATCH V2 5/5] arm: mvebu: Added SMP support for Armada XP
From: Gregory CLEMENT @ 2012-10-29 21:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351545108-18954-1-git-send-email-gregory.clement@free-electrons.com>
From: Yehuda Yitschak <yehuday@marvell.com>
1. added smp init functions in platsmp.c
2. added secondary cpu entry point in headsmp.S
3. added hotplog initial support in hotplug.c
4. added SMP support for PJ4B cpu
Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
arch/arm/boot/dts/armada-xp.dtsi | 4 ++
arch/arm/configs/mvebu_defconfig | 3 +
arch/arm/mach-mvebu/Kconfig | 1 +
arch/arm/mach-mvebu/Makefile | 2 +
arch/arm/mach-mvebu/armada-370-xp.c | 3 +
arch/arm/mach-mvebu/common.h | 3 +
arch/arm/mach-mvebu/headsmp.S | 66 +++++++++++++++++++
arch/arm/mach-mvebu/hotplug.c | 30 +++++++++
arch/arm/mach-mvebu/platsmp.c | 124 +++++++++++++++++++++++++++++++++++
arch/arm/mm/proc-v7.S | 3 +
10 files changed, 239 insertions(+)
create mode 100644 arch/arm/mach-mvebu/headsmp.S
create mode 100644 arch/arm/mach-mvebu/hotplug.c
create mode 100644 arch/arm/mach-mvebu/platsmp.c
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index 531619f..7f968dc 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -38,24 +38,28 @@
#size-cells = <0>;
cpu at 0 {
+ device_type = "cpu";
compatible = "marvell,sheeva-v7";
reg = <0>;
clocks = <&cpuclk 0>;
};
cpu at 1 {
+ device_type = "cpu";
compatible = "marvell,sheeva-v7";
reg = <1>;
clocks = <&cpuclk 1>;
};
cpu at 2 {
+ device_type = "cpu";
compatible = "marvell,sheeva-v7";
reg = <2>;
clocks = <&cpuclk 2>;
};
cpu at 3 {
+ device_type = "cpu";
compatible = "marvell,sheeva-v7";
reg = <3>;
clocks = <&cpuclk 3>;
diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig
index 3458752..da598d3 100644
--- a/arch/arm/configs/mvebu_defconfig
+++ b/arch/arm/configs/mvebu_defconfig
@@ -12,6 +12,9 @@ CONFIG_ARCH_MVEBU=y
CONFIG_MACH_ARMADA_370=y
CONFIG_MACH_ARMADA_XP=y
# CONFIG_CACHE_L2X0 is not set
+# CONFIG_SWP_EMULATE is not set
+CONFIG_SMP=y
+# CONFIG_LOCAL_TIMERS is not set
CONFIG_AEABI=y
CONFIG_HIGHMEM=y
# CONFIG_COMPACTION is not set
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 9bfaa0c..d70afe3 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -22,6 +22,7 @@ config MVEBU_CLK_CPU
config MACH_ARMADA_370_XP
bool
select ARMADA_370_XP_TIMER
+ select HAVE_SMP
select CPU_PJ4B
config MACH_ARMADA_370
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index 8e6e50b..eb3cbd1 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -3,3 +3,5 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
obj-y += system-controller.o
obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o addr-map.o coherency.o pmsu.o
+obj-$(CONFIG_SMP) += platsmp.o headsmp.o
+obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
index 2af6ce5..66befa1 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.c
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -22,6 +22,7 @@
#include <asm/mach/time.h>
#include "armada-370-xp.h"
#include "common.h"
+#include "coherency.h"
static struct map_desc armada_370_xp_io_desc[] __initdata = {
{
@@ -50,6 +51,7 @@ struct sys_timer armada_370_xp_timer = {
static void __init armada_370_xp_dt_init(void)
{
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+ coherency_init();
}
static const char * const armada_370_xp_dt_board_dt_compat[] = {
@@ -59,6 +61,7 @@ static const char * const armada_370_xp_dt_board_dt_compat[] = {
};
DT_MACHINE_START(ARMADA_XP_DT, "Marvell Aramada 370/XP (Device Tree)")
+ .smp = smp_ops(armada_xp_smp_ops),
.init_machine = armada_370_xp_dt_init,
.map_io = armada_370_xp_map_io,
.init_irq = armada_370_xp_init_irq,
diff --git a/arch/arm/mach-mvebu/common.h b/arch/arm/mach-mvebu/common.h
index 74ee0b2..86484bb 100644
--- a/arch/arm/mach-mvebu/common.h
+++ b/arch/arm/mach-mvebu/common.h
@@ -21,7 +21,10 @@ void mvebu_clocks_init(void);
void armada_370_xp_init_irq(void);
void armada_370_xp_handle_irq(struct pt_regs *regs);
+void armada_xp_cpu_die(unsigned int cpu);
int armada_370_xp_coherency_init(void);
int armada_370_xp_pmsu_init(void);
+void armada_xp_secondary_startup(void);
+extern struct smp_operations armada_xp_smp_ops;
#endif
diff --git a/arch/arm/mach-mvebu/headsmp.S b/arch/arm/mach-mvebu/headsmp.S
new file mode 100644
index 0000000..33db1d5
--- /dev/null
+++ b/arch/arm/mach-mvebu/headsmp.S
@@ -0,0 +1,66 @@
+/*
+ * SMP support: Entry point for secondary CPUs
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Yehuda Yitschak <yehuday@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * This file implements the assembly entry point for secondary CPUs
+ * in an SMP kernel. The only thing we need to do is to add the CPU
+ * to the coherency fabric by writing to 2 registers. Currently these
+ * register addresses are hard coded due to the early initialisation problems.
+ */
+
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+/*
+ * At this stage the secondary CPUs don't have acces yet to the MMU, so
+ * we have to provide physical addresses
+ */
+#define ARMADA_XP_COHERENCY_FABRIC_CTL_REG 0xD0020200
+#define ARMADA_XP_COHERENCY_FABRIC_CFG_REG 0xD0020204
+
+ __INIT
+
+/*
+ * Armada XP specific entry point for secondary CPUs.
+ * We add the CPU to the coherency fabric and then jump to secondary
+ * startup
+ */
+
+ENTRY(armada_xp_secondary_startup)
+
+ /* Read CPU id */
+ mrc p15, 0, r1, c0, c0, 5
+ and r1, r1, #0xF
+
+ /* Add CPU to coherency fabric */
+
+ /* Create bit by cpu index */
+ mov r2,r1
+ add r2,r2,#24
+ mov r3, #1
+ lsl r3, r3, r2
+
+ /* Add CPU to SMP group - Atomic */
+ ldr r0, = ARMADA_XP_COHERENCY_FABRIC_CTL_REG
+ ldr r10, [r0]
+ orr r10 , r10, r3
+ str r10,[r0]
+
+ /* Enable coherency on CPU - Atomic*/
+ ldr r0, = ARMADA_XP_COHERENCY_FABRIC_CFG_REG
+ ldr r10, [r0]
+ orr r10 , r10, r3
+ str r10,[r0]
+
+ b secondary_startup
+
+ENDPROC(armada_xp_secondary_startup)
diff --git a/arch/arm/mach-mvebu/hotplug.c b/arch/arm/mach-mvebu/hotplug.c
new file mode 100644
index 0000000..b228b6a
--- /dev/null
+++ b/arch/arm/mach-mvebu/hotplug.c
@@ -0,0 +1,30 @@
+/*
+ * Symmetric Multi Processing (SMP) support for Armada XP
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/smp.h>
+#include <asm/proc-fns.h>
+
+/*
+ * platform-specific code to shutdown a CPU
+ *
+ * Called with IRQs disabled
+ */
+void __ref armada_xp_cpu_die(unsigned int cpu)
+{
+ cpu_do_idle();
+
+ /* We should never return from idle */
+ panic("mvebu: cpu %d unexpectedly exit from shutdown\n", cpu);
+}
diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c
new file mode 100644
index 0000000..1cd6c08
--- /dev/null
+++ b/arch/arm/mach-mvebu/platsmp.c
@@ -0,0 +1,124 @@
+/*
+ * Symmetric Multi Processing (SMP) support for Armada XP
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ * Yehuda Yitschak <yehuday@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * The Armada XP SoC has 4 ARMv7 PJ4B CPUs running in full HW coherency
+ * This file implements the routines for preparing the SMP infrastructure
+ * and waking up the secondary CPUs
+ */
+
+#include <linux/init.h>
+#include <linux/smp.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <asm/cacheflush.h>
+#include <asm/smp_plat.h>
+#include "common.h"
+#include "armada-370-xp.h"
+#include "pmsu.h"
+#include "coherency.h"
+
+void __init set_secondary_cpus_clock(void)
+{
+ int cpu;
+ unsigned long rate;
+ struct clk *cpu_clk = NULL;
+ struct device_node *np = NULL;
+
+ cpu = smp_processor_id();
+ np = of_find_node_by_type(np, "cpu");
+ np = NULL;
+ while ((np = of_find_node_by_type(np, "cpu"))) {
+ const u32 *reg;
+ int len;
+ reg = of_get_property(np, "reg", &len);
+ if (!reg || len != 4) {
+ pr_err("%s missing reg property\n", np->full_name);
+ continue;
+ }
+ if (be32_to_cpup(reg) == cpu) {
+ cpu_clk = of_clk_get(np, 0);
+ break;
+ }
+ }
+ WARN_ON(IS_ERR(cpu_clk));
+ clk_prepare_enable(cpu_clk);
+ rate = clk_get_rate(cpu_clk);
+
+ /* set all the other CPU clk to the same rate than the boot CPU */
+ np = NULL;
+ while ((np = of_find_node_by_type(np, "cpu"))) {
+ const u32 *reg;
+ int len;
+ reg = of_get_property(np, "reg", &len);
+ if (!reg || len != 4) {
+ pr_err("%s missing reg property\n", np->full_name);
+ continue;
+ }
+ if (be32_to_cpup(reg) != cpu) {
+ cpu_clk = of_clk_get(np, 0);
+ clk_set_rate(cpu_clk, rate);
+ }
+ }
+}
+
+static void __cpuinit armada_xp_secondary_init(unsigned int cpu)
+{
+ armada_xp_mpic_smp_cpu_init();
+}
+
+static int __cpuinit armada_xp_boot_secondary(unsigned int cpu,
+ struct task_struct *idle)
+{
+ pr_info("Booting CPU %d\n", cpu);
+
+ armada_xp_boot_cpu(cpu, armada_xp_secondary_startup);
+
+ return 0;
+}
+
+static void __init armada_xp_smp_init_cpus(void)
+{
+ unsigned int i, ncores;
+ ncores = coherency_get_cpu_count();
+
+ /* Limit possbile CPUs to defconfig */
+ if (ncores > nr_cpu_ids) {
+ pr_warn("SMP: %d CPUs physically present. Only %d configured.",
+ ncores, nr_cpu_ids);
+ pr_warn("Clipping CPU count to %d\n", nr_cpu_ids);
+ ncores = nr_cpu_ids;
+ }
+
+ for (i = 0; i < ncores; i++)
+ set_cpu_possible(i, true);
+
+ set_smp_cross_call(armada_mpic_send_doorbell);
+}
+
+void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus)
+{
+ set_secondary_cpus_clock();
+ flush_cache_all();
+ set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0);
+}
+
+struct smp_operations armada_xp_smp_ops __initdata = {
+ .smp_init_cpus = armada_xp_smp_init_cpus,
+ .smp_prepare_cpus = armada_xp_smp_prepare_cpus,
+ .smp_secondary_init = armada_xp_secondary_init,
+ .smp_boot_secondary = armada_xp_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+ .cpu_die = armada_xp_cpu_die,
+#endif
+};
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 1a373c2..dcd97e4 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -191,6 +191,9 @@ __v7_pj4b_setup:
/* Auxiliary Functional Modes Control Register 0 */
mrc p15, 1, r0, c15, c2, 0
+#ifdef CONFIG_SMP
+ orr r0, r0, #(1 << 1) @ Set SMP mode. Join the coherency fabric
+#endif
orr r0, r0, #(1 << 2) @ Support L1 parity checking
orr r0, r0, #(1 << 8) @ Broadcast Cache and TLB maintenance
mcr p15, 1, r0, c15, c2, 0
--
1.7.9.5
^ permalink raw reply related
* [PATCH] watchdog: Support imx watchdog on SOC_IMX53
From: Sascha Hauer @ 2012-10-29 21:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351164513-27999-1-git-send-email-stigge@antcom.de>
On Thu, Oct 25, 2012 at 01:28:33PM +0200, Roland Stigge wrote:
> This patch fixes watchdog support after devicetree switch for imx53
>
> Signed-off-by: Roland Stigge <stigge@antcom.de>
Applied, thanks
Sascha
>
> ---
> arch/arm/mach-imx/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> --- linux-2.6.orig/arch/arm/mach-imx/Kconfig
> +++ linux-2.6/arch/arm/mach-imx/Kconfig
> @@ -739,6 +739,7 @@ config SOC_IMX53
> select ARCH_MX5
> select ARCH_MX53
> select HAVE_CAN_FLEXCAN if CAN
> + select IMX_HAVE_PLATFORM_IMX2_WDT
> select PINCTRL
> select PINCTRL_IMX53
> select SOC_IMX5
>
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply
* [PATCH 1/2] ARM: mach-imx: imx53.dtsi: pinctl update
From: Sascha Hauer @ 2012-10-29 21:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351164400-27940-1-git-send-email-stigge@antcom.de>
On Thu, Oct 25, 2012 at 01:26:39PM +0200, Roland Stigge wrote:
> This patch supplements pinctl support on i.MX53.
>
> Signed-off-by: Roland Stigge <stigge@antcom.de>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Shawn, probably better when you take this patch as it's quite likely
that you collect other patches to this file.
Sascha
> ---
> arch/arm/boot/dts/imx53.dtsi | 46 +++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 46 insertions(+)
>
> --- linux-2.6.orig/arch/arm/boot/dts/imx53.dtsi
> +++ linux-2.6/arch/arm/boot/dts/imx53.dtsi
> @@ -316,6 +316,24 @@
> };
> };
>
> + can1 {
> + pinctrl_can1_1: can1grp-1 {
> + fsl,pins = <
> + 847 0x80000000 /* MX53_PAD_PATA_INTRQ__CAN1_TXCAN */
> + 853 0x80000000 /* MX53_PAD_PATA_DIOR__CAN1_RXCAN */
> + >;
> + };
> + };
> +
> + can2 {
> + pinctrl_can2_1: can2grp-1 {
> + fsl,pins = <
> + 67 0x80000000 /* MX53_PAD_KEY_COL4__CAN2_TXCAN */
> + 74 0x80000000 /* MX53_PAD_KEY_ROW4__CAN2_RXCAN */
> + >;
> + };
> + };
> +
> i2c1 {
> pinctrl_i2c1_1: i2c1grp-1 {
> fsl,pins = <
> @@ -334,6 +352,15 @@
> };
> };
>
> + i2c3 {
> + pinctrl_i2c3_1: i2c3grp-1 {
> + fsl,pins = <
> + 1102 0xc0000000 /* MX53_PAD_GPIO_6__I2C3_SDA */
> + 1130 0xc0000000 /* MX53_PAD_GPIO_5__I2C3_SCL */
> + >;
> + };
> + };
> +
> uart1 {
> pinctrl_uart1_1: uart1grp-1 {
> fsl,pins = <
> @@ -369,6 +396,25 @@
> >;
> };
> };
> +
> + uart4 {
> + pinctrl_uart4_1: uart4grp-1 {
> + fsl,pins = <
> + 11 0x1c5 /* MX53_PAD_KEY_COL0__UART4_TXD_MUX */
> + 18 0x1c5 /* MX53_PAD_KEY_ROW0__UART4_RXD_MUX */
> + >;
> + };
> + };
> +
> + uart5 {
> + pinctrl_uart5_1: uart5grp-1 {
> + fsl,pins = <
> + 24 0x1c5 /* MX53_PAD_KEY_COL1__UART5_TXD_MUX */
> + 31 0x1c5 /* MX53_PAD_KEY_ROW1__UART5_RXD_MUX */
> + >;
> + };
> + };
> +
> };
>
> uart1: serial at 53fbc000 {
>
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply
* [PATCH 2/2] ARM: mach-imx: CAN clock fix for i.MX53
From: Sascha Hauer @ 2012-10-29 21:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351164400-27940-2-git-send-email-stigge@antcom.de>
Roland,
Do you have updates on this one? I think this patch is wrong, specifying
the clock rate in the devicetree is only for PowerPC, so I think this
needs further investigation.
Sascha
On Thu, Oct 25, 2012 at 01:26:40PM +0200, Roland Stigge wrote:
> This patch fixes CAN clocking on i.MX53.
>
> Signed-off-by: Roland Stigge <stigge@antcom.de>
>
> ---
> arch/arm/mach-imx/clk-imx51-imx53.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> --- linux-2.6.orig/arch/arm/mach-imx/clk-imx51-imx53.c
> +++ linux-2.6/arch/arm/mach-imx/clk-imx51-imx53.c
> @@ -426,10 +426,10 @@ int __init mx53_clocks_init(unsigned lon
> clk[usb_phy2_gate] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12);
> clk[can_sel] = imx_clk_mux("can_sel", MXC_CCM_CSCMR2, 6, 2,
> mx53_can_sel, ARRAY_SIZE(mx53_can_sel));
> - clk[can1_serial_gate] = imx_clk_gate2("can1_serial_gate", "can_sel", MXC_CCM_CCGR6, 22);
> - clk[can1_ipg_gate] = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR6, 20);
> - clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8);
> - clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6);
> + clk[can1_serial_gate] = imx_clk_gate2("can1_serial_gate", "can_sel", MXC_CCM_CCGR4, 6);
> + clk[can1_ipg_gate] = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR4, 8);
> + clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 6);
> + clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 8);
> clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
>
> for (i = 0; i < ARRAY_SIZE(clk); i++)
>
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply
* [PATCH] at91sam9m10g45-ek: rename leds to match board
From: Alexandre Belloni @ 2012-10-29 21:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121029161445.GB31214@game.jcrosoft.org>
On Mon, Oct 29, 2012 at 05:14:45PM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote :
> No here it's different teh same HW have different revision
>
> m10g45es
> m10ekes
> 9g45ekes
>
> the m10ekes is the first one and the leds does match
>
> So I agree we can put a comment in the c or the dts about it but do not change
> the content as the board support is like this for really long time
> And I do not want to ebd-up with 2 or 3 dts jsut for lesd naming
> That I will have to maintain
>
>From my discussion with atmel last week, I understood that the only
publicly available board is the m10g45ek. Support for the other boards
you mention is actually being dropped and you can't find them on ATMEL's
website anymore.
So, I agree you should support only one configuration but at least, let
it be the one for the current board.
Regards,
--
Alexandre Belloni
^ permalink raw reply
* [PATCH 2/2] ARM: mach-imx: CAN clock fix for i.MX53
From: Roland Stigge @ 2012-10-29 21:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121029212043.GA1641@pengutronix.de>
On 29/10/12 22:20, Sascha Hauer wrote:
> Roland,
>
> Do you have updates on this one? I think this patch is wrong, specifying
> the clock rate in the devicetree is only for PowerPC, so I think this
> needs further investigation.
Please ignore it for now. As discussed with Marc, the issue seemed to be
caused by me (wrongfully) using the "clock-frequency" dt property which
caused probe() to ignore the clocks.
A colleague of mine will notify me if the problem surfaces again. So for
now I assume it's gone.
Maybe the above strategy regarding "clock-frequency" needs to be
documented better or changed, though, to prevent more confusion like in
the above case.
Thanks,
Roland
> On Thu, Oct 25, 2012 at 01:26:40PM +0200, Roland Stigge wrote:
>> This patch fixes CAN clocking on i.MX53.
>>
>> Signed-off-by: Roland Stigge <stigge@antcom.de>
>>
>> ---
>> arch/arm/mach-imx/clk-imx51-imx53.c | 8 ++++----
>> 1 file changed, 4 insertions(+), 4 deletions(-)
>>
>> --- linux-2.6.orig/arch/arm/mach-imx/clk-imx51-imx53.c
>> +++ linux-2.6/arch/arm/mach-imx/clk-imx51-imx53.c
>> @@ -426,10 +426,10 @@ int __init mx53_clocks_init(unsigned lon
>> clk[usb_phy2_gate] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12);
>> clk[can_sel] = imx_clk_mux("can_sel", MXC_CCM_CSCMR2, 6, 2,
>> mx53_can_sel, ARRAY_SIZE(mx53_can_sel));
>> - clk[can1_serial_gate] = imx_clk_gate2("can1_serial_gate", "can_sel", MXC_CCM_CCGR6, 22);
>> - clk[can1_ipg_gate] = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR6, 20);
>> - clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8);
>> - clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6);
>> + clk[can1_serial_gate] = imx_clk_gate2("can1_serial_gate", "can_sel", MXC_CCM_CCGR4, 6);
>> + clk[can1_ipg_gate] = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR4, 8);
>> + clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 6);
>> + clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 8);
>> clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
>>
>> for (i = 0; i < ARRAY_SIZE(clk); i++)
>>
>
^ permalink raw reply
* [PATCH] ARM: dts: imx27-3ds: Remove local watchdog inclusion
From: Sascha Hauer @ 2012-10-29 21:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1348661261-7124-1-git-send-email-festevam@gmail.com>
On Wed, Sep 26, 2012 at 09:07:41AM -0300, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam@freescale.com>
>
> imx27.dtsi already register the watchdog, so no need to do it in the board dts
> file.
>
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Applied, thanks
Sascha
> ---
> arch/arm/boot/dts/imx27-3ds.dts | 4 ----
> 1 file changed, 4 deletions(-)
>
> diff --git a/arch/arm/boot/dts/imx27-3ds.dts b/arch/arm/boot/dts/imx27-3ds.dts
> index 0a8978a..b01c0d7 100644
> --- a/arch/arm/boot/dts/imx27-3ds.dts
> +++ b/arch/arm/boot/dts/imx27-3ds.dts
> @@ -23,10 +23,6 @@
> soc {
> aipi at 10000000 { /* aipi */
>
> - wdog at 10002000 {
> - status = "okay";
> - };
> -
> uart1: serial at 1000a000 {
> fsl,uart-has-rtscts;
> status = "okay";
> --
> 1.7.9.5
>
>
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply
* [PATCH] MMC: fix sdhci-dove removal
From: Russell King - ARM Linux @ 2012-10-29 21:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <87txtdq90y.fsf@octavius.laptop.org>
On Mon, Oct 29, 2012 at 05:10:37PM -0400, Chris Ball wrote:
> Hi Russell,
>
> On Mon, Oct 15 2012, Russell King - ARM Linux wrote:
> > Here's an updated patch which just about fixes the sdhci-dove driver.
> > I would not be surprised given the idiotic sdhci-pltfm API if many
> > other drivers suffered the same bug.
> >
> > 8<====
> > From: Russell King <rmk+kernel@arm.linux.org.uk>
> > Subject: [PATCH] MMC: fix sdhci-dove probe/removal
> >
> > 1. Never ever publish a device in the system before it has been setup
> > to a usable state.
> > 2. Unregister the device _BEFORE_ taking away any resources it may be
> > using.
> > 3. Don't check clks against NULL.
> >
> > Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
>
> This version of the patch doesn't apply cleanly or compile -- maybe you
> have a later revision?
Well, I'm only going to send a patch against 3.6 because that's the
kernel I'm running on the cubox - which is the platform I'm finding
these bugs on. As it's a platform which I want to keep stable for
other work, it's not getting -rc kernels on it.
It's also been through several revisions across conflict resolutions
which is why the above errors occurred (thanks to having to fix them
up multiple times.) And to top it off, there's additional patches
below this one too, so separating out just the fix is virtually
impossible to do safely.
Anyway, here's a replacement patch, updated against my cubox tree but
lacking the cubox gpio changes for it. Un-tested through: (a) I can't
test this on its own on the cubox, (b) I don't have a separate dove
tree to test it against and my disk space is all but out at the moment
for yet another build tree...
It would helpful of course to have _more_ of the cubox stuff in mainline
but unfortunately it's all non-DT so wouldn't be accepted.
drivers/mmc/host/sdhci-dove.c | 38 ++++++++++++++++++++------------------
1 files changed, 20 insertions(+), 18 deletions(-)
diff --git a/drivers/mmc/host/sdhci-dove.c b/drivers/mmc/host/sdhci-dove.c
index a6e53a1..bb3cefe 100644
--- a/drivers/mmc/host/sdhci-dove.c
+++ b/drivers/mmc/host/sdhci-dove.c
@@ -19,6 +19,7 @@
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
+#include <linux/err.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/err.h>
@@ -83,30 +84,32 @@ static int __devinit sdhci_dove_probe(struct platform_device *pdev)
struct sdhci_dove_priv *priv;
int ret;
- ret = sdhci_pltfm_register(pdev, &sdhci_dove_pdata);
- if (ret)
- goto sdhci_dove_register_fail;
-
priv = devm_kzalloc(&pdev->dev, sizeof(struct sdhci_dove_priv),
GFP_KERNEL);
if (!priv) {
dev_err(&pdev->dev, "unable to allocate private data");
- ret = -ENOMEM;
- goto sdhci_dove_allocate_fail;
+ return -ENOMEM;
}
+ priv->clk = clk_get(&pdev->dev, NULL);
+ if (!IS_ERR(priv->clk))
+ clk_prepare_enable(priv->clk);
+
+ ret = sdhci_pltfm_register(pdev, &sdhci_dove_pdata);
+ if (ret)
+ goto sdhci_dove_register_fail;
+
host = platform_get_drvdata(pdev);
pltfm_host = sdhci_priv(host);
pltfm_host->priv = priv;
- priv->clk = clk_get(&pdev->dev, NULL);
- if (!IS_ERR(priv->clk))
- clk_prepare_enable(priv->clk);
return 0;
-sdhci_dove_allocate_fail:
- sdhci_pltfm_unregister(pdev);
sdhci_dove_register_fail:
+ if (!IS_ERR(priv->clk)) {
+ clk_disable_unprepare(priv->clk);
+ clk_put(priv->clk);
+ }
return ret;
}
@@ -116,14 +119,13 @@ static int __devexit sdhci_dove_remove(struct platform_device *pdev)
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
struct sdhci_dove_priv *priv = pltfm_host->priv;
- if (priv->clk) {
- if (!IS_ERR(priv->clk)) {
- clk_disable_unprepare(priv->clk);
- clk_put(priv->clk);
- }
- devm_kfree(&pdev->dev, priv->clk);
+ sdhci_pltfm_unregister(pdev);
+
+ if (!IS_ERR(priv->clk)) {
+ clk_disable_unprepare(priv->clk);
+ clk_put(priv->clk);
}
- return sdhci_pltfm_unregister(pdev);
+ return 0;
}
static struct platform_driver sdhci_dove_driver = {
^ permalink raw reply related
* [PATCH 4/4] DMA: PL330: add device tree property for DMA_MEMCPY capability
From: Jassi Brar @ 2012-10-29 21:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351504796-24788-5-git-send-email-b.zolnierkie@samsung.com>
On Mon, Oct 29, 2012 at 10:59 AM, Bartlomiej Zolnierkiewicz
<b.zolnierkie@samsung.com> wrote:
> * Add device tree (DT) property ("pl330,dma-memcpy") for DMA_MEMCPY
> capability and instead of setting this capability unconditionally
> in pl330_probe() do it only when property is present.
>
Perhaps we should pass the array of peripheral interfaces via DT, the
lack of which could imply MEMCPY capability ? (while it works, I doubt
if pl330 is supposed to have SLAVE and MEMCPY capabilities in any
instance)
That would also be a step towards discarding "struct dma_pl330_platdata".
^ permalink raw reply
* [PATCH 1/4] DMA: PL330: fix locking in pl330_free_chan_resources()
From: Jassi Brar @ 2012-10-29 21:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351504796-24788-2-git-send-email-b.zolnierkie@samsung.com>
On Mon, Oct 29, 2012 at 10:59 AM, Bartlomiej Zolnierkiewicz
<b.zolnierkie@samsung.com> wrote:
> tasklet_kill() may sleep so call it before taking pch->lock.
>
> Fixes following lockup:
>
> [ 345.470000] BUG: scheduling while atomic: cat/2383/0x00000002
> [ 345.470000] Modules linked in:
> [ 345.470000] [<c0015858>] (unwind_backtrace+0x0/0xfc) from [<c004d980>] (__schedule_bug+0x4c/0x58)
> [ 345.470000] [<c004d980>] (__schedule_bug+0x4c/0x58) from [<c0360b6c>] (__schedule+0x690/0x6e0)
> [ 345.470000] [<c0360b6c>] (__schedule+0x690/0x6e0) from [<c004f2b4>] (sys_sched_yield+0x70/0x78)
> [ 345.470000] [<c004f2b4>] (sys_sched_yield+0x70/0x78) from [<c002acec>] (tasklet_kill+0x34/0x8c)
> [ 345.470000] [<c002acec>] (tasklet_kill+0x34/0x8c) from [<c01da4cc>] (pl330_free_chan_resources+0x24/0x88)
> [ 345.470000] [<c01da4cc>] (pl330_free_chan_resources+0x24/0x88) from [<c01d81f4>] (dma_chan_put+0x4c/0x50)
> [ 345.470000] [<c01d81f4>] (dma_chan_put+0x4c/0x50) from [<c01d82c0>] (dma_release_channel+0x28/0x98)
> [...]
> [ 368.335000] BUG: spinlock lockup suspected on CPU#0, swapper/0/0
> [ 368.340000] lock: 0xe52aa04c, .magic: dead4ead, .owner: cat/2383, .owner_cpu: 1
> [ 368.350000] [<c0015858>] (unwind_backtrace+0x0/0xfc) from [<c01b3d78>] (do_raw_spin_lock+0x194/0x204)
> [ 368.360000] [<c01b3d78>] (do_raw_spin_lock+0x194/0x204) from [<c0361adc>] (_raw_spin_lock_irqsave+0x20/0x28)
> [ 368.365000] [<c0361adc>] (_raw_spin_lock_irqsave+0x20/0x28) from [<c01da80c>] (pl330_tasklet+0x2c/0x5a8)
> [ 368.375000] [<c01da80c>] (pl330_tasklet+0x2c/0x5a8) from [<c002ac04>] (tasklet_action+0xfc/0x114)
> [ 368.385000] [<c002ac04>] (tasklet_action+0xfc/0x114) from [<c002b204>] (__do_softirq+0xe4/0x19c)
> [ 368.395000] [<c002b204>] (__do_softirq+0xe4/0x19c) from [<c002b398>] (irq_exit+0x98/0x9c)
> [ 368.405000] [<c002b398>] (irq_exit+0x98/0x9c) from [<c0013ebc>] (handle_IPI+0x124/0x16c)
> [ 368.410000] [<c0013ebc>] (handle_IPI+0x124/0x16c) from [<c000857c>] (gic_handle_irq+0x64/0x68)
> [ 368.420000] [<c000857c>] (gic_handle_irq+0x64/0x68) from [<c000e740>] (__irq_svc+0x40/0x70)
> [ 368.430000] Exception stack(0xc04a3f00 to 0xc04a3f48)
> [ 368.435000] 3f00: c04a3f48 00000000 6f9e23e8 00000050 c07492c8 c04a3f48 00000000 c04ccc88
> [ 368.440000] 3f20: 6f9dbac3 00000050 6f9e23e8 00000050 3b9aca00 c04a3f48 c005cfa4 c02946d4
> [ 368.450000] 3f40: 60000013 ffffffff
> [ 368.455000] [<c000e740>] (__irq_svc+0x40/0x70) from [<c02946d4>] (cpuidle_wrap_enter+0x4c/0xa0)
> [ 368.460000] [<c02946d4>] (cpuidle_wrap_enter+0x4c/0xa0) from [<c02940dc>] (cpuidle_enter_state+0x18/0x68)
> [ 368.470000] [<c02940dc>] (cpuidle_enter_state+0x18/0x68) from [<c02948e0>] (cpuidle_idle_call+0xac/0xe0)
> [ 368.480000] [<c02948e0>] (cpuidle_idle_call+0xac/0xe0) from [<c00102f8>] (cpu_idle+0xac/0xf0)
> [ 368.490000] [<c00102f8>] (cpu_idle+0xac/0xf0) from [<c04796a0>] (start_kernel+0x28c/0x294)
>
> Cc: Jassi Brar <jassisinghbrar@gmail.com>
> Cc: Vinod Koul <vinod.koul@linux.intel.com>
> Cc: Tomasz Figa <t.figa@samsung.com>
> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
> ---
> drivers/dma/pl330.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
> index 665668b..db7574b 100644
> --- a/drivers/dma/pl330.c
> +++ b/drivers/dma/pl330.c
> @@ -2459,10 +2459,10 @@ static void pl330_free_chan_resources(struct dma_chan *chan)
> struct dma_pl330_chan *pch = to_pchan(chan);
> unsigned long flags;
>
> - spin_lock_irqsave(&pch->lock, flags);
> -
> tasklet_kill(&pch->task);
>
> + spin_lock_irqsave(&pch->lock, flags);
> +
> pl330_release_channel(pch->pl330_chid);
> pch->pl330_chid = NULL;
>
Thanks.
Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
^ permalink raw reply
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