* [PATCH 11/15] ARM: OMAP: timer: Interchange clksrc and clkevt for AM33XX
From: Santosh Shilimkar @ 2012-11-03 16:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351859566-24818-12-git-send-email-vaibhav.bedia@ti.com>
On Friday 02 November 2012 06:02 PM, Vaibhav Bedia wrote:
> AM33XX has only one usable timer in the WKUP domain.
> Currently the timer instance in WKUP domain is used
> as the clockevent and the timer in non-WKUP domain
> as the clocksource. The timer in WKUP domain can keep
> running in suspend from a 32K clock and hence serve
> as the persistent clock. To enable this, interchange
> the timers used as clocksource and clockevent for
> AM33XX. A subsequent patch will add suspend-resume
> support for the clockevent to ensure that there are
> no issues with timekeeping.
>
> Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
> ---
> arch/arm/mach-omap2/timer.c | 2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
> index 565e575..6584ee0 100644
> --- a/arch/arm/mach-omap2/timer.c
> +++ b/arch/arm/mach-omap2/timer.c
> @@ -460,7 +460,7 @@ OMAP_SYS_TIMER(3_secure)
> #endif
>
> #ifdef CONFIG_SOC_AM33XX
> -OMAP_SYS_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, 2, OMAP4_MPU_SOURCE)
> +OMAP_SYS_TIMER_INIT(3_am33xx, 2, OMAP4_MPU_SOURCE, 1, OMAP4_MPU_SOURCE)
> OMAP_SYS_TIMER(3_am33xx)
> #endif
>
As mentioned on other patch comment, I think this might break your
SOC idle.
Regards
Santosh
^ permalink raw reply
* [PATCH 09/15] ARM: OMAP: AM33XX: Remove unnecessary include and use __ASSEMBLER__ macros
From: Santosh Shilimkar @ 2012-11-03 16:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351859566-24818-10-git-send-email-vaibhav.bedia@ti.com>
On Friday 02 November 2012 06:02 PM, Vaibhav Bedia wrote:
> Get rid of some unnecessary header file inclusions
> and also use __ASSEMBLER__ macros to allow the
> various register offsets from PM assembly code
> which be added in a subsequent patch.
>
> Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
Ideally you should split header clean-up and assembler
fix in seperate patches.
Regards
Santosh
^ permalink raw reply
* [PATCH 11/15] ARM: OMAP: timer: Interchange clksrc and clkevt for AM33XX
From: Kevin Hilman @ 2012-11-03 16:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351859566-24818-12-git-send-email-vaibhav.bedia@ti.com>
On 11/02/2012 12:32 PM, Vaibhav Bedia wrote:
> AM33XX has only one usable timer in the WKUP domain.
After reading the TRM, it seems there are two: DMTIMER0 and DMTIMER1.
Looking at the hwmod data though, I don't see a hwmod for DMTIMER0. Can
you explain a little about why DMTIMER0 is missing/broken?
Kevin
^ permalink raw reply
* [PATCH 08/15] ARM: OMAP2+: hwmod: Fix the omap_hwmod_addr_space for CPGMAC0
From: Santosh Shilimkar @ 2012-11-03 16:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351859566-24818-9-git-send-email-vaibhav.bedia@ti.com>
On Friday 02 November 2012 06:02 PM, Vaibhav Bedia wrote:
> The first entry for CPGMAC0 should be ADDR_MAP_ON_INIT
> instead of ADDR_TYPE_RT to ensure the omap hwmod code
> maps the memory space at init and writes to the SYSCONFIG
> registers.
>
> Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
> ---
Sorry again similar question.
Why CPGMAC0 should be mapped and sysconfig updated early ?
Regards
Santosh
^ permalink raw reply
* [PATCH 06/15] ARM: OMAP2+: hwmod: Enable OCMCRAM registration in AM33XX
From: Santosh Shilimkar @ 2012-11-03 16:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351859566-24818-7-git-send-email-vaibhav.bedia@ti.com>
On Friday 02 November 2012 06:02 PM, Vaibhav Bedia wrote:
> The hwmod data for OCMCRAM in AM33XX was commented out.
> This data is needed by the power management code, hence
> uncomment the same and register the OCP interface for it.
>
Why this data is needed by PM code ?
Regards
Santosh
^ permalink raw reply
* [PATCH 05/15] ARM: OMAP2+: AM33XX: Update WKUP_M3 hwmod entry for reset status
From: Santosh Shilimkar @ 2012-11-03 16:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351859566-24818-6-git-send-email-vaibhav.bedia@ti.com>
On Friday 02 November 2012 06:02 PM, Vaibhav Bedia wrote:
> Add the reset status offset for WKUP_M3 in the hwmod data
>
> Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
> ---
> arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 1 +
> 1 files changed, 1 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
> index 3c235d8..2e470ce 100644
> --- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
> @@ -269,6 +269,7 @@ static struct omap_hwmod am33xx_wkup_m3_hwmod = {
> .omap4 = {
> .clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
> .rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
> + .rstst_offs = AM33XX_RM_WKUP_RSTST_OFFSET,
> .modulemode = MODULEMODE_SWCTRL,
> },
> },
>
You are adding reset bit in this patch but using it in 4/15. Probably
you can re-order it to keep git bisect happy.
Regards
Santosh
^ permalink raw reply
* [PATCH 03/15] ARM: OMAP: mailbox: Convert to device_initcall
From: Santosh Shilimkar @ 2012-11-03 16:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351859566-24818-4-git-send-email-vaibhav.bedia@ti.com>
On Friday 02 November 2012 06:02 PM, Vaibhav Bedia wrote:
> The power management code for AM33XX is a late_initcall
> and the PM features depend on the mailbox for IPC.
> In preparation for this, convert the mailbox init to
> a device_initcall.
>
> Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
> ---
Looks fine
^ permalink raw reply
* [PATCH 02/15] ARM: OMAP2+: mailbox: Add support for AM33XX
From: Santosh Shilimkar @ 2012-11-03 16:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351859566-24818-3-git-send-email-vaibhav.bedia@ti.com>
On Friday 02 November 2012 06:02 PM, Vaibhav Bedia wrote:
> Mailbox IP on AM33XX, is the same as that present
> in OMAP4. The single instance of Mailbox module
> contains 8 sub-modules and facilitates communication
> between MPU, PRUs and WKUP_M3.
>
> The first mailbox sub-module is assigned for
> communication between MPU and WKUP-M3.
>
> Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
> ---
> arch/arm/mach-omap2/mailbox.c | 35 ++++++++++++++++++++++++++++++++++-
> 1 files changed, 34 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
> index f38b4fa..7a343aa 100644
> --- a/arch/arm/mach-omap2/mailbox.c
> +++ b/arch/arm/mach-omap2/mailbox.c
> @@ -155,7 +155,7 @@ static void omap2_mbox_disable_irq(struct omap_mbox *mbox,
> struct omap_mbox2_priv *p = mbox->priv;
> u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
>
> - if (!cpu_is_omap44xx())
> + if (!cpu_is_omap44xx() || !soc_is_am33xx())
> bit = mbox_read_reg(p->irqdisable) & ~bit;
>
> mbox_write_reg(bit, p->irqdisable);
> @@ -358,6 +358,32 @@ struct omap_mbox mbox_2_info = {
> struct omap_mbox *omap4_mboxes[] = { &mbox_1_info, &mbox_2_info, NULL };
> #endif
>
> +#if defined(CONFIG_SOC_AM33XX)
> +static struct omap_mbox2_priv omap2_mbox_wkup_m3_priv = {
> + .tx_fifo = {
> + .msg = MAILBOX_MESSAGE(0),
> + .fifo_stat = MAILBOX_FIFOSTATUS(0),
> + .msg_stat = MAILBOX_MSGSTATUS(0),
> + },
> + .rx_fifo = {
> + .msg = MAILBOX_MESSAGE(1),
> + .msg_stat = MAILBOX_MSGSTATUS(1),
> + },
> + .irqenable = OMAP4_MAILBOX_IRQENABLE(3),
> + .irqstatus = OMAP4_MAILBOX_IRQSTATUS(3),
> + .irqdisable = OMAP4_MAILBOX_IRQENABLE_CLR(3),
> + .notfull_bit = MAILBOX_IRQ_NOTFULL(0),
> + .newmsg_bit = MAILBOX_IRQ_NEWMSG(0),
> +};
> +
> +struct omap_mbox mbox_wkup_m3_info = {
> + .name = "wkup_m3",
> + .ops = &omap2_mbox_ops,
> + .priv = &omap2_mbox_wkup_m3_priv,
> +};
> +struct omap_mbox *am33xx_mboxes[] = { &mbox_wkup_m3_info, NULL };
> +#endif
> +
> static int __devinit omap2_mbox_probe(struct platform_device *pdev)
> {
> struct resource *mem;
> @@ -392,6 +418,13 @@ static int __devinit omap2_mbox_probe(struct platform_device *pdev)
> list[0]->irq = list[1]->irq = platform_get_irq(pdev, 0);
> }
> #endif
> +#if defined(CONFIG_SOC_AM33XX)
> + else if (soc_is_am33xx()) {
> + list = am33xx_mboxes;
> +
> + list[0]->irq = platform_get_irq(pdev, 0);
> + }
> +#endif
#ifdef in middle of the function looks really ugly. But I can't complain
just for your patch because looks like rest of the mailbox code is
flooded with #ifdeffery.
Mailbox needs cleanup. and probably can be moved out of
arch/arm/*omap*/ to some driver directory.
Regards
santosh
inside arch/arm/mach-omap2/* directory.
^ permalink raw reply
* [PATCH 01/15] ARM: OMAP2+: mailbox: Add an API for flushing the FIFO
From: Santosh Shilimkar @ 2012-11-03 16:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351859566-24818-2-git-send-email-vaibhav.bedia@ti.com>
On Friday 02 November 2012 06:02 PM, Vaibhav Bedia wrote:
> On AM33XX, the mailbox module between the MPU and the
> WKUP-M3 co-processor facilitates a one-way communication.
> MPU uses the assigned mailbox sub-module to issue the
> interrupt to the WKUP-M3 co-processor which then goes
> and reads the the IPC data from registers in the control
> module.
>
> WKUP-M3 is in the L4_WKUP and does not have any access to
> the Mailbox module. Due to this limitation, the MPU is
> completely responsible for FIFO maintenance and interrupt
> generation. MPU needs to ensure that the FIFO does not
> overflow by reading by the assigned mailbox sub-module.
>
> This patch adds an API in the mailbox code which the MPU
> can use to empty the FIFO by issuing a readback command.
>
> Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
> ---
> arch/arm/mach-omap2/mailbox.c | 42 ++++++++++++++++++++---------
> arch/arm/plat-omap/include/plat/mailbox.h | 3 ++
> arch/arm/plat-omap/mailbox.c | 35 ++++++++++++++++++++++++
> 3 files changed, 67 insertions(+), 13 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
> index 0d97456..f38b4fa 100644
> --- a/arch/arm/mach-omap2/mailbox.c
> +++ b/arch/arm/mach-omap2/mailbox.c
> @@ -123,6 +123,20 @@ static int omap2_mbox_fifo_full(struct omap_mbox *mbox)
> return mbox_read_reg(fifo->fifo_stat);
> }
>
> +static int omap2_mbox_fifo_needs_flush(struct omap_mbox *mbox)
> +{
> + struct omap_mbox2_fifo *fifo =
> + &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
type casting is generally avoided in linux code.
> + return mbox_read_reg(fifo->msg_stat);
> +}
> +
> +static mbox_msg_t omap2_mbox_fifo_readback(struct omap_mbox *mbox)
> +{
> + struct omap_mbox2_fifo *fifo =
> + &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
> + return (mbox_msg_t) mbox_read_reg(fifo->msg);
same here.
> +}
> +
> /* Mailbox IRQ handle functions */
> static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
> omap_mbox_type_t irq)
> @@ -205,19 +219,21 @@ static void omap2_mbox_restore_ctx(struct omap_mbox *mbox)
> }
>
> static struct omap_mbox_ops omap2_mbox_ops = {
> - .type = OMAP_MBOX_TYPE2,
> - .startup = omap2_mbox_startup,
> - .shutdown = omap2_mbox_shutdown,
> - .fifo_read = omap2_mbox_fifo_read,
> - .fifo_write = omap2_mbox_fifo_write,
> - .fifo_empty = omap2_mbox_fifo_empty,
> - .fifo_full = omap2_mbox_fifo_full,
> - .enable_irq = omap2_mbox_enable_irq,
> - .disable_irq = omap2_mbox_disable_irq,
> - .ack_irq = omap2_mbox_ack_irq,
> - .is_irq = omap2_mbox_is_irq,
> - .save_ctx = omap2_mbox_save_ctx,
> - .restore_ctx = omap2_mbox_restore_ctx,
> + .type = OMAP_MBOX_TYPE2,
> + .startup = omap2_mbox_startup,
> + .shutdown = omap2_mbox_shutdown,
> + .fifo_read = omap2_mbox_fifo_read,
> + .fifo_write = omap2_mbox_fifo_write,
> + .fifo_empty = omap2_mbox_fifo_empty,
> + .fifo_full = omap2_mbox_fifo_full,
> + .fifo_needs_flush = omap2_mbox_fifo_needs_flush,
> + .fifo_readback = omap2_mbox_fifo_readback,
> + .enable_irq = omap2_mbox_enable_irq,
> + .disable_irq = omap2_mbox_disable_irq,
> + .ack_irq = omap2_mbox_ack_irq,
> + .is_irq = omap2_mbox_is_irq,
> + .save_ctx = omap2_mbox_save_ctx,
> + .restore_ctx = omap2_mbox_restore_ctx,
You should do the indentation fix in another patch.
> };
>
> /*
> diff --git a/arch/arm/plat-omap/include/plat/mailbox.h b/arch/arm/plat-omap/include/plat/mailbox.h
> index cc3921e..e136529 100644
> --- a/arch/arm/plat-omap/include/plat/mailbox.h
> +++ b/arch/arm/plat-omap/include/plat/mailbox.h
> @@ -29,6 +29,8 @@ struct omap_mbox_ops {
> void (*fifo_write)(struct omap_mbox *mbox, mbox_msg_t msg);
> int (*fifo_empty)(struct omap_mbox *mbox);
> int (*fifo_full)(struct omap_mbox *mbox);
> + int (*fifo_needs_flush)(struct omap_mbox *mbox);
> + mbox_msg_t (*fifo_readback)(struct omap_mbox *mbox);
Do you think passing the msg structure as an argument and letting the
function populate it will be better instead of returning the msg
structure ? No strong opinion since from read_foo() point of view
what you have done might be right thing. In either case, please
get rid of typecasting.
Regards
Santosh
^ permalink raw reply
* [PATCH 2/2] ARM: dts: mxs: Add hog pins to Crystalfontz boards
From: Maxime Ripard @ 2012-11-03 15:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351958348-7327-1-git-send-email-maxime.ripard@free-electrons.com>
Use a hog_pins pinctrl group to force the muxing of GPIOs used on the
Crystalfonz CFA10036 and CFA10049 boards.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/imx28-cfa10036.dts | 13 +++++++++++++
arch/arm/boot/dts/imx28-cfa10049.dts | 16 ++++++++++++++++
2 files changed, 29 insertions(+)
diff --git a/arch/arm/boot/dts/imx28-cfa10036.dts b/arch/arm/boot/dts/imx28-cfa10036.dts
index 8760b87..1594694 100644
--- a/arch/arm/boot/dts/imx28-cfa10036.dts
+++ b/arch/arm/boot/dts/imx28-cfa10036.dts
@@ -23,6 +23,19 @@
apb at 80000000 {
apbh at 80000000 {
pinctrl at 80018000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&hog_pins_cfa10036>;
+
+ hog_pins_cfa10036: hog-10036 at 0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ 0x2073 /* MX28_PAD_SSP0_D7__GPIO_2_7 */
+ >;
+ fsl,drive-strength = <0>;
+ fsl,voltage = <1>;
+ fsl,pull-up = <0>;
+ };
+
led_pins_cfa10036: leds-10036 at 0 {
reg = <0>;
fsl,pinmux-ids = <
diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts
index 6c4c071..bdc80a4 100644
--- a/arch/arm/boot/dts/imx28-cfa10049.dts
+++ b/arch/arm/boot/dts/imx28-cfa10049.dts
@@ -22,6 +22,22 @@
apb at 80000000 {
apbh at 80000000 {
pinctrl@80018000 {
+ pinctrl-names = "default", "default";
+ pinctrl-1 = <&hog_pins_cfa10049>;
+
+ hog_pins_cfa10049: hog-10049 at 0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ 0x0073 /* MX28_PAD_GPMI_D7__GPIO_0_7 */
+ 0x1163 /* MX28_PAD_LCD_D22__GPIO_1_22 */
+ 0x1173 /* MX28_PAD_LCD_D22__GPIO_1_23 */
+ 0x2153 /* MX28_PAD_SSP2_D5__GPIO_2_21 */
+ >;
+ fsl,drive-strength = <0>;
+ fsl,voltage = <1>;
+ fsl,pull-up = <0>;
+ };
+
spi3_pins_cfa10049: spi3-cfa10049 at 0 {
reg = <0>;
fsl,pinmux-ids = <
--
1.7.9.5
^ permalink raw reply related
* [PATCH 1/2] ARM: dts: cfa10036: Use pinctrl for power led
From: Maxime Ripard @ 2012-11-03 15:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351958348-7327-1-git-send-email-maxime.ripard@free-electrons.com>
The leds-gpio driver recently got pinctrl support, so setup the power
led gpio muxing through pinctrl.
This avoids the warning:
leds-gpio leds.X: pins are not configured from the driver
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/imx28-cfa10036.dts | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/imx28-cfa10036.dts b/arch/arm/boot/dts/imx28-cfa10036.dts
index 816cae9..8760b87 100644
--- a/arch/arm/boot/dts/imx28-cfa10036.dts
+++ b/arch/arm/boot/dts/imx28-cfa10036.dts
@@ -22,6 +22,18 @@
apb at 80000000 {
apbh at 80000000 {
+ pinctrl at 80018000 {
+ led_pins_cfa10036: leds-10036 at 0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ 0x3043 /* MX28_PAD_AUART1_RX__GPIO_3_4 */
+ >;
+ fsl,drive-strength = <0>;
+ fsl,voltage = <1>;
+ fsl,pull-up = <0>;
+ };
+ };
+
ssp0: ssp at 80010000 {
compatible = "fsl,imx28-mmc";
pinctrl-names = "default";
@@ -62,6 +74,8 @@
leds {
compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins_cfa10036>;
power {
gpios = <&gpio3 4 1>;
--
1.7.9.5
^ permalink raw reply related
* [PATCH 0/2] Pinctrl muxing for the Crystalfontz boards
From: Maxime Ripard @ 2012-11-03 15:59 UTC (permalink / raw)
To: linux-arm-kernel
Hi all,
This patch serie add the hogpins to explicitly mux the GPIOs used
across the device tree as such for the two Crystalfontz boards, and
make the gpio-led driver use pinctrl.
This serie goes on top of the i2c-mux-gpios patches I sent on this
list.
Maxime
Maxime Ripard (2):
ARM: dts: cfa10036: Use pinctrl for power led
ARM: dts: mxs: Add hog pins to Crystalfontz boards
arch/arm/boot/dts/imx28-cfa10036.dts | 27 +++++++++++++++++++++++++++
arch/arm/boot/dts/imx28-cfa10049.dts | 16 ++++++++++++++++
2 files changed, 43 insertions(+)
--
1.7.9.5
^ permalink raw reply
* [PATCH 13/15] ARM: DTS: AM33XX: Add nodes for OCMCRAM and Mailbox
From: Santosh Shilimkar @ 2012-11-03 15:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351859566-24818-14-git-send-email-vaibhav.bedia@ti.com>
On Friday 02 November 2012 06:02 PM, Vaibhav Bedia wrote:
> Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
> ---
> arch/arm/boot/dts/am33xx.dtsi | 11 +++++++++++
> 1 files changed, 11 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
> index bb31bff..e2cbf24 100644
> --- a/arch/arm/boot/dts/am33xx.dtsi
> +++ b/arch/arm/boot/dts/am33xx.dtsi
> @@ -210,5 +210,16 @@
> interrupt-parent = <&intc>;
> interrupts = <91>;
> };
> +
> + ocmcram: ocmcram at 40300000 {
> + compatible = "ti,ocmcram";
> + ti,hwmods = "ocmcram";
> + ti,no_idle_on_suspend;
> + };
Whats the intention behind adding OCMRAM ?
Sorry if I missed any comments from the cover letter ?
Regards
Santosh
^ permalink raw reply
* [PATCH 12/15] ARM: OMAP: timer: Add suspend-resume callbacks for clockevent device
From: Santosh Shilimkar @ 2012-11-03 15:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351859566-24818-13-git-send-email-vaibhav.bedia@ti.com>
On Friday 02 November 2012 06:02 PM, Vaibhav Bedia wrote:
> From: Vaibhav Hiremath <hvaibhav@ti.com>
>
> The current OMAP timer code registers two timers -
> one as clocksource and one as clockevent.
Actually OMAP also uses only one timer. The clocksource
is taken care by 32K syntimer till OMAP4 and by realtime
counter on OMAP5. There is a clocksource registration of
timer is available but that is not being used in systems.
> AM33XX has only one usable timer in the WKUP domain
> so one of the timers needs suspend-resume support
> to restore the configuration to pre-suspend state.
>
> commit adc78e6 (timekeeping: Add suspend and resume
> of clock event devices) introduced .suspend and .resume
> callbacks for clock event devices. Leverages these
> callbacks to have AM33XX clockevent timer which is
> in not in WKUP domain to behave properly across system
> suspend.
>
So you use WKUP domain timer for clocksource and PER
domain one for clock-event ?
> Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
> Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
> ---
> arch/arm/mach-omap2/timer.c | 31 +++++++++++++++++++++++++++++++
> 1 files changed, 31 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
> index 6584ee0..e8781fd 100644
> --- a/arch/arm/mach-omap2/timer.c
> +++ b/arch/arm/mach-omap2/timer.c
> @@ -135,6 +135,35 @@ static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
> }
> }
>
> +static void omap_clkevt_suspend(struct clock_event_device *unused)
> +{
> + char name[10];
> + struct omap_hwmod *oh;
> +
> + sprintf(name, "timer%d", 2);
> + oh = omap_hwmod_lookup(name);
> + if (!oh)
> + return;
You can move all the look up stuff in init code and then
suspend resume hooks will be cleaner.
> +
> + omap_hwmod_idle(oh);
> +}
> +
> +static void omap_clkevt_resume(struct clock_event_device *unused)
> +{
> + char name[10];
> + struct omap_hwmod *oh;
> +
> + sprintf(name, "timer%d", 2);
> + oh = omap_hwmod_lookup(name);
> + if (!oh)
> + return;
> +
> + omap_hwmod_enable(oh);
> + __omap_dm_timer_load_start(&clkev,
> + OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 1);
> + __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
> +}
> +
OK. So since your clk_event stops when PER idles, how do you plan
to support the SOC idle. For CPUIDLE path, you need your clock-event
to wakeup the system based on next timer expiry. So you need your
clock event to be active. Indirectly, you can't let PER idle which
leads npo CORE idle->SOC idle.
How do you plan to address this ? Os is SOC idle is not suppose
to be added for AMXXX ?
Regards
Santosh
^ permalink raw reply
* [PATCH] ARM: dts: add board dts file for Exynos4412 based SMDK board
From: Thomas Abraham @ 2012-11-03 14:49 UTC (permalink / raw)
To: linux-arm-kernel
Add a minimal board dts file for Samsung Exynos4412 based SMDK board.
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
This patch depends the on the following patch posted by Tomasz Figa.
"ARM: dts: exynos4: Add support for Exynos4x12 SoCs"
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/exynos4412-smdk4412.dts | 45 +++++++++++++++++++++++++++++
2 files changed, 46 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/boot/dts/exynos4412-smdk4412.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index f37cf9f..36488a5 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -23,6 +23,7 @@ dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos4210-smdkv310.dtb \
exynos4210-trats.dtb \
+ exynos4412-smdk4412.dtb \
exynos5250-smdk5250.dtb
dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb
dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \
diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts b/arch/arm/boot/dts/exynos4412-smdk4412.dts
new file mode 100644
index 0000000..f05bf57
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4412-smdk4412.dts
@@ -0,0 +1,45 @@
+/*
+ * Samsung's Exynos4412 based SMDK board device tree source
+ *
+ * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Device tree source file for Samsung's SMDK4412 board which is based on
+ * Samsung's Exynos4412 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+/include/ "exynos4412.dtsi"
+
+/ {
+ model = "Samsung SMDK evaluation board based on Exynos4412";
+ compatible = "samsung,smdk4412", "samsung,exynos4412";
+
+ memory {
+ reg = <0x40000000 0x40000000>;
+ };
+
+ chosen {
+ bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc";
+ };
+
+ serial at 13800000 {
+ status = "okay";
+ };
+
+ serial at 13810000 {
+ status = "okay";
+ };
+
+ serial at 13820000 {
+ status = "okay";
+ };
+
+ serial at 13830000 {
+ status = "okay";
+ };
+};
--
1.6.6.rc2
^ permalink raw reply related
* [PATCH 5/5] ARM: dts: add mct device tree node for all supported Exynos SoC's
From: Thomas Abraham @ 2012-11-03 14:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351953938-13487-1-git-send-email-thomas.abraham@linaro.org>
Add MCT device tree node for Exynos4210, Exynos4212, Exynos4412 and Exynos5250.
Cc: Changhwan Youn <chaos.youn@samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
arch/arm/boot/dts/exynos4210.dtsi | 8 ++++++++
arch/arm/boot/dts/exynos4212.dtsi | 10 ++++++++++
arch/arm/boot/dts/exynos4412.dtsi | 8 ++++++++
arch/arm/boot/dts/exynos5250.dtsi | 21 +++++++++++++++++++++
4 files changed, 47 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 214c557..129762c 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -42,6 +42,14 @@
<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
};
+ mct at 10050000 {
+ compatible = "samsung,exynos4210-mct";
+ reg = <0x10050000 0x800>;
+ interrupts = <0 57 0>, <0 0 0>, <0 0 0>, <0 0 0>,
+ <0 42 0>, <0 48 0>;
+ samsung,mct-nr-local-irqs = <4>;
+ };
+
pinctrl_0: pinctrl at 11400000 {
compatible = "samsung,pinctrl-exynos4210";
reg = <0x11400000 0x1000>;
diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi
index c6ae200..87c6da4 100644
--- a/arch/arm/boot/dts/exynos4212.dtsi
+++ b/arch/arm/boot/dts/exynos4212.dtsi
@@ -25,4 +25,14 @@
gic:interrupt-controller at 10490000 {
cpu-offset = <0x8000>;
};
+
+ mct at 10050000 {
+ compatible = "samsung,exynos4210-mct";
+ reg = <0x10050000 0x800>;
+ interrupts = <0 57 0>, <0 0 0>, <0 0 0>, <0 0 0>,
+ <1 12 0>, <1 12 0>;
+ samsung,mct-nr-local-irqs = <2>;
+ };
+
+
};
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
index d7dfe31..ccf020a 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -25,4 +25,12 @@
gic:interrupt-controller at 10490000 {
cpu-offset = <0x4000>;
};
+
+ mct at 10050000 {
+ compatible = "samsung,exynos4210-mct";
+ reg = <0x10050000 0x800>;
+ interrupts = <0 57 0>, <0 0 0>, <0 0 0>, <0 0 0>,
+ <1 12 0>, <1 12 0>, <1 12 0>, <1 12 0>;
+ samsung,mct-nr-local-irqs = <4>;
+ };
};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 49546bc..688acf2 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -56,6 +56,27 @@
<0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
};
+ mct at 101C0000 {
+ compatible = "samsung,exynos4210-mct";
+ reg = <0x101C0000 0x800>;
+ interrupt-controller;
+ #interrups-cells = <2>;
+ interrupt-parent = <&mct_map>;
+ interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
+ <4 0>, <5 0>;
+ samsung,mct-nr-local-irqs = <2>;
+
+ mct_map: mct-map {
+ compatible = "samsung,mct-map";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-map = <0x0 0 &combiner 23 3>,
+ <0x4 0 &gic 0 120 0>,
+ <0x5 0 &gic 0 121 0>;
+ };
+ };
+
watchdog {
compatible = "samsung,s3c2410-wdt";
reg = <0x101D0000 0x100>;
--
1.6.6.rc2
^ permalink raw reply related
* [PATCH 4/5] ARM: Exynos: remove static io-remapping of mct registers for Exynos5
From: Thomas Abraham @ 2012-11-03 14:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351953938-13487-1-git-send-email-thomas.abraham@linaro.org>
With device tree support enabled for MCT controller, the static io-remapping
of the MCT controller address space is removed for Exynos5 platforms (which
supports only device tree based boot).
Cc: Changhwan Youn <chaos.youn@samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
arch/arm/mach-exynos/common.c | 5 -----
arch/arm/mach-exynos/include/mach/map.h | 1 -
2 files changed, 0 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 56844d1..44be55d 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -234,11 +234,6 @@ static struct map_desc exynos5_iodesc[] __initdata = {
.length = SZ_4K,
.type = MT_DEVICE,
}, {
- .virtual = (unsigned long)S5P_VA_SYSTIMER,
- .pfn = __phys_to_pfn(EXYNOS5_PA_SYSTIMER),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
.virtual = (unsigned long)S5P_VA_SYSRAM,
.pfn = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
.length = SZ_4K,
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index e737331..9355552 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -64,7 +64,6 @@
#define EXYNOS5_PA_CMU 0x10010000
#define EXYNOS4_PA_SYSTIMER 0x10050000
-#define EXYNOS5_PA_SYSTIMER 0x101C0000
#define EXYNOS4_PA_WATCHDOG 0x10060000
#define EXYNOS5_PA_WATCHDOG 0x101D0000
--
1.6.6.rc2
^ permalink raw reply related
* [PATCH 3/5] ARM: Exynos: add device tree support for MCT controller driver
From: Thomas Abraham @ 2012-11-03 14:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351953938-13487-1-git-send-email-thomas.abraham@linaro.org>
Allow the MCT controller base address and interrupts to be obtained from
device tree and remove unused static definitions of these. The non-dt support
for Exynos5250 is removed but retained for Exynos4210 based platforms.
Cc: Changhwan Youn <chaos.youn@samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
.../bindings/timer/samsung,exynos4210-mct.txt | 70 ++++++++++++++++++++
arch/arm/mach-exynos/include/mach/irqs.h | 6 --
arch/arm/mach-exynos/mct.c | 42 ++++++++----
3 files changed, 99 insertions(+), 19 deletions(-)
create mode 100644 Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
diff --git a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
new file mode 100644
index 0000000..c53fd93
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
@@ -0,0 +1,70 @@
+Samsung's Multi Core Timer (MCT)
+
+The Samsung's Multi Core Timer (MCT) module includes two main blocks, the
+global timer and CPU local timers. The global timer is a 64-bit free running
+up-counter and can generate 4 interrupts when the counter reaches one of the
+four preset counter values. The CPU local timers are 32-bit free running
+down-counters and generates an interrupt when the counter expires. There is
+one CPU local timer instantiated in MCT for every CPU in the system.
+
+Required properties:
+
+- compatible: should be "samsung,exynos4210-mct".
+- reg: base address of the mct controller and length of the address space
+ it occupies.
+- interrupts: the list of interrupts generated by the controller. The following
+ should be the order of the interrupts specified. The local timer interrupts
+ should be specified after the four global timer interrupts have been
+ specified.
+
+ 0: Global Timer Interrupt 0
+ 1: Global Timer Interrupt 1
+ 2: Global Timer Interrupt 2
+ 3: Global Timer Interrupt 3
+ 4: Local Timer Interrupt 0
+ 5: Local Timer Interrupt 1
+ 6: ..
+ 7: ..
+ i: Local Timer Interrupt n
+
+- samsung,mct-nr-local-irqs: The number of local timer interrupts supported
+ by the MCT controller.
+
+Example 1: In this example, the system uses only the first global timer
+ interrupt generated by MCT and the remaining three global timer
+ interrupts are unused. Two local timer interrupts have been
+ specified.
+
+ mct at 10050000 {
+ compatible = "samsung,exynos4210-mct";
+ reg = <0x10050000 0x800>;
+ interrupts = <0 57 0>, <0 0 0>, <0 0 0>, <0 0 0>,
+ <0 42 0>, <0 48 0>;
+ samsung,mct-nr-local-irqs = <4>;
+ };
+
+Example 2: In this example, the MCT global and local timer interrupts are
+ connected to two seperate interrupt controllers. Hence, an
+ interrupt-map is created to map the interrupts to the respective
+ interrupt controllers.
+
+ mct at 101C0000 {
+ compatible = "samsung,exynos4210-mct";
+ reg = <0x101C0000 0x800>;
+ interrupt-controller;
+ #interrups-cells = <2>;
+ interrupt-parent = <&mct_map>;
+ interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
+ <4 0>, <5 0>;
+ samsung,mct-nr-local-irqs = <2>;
+
+ mct_map: mct-map {
+ compatible = "samsung,mct-map";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-map = <0x0 0 &combiner 23 3>,
+ <0x4 0 &gic 0 120 0>,
+ <0x5 0 &gic 0 121 0>;
+ };
+ };
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index 6da3115..03c9f04 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -30,8 +30,6 @@
/* For EXYNOS4 and EXYNOS5 */
-#define EXYNOS_IRQ_MCT_LOCALTIMER IRQ_PPI(12)
-
#define EXYNOS_IRQ_EINT16_31 IRQ_SPI(32)
/* For EXYNOS4 SoCs */
@@ -320,8 +318,6 @@
#define EXYNOS5_IRQ_CEC IRQ_SPI(114)
#define EXYNOS5_IRQ_SATA IRQ_SPI(115)
-#define EXYNOS5_IRQ_MCT_L0 IRQ_SPI(120)
-#define EXYNOS5_IRQ_MCT_L1 IRQ_SPI(121)
#define EXYNOS5_IRQ_MMC44 IRQ_SPI(123)
#define EXYNOS5_IRQ_MDMA1 IRQ_SPI(124)
#define EXYNOS5_IRQ_FIMC_LITE0 IRQ_SPI(125)
@@ -411,8 +407,6 @@
#define EXYNOS5_IRQ_PMU_CPU1 COMBINER_IRQ(22, 4)
#define EXYNOS5_IRQ_EINT0 COMBINER_IRQ(23, 0)
-#define EXYNOS5_IRQ_MCT_G0 COMBINER_IRQ(23, 3)
-#define EXYNOS5_IRQ_MCT_G1 COMBINER_IRQ(23, 4)
#define EXYNOS5_IRQ_EINT1 COMBINER_IRQ(24, 0)
#define EXYNOS5_IRQ_SYSMMU_LITE1_0 COMBINER_IRQ(24, 1)
diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c
index d65d0c7..f7792b8 100644
--- a/arch/arm/mach-exynos/mct.c
+++ b/arch/arm/mach-exynos/mct.c
@@ -19,6 +19,9 @@
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/percpu.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
#include <asm/hardware/gic.h>
#include <asm/localtimer.h>
@@ -483,14 +486,16 @@ static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = {
};
#endif /* CONFIG_LOCAL_TIMERS */
-static void __init exynos4_timer_resources(void)
+static void __init exynos4_timer_resources(struct device_node *np)
{
struct clk *mct_clk;
mct_clk = clk_get(NULL, "xtal");
clk_rate = clk_get_rate(mct_clk);
- reg_base = S5P_VA_SYSTIMER;
+ reg_base = (np) ? of_iomap(np, 0) : S5P_VA_SYSTIMER;
+ if (!reg_base)
+ panic("%s: unable to ioremap mct address space\n", __func__);
#ifdef CONFIG_LOCAL_TIMERS
if (mct_int_type == MCT_INT_PPI) {
@@ -509,23 +514,34 @@ static void __init exynos4_timer_resources(void)
static void __init exynos4_timer_init(void)
{
- if (soc_is_exynos4210()) {
+ struct device_node *np;
+ u32 nr_irqs, i;
+
+ np = of_find_compatible_node(NULL, NULL, "samsung,exynos4210-mct");
+ if (np) {
+ if (of_machine_is_compatible("samsung,exynos4210") ||
+ of_machine_is_compatible("samsung,exynos5250"))
+ mct_int_type = MCT_INT_SPI;
+ else
+ mct_int_type = MCT_INT_PPI;
+
+ if (of_property_read_u32(np, "samsung,mct-nr-local-irqs",
+ &nr_irqs))
+ panic("%s: number of local irqs not specified\n",
+ __func__);
+
+ mct_irqs[MCT_G0_IRQ] = irq_of_parse_and_map(np, MCT_G0_IRQ);
+ for (i = 0; i < nr_irqs; i++)
+ mct_irqs[MCT_L0_IRQ + i] =
+ irq_of_parse_and_map(np, MCT_L0_IRQ + i);
+ } else if (soc_is_exynos4210()) {
mct_irqs[MCT_G0_IRQ] = EXYNOS4_IRQ_MCT_G0;
mct_irqs[MCT_L0_IRQ] = EXYNOS4_IRQ_MCT_L0;
mct_irqs[MCT_L1_IRQ] = EXYNOS4_IRQ_MCT_L1;
mct_int_type = MCT_INT_SPI;
- } else if (soc_is_exynos5250()) {
- mct_irqs[MCT_G0_IRQ] = EXYNOS5_IRQ_MCT_G0;
- mct_irqs[MCT_L0_IRQ] = EXYNOS5_IRQ_MCT_L0;
- mct_irqs[MCT_L1_IRQ] = EXYNOS5_IRQ_MCT_L1;
- mct_int_type = MCT_INT_SPI;
- } else {
- mct_irqs[MCT_G0_IRQ] = EXYNOS4_IRQ_MCT_G0;
- mct_irqs[MCT_L0_IRQ] = EXYNOS_IRQ_MCT_LOCALTIMER;
- mct_int_type = MCT_INT_PPI;
}
- exynos4_timer_resources();
+ exynos4_timer_resources(np);
exynos4_clocksource_init();
exynos4_clockevent_init();
}
--
1.6.6.rc2
^ permalink raw reply related
* [PATCH 2/5] ARM: Exynos: prepare an array of MCT interrupt numbers and use it
From: Thomas Abraham @ 2012-11-03 14:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351953938-13487-1-git-send-email-thomas.abraham@linaro.org>
Instead of using soc_is_xxx macro at more than one place in the MCT
controller driver to decide the MCT interrpt number to be setup, populate
a table of known MCT global and local timer interrupts and use the values
in table to setup the MCT interrupts.
This also helps in adding device tree support for MCT controller driver by
allowing the driver to retrieve interrupt numbers from device tree and
populating them into this table, thereby supporting both legacy and dt
functionality to co-exist.
Cc: Changhwan Youn <chaos.youn@samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
arch/arm/mach-exynos/mct.c | 57 +++++++++++++++++++++++++++----------------
1 files changed, 36 insertions(+), 21 deletions(-)
diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c
index c3c4799..d65d0c7 100644
--- a/arch/arm/mach-exynos/mct.c
+++ b/arch/arm/mach-exynos/mct.c
@@ -64,9 +64,22 @@ enum {
MCT_INT_PPI
};
+enum {
+ MCT_G0_IRQ,
+ MCT_G1_IRQ,
+ MCT_G2_IRQ,
+ MCT_G3_IRQ,
+ MCT_L0_IRQ,
+ MCT_L1_IRQ,
+ MCT_L2_IRQ,
+ MCT_L3_IRQ,
+ MCT_NR_IRQS,
+};
+
static void __iomem *reg_base;
static unsigned long clk_rate;
static unsigned int mct_int_type;
+static int mct_irqs[MCT_NR_IRQS];
struct mct_clock_event_device {
struct clock_event_device *evt;
@@ -285,11 +298,7 @@ static void exynos4_clockevent_init(void)
clockevent_delta2ns(0xf, &mct_comp_device);
mct_comp_device.cpumask = cpumask_of(0);
clockevents_register_device(&mct_comp_device);
-
- if (soc_is_exynos5250())
- setup_irq(EXYNOS5_IRQ_MCT_G0, &mct_comp_event_irq);
- else
- setup_irq(EXYNOS4_IRQ_MCT_G0, &mct_comp_event_irq);
+ setup_irq(mct_irqs[MCT_G0_IRQ], &mct_comp_event_irq);
}
#ifdef CONFIG_LOCAL_TIMERS
@@ -413,7 +422,6 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
{
struct mct_clock_event_device *mevt;
unsigned int cpu = smp_processor_id();
- int mct_lx_irq;
mevt = this_cpu_ptr(&percpu_mct_tick);
mevt->evt = evt;
@@ -440,21 +448,17 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
if (mct_int_type == MCT_INT_SPI) {
if (cpu == 0) {
- mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L0 :
- EXYNOS5_IRQ_MCT_L0;
mct_tick0_event_irq.dev_id = mevt;
- evt->irq = mct_lx_irq;
- setup_irq(mct_lx_irq, &mct_tick0_event_irq);
+ evt->irq = mct_irqs[MCT_L0_IRQ];
+ setup_irq(evt->irq, &mct_tick0_event_irq);
} else {
- mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L1 :
- EXYNOS5_IRQ_MCT_L1;
mct_tick1_event_irq.dev_id = mevt;
- evt->irq = mct_lx_irq;
- setup_irq(mct_lx_irq, &mct_tick1_event_irq);
- irq_set_affinity(mct_lx_irq, cpumask_of(1));
+ evt->irq = mct_irqs[MCT_L1_IRQ];
+ setup_irq(evt->irq, &mct_tick1_event_irq);
+ irq_set_affinity(evt->irq, cpumask_of(1));
}
} else {
- enable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER, 0);
+ enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0);
}
return 0;
@@ -470,7 +474,7 @@ static void exynos4_local_timer_stop(struct clock_event_device *evt)
else
remove_irq(evt->irq, &mct_tick1_event_irq);
else
- disable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER);
+ disable_percpu_irq(mct_irqs[MCT_L0_IRQ]);
}
static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = {
@@ -492,11 +496,11 @@ static void __init exynos4_timer_resources(void)
if (mct_int_type == MCT_INT_PPI) {
int err;
- err = request_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER,
+ err = request_percpu_irq(mct_irqs[MCT_L0_IRQ],
exynos4_mct_tick_isr, "MCT",
&percpu_mct_tick);
WARN(err, "MCT: can't request IRQ %d (%d)\n",
- EXYNOS_IRQ_MCT_LOCALTIMER, err);
+ mct_irqs[MCT_L0_IRQ], err);
}
local_timer_register(&exynos4_mct_tick_ops);
@@ -505,10 +509,21 @@ static void __init exynos4_timer_resources(void)
static void __init exynos4_timer_init(void)
{
- if ((soc_is_exynos4210()) || (soc_is_exynos5250()))
+ if (soc_is_exynos4210()) {
+ mct_irqs[MCT_G0_IRQ] = EXYNOS4_IRQ_MCT_G0;
+ mct_irqs[MCT_L0_IRQ] = EXYNOS4_IRQ_MCT_L0;
+ mct_irqs[MCT_L1_IRQ] = EXYNOS4_IRQ_MCT_L1;
mct_int_type = MCT_INT_SPI;
- else
+ } else if (soc_is_exynos5250()) {
+ mct_irqs[MCT_G0_IRQ] = EXYNOS5_IRQ_MCT_G0;
+ mct_irqs[MCT_L0_IRQ] = EXYNOS5_IRQ_MCT_L0;
+ mct_irqs[MCT_L1_IRQ] = EXYNOS5_IRQ_MCT_L1;
+ mct_int_type = MCT_INT_SPI;
+ } else {
+ mct_irqs[MCT_G0_IRQ] = EXYNOS4_IRQ_MCT_G0;
+ mct_irqs[MCT_L0_IRQ] = EXYNOS_IRQ_MCT_LOCALTIMER;
mct_int_type = MCT_INT_PPI;
+ }
exynos4_timer_resources();
exynos4_clocksource_init();
--
1.6.6.rc2
^ permalink raw reply related
* [PATCH 1/5] ARM: Exynos: add a register base address variable in mct controller driver
From: Thomas Abraham @ 2012-11-03 14:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351953938-13487-1-git-send-email-thomas.abraham@linaro.org>
All the MCT register read/writes use a fixed remapped address S5P_VA_SYSTIMER.
With device tree support for MCT controller, it is possible to remove the
static remap of the MCT controller address space and do the remap during the
initialization of the MCT controller with the physical address obtained from
the device tree.
So in preparation of adding device tree support for MCT controller, add a new
register base address variable that will hold the remapped MCT controller base
address and convert all MCT register read/writes to use this new variable as
the base address instead of the fixed S5P_VA_SYSTIMER.
While at it, the MCT register offset and bit mask definitions are moved into
the MCT controller driver file since there are no other consumers of these
definitions.
Cc: Changhwan Youn <chaos.youn@samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
---
arch/arm/mach-exynos/include/mach/regs-mct.h | 53 --------------
arch/arm/mach-exynos/mct.c | 97 ++++++++++++++++---------
2 files changed, 62 insertions(+), 88 deletions(-)
delete mode 100644 arch/arm/mach-exynos/include/mach/regs-mct.h
diff --git a/arch/arm/mach-exynos/include/mach/regs-mct.h b/arch/arm/mach-exynos/include/mach/regs-mct.h
deleted file mode 100644
index 80dd02a..0000000
--- a/arch/arm/mach-exynos/include/mach/regs-mct.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/* arch/arm/mach-exynos4/include/mach/regs-mct.h
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- * http://www.samsung.com
- *
- * EXYNOS4 MCT configutation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_REGS_MCT_H
-#define __ASM_ARCH_REGS_MCT_H __FILE__
-
-#include <mach/map.h>
-
-#define EXYNOS4_MCTREG(x) (S5P_VA_SYSTIMER + (x))
-
-#define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100)
-#define EXYNOS4_MCT_G_CNT_U EXYNOS4_MCTREG(0x104)
-#define EXYNOS4_MCT_G_CNT_WSTAT EXYNOS4_MCTREG(0x110)
-
-#define EXYNOS4_MCT_G_COMP0_L EXYNOS4_MCTREG(0x200)
-#define EXYNOS4_MCT_G_COMP0_U EXYNOS4_MCTREG(0x204)
-#define EXYNOS4_MCT_G_COMP0_ADD_INCR EXYNOS4_MCTREG(0x208)
-
-#define EXYNOS4_MCT_G_TCON EXYNOS4_MCTREG(0x240)
-
-#define EXYNOS4_MCT_G_INT_CSTAT EXYNOS4_MCTREG(0x244)
-#define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248)
-#define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C)
-
-#define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300)
-#define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x))
-#define EXYNOS4_MCT_L_MASK (0xffffff00)
-
-#define MCT_L_TCNTB_OFFSET (0x00)
-#define MCT_L_ICNTB_OFFSET (0x08)
-#define MCT_L_TCON_OFFSET (0x20)
-#define MCT_L_INT_CSTAT_OFFSET (0x30)
-#define MCT_L_INT_ENB_OFFSET (0x34)
-#define MCT_L_WSTAT_OFFSET (0x40)
-
-#define MCT_G_TCON_START (1 << 8)
-#define MCT_G_TCON_COMP0_AUTO_INC (1 << 1)
-#define MCT_G_TCON_COMP0_ENABLE (1 << 0)
-
-#define MCT_L_TCON_INTERVAL_MODE (1 << 2)
-#define MCT_L_TCON_INT_START (1 << 1)
-#define MCT_L_TCON_TIMER_START (1 << 0)
-
-#endif /* __ASM_ARCH_REGS_MCT_H */
diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c
index b601fb8..c3c4799 100644
--- a/arch/arm/mach-exynos/mct.c
+++ b/arch/arm/mach-exynos/mct.c
@@ -27,9 +27,36 @@
#include <mach/map.h>
#include <mach/irqs.h>
-#include <mach/regs-mct.h>
#include <asm/mach/time.h>
+#define EXYNOS4_MCTREG(x) (x)
+#define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100)
+#define EXYNOS4_MCT_G_CNT_U EXYNOS4_MCTREG(0x104)
+#define EXYNOS4_MCT_G_CNT_WSTAT EXYNOS4_MCTREG(0x110)
+#define EXYNOS4_MCT_G_COMP0_L EXYNOS4_MCTREG(0x200)
+#define EXYNOS4_MCT_G_COMP0_U EXYNOS4_MCTREG(0x204)
+#define EXYNOS4_MCT_G_COMP0_ADD_INCR EXYNOS4_MCTREG(0x208)
+#define EXYNOS4_MCT_G_TCON EXYNOS4_MCTREG(0x240)
+#define EXYNOS4_MCT_G_INT_CSTAT EXYNOS4_MCTREG(0x244)
+#define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248)
+#define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C)
+#define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300)
+#define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x))
+#define EXYNOS4_MCT_L_MASK (0xffffff00)
+
+#define MCT_L_TCNTB_OFFSET (0x00)
+#define MCT_L_ICNTB_OFFSET (0x08)
+#define MCT_L_TCON_OFFSET (0x20)
+#define MCT_L_INT_CSTAT_OFFSET (0x30)
+#define MCT_L_INT_ENB_OFFSET (0x34)
+#define MCT_L_WSTAT_OFFSET (0x40)
+#define MCT_G_TCON_START (1 << 8)
+#define MCT_G_TCON_COMP0_AUTO_INC (1 << 1)
+#define MCT_G_TCON_COMP0_ENABLE (1 << 0)
+#define MCT_L_TCON_INTERVAL_MODE (1 << 2)
+#define MCT_L_TCON_INT_START (1 << 1)
+#define MCT_L_TCON_TIMER_START (1 << 0)
+
#define TICK_BASE_CNT 1
enum {
@@ -37,64 +64,62 @@ enum {
MCT_INT_PPI
};
+static void __iomem *reg_base;
static unsigned long clk_rate;
static unsigned int mct_int_type;
struct mct_clock_event_device {
struct clock_event_device *evt;
- void __iomem *base;
+ unsigned long base;
char name[10];
};
-static void exynos4_mct_write(unsigned int value, void *addr)
+static void exynos4_mct_write(unsigned int value, unsigned long offset)
{
- void __iomem *stat_addr;
+ unsigned long stat_addr;
u32 mask;
u32 i;
- __raw_writel(value, addr);
+ __raw_writel(value, reg_base + offset);
- if (likely(addr >= EXYNOS4_MCT_L_BASE(0))) {
- u32 base = (u32) addr & EXYNOS4_MCT_L_MASK;
- switch ((u32) addr & ~EXYNOS4_MCT_L_MASK) {
- case (u32) MCT_L_TCON_OFFSET:
- stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
+ if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) {
+ stat_addr = (offset & ~EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET;
+ switch (offset & EXYNOS4_MCT_L_MASK) {
+ case MCT_L_TCON_OFFSET:
mask = 1 << 3; /* L_TCON write status */
break;
- case (u32) MCT_L_ICNTB_OFFSET:
- stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
+ case MCT_L_ICNTB_OFFSET:
mask = 1 << 1; /* L_ICNTB write status */
break;
- case (u32) MCT_L_TCNTB_OFFSET:
- stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
+ case MCT_L_TCNTB_OFFSET:
mask = 1 << 0; /* L_TCNTB write status */
break;
default:
return;
}
} else {
- switch ((u32) addr) {
- case (u32) EXYNOS4_MCT_G_TCON:
+ switch (offset) {
+ case EXYNOS4_MCT_G_TCON:
stat_addr = EXYNOS4_MCT_G_WSTAT;
mask = 1 << 16; /* G_TCON write status */
break;
- case (u32) EXYNOS4_MCT_G_COMP0_L:
+ case EXYNOS4_MCT_G_COMP0_L:
stat_addr = EXYNOS4_MCT_G_WSTAT;
mask = 1 << 0; /* G_COMP0_L write status */
break;
- case (u32) EXYNOS4_MCT_G_COMP0_U:
+ case EXYNOS4_MCT_G_COMP0_U:
stat_addr = EXYNOS4_MCT_G_WSTAT;
mask = 1 << 1; /* G_COMP0_U write status */
break;
- case (u32) EXYNOS4_MCT_G_COMP0_ADD_INCR:
+ case EXYNOS4_MCT_G_COMP0_ADD_INCR:
stat_addr = EXYNOS4_MCT_G_WSTAT;
mask = 1 << 2; /* G_COMP0_ADD_INCR w status */
break;
- case (u32) EXYNOS4_MCT_G_CNT_L:
+ case EXYNOS4_MCT_G_CNT_L:
stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
mask = 1 << 0; /* G_CNT_L write status */
break;
- case (u32) EXYNOS4_MCT_G_CNT_U:
+ case EXYNOS4_MCT_G_CNT_U:
stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
mask = 1 << 1; /* G_CNT_U write status */
break;
@@ -105,12 +130,12 @@ static void exynos4_mct_write(unsigned int value, void *addr)
/* Wait maximum 1 ms until written values are applied */
for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
- if (__raw_readl(stat_addr) & mask) {
- __raw_writel(mask, stat_addr);
+ if (__raw_readl(reg_base + stat_addr) & mask) {
+ __raw_writel(mask, reg_base + stat_addr);
return;
}
- panic("MCT hangs after writing %d (addr:0x%08x)\n", value, (u32)addr);
+ panic("MCT hangs after writing %d (offset:0x%lx)\n", value, offset);
}
/* Clocksource handling */
@@ -121,7 +146,7 @@ static void exynos4_mct_frc_start(u32 hi, u32 lo)
exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L);
exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U);
- reg = __raw_readl(EXYNOS4_MCT_G_TCON);
+ reg = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
reg |= MCT_G_TCON_START;
exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
}
@@ -129,12 +154,12 @@ static void exynos4_mct_frc_start(u32 hi, u32 lo)
static cycle_t exynos4_frc_read(struct clocksource *cs)
{
unsigned int lo, hi;
- u32 hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U);
+ u32 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
do {
hi = hi2;
- lo = __raw_readl(EXYNOS4_MCT_G_CNT_L);
- hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U);
+ lo = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_L);
+ hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
} while (hi != hi2);
return ((cycle_t)hi << 32) | lo;
@@ -166,7 +191,7 @@ static void exynos4_mct_comp0_stop(void)
{
unsigned int tcon;
- tcon = __raw_readl(EXYNOS4_MCT_G_TCON);
+ tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC);
exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
@@ -179,7 +204,7 @@ static void exynos4_mct_comp0_start(enum clock_event_mode mode,
unsigned int tcon;
cycle_t comp_cycle;
- tcon = __raw_readl(EXYNOS4_MCT_G_TCON);
+ tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
if (mode == CLOCK_EVT_MODE_PERIODIC) {
tcon |= MCT_G_TCON_COMP0_AUTO_INC;
@@ -276,12 +301,12 @@ static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
{
unsigned long tmp;
unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START;
- void __iomem *addr = mevt->base + MCT_L_TCON_OFFSET;
+ unsigned long offset = mevt->base + MCT_L_TCON_OFFSET;
- tmp = __raw_readl(addr);
+ tmp = __raw_readl(reg_base + offset);
if (tmp & mask) {
tmp &= ~mask;
- exynos4_mct_write(tmp, addr);
+ exynos4_mct_write(tmp, offset);
}
}
@@ -300,7 +325,7 @@ static void exynos4_mct_tick_start(unsigned long cycles,
/* enable MCT tick interrupt */
exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
- tmp = __raw_readl(mevt->base + MCT_L_TCON_OFFSET);
+ tmp = __raw_readl(reg_base + mevt->base + MCT_L_TCON_OFFSET);
tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START |
MCT_L_TCON_INTERVAL_MODE;
exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
@@ -352,7 +377,7 @@ static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
exynos4_mct_tick_stop(mevt);
/* Clear the MCT tick interrupt */
- if (__raw_readl(mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
+ if (__raw_readl(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
return 1;
} else {
@@ -461,6 +486,8 @@ static void __init exynos4_timer_resources(void)
clk_rate = clk_get_rate(mct_clk);
+ reg_base = S5P_VA_SYSTIMER;
+
#ifdef CONFIG_LOCAL_TIMERS
if (mct_int_type == MCT_INT_PPI) {
int err;
--
1.6.6.rc2
^ permalink raw reply related
* [PATCH 0/5] ARM: Exynos: Enable device tree support for MCT controller
From: Thomas Abraham @ 2012-11-03 14:45 UTC (permalink / raw)
To: linux-arm-kernel
This patch series adds device tree support for Exynos4/5 MCT controller. This
series depends on the device tree and smp support patches for Exynos4x12 posted
by Tomasz Figa. This patch series has been tested on Exynos4210 based Origen
board, Exynos4412 based SMDK board and Exynos5250 based SMDK board.
Thomas Abraham (5):
ARM: Exynos: add a register base address variable in mct controller driver
ARM: Exynos: prepare an array of MCT interrupt numbers and use it
ARM: Exynos: add device tree support for MCT controller driver
ARM: Exynos: remove static io-remapping of mct registers for Exynos5
ARM: dts: add mct device tree node for all supported Exynos SoC's
.../bindings/timer/samsung,exynos4210-mct.txt | 70 ++++++++
arch/arm/boot/dts/exynos4210.dtsi | 8 +
arch/arm/boot/dts/exynos4212.dtsi | 10 +
arch/arm/boot/dts/exynos4412.dtsi | 8 +
arch/arm/boot/dts/exynos5250.dtsi | 21 +++
arch/arm/mach-exynos/common.c | 5 -
arch/arm/mach-exynos/include/mach/irqs.h | 6 -
arch/arm/mach-exynos/include/mach/map.h | 1 -
arch/arm/mach-exynos/include/mach/regs-mct.h | 53 ------
arch/arm/mach-exynos/mct.c | 176 +++++++++++++-------
10 files changed, 234 insertions(+), 124 deletions(-)
create mode 100644 Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
delete mode 100644 arch/arm/mach-exynos/include/mach/regs-mct.h
^ permalink raw reply
* [PATCH] i2c: at91: add a sanity check on i2c message length
From: Wolfram Sang @ 2012-11-03 14:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5093EE2B.8080005@atmel.com>
> >>Yes SMBUS quick command is supported but is not managed in the
> >>driver, we have to tell explicitly the IP that we want to send this
> >>command.
> >
> >Ok, so unless you want to implement the support, please update this
> >patch with a comment that SMBUS_QUICK is a TODO and remove the
> >SMBUS_QUICK capability.
> >
>
> Implementation should not be a huge task, only one bit to set in a
> register but I have no device to test it.
'i2cdetect' from i2c-tools uses SMBUS_QUICK as one method to detect
chips. Most slaves (both I2C and SMBus) react to that, so that would do
in my book.
> Did you test the driver with SMBus compatible devices? Can I keep
> other SMBus capabilities from SMBUS_EMUL?
The rest should be fine.
--
Pengutronix e.K. | Wolfram Sang |
Industrial Linux Solutions | http://www.pengutronix.de/ |
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^ permalink raw reply
* [PATCH 12/15] ARM: OMAP: timer: Add suspend-resume callbacks for clockevent device
From: Bedia, Vaibhav @ 2012-11-03 14:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50951F22.1070904@deeprootsystems.com>
On Sat, Nov 03, 2012 at 19:11:54, Kevin Hilman wrote:
[...]
>
> Yes, please try with that. Won't that be necessary anyways for situations
> where the powerdomain goes off?
>
Yes, we probably got lucky with the minimal resume routine.
Regards,
Vaibhav
^ permalink raw reply
* [PATCH 02/15] ARM: OMAP2+: mailbox: Add support for AM33XX
From: Bedia, Vaibhav @ 2012-11-03 13:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CA+Bv8XY8x=BDgGDNHPMRqz3xUbzKf8+o0MJQDovHY+NqBh6NVw@mail.gmail.com>
On Sat, Nov 03, 2012 at 14:06:38, Bedia, Vaibhav wrote:
> Hi Russ,
>
> On Sat, Nov 03, 2012 at 05:44:21, Russ Dill wrote:
> [...]
> > > - if (!cpu_is_omap44xx())
> > > + if (!cpu_is_omap44xx() || !soc_is_am33xx())
> > > bit = mbox_read_reg(p->irqdisable) & ~bit;
> >
> > Do you mean &&?
> >
>
Ok I understood what you meant. Will fix it in next rev.
Regards,
Vaibhav
^ permalink raw reply
* [PATCH 11/15] ARM: OMAP: timer: Interchange clksrc and clkevt for AM33XX
From: Bedia, Vaibhav @ 2012-11-03 13:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5095165E.10403@deeprootsystems.com>
On Sat, Nov 03, 2012 at 18:34:30, Kevin Hilman wrote:
[...]
> >>
> >> Doesn't this also mean that you won't get timer wakeups
> >> in idle? Or are you keeping the domain where the clockevent is
> >> on during idle?
> >>
> >
> > The lowest idle state that we are targeting will have MPU powered
> > off with external memory in self-refresh mode. Peripheral domain
> > with the clockevent will be kept on.
>
> Is this a limitation of the hardware? or the software?
>
Well, making the lowest idle state same as the suspend state will require
us to involve WKUP_M3 in the idle path and wakeup sources get limited to
the IPs in the WKUP domain alone. There's no IO daisy chaining in AM33XX
so that's one big difference compared to OMAP.
The other potential problem is that the IPC mechanism that we have
uses interrupts. Assuming that the lowest idle state, say Cx, is the same
as the suspend state, we'll need to communicate with the WKUP_M3 using
interrupts once we decide to enter Cx. I am not sure if we can do something
in the cpuidle implementation to work around the "interrupt for idle"
problem. We could probably not wait for an ACK when we want to enter Cx,
but the problem of limited wakeup sources remains. If we let the various
drivers block the entry to Cx, since almost all the IPs are in the
peripheral domain a system which uses anything other than UART and Timer
in WKUP domain will probably never be able enter Cx.
Regards,
Vaibhav
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