* [PATCH 11/15] ARM: OMAP: timer: Interchange clksrc and clkevt for AM33XX
From: Santosh Shilimkar @ 2012-11-03 16:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351859566-24818-12-git-send-email-vaibhav.bedia@ti.com>
On Friday 02 November 2012 06:02 PM, Vaibhav Bedia wrote:
> AM33XX has only one usable timer in the WKUP domain.
> Currently the timer instance in WKUP domain is used
> as the clockevent and the timer in non-WKUP domain
> as the clocksource. The timer in WKUP domain can keep
> running in suspend from a 32K clock and hence serve
> as the persistent clock. To enable this, interchange
> the timers used as clocksource and clockevent for
> AM33XX. A subsequent patch will add suspend-resume
> support for the clockevent to ensure that there are
> no issues with timekeeping.
>
> Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
> ---
> arch/arm/mach-omap2/timer.c | 2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
> index 565e575..6584ee0 100644
> --- a/arch/arm/mach-omap2/timer.c
> +++ b/arch/arm/mach-omap2/timer.c
> @@ -460,7 +460,7 @@ OMAP_SYS_TIMER(3_secure)
> #endif
>
> #ifdef CONFIG_SOC_AM33XX
> -OMAP_SYS_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, 2, OMAP4_MPU_SOURCE)
> +OMAP_SYS_TIMER_INIT(3_am33xx, 2, OMAP4_MPU_SOURCE, 1, OMAP4_MPU_SOURCE)
> OMAP_SYS_TIMER(3_am33xx)
> #endif
>
As mentioned on other patch comment, I think this might break your
SOC idle.
Regards
Santosh
^ permalink raw reply
* [PATCH 6/9] uprobes: flush cache after xol write
From: Oleg Nesterov @ 2012-11-03 16:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121029053522.GC3400@in.ibm.com>
On 10/29, Ananth N Mavinakayanahalli wrote:
>
> On Fri, Oct 26, 2012 at 06:39:51PM +0200, Oleg Nesterov wrote:
> > >
> > > > OTOH, I do not understand this stuff, everything is nop on x86. And
> > > > when I look into Documentation/cachetlb.txt I am starting to think
> > > > that may be this needs flush_icache_user_range instead?
> > > >
> > > > Rabin, Ananth could you clarify this?
> > >
> > > Yes. We need flush_icache_user_range(). Though for x86 its always been a
> > > nop, one never knows if there is some Power4 or older machine out there
> > > that is still being used. We are fine for Power5 and later.
> >
> > This is bad...
> >
> > flush_icache_user needs vma. perhaps just to check VM_EXEC...
> >
> > So let me repeat to be sure I really understand, do you confirm that
> > _in general_ flush_dcache_page() is not enough?
>
> flush_dcache_page() on powerpc already checks for
> CPU_FTR_COHERENT_ICACHE. So, yes, that is enough.
Thanks Ananth.
Still it is not clear to me if flush_dcache_page() would be always right
if we add the new port.
OK. So I assume we need the fix and I am going to apply the patch below.
Ananth, Rabin, will you ack it (including the comment I affed) ?
Oleg.
------------------------------------------------------------------------------
[PATCH] uprobes: flush cache after xol write
From: Rabin Vincent <rabin@rab.in>
Flush the cache so that the instructions written to the XOL area are
visible.
Signed-off-by: Rabin Vincent <rabin@rab.in>
--- x/kernel/events/uprobes.c
+++ x/kernel/events/uprobes.c
@@ -1199,6 +1199,11 @@ static unsigned long xol_get_insn_slot(s
vaddr = kmap_atomic(area->page);
memcpy(vaddr + offset, uprobe->arch.insn, MAX_UINSN_BYTES);
kunmap_atomic(vaddr);
+ /*
+ * We probably need flush_icache_user_range() but it needs vma.
+ * This should work on supported architectures too.
+ */
+ flush_dcache_page(area->page);
return current->utask->xol_vaddr;
}
^ permalink raw reply
* [PATCH 3/5] ARM: Exynos: add device tree support for MCT controller driver
From: Sylwester Nawrocki @ 2012-11-03 16:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351953938-13487-4-git-send-email-thomas.abraham@linaro.org>
Hi Thomas,
On 11/03/2012 03:45 PM, Thomas Abraham wrote:
> Allow the MCT controller base address and interrupts to be obtained from
> device tree and remove unused static definitions of these. The non-dt support
> for Exynos5250 is removed but retained for Exynos4210 based platforms.
>
> Cc: Changhwan Youn<chaos.youn@samsung.com>
> Signed-off-by: Thomas Abraham<thomas.abraham@linaro.org>
> ---
> .../bindings/timer/samsung,exynos4210-mct.txt | 70 ++++++++++++++++++++
> arch/arm/mach-exynos/include/mach/irqs.h | 6 --
> arch/arm/mach-exynos/mct.c | 42 ++++++++----
> 3 files changed, 99 insertions(+), 19 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
>
> diff --git a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
> new file mode 100644
> index 0000000..c53fd93
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
> @@ -0,0 +1,70 @@
> +Samsung's Multi Core Timer (MCT)
> +
> +The Samsung's Multi Core Timer (MCT) module includes two main blocks, the
> +global timer and CPU local timers. The global timer is a 64-bit free running
> +up-counter and can generate 4 interrupts when the counter reaches one of the
> +four preset counter values. The CPU local timers are 32-bit free running
> +down-counters and generates an interrupt when the counter expires. There is
s/generates/generate ?
> +one CPU local timer instantiated in MCT for every CPU in the system.
> +
> +Required properties:
> +
> +- compatible: should be "samsung,exynos4210-mct".
> +- reg: base address of the mct controller and length of the address space
> + it occupies.
> +- interrupts: the list of interrupts generated by the controller. The following
> + should be the order of the interrupts specified. The local timer interrupts
> + should be specified after the four global timer interrupts have been
> + specified.
> +
> + 0: Global Timer Interrupt 0
> + 1: Global Timer Interrupt 1
> + 2: Global Timer Interrupt 2
> + 3: Global Timer Interrupt 3
> + 4: Local Timer Interrupt 0
> + 5: Local Timer Interrupt 1
> + 6: ..
> + 7: ..
> + i: Local Timer Interrupt n
> +
> +- samsung,mct-nr-local-irqs: The number of local timer interrupts supported
> + by the MCT controller.
> +
> +Example 1: In this example, the system uses only the first global timer
> + interrupt generated by MCT and the remaining three global timer
> + interrupts are unused. Two local timer interrupts have been
> + specified.
> +
> + mct at 10050000 {
> + compatible = "samsung,exynos4210-mct";
> + reg =<0x10050000 0x800>;
> + interrupts =<0 57 0>,<0 0 0>,<0 0 0>,<0 0 0>,
> + <0 42 0>,<0 48 0>;
> + samsung,mct-nr-local-irqs =<4>;
Then this means the MCT supports 4 local interrupts but only 2 are
specified here ? Doesn't the code below expect
samsung,mct-nr-local-irqs = <2>;
in this case ? Or should interrupts really be
interrupts =<0 57 0>, <0 0 0>, <0 0 0>, <0 0 0>,
<0 42 0>, <0 48 0>, <0 0 0>, <0 0 0>;
?
> + };
> +
> +Example 2: In this example, the MCT global and local timer interrupts are
> + connected to two seperate interrupt controllers. Hence, an
> + interrupt-map is created to map the interrupts to the respective
> + interrupt controllers.
> +
> + mct at 101C0000 {
> + compatible = "samsung,exynos4210-mct";
> + reg =<0x101C0000 0x800>;
> + interrupt-controller;
> + #interrups-cells =<2>;
> + interrupt-parent =<&mct_map>;
> + interrupts =<0 0>,<1 0>,<2 0>,<3 0>,
> + <4 0>,<5 0>;
> + samsung,mct-nr-local-irqs =<2>;
Here the samsung,mct-nr-local-irqs' value matches what's specified in
the interrupts property.
> +
> + mct_map: mct-map {
> + compatible = "samsung,mct-map";
Do we need a compatible property in sub-nodes like this one ?
Wouldn't it be sufficient to reference this node, for example by name ?
> + #interrupt-cells =<2>;
> + #address-cells =<0>;
> + #size-cells =<0>;
> + interrupt-map =<0x0 0&combiner 23 3>,
> + <0x4 0&gic 0 120 0>,
> + <0x5 0&gic 0 121 0>;
> + };
> + };
> diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
> index 6da3115..03c9f04 100644
> --- a/arch/arm/mach-exynos/include/mach/irqs.h
> +++ b/arch/arm/mach-exynos/include/mach/irqs.h
> @@ -30,8 +30,6 @@
>
> /* For EXYNOS4 and EXYNOS5 */
>
> -#define EXYNOS_IRQ_MCT_LOCALTIMER IRQ_PPI(12)
> -
> #define EXYNOS_IRQ_EINT16_31 IRQ_SPI(32)
>
> /* For EXYNOS4 SoCs */
> @@ -320,8 +318,6 @@
> #define EXYNOS5_IRQ_CEC IRQ_SPI(114)
> #define EXYNOS5_IRQ_SATA IRQ_SPI(115)
>
> -#define EXYNOS5_IRQ_MCT_L0 IRQ_SPI(120)
> -#define EXYNOS5_IRQ_MCT_L1 IRQ_SPI(121)
> #define EXYNOS5_IRQ_MMC44 IRQ_SPI(123)
> #define EXYNOS5_IRQ_MDMA1 IRQ_SPI(124)
> #define EXYNOS5_IRQ_FIMC_LITE0 IRQ_SPI(125)
> @@ -411,8 +407,6 @@
> #define EXYNOS5_IRQ_PMU_CPU1 COMBINER_IRQ(22, 4)
>
> #define EXYNOS5_IRQ_EINT0 COMBINER_IRQ(23, 0)
> -#define EXYNOS5_IRQ_MCT_G0 COMBINER_IRQ(23, 3)
> -#define EXYNOS5_IRQ_MCT_G1 COMBINER_IRQ(23, 4)
>
> #define EXYNOS5_IRQ_EINT1 COMBINER_IRQ(24, 0)
> #define EXYNOS5_IRQ_SYSMMU_LITE1_0 COMBINER_IRQ(24, 1)
> diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c
> index d65d0c7..f7792b8 100644
> --- a/arch/arm/mach-exynos/mct.c
> +++ b/arch/arm/mach-exynos/mct.c
> @@ -19,6 +19,9 @@
> #include<linux/platform_device.h>
> #include<linux/delay.h>
> #include<linux/percpu.h>
> +#include<linux/of.h>
> +#include<linux/of_irq.h>
> +#include<linux/of_address.h>
>
> #include<asm/hardware/gic.h>
> #include<asm/localtimer.h>
> @@ -483,14 +486,16 @@ static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = {
> };
> #endif /* CONFIG_LOCAL_TIMERS */
>
> -static void __init exynos4_timer_resources(void)
> +static void __init exynos4_timer_resources(struct device_node *np)
> {
> struct clk *mct_clk;
> mct_clk = clk_get(NULL, "xtal");
>
> clk_rate = clk_get_rate(mct_clk);
>
> - reg_base = S5P_VA_SYSTIMER;
> + reg_base = (np) ? of_iomap(np, 0) : S5P_VA_SYSTIMER;
nit: Parentheses around np look redundant.
> + if (!reg_base)
> + panic("%s: unable to ioremap mct address space\n", __func__);
How about adding a line like:
#define pr_fmt(fmt) "%s: " fmt, __func__
on top of this file and dropping "%s: " and __func__ in those panic()
calls ? It would make the logs more consistent across whole file.
> #ifdef CONFIG_LOCAL_TIMERS
> if (mct_int_type == MCT_INT_PPI) {
> @@ -509,23 +514,34 @@ static void __init exynos4_timer_resources(void)
>
> static void __init exynos4_timer_init(void)
> {
> - if (soc_is_exynos4210()) {
> + struct device_node *np;
> + u32 nr_irqs, i;
> +
> + np = of_find_compatible_node(NULL, NULL, "samsung,exynos4210-mct");
> + if (np) {
> + if (of_machine_is_compatible("samsung,exynos4210") ||
> + of_machine_is_compatible("samsung,exynos5250"))
> + mct_int_type = MCT_INT_SPI;
> + else
> + mct_int_type = MCT_INT_PPI;
Does it make sense to specify this mct_int_type as a property of
the mct node ?
> +
> + if (of_property_read_u32(np, "samsung,mct-nr-local-irqs",
> + &nr_irqs))
> + panic("%s: number of local irqs not specified\n",
> + __func__);
> +
> + mct_irqs[MCT_G0_IRQ] = irq_of_parse_and_map(np, MCT_G0_IRQ);
> + for (i = 0; i< nr_irqs; i++)
> + mct_irqs[MCT_L0_IRQ + i] =
> + irq_of_parse_and_map(np, MCT_L0_IRQ + i);
> + } else if (soc_is_exynos4210()) {
> mct_irqs[MCT_G0_IRQ] = EXYNOS4_IRQ_MCT_G0;
> mct_irqs[MCT_L0_IRQ] = EXYNOS4_IRQ_MCT_L0;
> mct_irqs[MCT_L1_IRQ] = EXYNOS4_IRQ_MCT_L1;
> mct_int_type = MCT_INT_SPI;
> - } else if (soc_is_exynos5250()) {
> - mct_irqs[MCT_G0_IRQ] = EXYNOS5_IRQ_MCT_G0;
> - mct_irqs[MCT_L0_IRQ] = EXYNOS5_IRQ_MCT_L0;
> - mct_irqs[MCT_L1_IRQ] = EXYNOS5_IRQ_MCT_L1;
> - mct_int_type = MCT_INT_SPI;
> - } else {
> - mct_irqs[MCT_G0_IRQ] = EXYNOS4_IRQ_MCT_G0;
> - mct_irqs[MCT_L0_IRQ] = EXYNOS_IRQ_MCT_LOCALTIMER;
> - mct_int_type = MCT_INT_PPI;
> }
>
> - exynos4_timer_resources();
> + exynos4_timer_resources(np);
> exynos4_clocksource_init();
> exynos4_clockevent_init();
> }
--
Regards,
Sylwester
^ permalink raw reply
* [PATCH 15/15] ARM: OMAP2+: AM33XX: Basic suspend resume support
From: Santosh Shilimkar @ 2012-11-03 16:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351859566-24818-16-git-send-email-vaibhav.bedia@ti.com>
On Friday 02 November 2012 06:02 PM, Vaibhav Bedia wrote:
> AM335x supports various low power modes as documented
> in section 8.1.4.3 of the AM335x TRM which is available
> @ http://www.ti.com/litv/pdf/spruh73f
>
> DeepSleep0 mode offers the lowest power mode with limited
> wakeup sources without a system reboot and is mapped as
> the suspend state in the kernel. In this state, MPU and
> PER domains are turned off with the internal RAM held in
> retention to facilitate resume process. As part of the boot
> process, the assembly code is copied over to OCMCRAM using
> the OMAP SRAM code.
>
> AM335x has a Cortex-M3 (WKUP_M3) which assists the MPU
> in DeepSleep0 entry and exit. WKUP_M3 takes care of the
> clockdomain and powerdomain transitions based on the
> intended low power state. MPU needs to load the appropriate
> WKUP_M3 binary onto the WKUP_M3 memory space before it can
> leverage any of the PM features like DeepSleep.
>
> The IPC mechanism between MPU and WKUP_M3 uses a mailbox
> sub-module and 8 IPC registers in the Control module. MPU
> uses the assigned Mailbox for issuing an interrupt to
> WKUP_M3 which then goes and checks the IPC registers for
> the payload. WKUP_M3 has the ability to trigger on interrupt
> to MPU by executing the "sev" instruction.
>
> In the current implementation when the suspend process
> is initiated MPU interrupts the WKUP_M3 to let about the
> intent of entering DeepSleep0 and waits for an ACK. When
> the ACK is received, MPU continues with its suspend process
> to suspend all the drivers and then jumps to assembly in
> OCMC RAM to put the PLLs in bypass, put the external RAM in
> self-refresh mode and then finally execute the WFI instruction.
> The WFI instruction triggers another interrupt to the WKUP_M3
> which then continues wiht the power down sequence wherein the
> clockdomain and powerdomain transition takes place. As part of
> the sleep sequence, WKUP_M3 unmasks the interrupt lines for
> the wakeup sources. When WKUP_M3 executes WFI, the hardware
> disables the main oscillator.
>
> When a wakeup event occurs, WKUP_M3 starts the power-up
> sequence by switching on the power domains and finally
> enabling the clock to MPU. Since the MPU gets powered down
> as part of the sleep sequence, in the resume path ROM code
> starts executing. The ROM code detects a wakeup from sleep
> and then jumps to the resume location in OCMC which was
> populated in one of the IPC registers as part of the suspend
> sequence.
>
> The low level code in OCMC relocks the PLLs, enables access
> to external RAM and then jumps to the cpu_resume code of
> the kernel to finish the resume process.
>
Nice descriptive change log Vaibhav.
> Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
> ---
> arch/arm/mach-omap2/Makefile | 2 +
> arch/arm/mach-omap2/board-generic.c | 1 +
> arch/arm/mach-omap2/common.h | 10 +
> arch/arm/mach-omap2/io.c | 7 +
> arch/arm/mach-omap2/pm.h | 7 +
> arch/arm/mach-omap2/pm33xx.c | 429 ++++++++++++++++++++++++++
> arch/arm/mach-omap2/pm33xx.h | 100 ++++++
> arch/arm/mach-omap2/sleep33xx.S | 571 +++++++++++++++++++++++++++++++++++
> arch/arm/plat-omap/sram.c | 10 +-
> arch/arm/plat-omap/sram.h | 2 +
> 10 files changed, 1138 insertions(+), 1 deletions(-)
> create mode 100644 arch/arm/mach-omap2/pm33xx.c
> create mode 100644 arch/arm/mach-omap2/pm33xx.h
> create mode 100644 arch/arm/mach-omap2/sleep33xx.S
>
> diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
> index ae87a3e..80736aa 100644
> --- a/arch/arm/mach-omap2/Makefile
> +++ b/arch/arm/mach-omap2/Makefile
> @@ -71,6 +71,7 @@ endif
> ifeq ($(CONFIG_PM),y)
> obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o
> obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o
> +obj-$(CONFIG_SOC_AM33XX) += pm33xx.o sleep33xx.o
> obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o
> obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o omap-mpuss-lowpower.o
> obj-$(CONFIG_SOC_OMAP5) += omap-mpuss-lowpower.o
> @@ -80,6 +81,7 @@ obj-$(CONFIG_POWER_AVS_OMAP) += sr_device.o
> obj-$(CONFIG_POWER_AVS_OMAP_CLASS3) += smartreflex-class3.o
>
> AFLAGS_sleep24xx.o :=-Wa,-march=armv6
> +AFLAGS_sleep33xx.o :=-Wa,-march=armv7-a$(plus_sec)
> AFLAGS_sleep34xx.o :=-Wa,-march=armv7-a$(plus_sec)
>
> ifeq ($(CONFIG_PM_VERBOSE),y)
> diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
> index 601ecdf..23894df 100644
> --- a/arch/arm/mach-omap2/board-generic.c
> +++ b/arch/arm/mach-omap2/board-generic.c
> @@ -109,6 +109,7 @@ DT_MACHINE_START(AM33XX_DT, "Generic AM33XX (Flattened Device Tree)")
> .reserve = omap_reserve,
> .map_io = am33xx_map_io,
> .init_early = am33xx_init_early,
> + .init_late = am33xx_init_late,
> .init_irq = omap_intc_of_init,
> .handle_irq = omap3_intc_handle_irq,
> .init_machine = omap_generic_init,
> diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
> index c925c80..d4319ad 100644
> --- a/arch/arm/mach-omap2/common.h
> +++ b/arch/arm/mach-omap2/common.h
> @@ -109,6 +109,15 @@ static inline int omap3_pm_init(void)
> }
> #endif
>
> +#if defined(CONFIG_PM) && defined(CONFIG_SOC_AM33XX)
> +int am33xx_pm_init(void);
> +#else
> +static inline int am33xx_pm_init(void)
> +{
> + return 0;
> +}
> +#endif
> +
> #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP4)
> int omap4_pm_init(void);
> #else
> @@ -157,6 +166,7 @@ void am33xx_init_early(void);
> void omap4430_init_early(void);
> void omap5_init_early(void);
> void omap3_init_late(void); /* Do not use this one */
> +void am33xx_init_late(void);
> void omap4430_init_late(void);
> void omap2420_init_late(void);
> void omap2430_init_late(void);
> diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
> index 4fadc78..d06f84a 100644
> --- a/arch/arm/mach-omap2/io.c
> +++ b/arch/arm/mach-omap2/io.c
> @@ -528,6 +528,13 @@ void __init am33xx_init_early(void)
> omap_hwmod_init_postsetup();
> am33xx_clk_init();
> }
> +
> +void __init am33xx_init_late(void)
> +{
> + omap_mux_late_init();
> + omap2_common_pm_late_init();
> + am33xx_pm_init();
> +}
> #endif
>
> #ifdef CONFIG_ARCH_OMAP4
> diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
> index 67d6613..d37f20e 100644
> --- a/arch/arm/mach-omap2/pm.h
> +++ b/arch/arm/mach-omap2/pm.h
> @@ -83,6 +83,13 @@ extern unsigned int omap3_do_wfi_sz;
> /* ... and its pointer from SRAM after copy */
> extern void (*omap3_do_wfi_sram)(void);
>
> +/* am33xx_do_wfi function pointer and size, for copy to SRAM */
> +extern void am33xx_do_wfi(void);
> +extern unsigned int am33xx_do_wfi_sz;
> +extern unsigned int am33xx_resume_offset;
> +/* ... and its pointer from SRAM after copy */
> +extern void (*am33xx_do_wfi_sram)(void);
> +
> /* save_secure_ram_context function pointer and size, for copy to SRAM */
> extern int save_secure_ram_context(u32 *addr);
> extern unsigned int save_secure_ram_context_sz;
> diff --git a/arch/arm/mach-omap2/pm33xx.c b/arch/arm/mach-omap2/pm33xx.c
> new file mode 100644
> index 0000000..836af52
> --- /dev/null
> +++ b/arch/arm/mach-omap2/pm33xx.c
> @@ -0,0 +1,429 @@
> +/*
> + * AM33XX Power Management Routines
> + *
> + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
> + * Vaibhav Bedia <vaibhav.bedia@ti.com>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation version 2.
> + *
> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> + * kind, whether express or implied; without even the implied warranty
> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/init.h>
> +#include <linux/err.h>
> +#include <linux/firmware.h>
> +#include <linux/io.h>
> +#include <linux/platform_device.h>
> +#include <linux/sched.h>
> +#include <linux/suspend.h>
> +#include <linux/completion.h>
> +#include <linux/module.h>
> +
> +#include <plat/prcm.h>
> +#include <plat/mailbox.h>
> +#include "../plat-omap/sram.h"
> +
> +#include <asm/suspend.h>
> +#include <asm/proc-fns.h>
> +#include <asm/sizes.h>
> +#include <asm/system_misc.h>
> +
> +#include "pm.h"
> +#include "cm33xx.h"
> +#include "pm33xx.h"
> +#include "control.h"
> +#include "clockdomain.h"
> +#include "powerdomain.h"
> +#include "omap_hwmod.h"
> +#include "omap_device.h"
> +#include "soc.h"
> +
In case not checked yet, see if you need
all above headers.
> +void (*am33xx_do_wfi_sram)(void);
> +
> +static void __iomem *am33xx_emif_base;
> +static struct powerdomain *cefuse_pwrdm, *gfx_pwrdm, *per_pwrdm;
> +static struct clockdomain *gfx_l3_clkdm, *gfx_l4ls_clkdm;
> +static struct wkup_m3_context *wkup_m3;
> +
> +static DECLARE_COMPLETION(wkup_m3_sync);
> +
> +#ifdef CONFIG_SUSPEND
> +static int am33xx_do_sram_idle(long unsigned int unused)
> +{
> + am33xx_do_wfi_sram();
> + return 0;
> +}
> +
> +static int am33xx_pm_suspend(void)
> +{
> + int status, ret = 0;
> +
> + struct omap_hwmod *gpmc_oh, *usb_oh;
> + struct omap_hwmod *tptc0_oh, *tptc1_oh, *tptc2_oh;
> +
> + /*
> + * By default the following IPs do not have MSTANDBY asserted
> + * which is necessary for PER domain transition. If the drivers
> + * are not compiled into the kernel HWMOD code will not change the
> + * state of the IPs if the IP was not never enabled
> + */
> + usb_oh = omap_hwmod_lookup("usb_otg_hs");
> + gpmc_oh = omap_hwmod_lookup("gpmc");
> + tptc0_oh = omap_hwmod_lookup("tptc0");
> + tptc1_oh = omap_hwmod_lookup("tptc1");
> + tptc2_oh = omap_hwmod_lookup("tptc2");
> +
This look you don't need every suspend.
> + omap_hwmod_enable(usb_oh);
> + omap_hwmod_enable(gpmc_oh);
> + omap_hwmod_enable(tptc0_oh);
> + omap_hwmod_enable(tptc1_oh);
> + omap_hwmod_enable(tptc2_oh);
> +
> + omap_hwmod_idle(usb_oh);
> + omap_hwmod_idle(gpmc_oh);
> + omap_hwmod_idle(tptc0_oh);
> + omap_hwmod_idle(tptc1_oh);
> + omap_hwmod_idle(tptc2_oh);
> +
Calling omap_hwmod_idle() directly tells me something is not
right. Can these module not idle themself with respective device
drivers ?
> + /* Put the GFX clockdomains to sleep */
> + clkdm_sleep(gfx_l3_clkdm);
> + clkdm_sleep(gfx_l4ls_clkdm);
Can GFX driver suspend code not take care of above ?
Also are these clock domains are not supporting HW supervised
mode ?
> + /* Try to put GFX to sleep */
> + pwrdm_set_next_pwrst(gfx_pwrdm, PWRDM_POWER_OFF);
> +
Above as well can be taken care by constraint QOS API by
GFX driver.
> + ret = cpu_suspend(0, am33xx_do_sram_idle);
> +
> + status = pwrdm_read_pwrst(gfx_pwrdm);
> + if (status != PWRDM_POWER_OFF)
> + pr_err("GFX domain did not transition\n");
> + else
> + pr_info("GFX domain entered low power state\n");
> +
> + /* Needed to ensure L4LS clockdomain transitions properly */
> + clkdm_wakeup(gfx_l3_clkdm);
> + clkdm_wakeup(gfx_l4ls_clkdm);
> +
> + if (ret) {
> + pr_err("Kernel suspend failure\n");
> + } else {
> + status = omap_ctrl_readl(AM33XX_CONTROL_IPC_MSG_REG1);
> + status &= IPC_RESP_MASK;
> + status >>= __ffs(IPC_RESP_MASK);
> +
> + switch (status) {
> + case 0:
> + pr_info("Successfully transitioned to low power state\n");
> + if (wkup_m3->sleep_mode == IPC_CMD_DS0)
> + /* XXX: Use SOC specific ops for this? */
> + per_pwrdm->ret_logic_off_counter++;
> + break;
> + case 1:
> + pr_err("Could not enter low power state\n");
> + ret = -1;
> + break;
> + default:
> + pr_err("Something is terribly wrong :(\nStatus = %d\n",
> + status);
Sounds terrible :-)
> + ret = -1;
> + }
> + }
> +
> + return ret;
> +}
> +
> +static int am33xx_pm_enter(suspend_state_t suspend_state)
> +{
> + int ret = 0;
> +
> + switch (suspend_state) {
> + case PM_SUSPEND_STANDBY:
> + case PM_SUSPEND_MEM:
> + ret = am33xx_pm_suspend();
> + break;
> + default:
> + ret = -EINVAL;
> + }
> +
> + return ret;
> +}
> +
> +static int am33xx_pm_begin(suspend_state_t state)
> +{
> + int ret = 0;
> +
> + disable_hlt();
> +
> + /*
> + * Physical resume address to be used by ROM code
> + */
> + wkup_m3->resume_addr = (AM33XX_OCMC_END - am33xx_do_wfi_sz +
> + am33xx_resume_offset + 0x4);
> +
> + wkup_m3->sleep_mode = IPC_CMD_DS0;
> + wkup_m3->ipc_data1 = DS_IPC_DEFAULT;
> + wkup_m3->ipc_data2 = DS_IPC_DEFAULT;
> +
> + am33xx_ipc_cmd();
> +
> + wkup_m3->state = M3_STATE_MSG_FOR_LP;
> +
> + omap_mbox_enable_irq(wkup_m3->mbox, IRQ_RX);
> +
> + ret = omap_mbox_msg_send(wkup_m3->mbox, 0xABCDABCD);
> + if (ret) {
> + pr_err("A8<->CM3 MSG for LP failed\n");
> + am33xx_m3_state_machine_reset();
> + ret = -1;
> + }
> +
> + if (!wait_for_completion_timeout(&wkup_m3_sync,
> + msecs_to_jiffies(500))) {
500 is from spec or arbitrary timeout ?
> +/*
> + * Push the minimal suspend-resume code to SRAM
> + */
> +void am33xx_push_sram_idle(void)
> +{
> + am33xx_do_wfi_sram = (void *)omap_sram_push
> + (am33xx_do_wfi, am33xx_do_wfi_sz);
> +}
> +
> +static int __init am33xx_map_emif(void)
> +{
> + am33xx_emif_base = ioremap(AM33XX_EMIF_BASE, SZ_32K);
> +
> + if (!am33xx_emif_base)
> + return -ENOMEM;
> +
> + return 0;
> +}
> +
> +void __iomem *am33xx_get_emif_base(void)
> +{
> + return am33xx_emif_base;
> +}
> +
> +int __init am33xx_pm_init(void)
> +{
> + int ret;
> +
> + if (!soc_is_am33xx())
> + return -ENODEV;
> +
> + pr_info("Power Management for AM33XX family\n");
> +
> + wkup_m3 = kzalloc(sizeof(struct wkup_m3_context), GFP_KERNEL);
> + if (!wkup_m3) {
> + pr_err("Memory allocation failed\n");
> + return -ENOMEM;
> + }
> +
> + ret = am33xx_map_emif();
> +
No EMIF driver to handle EMIF MAP, registers etc ?
> + (void) clkdm_for_each(omap_pm_clkdms_setup, NULL);
> +
> + /* CEFUSE domain should be turned off post bootup */
> + cefuse_pwrdm = pwrdm_lookup("cefuse_pwrdm");
> + if (cefuse_pwrdm)
> + pwrdm_set_next_pwrst(cefuse_pwrdm, PWRDM_POWER_OFF);
> + else
> + pr_err("Failed to get cefuse_pwrdm\n");
> +
> + gfx_pwrdm = pwrdm_lookup("gfx_pwrdm");
> + per_pwrdm = pwrdm_lookup("per_pwrdm");
> +
> + gfx_l3_clkdm = clkdm_lookup("gfx_l3_clkdm");
> + gfx_l4ls_clkdm = clkdm_lookup("gfx_l4ls_gfx_clkdm");
> +
> + wkup_m3->dev = omap_device_get_by_hwmod_name("wkup_m3");
> +
> + ret = wkup_m3_init();
> + if (ret)
> + pr_err("Could not initialise firmware loading\n");
> +
> + return ret;
> +}
> diff --git a/arch/arm/mach-omap2/pm33xx.h b/arch/arm/mach-omap2/pm33xx.h
> new file mode 100644
> index 0000000..38f8ae7
> --- /dev/null
> +++ b/arch/arm/mach-omap2/pm33xx.h
> @@ -0,0 +1,100 @@
> +/*
> + * AM33XX Power Management Routines
> + *
> + * Copyright (C) 2012 Texas Instruments Inc.
> + * Vaibhav Bedia <vaibhav.bedia@ti.com>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation version 2.
> + *
> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> + * kind, whether express or implied; without even the implied warranty
> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#ifndef __ARCH_ARM_MACH_OMAP2_PM33XX_H
> +#define __ARCH_ARM_MACH_OMAP2_PM33XX_H
> +
> +#ifndef __ASSEMBLER__
> +struct wkup_m3_context {
> + struct device *dev;
> + struct firmware *firmware;
> + struct omap_mbox *mbox;
> + void __iomem *code;
> + int resume_addr;
> + int ipc_data1;
> + int ipc_data2;
> + int sleep_mode;
> + u8 state;
> +};
> +
> +#ifdef CONFIG_SUSPEND
> +static void am33xx_ipc_cmd(void);
> +static void am33xx_m3_state_machine_reset(void);
> +#else
> +static inline void am33xx_ipc_cmd(void) {}
> +static inline void am33xx_m3_state_machine_reset(void) {}
> +#endif /* CONFIG_SUSPEND */
> +
> +extern void __iomem *am33xx_get_emif_base(void);
> +int wkup_mbox_msg(struct notifier_block *self, unsigned long len, void *msg);
> +#endif
> +
> +#define IPC_CMD_DS0 0x3
> +#define IPC_CMD_RESET 0xe
> +#define DS_IPC_DEFAULT 0xffffffff
> +
> +#define IPC_RESP_SHIFT 16
> +#define IPC_RESP_MASK (0xffff << 16)
> +
> +#define M3_STATE_UNKNOWN 0
> +#define M3_STATE_RESET 1
> +#define M3_STATE_INITED 2
> +#define M3_STATE_MSG_FOR_LP 3
> +#define M3_STATE_MSG_FOR_RESET 4
> +
> +#define AM33XX_OCMC_END 0x40310000
> +#define AM33XX_EMIF_BASE 0x4C000000
> +
> +/*
> + * This a subset of registers defined in drivers/memory/emif.h
> + * Move that to include/linux/?
> + */
> +#define EMIF_MODULE_ID_AND_REVISION 0x0000
> +#define EMIF_STATUS 0x0004
> +#define EMIF_SDRAM_CONFIG 0x0008
> +#define EMIF_SDRAM_CONFIG_2 0x000c
> +#define EMIF_SDRAM_REFRESH_CONTROL 0x0010
> +#define EMIF_SDRAM_REFRESH_CTRL_SHDW 0x0014
> +#define EMIF_SDRAM_TIMING_1 0x0018
> +#define EMIF_SDRAM_TIMING_1_SHDW 0x001c
> +#define EMIF_SDRAM_TIMING_2 0x0020
> +#define EMIF_SDRAM_TIMING_2_SHDW 0x0024
> +#define EMIF_SDRAM_TIMING_3 0x0028
> +#define EMIF_SDRAM_TIMING_3_SHDW 0x002c
> +#define EMIF_LPDDR2_NVM_TIMING 0x0030
> +#define EMIF_LPDDR2_NVM_TIMING_SHDW 0x0034
> +#define EMIF_POWER_MANAGEMENT_CONTROL 0x0038
> +#define EMIF_POWER_MANAGEMENT_CTRL_SHDW 0x003c
> +#define EMIF_PERFORMANCE_COUNTER_1 0x0080
> +#define EMIF_PERFORMANCE_COUNTER_2 0x0084
> +#define EMIF_PERFORMANCE_COUNTER_CONFIG 0x0088
> +#define EMIF_PERFORMANCE_COUNTER_MASTER_REGION_SELECT 0x008c
> +#define EMIF_PERFORMANCE_COUNTER_TIME 0x0090
> +#define EMIF_MISC_REG 0x0094
> +#define EMIF_DLL_CALIB_CTRL 0x0098
> +#define EMIF_DLL_CALIB_CTRL_SHDW 0x009c
> +#define EMIF_SYSTEM_OCP_INTERRUPT_RAW_STATUS 0x00a4
> +#define EMIF_SYSTEM_OCP_INTERRUPT_STATUS 0x00ac
> +#define EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET 0x00b4
> +#define EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_CLEAR 0x00bc
> +#define EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG 0x00c8
> +#define EMIF_READ_WRITE_LEVELING_RAMP_WINDOW 0x00d4
> +#define EMIF_READ_WRITE_LEVELING_RAMP_CONTROL 0x00d8
> +#define EMIF_READ_WRITE_LEVELING_CONTROL 0x00dc
> +#define EMIF_DDR_PHY_CTRL_1 0x00e4
> +#define EMIF_DDR_PHY_CTRL_1_SHDW 0x00e8
> +
Above should be part of the EMIF driver, no ?
> +#endif
> diff --git a/arch/arm/mach-omap2/sleep33xx.S b/arch/arm/mach-omap2/sleep33xx.S
> new file mode 100644
> index 0000000..f7b34e5
> --- /dev/null
> +++ b/arch/arm/mach-omap2/sleep33xx.S
> @@ -0,0 +1,571 @@
> +/*
> + * Low level suspend code for AM33XX SoCs
> + *
> + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
> + * Vaibhav Bedia <vaibhav.bedia@ti.com>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation version 2.
> + *
> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> + * kind, whether express or implied; without even the implied warranty
> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/linkage.h>
> +#include <asm/memory.h>
> +#include <asm/assembler.h>
> +
> +#include "cm33xx.h"
> +#include "pm33xx.h"
> +#include "prm33xx.h"
> +#include "control.h"
> +
> +/* replicated define because linux/bitops.h cannot be included in assembly */
> +#define BIT(nr) (1 << (nr))
> +
> + .text
> + .align 3
> +
Sleep code looks pretty big so I will have a closer look at it bit
later. At least from the code it seems, the EMIF registers and hence
memory controller needs to be maneged by SW which is really bad.
Regards
Santosh
^ permalink raw reply
* Possible regression in 3.7-rc3 on Marvell Kirkwood
From: Andrew Lunn @ 2012-11-03 17:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAMW5UfYmjCq0nnGY6bxV_HxizHSV0UiW74thhers096ufv3E_g@mail.gmail.com>
On Sat, Nov 03, 2012 at 08:54:21AM -0400, Josh Coombs wrote:
> I'll fire up with ignore log level to get the full traces and post
> those this afternoon. Given it will be a LOT of text, would you
> prefer I include them in the email, pastebin the output and provide
> links, or dump the log onto my webserver with a link?
Hi Josh
I'm kind of expecting they will all look very similar. By looking at
what is common it might quick become clear where the lock is being
taken which is causing the problem.
Anyway, i would suggest posting the first couple of traces to the list
and a few more to me directly.
Andrew
^ permalink raw reply
* [PATCH RFC net-next 0/1] Simplify the CPSW DT
From: Richard Cochran @ 2012-11-03 17:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <509240CF.6060909@ti.com>
This patch is a follow up to show how to remove all the various
register offsets from the DT for the CPSW driver. This applies on top
of the bug fix I posted earlier for IO mapping leak.
Since I am currently awaiting a replacement for my defective
BeagleBone, this patch is compile tested only.
Thanks,
Richard
Richard Cochran (1):
cpsw: simplify the setup of the register pointers
Documentation/devicetree/bindings/net/cpsw.txt | 34 ----
drivers/net/ethernet/ti/cpsw.c | 209 +++++++++--------------
include/linux/platform_data/cpsw.h | 19 --
3 files changed, 82 insertions(+), 180 deletions(-)
--
1.7.2.5
^ permalink raw reply
* [PATCH RFC net-next 1/1] cpsw: simplify the setup of the register pointers
From: Richard Cochran @ 2012-11-03 17:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <509240CF.6060909@ti.com>
Instead of having a host of different register offsets in the device tree,
this patch simplifies the CPSW code by letting the driver set the proper
register offsets automatically, based on the CPSW version.
Signed-off-by: Richard Cochran <richardcochran@gmail.com>
---
Documentation/devicetree/bindings/net/cpsw.txt | 34 ----
drivers/net/ethernet/ti/cpsw.c | 209 +++++++++--------------
include/linux/platform_data/cpsw.h | 19 --
3 files changed, 82 insertions(+), 180 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/cpsw.txt b/Documentation/devicetree/bindings/net/cpsw.txt
index 2214607..6cf5d92 100644
--- a/Documentation/devicetree/bindings/net/cpsw.txt
+++ b/Documentation/devicetree/bindings/net/cpsw.txt
@@ -9,15 +9,7 @@ Required properties:
number
- interrupt-parent : The parent interrupt controller
- cpdma_channels : Specifies number of channels in CPDMA
-- host_port_no : Specifies host port shift
-- cpdma_reg_ofs : Specifies CPDMA submodule register offset
-- cpdma_sram_ofs : Specifies CPDMA SRAM offset
-- ale_reg_ofs : Specifies ALE submodule register offset
- ale_entries : Specifies No of entries ALE can hold
-- host_port_reg_ofs : Specifies host port register offset
-- hw_stats_reg_ofs : Specifies hardware statistics register offset
-- cpts_reg_ofs : Specifies the offset of the CPTS registers
-- bd_ram_ofs : Specifies internal desciptor RAM offset
- bd_ram_size : Specifies internal descriptor RAM size
- rx_descs : Specifies number of Rx descriptors
- mac_control : Specifies Default MAC control register content
@@ -26,8 +18,6 @@ Required properties:
- cpts_active_slave : Specifies the slave to use for time stamping
- cpts_clock_mult : Numerator to convert input clock ticks into nanoseconds
- cpts_clock_shift : Denominator to convert input clock ticks into nanoseconds
-- slave_reg_ofs : Specifies slave register offset
-- sliver_reg_ofs : Specifies slave sliver register offset
- phy_id : Specifies slave phy id
- mac-address : Specifies slave MAC address
@@ -49,15 +39,7 @@ Examples:
interrupts = <55 0x4>;
interrupt-parent = <&intc>;
cpdma_channels = <8>;
- host_port_no = <0>;
- cpdma_reg_ofs = <0x800>;
- cpdma_sram_ofs = <0xa00>;
- ale_reg_ofs = <0xd00>;
ale_entries = <1024>;
- host_port_reg_ofs = <0x108>;
- hw_stats_reg_ofs = <0x900>;
- cpts_reg_ofs = <0xc00>;
- bd_ram_ofs = <0x2000>;
bd_ram_size = <0x2000>;
no_bd_ram = <0>;
rx_descs = <64>;
@@ -67,15 +49,11 @@ Examples:
cpts_clock_mult = <0x80000000>;
cpts_clock_shift = <29>;
cpsw_emac0: slave at 0 {
- slave_reg_ofs = <0x200>;
- sliver_reg_ofs = <0xd80>;
phy_id = "davinci_mdio.16:00";
/* Filled in by U-Boot */
mac-address = [ 00 00 00 00 00 00 ];
};
cpsw_emac1: slave at 1 {
- slave_reg_ofs = <0x300>;
- sliver_reg_ofs = <0xdc0>;
phy_id = "davinci_mdio.16:01";
/* Filled in by U-Boot */
mac-address = [ 00 00 00 00 00 00 ];
@@ -87,15 +65,7 @@ Examples:
compatible = "ti,cpsw";
ti,hwmods = "cpgmac0";
cpdma_channels = <8>;
- host_port_no = <0>;
- cpdma_reg_ofs = <0x800>;
- cpdma_sram_ofs = <0xa00>;
- ale_reg_ofs = <0xd00>;
ale_entries = <1024>;
- host_port_reg_ofs = <0x108>;
- hw_stats_reg_ofs = <0x900>;
- cpts_reg_ofs = <0xc00>;
- bd_ram_ofs = <0x2000>;
bd_ram_size = <0x2000>;
no_bd_ram = <0>;
rx_descs = <64>;
@@ -105,15 +75,11 @@ Examples:
cpts_clock_mult = <0x80000000>;
cpts_clock_shift = <29>;
cpsw_emac0: slave at 0 {
- slave_reg_ofs = <0x200>;
- sliver_reg_ofs = <0xd80>;
phy_id = "davinci_mdio.16:00";
/* Filled in by U-Boot */
mac-address = [ 00 00 00 00 00 00 ];
};
cpsw_emac1: slave at 1 {
- slave_reg_ofs = <0x300>;
- sliver_reg_ofs = <0xdc0>;
phy_id = "davinci_mdio.16:01";
/* Filled in by U-Boot */
mac-address = [ 00 00 00 00 00 00 ];
diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index 7654a62..cf53379 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -80,6 +80,29 @@ do { \
#define CPSW_VERSION_1 0x19010a
#define CPSW_VERSION_2 0x19010c
+
+#define HOST_PORT_NUM 0
+#define SLIVER_SIZE 0x40
+
+#define CPSW1_HOST_PORT_OFFSET 0x028
+#define CPSW1_SLAVE_OFFSET 0x050
+#define CPSW1_SLAVE_SIZE 0x040
+#define CPSW1_CPDMA_OFFSET 0x100
+#define CPSW1_STATERAM_OFFSET 0x200
+#define CPSW1_CPTS_OFFSET 0x500
+#define CPSW1_ALE_OFFSET 0x600
+#define CPSW1_SLIVER_OFFSET 0x700
+
+#define CPSW2_HOST_PORT_OFFSET 0x108
+#define CPSW2_SLAVE_OFFSET 0x200
+#define CPSW2_SLAVE_SIZE 0x100
+#define CPSW2_CPDMA_OFFSET 0x800
+#define CPSW2_STATERAM_OFFSET 0xa00
+#define CPSW2_CPTS_OFFSET 0xc00
+#define CPSW2_ALE_OFFSET 0xd00
+#define CPSW2_SLIVER_OFFSET 0xd80
+#define CPSW2_BD_OFFSET 0x2000
+
#define CPDMA_RXTHRESH 0x0c0
#define CPDMA_RXFREE 0x0e0
#define CPDMA_TXHDP 0x00
@@ -87,21 +110,6 @@ do { \
#define CPDMA_TXCP 0x40
#define CPDMA_RXCP 0x60
-#define cpsw_dma_regs(base, offset) \
- (void __iomem *)((base) + (offset))
-#define cpsw_dma_rxthresh(base, offset) \
- (void __iomem *)((base) + (offset) + CPDMA_RXTHRESH)
-#define cpsw_dma_rxfree(base, offset) \
- (void __iomem *)((base) + (offset) + CPDMA_RXFREE)
-#define cpsw_dma_txhdp(base, offset) \
- (void __iomem *)((base) + (offset) + CPDMA_TXHDP)
-#define cpsw_dma_rxhdp(base, offset) \
- (void __iomem *)((base) + (offset) + CPDMA_RXHDP)
-#define cpsw_dma_txcp(base, offset) \
- (void __iomem *)((base) + (offset) + CPDMA_TXCP)
-#define cpsw_dma_rxcp(base, offset) \
- (void __iomem *)((base) + (offset) + CPDMA_RXCP)
-
#define CPSW_POLL_WEIGHT 64
#define CPSW_MIN_PACKET_SIZE 60
#define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4)
@@ -629,8 +637,7 @@ static int cpsw_ndo_open(struct net_device *ndev)
pm_runtime_get_sync(&priv->pdev->dev);
- reg = __raw_readl(&priv->regs->id_ver);
- priv->version = reg;
+ reg = priv->version;
dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
@@ -995,15 +1002,16 @@ static const struct ethtool_ops cpsw_ethtool_ops = {
.get_ts_info = cpsw_get_ts_info,
};
-static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv)
+static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv,
+ u32 slave_reg_ofs, u32 sliver_reg_ofs)
{
void __iomem *regs = priv->regs;
int slave_num = slave->slave_num;
struct cpsw_slave_data *data = priv->data.slave_data + slave_num;
slave->data = data;
- slave->regs = regs + data->slave_reg_ofs;
- slave->sliver = regs + data->sliver_reg_ofs;
+ slave->regs = regs + slave_reg_ofs;
+ slave->sliver = regs + sliver_reg_ofs;
}
static int cpsw_probe_dt(struct cpsw_platform_data *data,
@@ -1051,8 +1059,6 @@ static int cpsw_probe_dt(struct cpsw_platform_data *data,
return -EINVAL;
}
- data->no_bd_ram = of_property_read_bool(node, "no_bd_ram");
-
if (of_property_read_u32(node, "cpdma_channels", &prop)) {
pr_err("Missing cpdma_channels property in the DT.\n");
ret = -EINVAL;
@@ -1060,34 +1066,6 @@ static int cpsw_probe_dt(struct cpsw_platform_data *data,
}
data->channels = prop;
- if (of_property_read_u32(node, "host_port_no", &prop)) {
- pr_err("Missing host_port_no property in the DT.\n");
- ret = -EINVAL;
- goto error_ret;
- }
- data->host_port_num = prop;
-
- if (of_property_read_u32(node, "cpdma_reg_ofs", &prop)) {
- pr_err("Missing cpdma_reg_ofs property in the DT.\n");
- ret = -EINVAL;
- goto error_ret;
- }
- data->cpdma_reg_ofs = prop;
-
- if (of_property_read_u32(node, "cpdma_sram_ofs", &prop)) {
- pr_err("Missing cpdma_sram_ofs property in the DT.\n");
- ret = -EINVAL;
- goto error_ret;
- }
- data->cpdma_sram_ofs = prop;
-
- if (of_property_read_u32(node, "ale_reg_ofs", &prop)) {
- pr_err("Missing ale_reg_ofs property in the DT.\n");
- ret = -EINVAL;
- goto error_ret;
- }
- data->ale_reg_ofs = prop;
-
if (of_property_read_u32(node, "ale_entries", &prop)) {
pr_err("Missing ale_entries property in the DT.\n");
ret = -EINVAL;
@@ -1095,34 +1073,6 @@ static int cpsw_probe_dt(struct cpsw_platform_data *data,
}
data->ale_entries = prop;
- if (of_property_read_u32(node, "host_port_reg_ofs", &prop)) {
- pr_err("Missing host_port_reg_ofs property in the DT.\n");
- ret = -EINVAL;
- goto error_ret;
- }
- data->host_port_reg_ofs = prop;
-
- if (of_property_read_u32(node, "hw_stats_reg_ofs", &prop)) {
- pr_err("Missing hw_stats_reg_ofs property in the DT.\n");
- ret = -EINVAL;
- goto error_ret;
- }
- data->hw_stats_reg_ofs = prop;
-
- if (of_property_read_u32(node, "cpts_reg_ofs", &prop)) {
- pr_err("Missing cpts_reg_ofs property in the DT.\n");
- ret = -EINVAL;
- goto error_ret;
- }
- data->cpts_reg_ofs = prop;
-
- if (of_property_read_u32(node, "bd_ram_ofs", &prop)) {
- pr_err("Missing bd_ram_ofs property in the DT.\n");
- ret = -EINVAL;
- goto error_ret;
- }
- data->bd_ram_ofs = prop;
-
if (of_property_read_u32(node, "bd_ram_size", &prop)) {
pr_err("Missing bd_ram_size property in the DT.\n");
ret = -EINVAL;
@@ -1156,22 +1106,6 @@ static int cpsw_probe_dt(struct cpsw_platform_data *data,
}
slave_data->phy_id = phy_id;
- if (of_property_read_u32(slave_node, "slave_reg_ofs", &prop)) {
- pr_err("Missing slave[%d] slave_reg_ofs property\n", i);
- ret = -EINVAL;
- goto error_ret;
- }
- slave_data->slave_reg_ofs = prop;
-
- if (of_property_read_u32(slave_node, "sliver_reg_ofs",
- &prop)) {
- pr_err("Missing slave[%d] sliver_reg_ofs property\n",
- i);
- ret = -EINVAL;
- goto error_ret;
- }
- slave_data->sliver_reg_ofs = prop;
-
mac_addr = of_get_mac_address(slave_node);
if (mac_addr)
memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
@@ -1193,8 +1127,9 @@ static int __devinit cpsw_probe(struct platform_device *pdev)
struct cpsw_priv *priv;
struct cpdma_params dma_params;
struct cpsw_ale_params ale_params;
- void __iomem *regs;
+ void __iomem *ss_regs, *wr_regs;
struct resource *res;
+ u32 slave_offset, sliver_offset, slave_size;
int ret = 0, i, k = 0;
ndev = alloc_etherdev(sizeof(struct cpsw_priv));
@@ -1258,15 +1193,14 @@ static int __devinit cpsw_probe(struct platform_device *pdev)
ret = -ENXIO;
goto clean_clk_ret;
}
- regs = ioremap(priv->cpsw_res->start, resource_size(priv->cpsw_res));
- if (!regs) {
+ ss_regs = ioremap(priv->cpsw_res->start, resource_size(priv->cpsw_res));
+ if (!ss_regs) {
dev_err(priv->dev, "unable to map i/o region\n");
goto clean_cpsw_iores_ret;
}
- priv->regs = regs;
- priv->host_port = data->host_port_num;
- priv->host_port_regs = regs + data->host_port_reg_ofs;
- priv->cpts.reg = regs + data->cpts_reg_ofs;
+ priv->regs = ss_regs;
+ priv->version = __raw_readl(&priv->regs->id_ver);
+ priv->host_port = HOST_PORT_NUM;
priv->cpsw_wr_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
if (!priv->cpsw_wr_res) {
@@ -1280,32 +1214,59 @@ static int __devinit cpsw_probe(struct platform_device *pdev)
ret = -ENXIO;
goto clean_iomap_ret;
}
- regs = ioremap(priv->cpsw_wr_res->start,
+ wr_regs = ioremap(priv->cpsw_wr_res->start,
resource_size(priv->cpsw_wr_res));
- if (!regs) {
+ if (!wr_regs) {
dev_err(priv->dev, "unable to map i/o region\n");
goto clean_cpsw_wr_iores_ret;
}
- priv->wr_regs = regs;
-
- for_each_slave(priv, cpsw_slave_init, priv);
+ priv->wr_regs = wr_regs;
memset(&dma_params, 0, sizeof(dma_params));
+ memset(&ale_params, 0, sizeof(ale_params));
+
+ switch (priv->version) {
+ case CPSW_VERSION_1:
+ priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
+ priv->cpts.reg = ss_regs + CPSW1_CPTS_OFFSET;
+ dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET;
+ dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET;
+ ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET;
+ slave_offset = CPSW1_SLAVE_OFFSET;
+ slave_size = CPSW1_SLAVE_SIZE;
+ sliver_offset = CPSW1_SLIVER_OFFSET;
+ dma_params.desc_mem_phys = 0;
+ break;
+ case CPSW_VERSION_2:
+ priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
+ priv->cpts.reg = ss_regs + CPSW2_CPTS_OFFSET;
+ dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET;
+ dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET;
+ ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET;
+ slave_offset = CPSW2_SLAVE_OFFSET;
+ slave_size = CPSW2_SLAVE_SIZE;
+ sliver_offset = CPSW2_SLIVER_OFFSET;
+ dma_params.desc_mem_phys =
+ (u32 __force) priv->cpsw_res->start + CPSW2_BD_OFFSET;
+ break;
+ default:
+ dev_err(priv->dev, "unknown version 0x%08x\n", priv->version);
+ ret = -ENODEV;
+ goto clean_cpsw_wr_iores_ret;
+ }
+ for (i = 0; i < priv->data.slaves; i++) {
+ struct cpsw_slave *slave = &priv->slaves[i];
+ cpsw_slave_init(slave, priv, slave_offset, sliver_offset);
+ slave_offset += slave_size;
+ sliver_offset += SLIVER_SIZE;
+ }
+
dma_params.dev = &pdev->dev;
- dma_params.dmaregs = cpsw_dma_regs((u32)priv->regs,
- data->cpdma_reg_ofs);
- dma_params.rxthresh = cpsw_dma_rxthresh((u32)priv->regs,
- data->cpdma_reg_ofs);
- dma_params.rxfree = cpsw_dma_rxfree((u32)priv->regs,
- data->cpdma_reg_ofs);
- dma_params.txhdp = cpsw_dma_txhdp((u32)priv->regs,
- data->cpdma_sram_ofs);
- dma_params.rxhdp = cpsw_dma_rxhdp((u32)priv->regs,
- data->cpdma_sram_ofs);
- dma_params.txcp = cpsw_dma_txcp((u32)priv->regs,
- data->cpdma_sram_ofs);
- dma_params.rxcp = cpsw_dma_rxcp((u32)priv->regs,
- data->cpdma_sram_ofs);
+ dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH;
+ dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE;
+ dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP;
+ dma_params.txcp = dma_params.txhdp + CPDMA_TXCP;
+ dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP;
dma_params.num_chan = data->channels;
dma_params.has_soft_reset = true;
@@ -1313,10 +1274,7 @@ static int __devinit cpsw_probe(struct platform_device *pdev)
dma_params.desc_mem_size = data->bd_ram_size;
dma_params.desc_align = 16;
dma_params.has_ext_regs = true;
- dma_params.desc_mem_phys = data->no_bd_ram ? 0 :
- (u32 __force)priv->cpsw_res->start + data->bd_ram_ofs;
- dma_params.desc_hw_addr = data->hw_ram_addr ?
- data->hw_ram_addr : dma_params.desc_mem_phys ;
+ dma_params.desc_hw_addr = dma_params.desc_mem_phys;
priv->dma = cpdma_ctlr_create(&dma_params);
if (!priv->dma) {
@@ -1336,10 +1294,7 @@ static int __devinit cpsw_probe(struct platform_device *pdev)
goto clean_dma_ret;
}
- memset(&ale_params, 0, sizeof(ale_params));
ale_params.dev = &ndev->dev;
- ale_params.ale_regs = (void *)((u32)priv->regs) +
- ((u32)data->ale_reg_ofs);
ale_params.ale_ageout = ale_ageout;
ale_params.ale_entries = data->ale_entries;
ale_params.ale_ports = data->slaves;
diff --git a/include/linux/platform_data/cpsw.h b/include/linux/platform_data/cpsw.h
index b5c16c3..4b0ed74 100644
--- a/include/linux/platform_data/cpsw.h
+++ b/include/linux/platform_data/cpsw.h
@@ -18,8 +18,6 @@
#include <linux/if_ether.h>
struct cpsw_slave_data {
- u32 slave_reg_ofs;
- u32 sliver_reg_ofs;
const char *phy_id;
int phy_if;
u8 mac_addr[ETH_ALEN];
@@ -28,31 +26,14 @@ struct cpsw_slave_data {
struct cpsw_platform_data {
u32 ss_reg_ofs; /* Subsystem control register offset */
u32 channels; /* number of cpdma channels (symmetric) */
- u32 cpdma_reg_ofs; /* cpdma register offset */
- u32 cpdma_sram_ofs; /* cpdma sram offset */
-
u32 slaves; /* number of slave cpgmac ports */
struct cpsw_slave_data *slave_data;
u32 cpts_active_slave; /* time stamping slave */
u32 cpts_clock_mult; /* convert input clock ticks to nanoseconds */
u32 cpts_clock_shift; /* convert input clock ticks to nanoseconds */
-
- u32 ale_reg_ofs; /* address lookup engine reg offset */
u32 ale_entries; /* ale table size */
-
- u32 host_port_reg_ofs; /* cpsw cpdma host port registers */
- u32 host_port_num; /* The port number for the host port */
-
- u32 hw_stats_reg_ofs; /* cpsw hardware statistics counters */
- u32 cpts_reg_ofs; /* cpts registers */
-
- u32 bd_ram_ofs; /* embedded buffer descriptor RAM offset*/
u32 bd_ram_size; /*buffer descriptor ram size */
- u32 hw_ram_addr; /*if the HW address for BD RAM is different */
- bool no_bd_ram; /* no embedded BD ram*/
-
u32 rx_descs; /* Number of Rx Descriptios */
-
u32 mac_control; /* Mac control register */
};
--
1.7.2.5
^ permalink raw reply related
* [PATCH] net/at91_ether: fix the use of macb structure
From: David Miller @ 2012-11-03 19:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351596628-3405-1-git-send-email-nicolas.ferre@atmel.com>
From: Nicolas Ferre <nicolas.ferre@atmel.com>
Date: Tue, 30 Oct 2012 12:30:28 +0100
> Due to the use of common structure in at91_ether and macb drivers,
> change the name of DMA descriptor structures in at91_ether as well:
> dma_desc => macb_dma_desc
>
> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
This does not apply to net-next, respin it if this change is
still relevant.
^ permalink raw reply
* [PATCH] ARM: OMAP2+: AM33XX: clock data: fix mcasp entries
From: Joel A Fernandes @ 2012-11-03 19:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1BAFE6F6C881BF42822005164F1491C33EAB973D@DBDE01.ent.ti.com>
Hi Gururaja,
On Wed, Oct 31, 2012 at 12:39 AM, Hebbar, Gururaja
<gururaja.hebbar@ti.com> wrote:
> On Wed, Oct 31, 2012 at 01:58:32, Joel A Fernandes wrote:
>> Hi Gururaja,
>>
>> On Mon, Oct 29, 2012 at 10:45 AM, Hebbar, Gururaja
>> <gururaja.hebbar@ti.com> wrote:
>> > Matt,
>> >
>> > On Wed, Oct 10, 2012 at 20:00:49, Porter, Matt wrote:
>> >> 6ea74cb ARM: OMAP2+: hwmod: get rid of all omap_clk_get_by_name usage
>> >> exposes a bug in the AM33XX clock data for mcasp. After moving to
>> >> clk_get() usage, the _init() of all registered hwmods fails on mcasp0
>> >> due to incorrect clock data causing clk_get() to fail. This causes all
>> >> successive hwmods to fail to _init() leaving them in a bad state.
>> >>
>> >> This patch updates the mcasp clock entries so clk_get() will succeed.
>> >> It is tested on BeagleBone and is needed for 3.7-rc1 to fix AM33xx
>> >> boot.
>> >
>> >
>> > I want to test Audio on AM335x Evm with your EDMA patches. I have few
>> > patches for AM335x.
>> > Can you share the link to the repo & branch on which I need to rebase?
>> > The patches are related to mcasp dt node, mcasp pinmux in dt, etc...
>> >
>>
>> I was wondering about the status of following patches you wrote, not
>> added to mainline yet:
>>
>> (1)
>> ASoC: Davinci: machine: Add device tree binding
>> https://patchwork.kernel.org/patch/1380511/ - will this be resubmitted?
>
> There was no review comments for V3 I submitted.
>
>>
>> (2)
>> ASoC: AM33XX: Add support for AM33xx SoC Audio
>> https://github.com/joelagnel/linux-kernel/commit/973cfb48bdb70018b3869a21595bde8630efb29d
>
> I want to re-submit both the patches along with 2 more patch-set [1]. I am
> waiting for Matt Porters to reply with his recent branch, so that I can do
> a final test and re-submit.
>
> [1].
> arm/dts: Add tlv320aic3x codec DT data to am335x-evm.dts
> arm/dts: add mcasp1 dt node to am335x-evm.dt
> ASoC: davinci-mcasp: Add pinctrl support
> arm/dts: AM33XX: setup pinctrl for mcasp1 on am335x-evm
>
Thanks, I think I have all of your patches now in my tree, I made a
few more changes to make it compile and run for me on 3.7-rc2
beaglebone_defconfig: Add dummy regulator to init tlv320aic3x
https://github.com/joelagnel/linux-kernel/commit/db5672dfe548d82625cf40ed688d05ba7cee5c93
ASoC: davinci-evm: cpu_dai_of_node has changed to cpu_of_node
https://github.com/joelagnel/linux-kernel/commit/8781c69553d0faf7cec0119e593447f27fdc07e9
I don't get a crash anymore (after correcting mcasp0 base address in
dts), but I still don't get any audio output from the codec. I will
probe the audio signals next week to make sure the I2S output is
correct.
Regards,
Joel
^ permalink raw reply
* [PATCH net-next] macb: Keep driver's speed/duplex in sync with actual NCFGR
From: David Miller @ 2012-11-03 19:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <201211021909.25473.vitas@nppfactor.kiev.ua>
From: Vitalii Demianets <vitas@nppfactor.kiev.ua>
Date: Fri, 2 Nov 2012 19:09:24 +0200
> When underlying phy driver restores its state very fast after being brought
> down and up so that macb driver function macb_handle_link_change() was never
> called with link state "down", driver's internal representation of phy speed
> and duplex (bp->speed and bp->duplex) didn't change. So, macb driver sees no
> reason to perform actual write to the NCFGR register, although the speed and
> duplex settings in that register were reset when interface was brought down
> and up. In that case actual phy speed and duplex differ from NCFGR settings.
> The patch fixes that by keeping internal driver representation of speed and
> duplex in sync with actual content of NCFGR.
>
> Signed-off-by: Vitalii Demianets <vitas@nppfactor.kiev.ua>
Applied.
^ permalink raw reply
* [PATCH net-next 0/2] cpsw: fix resource leak for v3.8
From: David Miller @ 2012-11-03 19:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1351930782.git.richardcochran@gmail.com>
From: Richard Cochran <richardcochran@gmail.com>
Date: Sat, 3 Nov 2012 09:25:28 +0100
> While looking at the idea of removing all of the register offsets in
> the CPSW's device tree, I noticed that the driver would be leaking IO
> mappings. Although this is, strictly speaking, a bug fix, still it can
> wait to appear in v3.8, since there is no way to use the driver in
> v3.7 (or earlier) anyhow.
All applied, thanks.
^ permalink raw reply
* [PATCH 6/8] arch/arm/mach-omap2/dpll3xxx.c: drop if around WARN_ON
From: Julia Lawall @ 2012-11-03 20:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351974625-10282-1-git-send-email-Julia.Lawall@lip6.fr>
From: Julia Lawall <Julia.Lawall@lip6.fr>
Just use WARN_ON rather than an if containing only WARN_ON(1).
A simplified version of the semantic patch that makes this transformation
is as follows: (http://coccinelle.lip6.fr/)
// <smpl>
@@
expression e;
@@
- if (e) WARN_ON(1);
+ WARN_ON(e);
// </smpl>
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
---
arch/arm/mach-omap2/dpll3xxx.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index eacf51f..ed855b0 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -478,8 +478,7 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
if (!soc_is_am33xx() && !cpu_is_omap44xx() && !cpu_is_omap3630()) {
freqsel = _omap3_dpll_compute_freqsel(clk,
dd->last_rounded_n);
- if (!freqsel)
- WARN_ON(1);
+ WARN_ON(!freqsel);
}
pr_debug("clock: %s: set rate: locking rate to %lu.\n",
^ permalink raw reply related
* OMAP baseline test results for v3.7-rc1
From: Jean Pihet @ 2012-11-03 21:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAORVsuXHxqhcTHv8Y=8gw4N+0+rx+N91bh971zK-TmcsrTu5nQ@mail.gmail.com>
Hi Paul,
On Thu, Nov 1, 2012 at 8:51 AM, Jean Pihet <jean.pihet@newoldbits.com> wrote:
> Hi Paul,
>
> On Wed, Oct 31, 2012 at 10:44 PM, Paul Walmsley <paul@pwsan.com> wrote:
>> Hi
>>
>> On Wed, 31 Oct 2012, Jean Pihet wrote:
>>
>>> Paul,
>>> Could you please check with the 2 calls to PM QoS from the I2C code
>>> commented out? This will rule out the PM QoS impact.
>>
>> Will be happy to do a test run for you, after the boot log from your local
>> test run is posted:
>>
>> http://marc.info/?l=linux-arm-kernel&m=135167153510814&w=2
Here are some more details after investigation.
The setup is as identical as possible to yours:
- U-Boot 2011.06-dirty (Sep 04 2012 - 17:06:58) from
http://www.pwsan.com/tmp/3530es3beagle-MLO-u-boot-20121023.tar.bz2.
Please note that the MLO image does not run on my board and so I had
to use my known-to-work image.
- 3.7.0-rc1 kernel, omap2plus_defconfig,
- same kernel parameters,
- Angstrom rootfs from
http://www.pwsan.com/tmp/20121023-beagleboard-angstrom-userspace.tar.bz2
The differences are:
- OMAP revision (ES2.1 vs ES3.0),
- Beagleboard revision (B5 vs Cx),
- RAM amount (128 vs 256MB),
- compiler: gcc version 4.5.1 (Sourcery G++ Lite 2010.09-50) vs 4.5.2
(Sourcery G++ Lite 2011.03-41)
The result is that I could reproduce the issue but it happens much
more rarely on my side (only once vs quasi 100% on ~50 boot cycles).
The issue is triggered by running 'hwclock --systohc' while the
system is heavily loaded (running depmod etc.). The system recovers
nicely after the issue, the RTC can be used correctly later on.
Here is the log:
U-Boot 2011.06-dirty (Sep 04 2012 - 17:06:58)
OMAP3530-GP ES2.1, CPU-OPP2, L3-165MHz, Max CPU Clock 600 mHz
OMAP3 Beagle board + LPDDR/NAND
I2C: ready
DRAM: 128 MiB
NAND: 256 MiB
MMC: OMAP SD/MMC: 0
In: serial
Out: serial
Err: serial
Beagle Rev Ax/Bx
timed out in wait_for_pin: I2C_STAT=0
I2C read: I/O error
Unrecognized expansion board: 0
Die ID #0f6000020000000004013ef109008009
Hit any key to stop autoboot: 0
reading uimage
4148008 bytes read
## Booting kernel from Legacy Image at 80300000 ...
Image Name: Linux-3.7.0-rc1
Image Type: ARM Linux Kernel Image (uncompressed)
Data Size: 4147944 Bytes = 4 MiB
Load Address: 80008000
Entry Point: 80008000
Verifying Checksum ... OK
Loading Kernel Image ... OK
OK
Starting kernel ...
Uncompressing Linux... done, booting the kernel.
[ 0.000000] Booting Linux on physical CPU 0
[ 0.000000] Linux version 3.7.0-rc1 (def at rachael) (gcc version
4.5.2 (Sourcery G++ Lite 2011.03-41) ) #2 SMP Sat Nov 3 21:56:11 CET
2012
[ 0.000000] CPU: ARMv7 Processor [411fc082] revision 2 (ARMv7), cr=10c53c7d
[ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT
nonaliasing instruction cache
[ 0.000000] Machine: OMAP3 Beagle Board
[ 0.000000] Memory policy: ECC disabled, Data cache writeback
[ 0.000000] OMAP3430/3530 ES2.1 (l2cache iva sgx neon isp )
[ 0.000000] Clocking rate (Crystal/Core/MPU): 26.0/332/500 MHz
[ 0.000000] PERCPU: Embedded 9 pages/cpu @c0e40000 s12928 r8192 d15744 u36864
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on.
Total pages: 32256
[ 0.000000] Kernel command line: console=ttyO2,230400n8
root=/dev/mmcblk0p2 rw rootfstype=ext3 rootwait
[ 0.000000] PID hash table entries: 512 (order: -1, 2048 bytes)
[ 0.000000] Dentry cache hash table entries: 16384 (order: 4, 65536 bytes)
[ 0.000000] Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)
[ 0.000000] Memory: 127MB = 127MB total
[ 0.000000] Memory: 115316k/115316k available, 15756k reserved, 0K highmem
[ 0.000000] Virtual kernel memory layout:
[ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB)
[ 0.000000] fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
[ 0.000000] vmalloc : 0xc8800000 - 0xff000000 ( 872 MB)
[ 0.000000] lowmem : 0xc0000000 - 0xc8000000 ( 128 MB)
[ 0.000000] pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB)
[ 0.000000] modules : 0xbf000000 - 0xbfe00000 ( 14 MB)
[ 0.000000] .text : 0xc0008000 - 0xc07037dc (7150 kB)
[ 0.000000] .init : 0xc0704000 - 0xc0754280 ( 321 kB)
[ 0.000000] .data : 0xc0756000 - 0xc07e15a0 ( 558 kB)
[ 0.000000] .bss : 0xc07e15c4 - 0xc0d3bfac (5483 kB)
[ 0.000000] Hierarchical RCU implementation.
[ 0.000000] RCU restricting CPUs from NR_CPUS=2 to nr_cpu_ids=1.
[ 0.000000] NR_IRQS:16 nr_irqs:16 16
[ 0.000000] IRQ: Found an INTC at 0xfa200000 (revision 4.0) with 96
interrupts
[ 0.000000] Total of 96 interrupts on 1 active controller
[ 0.000000] OMAP clockevent source: GPTIMER12 at 32768 Hz
[ 0.000000] sched_clock: 32 bits at 32kHz, resolution 30517ns,
wraps every 131071999ms
[ 0.000000] OMAP clocksource: 32k_counter at 32768 Hz
[ 0.000000] Console: colour dummy device 80x30
[ 0.000000] Lock dependency validator: Copyright (c) 2006 Red Hat,
Inc., Ingo Molnar
[ 0.000000] ... MAX_LOCKDEP_SUBCLASSES: 8
[ 0.000000] ... MAX_LOCK_DEPTH: 48
[ 0.000000] ... MAX_LOCKDEP_KEYS: 8191
[ 0.000000] ... CLASSHASH_SIZE: 4096
[ 0.000000] ... MAX_LOCKDEP_ENTRIES: 16384
[ 0.000000] ... MAX_LOCKDEP_CHAINS: 32768
[ 0.000000] ... CHAINHASH_SIZE: 16384
[ 0.000000] memory used by lock dependency info: 3695 kB
[ 0.000000] per task-struct memory footprint: 1152 bytes
[ 0.001190] Calibrating delay loop... 324.52 BogoMIPS (lpj=1265664)
[ 0.106964] pid_max: default: 32768 minimum: 301
[ 0.107757] Security Framework initialized
[ 0.108001] Mount-cache hash table entries: 512
[ 0.114196] CPU: Testing write buffer coherency: ok
[ 0.115478] CPU0: thread -1, cpu 0, socket -1, mpidr 0
[ 0.115600] Setting up static identity map for 0x8051ebe0 - 0x8051ec50
[ 0.119537] Brought up 1 CPUs
[ 0.119567] SMP: Total of 1 processors activated (324.52 BogoMIPS).
[ 0.142547] pinctrl core: initialized pinctrl subsystem
[ 0.151123] regulator-dummy: no parameters
[ 0.154083] NET: Registered protocol family 16
[ 0.155853] DMA: preallocated 256 KiB pool for atomic coherent allocations
[ 0.158386] omap-gpmc omap-gpmc: GPMC revision 5.0
[ 0.175537] OMAP GPIO hardware version 2.5
[ 0.202301] omap_mux_init: Add partition: #1: core, flags: 0
[ 0.205810] OMAP3 Beagle Rev: Ax/Bx
[ 0.236938] Reprogramming SDRC clock to 332000000 Hz
[ 0.238708] Found NAND on CS0
[ 0.238739] Registering NAND on CS0
[ 0.240417] find_device_opp: Invalid parameters
[ 0.240661] find_device_opp: Invalid parameters
[ 0.240722] find_device_opp: Invalid parameters
[ 0.240783] find_device_opp: Invalid parameters
[ 0.240844] find_device_opp: Invalid parameters
[ 0.241149] hw-breakpoint: debug architecture 0x4 unsupported.
[ 0.262451] omap-mcbsp.2: alias fck already exists
[ 0.263702] omap-mcbsp.3: alias fck already exists
[ 0.269287] OMAP DMA hardware revision 4.0
[ 0.275695] arm-pmu: alias fck already exists
[ 0.372833] bio: create slab <bio-0> at 0
[ 0.504943] omap-dma-engine omap-dma-engine: OMAP DMA engine driver
[ 0.513244] SCSI subsystem initialized
[ 0.517700] usbcore: registered new interface driver usbfs
[ 0.518524] usbcore: registered new interface driver hub
[ 0.519470] usbcore: registered new device driver usb
[ 0.542327] twl 1-0048: PIH (irq 23) chaining IRQs 338..346
[ 0.543212] twl 1-0048: power (irq 343) chaining IRQs 346..353
[ 0.547882] twl4030_gpio twl4030_gpio: gpio (irq 338) chaining IRQs 354..371
[ 0.560913] vdd_mpu_iva: 600 <--> 1450 mV normal
[ 0.564697] vdd_core: 600 <--> 1450 mV normal
[ 0.568145] VMMC1: 1850 <--> 3150 mV at 3000 mV normal standby
[ 0.572204] VDAC: 1800 mV normal standby
[ 0.575622] VDVI: 1800 mV normal standby
[ 0.579803] VSIM: 1800 <--> 3000 mV at 1800 mV normal standby
[ 0.581176] omap_i2c omap_i2c.1: bus 1 rev1.3.12 at 2600 kHz
[ 0.584350] omap_i2c omap_i2c.3: bus 3 rev1.3.12 at 100 kHz
[ 0.595794] Switching to clocksource 32k_counter
[ 0.784149] NET: Registered protocol family 2
[ 0.787017] TCP established hash table entries: 4096 (order: 3, 32768 bytes)
[ 0.787414] TCP bind hash table entries: 4096 (order: 5, 147456 bytes)
[ 0.790130] TCP: Hash tables configured (established 4096 bind 4096)
[ 0.790435] TCP: reno registered
[ 0.790496] UDP hash table entries: 256 (order: 2, 20480 bytes)
[ 0.790863] UDP-Lite hash table entries: 256 (order: 2, 20480 bytes)
[ 0.792205] NET: Registered protocol family 1
[ 0.794158] RPC: Registered named UNIX socket transport module.
[ 0.794189] RPC: Registered udp transport module.
[ 0.794219] RPC: Registered tcp transport module.
[ 0.794219] RPC: Registered tcp NFSv4.1 backchannel transport module.
[ 0.795715] NetWinder Floating Point Emulator V0.97 (double precision)
[ 0.796173] CPU PMU: probing PMU on CPU 0
[ 0.796386] hw perfevents: enabled with ARMv7 Cortex-A8 PMU driver,
5 counters available
[ 1.017608] VFS: Disk quotas dquot_6.5.2
[ 1.018005] Dquot-cache hash table entries: 1024 (order 0, 4096 bytes)
[ 1.022155] NFS: Registering the id_resolver key type
[ 1.022857] Key type id_resolver registered
[ 1.022888] Key type id_legacy registered
[ 1.023101] jffs2: version 2.2. (NAND) (SUMMARY) ? 2001-2006 Red Hat, Inc.
[ 1.023986] msgmni has been set to 225
[ 1.029388] io scheduler noop registered
[ 1.029449] io scheduler deadline registered
[ 1.029571] io scheduler cfq registered (default)
[ 1.034118] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
[ 1.044128] omap_uart.0: ttyO0 at MMIO 0x4806a000 (irq = 88) is a OMAP UART0
[ 1.047027] omap_uart.1: ttyO1 at MMIO 0x4806c000 (irq = 89) is a OMAP UART1
[ 1.049133] omap_uart.2: ttyO2 at MMIO 0x49020000 (irq = 90) is a OMAP UART2
[ 1.408569] console [ttyO2] enabled
[ 1.459045] brd: module loaded
[ 1.491302] loop: module loaded
[ 1.504882] mtdoops: mtd device (mtddev=name/number) must be supplied
[ 1.509094] NAND device: Manufacturer ID: 0x2c, Chip ID: 0xba
(Micron NAND 256MiB 1,8V 16-bit), page size: 2048, OOB size: 64
[ 1.515777] Creating 5 MTD partitions on "omap2-nand.0":
[ 1.518737] 0x000000000000-0x000000080000 : "X-Loader"
[ 1.531433] 0x000000080000-0x000000260000 : "U-Boot"
[ 1.542541] 0x000000260000-0x000000280000 : "U-Boot Env"
[ 1.551788] 0x000000280000-0x000000680000 : "Kernel"
[ 1.564239] 0x000000680000-0x000010000000 : "File System"
[ 1.793273] OneNAND driver initializing
[ 1.812469] usbcore: registered new interface driver asix
[ 1.816345] usbcore: registered new interface driver cdc_ether
[ 1.820343] usbcore: registered new interface driver smsc95xx
[ 1.824310] usbcore: registered new interface driver net1080
[ 1.828124] usbcore: registered new interface driver cdc_subset
[ 1.832153] usbcore: registered new interface driver zaurus
[ 1.835937] usbcore: registered new interface driver cdc_ncm
[ 1.842102] usbcore: registered new interface driver cdc_wdm
[ 1.845184] Initializing USB Mass Storage driver...
[ 1.848754] usbcore: registered new interface driver usb-storage
[ 1.852020] USB Mass Storage support registered.
[ 1.855407] usbcore: registered new interface driver usbtest
[ 1.860931] mousedev: PS/2 mouse device common for all mice
[ 1.872131] input: twl4030_pwrbutton as
/devices/platform/omap_i2c.1/i2c-1/1-0049/twl4030_pwrbutton/input/input0
[ 1.882110] twl_rtc twl_rtc: Enabling TWL-RTC
[ 1.890533] twl_rtc twl_rtc: rtc core: registered twl_rtc as rtc0
[ 1.897399] i2c /dev entries driver
[ 1.903747] Driver for 1-wire Dallas network protocol.
[ 1.911224] omap_wdt: OMAP Watchdog Timer Rev 0x31: initial timeout 60 sec
[ 1.916412] twl4030_wdt twl4030_wdt: Failed to register misc device
[ 1.920318] twl4030_wdt: probe of twl4030_wdt failed with error -16
[ 1.929351] omap_hsmmc omap_hsmmc.0: multiblock reads disabled due
to 35xx erratum 2.1.1.128; MMC read performance may suffer
[ 1.936065] omap_hsmmc omap_hsmmc.0: Failed to get debounce clk
[ 1.939361] omap-dma-engine omap-dma-engine: allocating channel for 62
[ 1.943084] omap-dma-engine omap-dma-engine: allocating channel for 61
[ 2.332794] usbcore: registered new interface driver usbhid
[ 2.335906] usbhid: USB HID core driver
[ 2.343688] oprofile: using arm/armv7
[ 2.346954] TCP: cubic registered
[ 2.348754] Initializing XFRM netlink socket
[ 2.351257] NET: Registered protocol family 17
[ 2.353790] NET: Registered protocol family 15
[ 2.356872] Key type dns_resolver registered
[ 2.359313] VFP support v0.3: implementor 41 architecture 3 part 30
variant c rev 1
[ 2.376007] omap2_set_init_voltage: unable to find boot up OPP for
vdd_mpu_iva
[ 2.380218] omap2_set_init_voltage: unable to set vdd_mpu_iva
[ 2.384307] PM: no software I/O chain control; some wakeups may be lost
[ 2.388549] ThumbEE CPU extension supported.
[ 2.435852] clock: disabling unused clocks to save power
[ 2.445678] VDVI: incomplete constraints, leaving on
[ 2.448852] VDAC: incomplete constraints, leaving on
[ 2.456817] input: gpio-keys as /devices/platform/gpio-keys/input/input1
[ 2.465118] twl_rtc twl_rtc: setting system clock to 2010-07-22
02:43:19 UTC (1279766599)
[ 2.475555] Waiting for root device /dev/mmcblk0p2...
[ 2.499633] mmc0: new SD card at address e624
[ 2.506134] mmcblk0: mmc0:e624 SD01G 968 MiB
[ 2.520111] mmcblk0: p1 p2
[ 4.051177] kjournald starting. Commit interval 5 seconds
[ 4.059448] EXT3-fs (mmcblk0p2): using internal journal
[ 4.067016] EXT3-fs (mmcblk0p2): recovery complete
[ 4.069641] EXT3-fs (mmcblk0p2): mounted filesystem with ordered data mode
[ 4.074005] VFS: Mounted root (ext3 filesystem) on device 179:2.
[ 4.078399] Freeing init memory: 320K
INIT: version 2.86 booting
Starting the hotplug events dispatcher udevd
Synthesizing the initial hotplug events
Remounting root file system...
mount: according to mtab, /proc is already mounted on /proc
WARNING: Couldn't open directory /lib/modules/3.7.0-rc1: No such file
or directory
FATAL: Could not open /lib/modules/3.7.0-rc1/modules.dep.temp for
writing: No such file or directory
root: mount: mount point /proc/bus/usb does not exist
Setting up IP spoofing protection: rp_filter.
Configuring network interfaces... modprobe: FATAL: Could not load
/lib/modules/3.7.0-rc1/modules.dep: No such file or directory
modprobe: FATAL: Could not load /lib/modules/3.7.0-rc1/modules.dep: No
such file or directory
ifconfig: SIOCGIFFLAGS: No such device
modprobe: FATAL: Could not load /lib/modules/3.7.0-rc1/modules.dep: No
such file or directory
modprobe: FATAL: Could not load /lib/modules/3.7.0-rc1/modules.dep: No
such file or directory
modprobe: FATAL: Could not load /lib/modules/3.7.0-rc1/modules.dep: No
such file or directory
modprobe: FATAL: Could not load /lib/modules/3.7.0-rc1/modules.dep: No
such file or directory
eth0 No such device
modprobe: FATAL: Could not load /lib/modules/3.7.0-rc1/modules.dep: No
such file or directory
modprobe: FATAL: Could not load /lib/modules/3.7.0-rc1/modules.dep: No
such file or directory
udhcpc: SIOCGIFINDEX: No such device
done.
Starting portmap daemon: portmap.
Fri Jul 22 02:12:00 UTC 2011
[ 33.424743] omap_i2c omap_i2c.1: timeout waiting for bus ready
[ 34.440338] omap_i2c omap_i2c.1: timeout waiting for bus ready
[ 34.443603] twl: i2c_read failed to transfer all messages
[ 34.446533] twl_rtc: Could not read TWLregister D - error -110
[ 34.449768] twl_rtc twl_rtc: twl_rtc_read_time: reading CTRL_REG, error -110
INIT: Entering runlevel: 5
ALSA: Restoring mixer settings...
/usr/sbin/alsactl: load_state:1327: No soundcards found...
Starting Dropbear SSH server: modprobe: FATAL: Could not load
/lib/modules/3.7.0-rc1/modules.dep: No such file or directory
modprobe: FATAL: Could not load /lib/modules/3.7.0-rc1/modules.dep: No
such file or directory
dropbear.
Starting advanced power management daemon: No APM support in kernel
(failed.)
Starting system message bus: dbus.
Starting syslogd/klogd: start-stop-daemon: lseek: Invalid argument
* Starting Avahi mDNS/DNS-SD Daemon: avahi-daemon
[ ok ]
Starting Bluetooth subsystem:modprobe: FATAL: Could not load
/lib/modules/3.7.0-rc1/modules.dep: No such file or directory
hcid
hid2hci.
.-------.
| | .-.
| | |-----.-----.-----.| | .----..-----.-----.
| | | __ | ---'| '--.| .-'| | |
| | | | | |--- || --'| | | ' | | | |
'---'---'--'--'--. |-----''----''--' '-----'-'-'-'
-' |
'---'
The Angstrom Distribution beagleboard ttyO2
Angstrom 2008.1-test-20080712 beagleboard ttyO2
beagleboard login: root
login[2013]: root login on `ttyO2'
root at beagleboard:~# hwclock -s
root at beagleboard:~# cat
/sys/devices/platform/omap_i2c.1/i2c-1/1-004b/twl_rtc/rtc/rtc0/date
2011-07-22
root at beagleboard:~# cat
/sys/devices/platform/omap_i2c.1/i2c-1/1-004b/twl_rtc/rtc/rtc0/time
02:12:00
root at beagleboard:~#
>>
>>
>> - Paul
More investigation on-going, so more to come!
Regards,
Jean
^ permalink raw reply
* [PATCH 1/9] ARM: integrator: Remove unused icst_params lclk_params structure
From: Lee Jones @ 2012-11-03 22:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351980150-24145-1-git-send-email-lee.jones@linaro.org>
This was introduced way back before 2005 and has remained unused for
over 7 years. Let's remove it.
Cc: Russell King <linux@arm.linux.org.uk>
Cc: linux-arm-kernel at lists.infradead.org
Signed-off-by: Lee Jones <lee.jones@linaro.org>
---
arch/arm/mach-integrator/cpu.c | 12 ------------
1 file changed, 12 deletions(-)
diff --git a/arch/arm/mach-integrator/cpu.c b/arch/arm/mach-integrator/cpu.c
index 590c192..4e0a689 100644
--- a/arch/arm/mach-integrator/cpu.c
+++ b/arch/arm/mach-integrator/cpu.c
@@ -30,18 +30,6 @@ static struct cpufreq_driver integrator_driver;
#define CM_STAT __io_address(INTEGRATOR_HDR_STAT)
#define CM_LOCK __io_address(INTEGRATOR_HDR_LOCK)
-static const struct icst_params lclk_params = {
- .ref = 24000000,
- .vco_max = ICST525_VCO_MAX_5V,
- .vco_min = ICST525_VCO_MIN,
- .vd_min = 8,
- .vd_max = 132,
- .rd_min = 24,
- .rd_max = 24,
- .s2div = icst525_s2div,
- .idx2s = icst525_idx2s,
-};
-
static const struct icst_params cclk_params = {
.ref = 24000000,
.vco_max = ICST525_VCO_MAX_5V,
--
1.7.9.5
^ permalink raw reply related
* [PATCH 2/9] ARM: at91: Remove unused struct at91sam9g45_isi_device and its resources
From: Lee Jones @ 2012-11-03 22:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351980150-24145-1-git-send-email-lee.jones@linaro.org>
This the at91sam9g45_isi_device structure and its associated resources
were added in 2008 and have been unused ever since. Let's remove them.
Cc: Russell King <linux@arm.linux.org.uk>
Cc: linux-arm-kernel at lists.infradead.org
Signed-off-by: Lee Jones <lee.jones@linaro.org>
---
arch/arm/mach-at91/at91sam9263_devices.c | 20 --------------------
1 file changed, 20 deletions(-)
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index cb85da2..0562a9d 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -901,26 +901,6 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
#if defined(CONFIG_VIDEO_AT91_ISI) || defined(CONFIG_VIDEO_AT91_ISI_MODULE)
-struct resource isi_resources[] = {
- [0] = {
- .start = AT91SAM9263_BASE_ISI,
- .end = AT91SAM9263_BASE_ISI + SZ_16K - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = NR_IRQS_LEGACY + AT91SAM9263_ID_ISI,
- .end = NR_IRQS_LEGACY + AT91SAM9263_ID_ISI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device at91sam9263_isi_device = {
- .name = "at91_isi",
- .id = -1,
- .resource = isi_resources,
- .num_resources = ARRAY_SIZE(isi_resources),
-};
-
void __init at91_add_device_isi(struct isi_platform_data *data,
bool use_pck_as_mck)
{
--
1.7.9.5
^ permalink raw reply related
* [PATCH] ARM: S3C64XX: Fix up IRQ mapping for balblair on Cragganmore
From: Sergei Shtylyov @ 2012-11-03 22:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351861289-19691-1-git-send-email-dp@opensource.wolfsonmicro.com>
Hello.
On 02-11-2012 17:01, Dimitris Papastamos wrote:
> We are using S3C_EINT(4) instead of S3C_EINT(5).
> Change-Id: I84e77fd75d59c6b8fecbcb11e81dc78dbf07f156
You still hasven't removed this line. :-)
> Signed-off-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
WBR, Sergei
^ permalink raw reply
* Possible regression in 3.7-rc3 on Marvell Kirkwood
From: Josh Coombs @ 2012-11-04 1:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121103170622.GD6832@lunn.ch>
As of now I can't reproduce, so I can only assume it was something
with my config. Once I nail down exactly what triggers the behavior
I'll post up. For now, ignore my suggestion that there is a
regression.
Josh C
On Sat, Nov 3, 2012 at 1:06 PM, Andrew Lunn <andrew@lunn.ch> wrote:
> On Sat, Nov 03, 2012 at 08:54:21AM -0400, Josh Coombs wrote:
>> I'll fire up with ignore log level to get the full traces and post
>> those this afternoon. Given it will be a LOT of text, would you
>> prefer I include them in the email, pastebin the output and provide
>> links, or dump the log onto my webserver with a link?
>
> Hi Josh
>
> I'm kind of expecting they will all look very similar. By looking at
> what is common it might quick become clear where the lock is being
> taken which is causing the problem.
>
> Anyway, i would suggest posting the first couple of traces to the list
> and a few more to me directly.
>
> Andrew
^ permalink raw reply
* [4/4] arm: mvebu: enable Ethernet controllers on Armada 370/XP eval boards
From: Jason Gunthorpe @ 2012-11-04 2:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351245804-31478-5-git-send-email-thomas.petazzoni@free-electrons.com>
+ ethernet at d0070000 {
+ clock-frequency = <200000000>;
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-addr = <0>;
+ };
We've been using the patches from Ian Molton for the mv643xx driver
that make it use the more standard, separately described MDIO
bus..
Please consider not copying the unsual 'phy-addr' binding
for the new driver.
What we are used to seeing for ethernet+mdio is more like:
smi0: mdio at 72000 {
device_type = "mdio";
compatible = "marvell,mdio-mv643xx";
reg = <0x72000 0x4000>;
interrupts = <46>;
tx_csum_limit = <1600>;
#address-cells = <1>;
#size-cells = <0>;
PHY1: ethernet-phy at 1 {
reg = <1>;
device_type = "ethernet-phy";
phy-id = <0x01410e90>;
};
};
egiga0 {
device_type = "network";
compatible = "marvell,mv643xx-eth";
reg = <0x72000 0x4000>;
mdio = <&smi0>;
port_number = <0>;
phy-handle = <&PHY1>;
interrupts = <11>;
};
};
Where the MDIO bus is explicit, the PHY, its address and parameters
are explicit - the PHY has an of_node pointer - and phy-handle is used
to connect them.
I'm not sure having the MDIO bus as a distinct top level item is
great, considering how the registers overlap.. It might be better
to put it under the egiga0 block? But that is a minor nit :)
Regards,
Jason
^ permalink raw reply
* Possible regression in 3.7-rc3 on Marvell Kirkwood
From: Andrew Lunn @ 2012-11-04 9:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAMW5UfZLYzCf357Z0Ncd6p5G7VYLwq3nhXVb=nAXZOxONa8yeQ@mail.gmail.com>
On Sat, Nov 03, 2012 at 09:39:55PM -0400, Josh Coombs wrote:
> As of now I can't reproduce, so I can only assume it was something
> with my config. Once I nail down exactly what triggers the behavior
> I'll post up. For now, ignore my suggestion that there is a
> regression.
O.K.
I also tried reproducing it. On my QNAP Kirkwood I made a fresh
checkout of the kernel and built it. No problems.
If you do see it again, please let us know.
Thanks
Andrew
^ permalink raw reply
* [4/4] arm: mvebu: enable Ethernet controllers on Armada 370/XP eval boards
From: Thomas Petazzoni @ 2012-11-04 9:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121104020311.GA26747@obsidianresearch.com>
Hello Jason,
On Sat, 3 Nov 2012 20:03:11 -0600, Jason Gunthorpe wrote:
> We've been using the patches from Ian Molton for the mv643xx driver
> that make it use the more standard, separately described MDIO
> bus..
[...]
> Where the MDIO bus is explicit, the PHY, its address and parameters
> are explicit - the PHY has an of_node pointer - and phy-handle is used
> to connect them.
>
> I'm not sure having the MDIO bus as a distinct top level item is
> great, considering how the registers overlap.. It might be better
> to put it under the egiga0 block? But that is a minor nit :)
Thanks for your comment. I'll see what I can come up with to make the
phy a separate DT entity.
Thanks!
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply
* [PATCH] ARM: quiet down the non make -s output
From: Russell King - ARM Linux @ 2012-11-04 9:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121029153425.GA9486@beefymiracle.amer.corp.natinst.com>
On Mon, Oct 29, 2012 at 09:34:25AM -0600, Josh Cartwright wrote:
> Commit edc88ceb0c7d285b9f58bc29a638cd8163b59989 silenced the make -s build, but
> inadvertently made louder the non-silent build. Fix by prepending '@' to each
> of the added $(kecho) statements.
Please put this in the patch system, thanks.
^ permalink raw reply
* [PATCH 1/6 v2] arm: use devicetree to get smp_twd clock
From: Russell King - ARM Linux @ 2012-11-04 10:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351882309-733-2-git-send-email-mark.langsdorf@calxeda.com>
On Fri, Nov 02, 2012 at 01:51:44PM -0500, Mark Langsdorf wrote:
> -static struct clk *twd_get_clock(void)
> +static struct clk *twd_get_clock(struct device_node *np)
> {
> - struct clk *clk;
> + struct clk *clk = NULL;
> int err;
>
> - clk = clk_get_sys("smp_twd", NULL);
> + if (np)
> + clk = of_clk_get(np, 0);
> + if (!clk)
What does a NULL return from of_clk_get() mean? Where is this defined?
> @@ -349,6 +348,10 @@ int __init twd_local_timer_register(struct twd_local_timer *tlt)
> if (!twd_base)
> return -ENOMEM;
>
> + twd_clk = twd_get_clock(NULL);
> +
> + twd_clk = twd_get_clock(NULL);
> +
Why twice?
^ permalink raw reply
* [PATCH 8/9] ARM: support uprobe handling
From: Russell King - ARM Linux @ 2012-11-04 10:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350242593-17761-8-git-send-email-rabin@rab.in>
On Sun, Oct 14, 2012 at 09:23:12PM +0200, Rabin Vincent wrote:
> Extend the kprobes code to handle user-space probes. Much of the code
> can be reused so currently the ARM uprobes code reuses the kprobes
> structures. The decode tables are reused, with the modification that
> for those instruction that require custom decoding for uprobes, a new
> element is added in the table to specify a custom decoder function.
How are accesses to userspace handled by the kprobes code? Please point
me to where these accesses are performed.
^ permalink raw reply
* [PATCH 2/9] ARM: at91: Remove unused struct at91sam9g45_isi_device and its resources
From: Jean-Christophe PLAGNIOL-VILLARD @ 2012-11-04 10:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351980150-24145-3-git-send-email-lee.jones@linaro.org>
On 23:02 Sat 03 Nov , Lee Jones wrote:
> This the at91sam9g45_isi_device structure and its associated resources
> were added in 2008 and have been unused ever since. Let's remove them.
next time you need to Cc the matinaers
NACK
Best Regards,
J.
>
> Cc: Russell King <linux@arm.linux.org.uk>
> Cc: linux-arm-kernel at lists.infradead.org
> Signed-off-by: Lee Jones <lee.jones@linaro.org>
> ---
> arch/arm/mach-at91/at91sam9263_devices.c | 20 --------------------
> 1 file changed, 20 deletions(-)
>
> diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
> index cb85da2..0562a9d 100644
> --- a/arch/arm/mach-at91/at91sam9263_devices.c
> +++ b/arch/arm/mach-at91/at91sam9263_devices.c
> @@ -901,26 +901,6 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
>
> #if defined(CONFIG_VIDEO_AT91_ISI) || defined(CONFIG_VIDEO_AT91_ISI_MODULE)
>
> -struct resource isi_resources[] = {
> - [0] = {
> - .start = AT91SAM9263_BASE_ISI,
> - .end = AT91SAM9263_BASE_ISI + SZ_16K - 1,
> - .flags = IORESOURCE_MEM,
> - },
> - [1] = {
> - .start = NR_IRQS_LEGACY + AT91SAM9263_ID_ISI,
> - .end = NR_IRQS_LEGACY + AT91SAM9263_ID_ISI,
> - .flags = IORESOURCE_IRQ,
> - },
> -};
> -
> -static struct platform_device at91sam9263_isi_device = {
> - .name = "at91_isi",
> - .id = -1,
> - .resource = isi_resources,
> - .num_resources = ARRAY_SIZE(isi_resources),
> -};
> -
> void __init at91_add_device_isi(struct isi_platform_data *data,
> bool use_pck_as_mck)
> {
> --
> 1.7.9.5
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCHv2 0/7] i2c: omap: updates
From: Shubhrajyoti D @ 2012-11-04 10:44 UTC (permalink / raw)
To: linux-arm-kernel
Does the followiing
- Make the revision a 32- bit consisting of rev_lo amd rev_hi each
of 16 bits.
- Also use the revision register for the erratum i207.
- Refactor the i2c_omap_init code.
Also more cleanup is possible will check on that subsequently.
Tested on OMAP4430sdp ,4460 ,omap3630 ,3430 and omap2430.
For omap2 testing the below patch was used
[PATCH] ARM: vfp: fix save and restore when running on pre-VFPv3 and CONFIG_VFPv3 set
Also for using the pm testing below patches are used.
arm: sched: stop sched_clock() during suspend
ARM: OMAP: hwmod: wait for sysreset complete after enabling hwmod
Also available through
git://gitorious.org/linus-tree/linus-tree.git i2c_omap/for_3.8
Shubhrajyoti D (7):
i2c: omap: Fix the revision register read
i2c: omap: use revision check for OMAP_I2C_FLAG_APPLY_ERRATA_I207
i2c: omap: remove the dtrev
ARM: i2c: omap: Remove the i207 errata flag
i2c: omap: re-factor omap_i2c_init function
i2c: omap: make reset a seperate function
i2c: omap: Restore i2c context always
arch/arm/mach-omap2/omap_hwmod_2430_data.c | 3 +-
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 9 +-
drivers/i2c/busses/i2c-omap.c | 166 +++++++++++++++++-----------
include/linux/i2c-omap.h | 1 -
4 files changed, 104 insertions(+), 75 deletions(-)
--
1.7.5.4
^ permalink raw reply
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