* what's the purpose for the few bytes at the end of kernel stack
From: He, Dander @ 2012-11-07 1:24 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
Recently I?m studying linux kernel. I have a question about the space after struct pt_regs in kernel stack.
Why reserved 8 bytes at the end of kernel stack for ARM and 32 bytes for MIPS?
Do you know what?s the purpose for it? Who and where use it?
I checked the real kernel stack for some processes. Some of them are all zero. Some of them are not.
Here are some sample data on ARM for those 8 bytes in different kernel stack:
0x55555575 0x55155545
0x5d555574 0xf17d5552
0x55155555 0x15155151
0x51555d55 0x55515545
0x5d555574 0x7579d552
0x55795534 0xf1055515
0xa83fc821 0xa83fcc21
0x55795534 0xf1055d15
0x557555dd 0x55659155
0x51555d55 0x55515545
0x5355545d 0x54c45135
0x57555455 0x6f45f545
Br/Dander
1. In arm, it?s reserved 8 bytes
kernel/arch/arm/include/asm/thread_info.h
#define THREAD_START_SP (THREAD_SIZE - 8)
2. In mips, it?s reserved 32 bytes.
kernel/arch/mips/kernel/r4k_switch.S
/*
* Offset to the current process status flags, the first 32 bytes of the
* stack are not used.
*/
#define ST_OFF (_THREAD_SIZE - 32 - PT_SIZE + PT_STATUS)
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20121107/6af4d04a/attachment-0001.html>
^ permalink raw reply
* [PATCH] ARM: tegra: enable data prefetch on L2
From: Joseph Lo @ 2012-11-07 1:26 UTC (permalink / raw)
To: linux-arm-kernel
Enable the data prefetch on L2. The bit28 in aux ctrl register.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
arch/arm/mach-tegra/common.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index c25746e..c3dee56 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -124,7 +124,7 @@ static void __init tegra_init_cache(void)
cache_type = readl(p + L2X0_CACHE_TYPE);
aux_ctrl = (cache_type & 0x700) << (17-8);
- aux_ctrl |= 0x6C000001;
+ aux_ctrl |= 0x7C000001;
ret = l2x0_of_init(aux_ctrl, 0x8200c3fe);
if (!ret)
--
1.7.0.4
^ permalink raw reply related
* [GIT PULL] ARM: OMAP: second set of PRCM cleanups for 3.8
From: Paul Walmsley @ 2012-11-07 1:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121106220833.GQ6801@atomide.com>
On Tue, 6 Nov 2012, Tony Lindgren wrote:
> ..now wondering which configs do not build for you at 7fc54fd3?
>
> It builds at least all my test configs. Well at least the ones
> I have recovered after accidentally deleting some files yesterday,
> did not have a back up copy of two of them.
>
> However if I pull your branch in, build breaks for me for
> with the rmk-omap3430-ldp-noconfig and rmk-omap4430-sdp-noconfig:
>
> arch/arm/mach-omap2/built-in.o:(.arch.info.init+0x48): undefined reference to `omap44xx_restart'
They all build successfully here. Here are the rmk config results:
rmk-omap3430-ldp:
http://www.pwsan.com/omap/testlogs/prcm_cleanup_b_3.8/20121101044824/build/rmk_omap3430_ldp_oldconfig/
rmk-omap4430-sdp:
http://www.pwsan.com/omap/testlogs/prcm_cleanup_b_3.8/20121101044824/build/rmk_omap4430_sdp_oldconfig/
Maybe the versions of the rmk configs you're using are different than
mine? The ones here were updated during the v3.6 -> v3.7-rc1 transition.
You can find mine at:
http://www.pwsan.com/omap/testlogs/prcm_cleanup_b_3.8/20121101044824/build/rmk_omap3430_ldp_oldconfig/rmk_omap3430_ldp_oldconfig
http://www.pwsan.com/omap/testlogs/prcm_cleanup_b_3.8/20121101044824/build/rmk_omap4430_sdp_oldconfig/rmk_omap4430_sdp_oldconfig
- Paul
^ permalink raw reply
* [GIT PULL] ARM: OMAP: second set of PRCM cleanups for 3.8
From: Tony Lindgren @ 2012-11-07 1:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.DEB.2.00.1211070150100.8758@utopia.booyaka.com>
* Paul Walmsley <paul@pwsan.com> [121106 17:54]:
> On Tue, 6 Nov 2012, Tony Lindgren wrote:
>
> > ..now wondering which configs do not build for you at 7fc54fd3?
> >
> > It builds at least all my test configs. Well at least the ones
> > I have recovered after accidentally deleting some files yesterday,
> > did not have a back up copy of two of them.
The build errors you are talking about are the ones I already pulled
into one of the cleanup branches, right? If so, that's fine.
> > However if I pull your branch in, build breaks for me for
> > with the rmk-omap3430-ldp-noconfig and rmk-omap4430-sdp-noconfig:
> >
> > arch/arm/mach-omap2/built-in.o:(.arch.info.init+0x48): undefined reference to `omap44xx_restart'
>
> They all build successfully here. Here are the rmk config results:
>
> rmk-omap3430-ldp:
> http://www.pwsan.com/omap/testlogs/prcm_cleanup_b_3.8/20121101044824/build/rmk_omap3430_ldp_oldconfig/
>
> rmk-omap4430-sdp:
> http://www.pwsan.com/omap/testlogs/prcm_cleanup_b_3.8/20121101044824/build/rmk_omap4430_sdp_oldconfig/
>
> Maybe the versions of the rmk configs you're using are different than
> mine? The ones here were updated during the v3.6 -> v3.7-rc1 transition.
> You can find mine at:
>
> http://www.pwsan.com/omap/testlogs/prcm_cleanup_b_3.8/20121101044824/build/rmk_omap3430_ldp_oldconfig/rmk_omap3430_ldp_oldconfig
>
> http://www.pwsan.com/omap/testlogs/prcm_cleanup_b_3.8/20121101044824/build/rmk_omap4430_sdp_oldconfig/rmk_omap4430_sdp_oldconfig
I'm getting errors with the allnoconfig ones, there are total four
omap defconfigs there not counting the randconfigs.
Regards,
Tony
^ permalink raw reply
* arm: Add ARM ERRATA 775420 workaround
From: jungseung lee @ 2012-11-07 2:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACEL3L3O-9v8T1ELVK3gUBaqG0=+vkuLhbQ=dx3-5kJHg6t9UA@mail.gmail.com>
2012. 11. 6. ?? 3:55? "jungseung lee" <lkml.js@gmail.com>?? ??:
Hi,
I have question the work-around code.
The below code will be enter after handling exception handling path. (that
is fix-up code)
As far as i know, the dsb instruction should be inserted before the any isb
instruction on exception handling code for breaking erratum condition .
It could meet the requirement?
> source "arch/arm/common/Kconfig"
> diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
> index 39e3fb3..3b17227 100644
> --- a/arch/arm/mm/cache-v7.S
> +++ b/arch/arm/mm/cache-v7.S
> @@ -211,6 +211,9 @@ ENTRY(v7_coherent_user_range)
> * isn't mapped, fail with -EFAULT.
> */
> 9001:
> +#ifdef CONFIG_ARM_ERRATA_775420
> + dsb
> +#endif
> mov r0, #-EFAULT
> mov pc, lr
> UNWIND(.fnend )
>
>
thanks
> > On Thu, Sep 20, 2012 at 10:58:53AM +0100, Catalin Marinas wrote:
> > > On 12 September 2012 08:14, Simon Horman wrote:
> > > > +config ARM_ERRATA_775420
> > > > + bool "ARM errata: A data cache maintenance operation which
aborts, might lead to deadlock"
> > > > + depends on CPU_V7
> > > > + help
> > > > + This option enables the workaround for the 775420
Cortex-A9 (r2p2,
> > > > + r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache
maintenance
> > > > + operation aborts with MMU exception, it might cause the
processor
> > > > + deadlock. This workaround puts DSB before executing ISB
at the
> > > > + beginning of the abort exception handler.
> > > > +
> > > > endmenu
> > >
> > > The only case where we can get an abort on cache maintenance is
> > > v7_coherent_user_range(). I don't think we have any ISB on the
> > > exception handling path for this function, so we could just add the
> > > DSB there:
> >
> > I think that an advantage of Abe-san's implementation is that
> > it might to be a bit more robust. But your proposal is certainly
> > much cleaner and for that reason I agree it is a good option.
> >
> > I've updated the patch, but since the code is now all yours
> > I'm unsure if the author should be changed or not.
> >
> > ----------------------------------------------------------------
> > From: Kouei Abe
> >
> > arm: Add ARM ERRATA 775420 workaround
> >
> > Workaround for the 775420 Cortex-A9 (r2p2, r2p6,r2p8,r2p10,r3p0)
erratum.
> > In case a date cache maintenance operation aborts with MMU exception, it
> > might cause the processor to deadlock. This workaround puts DSB before
> > executing ISB if an abort may occur on cache maintenance.
> >
> > Based on work by Kouei Abe and feedback from Catalin Marinas.
> >
> > Cc: Catalin Marinas
> > Signed-off-by: Kouei Abe
> > Signed-off-by: Simon Horman
> >
> > ---
> >
> > v2
> > * Add some details to changelog entry
> > * Alternate implementation suggested by Catalin Marinas
> > - Add the dsb directly to v7_coherent_user_range() rather
> > than the exception handler
> > ---
> > arch/arm/Kconfig | 10 ++++++++++
> > arch/arm/mm/cache-v7.S | 3 +++
> > 2 files changed, 13 insertions(+)
> >
> > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> > index 2f88d8d..48c19d4 100644
> > --- a/arch/arm/Kconfig
> > +++ b/arch/arm/Kconfig
> > @@ -1413,6 +1413,16 @@ config PL310_ERRATA_769419
> > on systems with an outer cache, the store buffer is drained
> > explicitly.
> >
> > +config ARM_ERRATA_775420
> > + bool "ARM errata: A data cache maintenance operation which
aborts, might lead to deadlock"
> > + depends on CPU_V7
> > + help
> > + This option enables the workaround for the 775420 Cortex-A9 (r2p2,
> > + r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
> > + operation aborts with MMU exception, it might cause the processor
> > + to deadlock. This workaround puts DSB before executing ISB if
> > + an abort may occur on cache maintenance.
> > +
> > endmenu
> >
> > source "arch/arm/common/Kconfig"
> > diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
> > index 39e3fb3..3b17227 100644
> > --- a/arch/arm/mm/cache-v7.S
> > +++ b/arch/arm/mm/cache-v7.S
> > @@ -211,6 +211,9 @@ ENTRY(v7_coherent_user_range)
> > * isn't mapped, fail with -EFAULT.
> > */
> > 9001:
> > +#ifdef CONFIG_ARM_ERRATA_775420
> > + dsb
> > +#endif
> > mov r0, #-EFAULT
> > mov pc, lr
> > UNWIND(.fnend )
> > --
> > 1.7.10.4
> >
> >
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20121107/cbcf2f25/attachment-0001.html>
^ permalink raw reply
* arm: Add ARM ERRATA 775420 workaround
From: jungseung lee @ 2012-11-07 2:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACEL3L1cZkvxBMSyTp3kr=+5y-aso+gZYBvuCPXk3ZQnHZQOzQ@mail.gmail.com>
Hi,
I have question the work-around code.
The below code will be enter after handling exception handling path. (that
is fix-up code)
As far as i know, the dsb instruction should be inserted before the any isb
instruction on exception handling code for breaking erratum condition .
It could meet the requirement?
> source "arch/arm/common/Kconfig"
> > diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
> > index 39e3fb3..3b17227 100644
> > --- a/arch/arm/mm/cache-v7.S
> > +++ b/arch/arm/mm/cache-v7.S
> > @@ -211,6 +211,9 @@ ENTRY(v7_coherent_user_range)
> > * isn't mapped, fail with -EFAULT.
> > */
> > 9001:
> > +#ifdef CONFIG_ARM_ERRATA_775420
> > + dsb
> > +#endif
> > mov r0, #-EFAULT
> > mov pc, lr
> > UNWIND(.fnend )
> >
> >
> thanks
>
> > On Thu, Sep 20, 2012 at 10:58:53AM +0100, Catalin Marinas wrote:
> > > On 12 September 2012 08:14, Simon Horman wrote:
> > > > +config ARM_ERRATA_775420
> > > > + bool "ARM errata: A data cache maintenance operation which
aborts, might lead to deadlock"
> > > > + depends on CPU_V7
> > > > + help
> > > > + This option enables the workaround for the 775420
Cortex-A9 (r2p2,
> > > > + r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache
maintenance
> > > > + operation aborts with MMU exception, it might cause the
processor
> > > > + deadlock. This workaround puts DSB before executing ISB
at the
> > > > + beginning of the abort exception handler.
> > > > +
> > > > endmenu
> > >
> > > The only case where we can get an abort on cache maintenance is
> > > v7_coherent_user_range(). I don't think we have any ISB on the
> > > exception handling path for this function, so we could just add the
> > > DSB there:
> >
> > I think that an advantage of Abe-san's implementation is that
> > it might to be a bit more robust. But your proposal is certainly
> > much cleaner and for that reason I agree it is a good option.
> >
> > I've updated the patch, but since the code is now all yours
> > I'm unsure if the author should be changed or not.
> >
> > ----------------------------------------------------------------
> > From: Kouei Abe
> >
> > arm: Add ARM ERRATA 775420 workaround
> >
> > Workaround for the 775420 Cortex-A9 (r2p2, r2p6,r2p8,r2p10,r3p0)
erratum.
> > In case a date cache maintenance operation aborts with MMU exception, it
> > might cause the processor to deadlock. This workaround puts DSB before
> > executing ISB if an abort may occur on cache maintenance.
> >
> > Based on work by Kouei Abe and feedback from Catalin Marinas.
> >
> > Cc: Catalin Marinas
> > Signed-off-by: Kouei Abe
> > Signed-off-by: Simon Horman
> >
> > ---
> >
> > v2
> > * Add some details to changelog entry
> > * Alternate implementation suggested by Catalin Marinas
> > - Add the dsb directly to v7_coherent_user_range() rather
> > than the exception handler
> > ---
> > arch/arm/Kconfig | 10 ++++++++++
> > arch/arm/mm/cache-v7.S | 3 +++
> > 2 files changed, 13 insertions(+)
> >
> > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> > index 2f88d8d..48c19d4 100644
> > --- a/arch/arm/Kconfig
> > +++ b/arch/arm/Kconfig
> > @@ -1413,6 +1413,16 @@ config PL310_ERRATA_769419
> > on systems with an outer cache, the store buffer is drained
> > explicitly.
> >
> > +config ARM_ERRATA_775420
> > + bool "ARM errata: A data cache maintenance operation which
aborts, might lead to deadlock"
> > + depends on CPU_V7
> > + help
> > + This option enables the workaround for the 775420 Cortex-A9 (r2p2,
> > + r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
> > + operation aborts with MMU exception, it might cause the processor
> > + to deadlock. This workaround puts DSB before executing ISB if
> > + an abort may occur on cache maintenance.
> > +
> > endmenu
> >
> > source "arch/arm/common/Kconfig"
> > diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
> > index 39e3fb3..3b17227 100644
> > --- a/arch/arm/mm/cache-v7.S
> > +++ b/arch/arm/mm/cache-v7.S
> > @@ -211,6 +211,9 @@ ENTRY(v7_coherent_user_range)
> > * isn't mapped, fail with -EFAULT.
> > */
> > 9001:
> > +#ifdef CONFIG_ARM_ERRATA_775420
> > + dsb
> > +#endif
> > mov r0, #-EFAULT
> > mov pc, lr
> > UNWIND(.fnend )
> > --
> > 1.7.10.4
> >
> >
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20121107/5e13cf89/attachment-0001.html>
^ permalink raw reply
* [PATCH] ARM: dts: exynos4: Add support for Exynos4x12 SoCs
From: Kukjin Kim @ 2012-11-07 2:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1351089359-7318-1-git-send-email-t.figa@samsung.com>
Kukjin Kim wrote:
>
> Tomasz Figa wrote:
> >
> > This patch adds device tree sources for Exynos4x12 SoC series (currently
> > Exynos4212 and Exynos4412) and enables mach-exynos4-dt to support these
> > SoCs.
> >
> > Signed-off-by: Tomasz Figa <t.figa@samsung.com>
> > Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
> > ---
> > arch/arm/boot/dts/exynos4212.dtsi | 28
++++++++++++++++++++++++++++
> > arch/arm/boot/dts/exynos4412.dtsi | 28
++++++++++++++++++++++++++++
> > arch/arm/boot/dts/exynos4x12.dtsi | 31
> > +++++++++++++++++++++++++++++++
> > arch/arm/mach-exynos/mach-exynos4-dt.c | 2 ++
> > 4 files changed, 89 insertions(+)
> > create mode 100644 arch/arm/boot/dts/exynos4212.dtsi
> > create mode 100644 arch/arm/boot/dts/exynos4412.dtsi
> > create mode 100644 arch/arm/boot/dts/exynos4x12.dtsi
> >
>
> Looks good to me, applied.
>
[...]
> +/include/ "exynos4x12-pinctrl.dtsi"
BTW, I think, above line should be added when exynos4x12-pinctrl patches
applied.
[...]
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply
* [GIT PULL] ARM: OMAP: second set of PRCM cleanups for 3.8
From: Paul Walmsley @ 2012-11-07 2:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121107015841.GC6801@atomide.com>
On Tue, 6 Nov 2012, Tony Lindgren wrote:
> * Paul Walmsley <paul@pwsan.com> [121106 17:54]:
> > On Tue, 6 Nov 2012, Tony Lindgren wrote:
> >
> > > ..now wondering which configs do not build for you at 7fc54fd3?
> > >
> > > It builds at least all my test configs. Well at least the ones
> > > I have recovered after accidentally deleting some files yesterday,
> > > did not have a back up copy of two of them.
>
> The build errors you are talking about are the ones I already pulled
> into one of the cleanup branches, right? If so, that's fine.
The build logs I sent were for the "ARM: OMAP: second set of PRCM
cleanups for 3.8" branch. The last commit in that branch is
f17d60d20eb8e679cdd1e9d507394237e58ce0d8 and it is based on
7fc54fd3084457c7f11b9e2e1e3fcd19a3badc33. That one builds cleanly.
If you're asking for a test build of the base commit,
7fc54fd3084457c7f11b9e2e1e3fcd19a3badc33, I just kicked off a test build
of that; will post when done.
> > Maybe the versions of the rmk configs you're using are different than
> > mine? The ones here were updated during the v3.6 -> v3.7-rc1 transition.
> > You can find mine at:
> >
> > http://www.pwsan.com/omap/testlogs/prcm_cleanup_b_3.8/20121101044824/build/rmk_omap3430_ldp_oldconfig/rmk_omap3430_ldp_oldconfig
> >
> > http://www.pwsan.com/omap/testlogs/prcm_cleanup_b_3.8/20121101044824/build/rmk_omap4430_sdp_oldconfig/rmk_omap4430_sdp_oldconfig
>
> I'm getting errors with the allnoconfig ones, there are total four
> omap defconfigs there not counting the randconfigs.
That might indeed explain the discrepancy; so far only have been building
his oldconfig seeds here. Will add his allnoconfig seeds and test again.
- Paul
^ permalink raw reply
* [PATCH v3 0/7] crypto: omap-sham updates
From: Mark A. Greer @ 2012-11-07 2:57 UTC (permalink / raw)
To: linux-arm-kernel
From: "Mark A. Greer" <mgreer@animalcreek.com>
Changes since v2:
- Reworked pm_runtime calls to match where original clk_*
calls were so provide better PM (as per Kevin Hilman's
comments).
Changes since v1:
- Removed the check of CM_IDLEST to see if the module exists
and instead add the hwmod data for all omap2's and omap3 GP's.
- Placed new sha_ick clk entries after the 'omap-sham' entry
in the clockxxx_data.c files
- Removed cpu_is_xxx() checks in
arch/arm/mach-omap2/devices.c:omap_init_sham()
- Rebased on the latest k.o. kernel
This series updates the crypto omap-sham driver and supporting
infrastructure.
Notes:
a) Based on v3.7-rc4
b) Since these patches will likely go though the OMAP tree (and not
through the crypto tree), it would be nice if the crypto guy(s)
would ACK or NACK patches 5-7 which modify the
drivers/crypto/omap-sham.c driver.
c) These have only been tested on an omap2420 h4 and an am37x evm. If you
have different hardware available and a few minutes, please test them.
A quick and easy test is to enable tcrypt as a module
(CONFIG_CRYPTO_TEST=m), boot, then run 'modprobe tcrypt sec=2 mode=403'.
'CONFIG_CRYPTO_SHA1' and 'CONFIG_CRYPTO_DEV_OMAP_SHAM' also have to be
enabled. A quick 'grep omap-sham /proc/interrupts' will tell you if
the omap-sham driver was really used.
d) To test these patches, you will likely need...
i) The patch included here:
http://marc.info/?l=kernel-janitors&m=134910841909057&w=2
ii) This patch from linux-omap/master:
27615a9 (ARM: OMAP: Trivial driver changes to remove include
plat/cpu.h)
iii) This patch from Paul Walmsley:
http://www.spinics.net/lists/linux-omap/msg79436.html
e) If you prefer, a version you can test is available at
git at github.com:mgreeraz/linux-mag.git wip/crypto/sham-v3+test
f) There is a reduction in DMA performance after switching to dmaengine
(see http://www.spinics.net/lists/linux-omap/msg79855.html)
g) Many thanks to Jon Hunter for testing on his omap2420 h4.
Mark A. Greer (7):
ARM: OMAP2xxx: hwmod: Convert SHAM crypto device data to hwmod
ARM: OMAP2xxx: hwmod: Add DMA support for SHAM module
ARM: OMAP3xxx: hwmod: Convert SHAM crypto device data to hwmod
ARM: OMAP2+: Remove unnecessary message when no SHA IP is present
crypto: omap-sham: Convert to use pm_runtime API
crypto: omap-sham: Add code to use dmaengine API
crypto: omap_sham: Remove usage of private DMA API
arch/arm/mach-omap2/clock2430_data.c | 1 +
arch/arm/mach-omap2/clock3xxx_data.c | 1 +
arch/arm/mach-omap2/devices.c | 73 ++------
arch/arm/mach-omap2/omap_hwmod_2420_data.c | 1 +
arch/arm/mach-omap2/omap_hwmod_2430_data.c | 1 +
.../mach-omap2/omap_hwmod_2xxx_interconnect_data.c | 18 ++
arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c | 43 +++++
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 60 +++++++
arch/arm/mach-omap2/omap_hwmod_common_data.h | 2 +
drivers/crypto/omap-sham.c | 195 +++++++++++----------
10 files changed, 245 insertions(+), 150 deletions(-)
--
1.7.12
^ permalink raw reply
* [PATCH v3 1/7] ARM: OMAP2xxx: hwmod: Convert SHAM crypto device data to hwmod
From: Mark A. Greer @ 2012-11-07 2:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352257033-32495-1-git-send-email-mgreer@animalcreek.com>
From: "Mark A. Greer" <mgreer@animalcreek.com>
Convert the device data for the OMAP2 SHAM crypto IP from
explicit platform_data to hwmod.
CC: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
---
arch/arm/mach-omap2/clock2430_data.c | 1 +
arch/arm/mach-omap2/devices.c | 34 ++++++++------------
arch/arm/mach-omap2/omap_hwmod_2420_data.c | 1 +
arch/arm/mach-omap2/omap_hwmod_2430_data.c | 1 +
.../mach-omap2/omap_hwmod_2xxx_interconnect_data.c | 18 +++++++++++
arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c | 37 ++++++++++++++++++++++
arch/arm/mach-omap2/omap_hwmod_common_data.h | 2 ++
7 files changed, 73 insertions(+), 21 deletions(-)
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
index 22404fe..4d52ec6 100644
--- a/arch/arm/mach-omap2/clock2430_data.c
+++ b/arch/arm/mach-omap2/clock2430_data.c
@@ -1993,6 +1993,7 @@ static struct omap_clk omap2430_clks[] = {
CLK(NULL, "sdrc_ick", &sdrc_ick, CK_243X),
CLK(NULL, "des_ick", &des_ick, CK_243X),
CLK("omap-sham", "ick", &sha_ick, CK_243X),
+ CLK(NULL, "sha_ick", &sha_ick, CK_242X),
CLK("omap_rng", "ick", &rng_ick, CK_243X),
CLK(NULL, "rng_ick", &rng_ick, CK_243X),
CLK("omap-aes", "ick", &aes_ick, CK_243X),
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index cba60e0..f18fa50 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -34,6 +34,8 @@
#include "mux.h"
#include "control.h"
#include "devices.h"
+#include "cm2xxx_3xxx.h"
+#include "cm-regbits-24xx.h"
#define L3_MODULES_MAX_LEN 12
#define L3_MODULES 3
@@ -453,24 +455,6 @@ static void omap_init_rng(void)
#if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE)
-#ifdef CONFIG_ARCH_OMAP2
-static struct resource omap2_sham_resources[] = {
- {
- .start = OMAP24XX_SEC_SHA1MD5_BASE,
- .end = OMAP24XX_SEC_SHA1MD5_BASE + 0x64,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = 51 + OMAP_INTC_START,
- .flags = IORESOURCE_IRQ,
- }
-};
-static int omap2_sham_resources_sz = ARRAY_SIZE(omap2_sham_resources);
-#else
-#define omap2_sham_resources NULL
-#define omap2_sham_resources_sz 0
-#endif
-
#ifdef CONFIG_ARCH_OMAP3
static struct resource omap3_sham_resources[] = {
{
@@ -501,16 +485,24 @@ static struct platform_device sham_device = {
static void omap_init_sham(void)
{
if (cpu_is_omap24xx()) {
- sham_device.resource = omap2_sham_resources;
- sham_device.num_resources = omap2_sham_resources_sz;
+ struct omap_hwmod *oh;
+ struct platform_device *pdev;
+
+ oh = omap_hwmod_lookup("sham");
+ if (!oh)
+ return;
+
+ pdev = omap_device_build("omap-sham", -1, oh, NULL, 0, NULL,
+ 0, 0);
+ WARN(IS_ERR(pdev), "Can't build omap_device for omap-sham\n");
} else if (cpu_is_omap34xx()) {
sham_device.resource = omap3_sham_resources;
sham_device.num_resources = omap3_sham_resources_sz;
+ platform_device_register(&sham_device);
} else {
pr_err("%s: platform not supported\n", __func__);
return;
}
- platform_device_register(&sham_device);
}
#else
static inline void omap_init_sham(void) { }
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index b5db600..b102a53 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -603,6 +603,7 @@ static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
&omap2420_l4_core__mcbsp2,
&omap2420_l4_core__msdi1,
&omap2xxx_l4_core__rng,
+ &omap2xxx_l4_core__sham,
&omap2420_l4_core__hdq1w,
&omap2420_l4_wkup__counter_32k,
&omap2420_l3__gpmc,
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index c455e41..b1ce7b0 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -963,6 +963,7 @@ static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
&omap2430_l4_core__mcbsp5,
&omap2430_l4_core__hdq1w,
&omap2xxx_l4_core__rng,
+ &omap2xxx_l4_core__sham,
&omap2430_l4_wkup__counter_32k,
&omap2430_l3__gpmc,
NULL,
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
index 1a1287d..bb314c5 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
@@ -138,6 +138,15 @@ static struct omap_hwmod_addr_space omap2_rng_addr_space[] = {
{ }
};
+struct omap_hwmod_addr_space omap2xxx_sham_addrs[] = {
+ {
+ .pa_start = 0x480a4000,
+ .pa_end = 0x480a4000 + 0x64 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
/*
* Common interconnect data
*/
@@ -389,3 +398,12 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__rng = {
.addr = omap2_rng_addr_space,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+
+/* l4 core -> sham interface */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__sham = {
+ .master = &omap2xxx_l4_core_hwmod,
+ .slave = &omap2xxx_sham_hwmod,
+ .clk = "sha_ick",
+ .addr = omap2xxx_sham_addrs,
+ .user = OCP_USER_MPU,
+};
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
index bd9220e..a041670 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -851,3 +851,40 @@ struct omap_hwmod omap2xxx_rng_hwmod = {
.flags = HWMOD_INIT_NO_RESET,
.class = &omap2_rng_hwmod_class,
};
+
+/* SHAM */
+
+static struct omap_hwmod_class_sysconfig omap2_sham_sysc = {
+ .rev_offs = 0x5c,
+ .sysc_offs = 0x60,
+ .syss_offs = 0x64,
+ .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+ SYSS_HAS_RESET_STATUS),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2xxx_sham_class = {
+ .name = "sham",
+ .sysc = &omap2_sham_sysc,
+};
+
+struct omap_hwmod_irq_info omap2_sham_mpu_irqs[] = {
+ { .irq = 51 + OMAP_INTC_START, },
+ { .irq = -1 }
+};
+
+struct omap_hwmod omap2xxx_sham_hwmod = {
+ .name = "sham",
+ .mpu_irqs = omap2_sham_mpu_irqs,
+ .main_clk = "l4_ck",
+ .prcm = {
+ .omap2 = {
+ .module_offs = CORE_MOD,
+ .prcm_reg_id = 4,
+ .module_bit = OMAP24XX_EN_SHA_SHIFT,
+ .idlest_reg_id = 4,
+ .idlest_idle_bit = OMAP24XX_ST_SHA_SHIFT,
+ },
+ },
+ .class = &omap2xxx_sham_class,
+};
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h
index 2bc8f17..74a7b7a 100644
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.h
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h
@@ -78,6 +78,7 @@ extern struct omap_hwmod omap2xxx_mcspi2_hwmod;
extern struct omap_hwmod omap2xxx_counter_32k_hwmod;
extern struct omap_hwmod omap2xxx_gpmc_hwmod;
extern struct omap_hwmod omap2xxx_rng_hwmod;
+extern struct omap_hwmod omap2xxx_sham_hwmod;
/* Common interface data across OMAP2xxx */
extern struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core;
@@ -105,6 +106,7 @@ extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc;
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi;
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc;
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__rng;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__sham;
/* Common IP block data */
extern struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[];
--
1.7.12
^ permalink raw reply related
* [PATCH v3 2/7] ARM: OMAP2xxx: hwmod: Add DMA support for SHAM module
From: Mark A. Greer @ 2012-11-07 2:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352257033-32495-1-git-send-email-mgreer@animalcreek.com>
From: "Mark A. Greer" <mgreer@animalcreek.com>
The current OMAP2 SHAM support doesn't enable DMA
so add that support so it can use DMA just like OMAP3.
CC: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
---
arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c | 2 +-
arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c | 6 ++++++
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
index bb314c5..4b4fd5f 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
@@ -405,5 +405,5 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__sham = {
.slave = &omap2xxx_sham_hwmod,
.clk = "sha_ick",
.addr = omap2xxx_sham_addrs,
- .user = OCP_USER_MPU,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
};
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
index a041670..703b269 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -873,9 +873,15 @@ struct omap_hwmod_irq_info omap2_sham_mpu_irqs[] = {
{ .irq = -1 }
};
+struct omap_hwmod_dma_info omap2_sham_sdma_chs[] = {
+ { .name = "rx", .dma_req = OMAP24XX_DMA_SHA1MD5_RX },
+ { .dma_req = -1 }
+};
+
struct omap_hwmod omap2xxx_sham_hwmod = {
.name = "sham",
.mpu_irqs = omap2_sham_mpu_irqs,
+ .sdma_reqs = omap2_sham_sdma_chs,
.main_clk = "l4_ck",
.prcm = {
.omap2 = {
--
1.7.12
^ permalink raw reply related
* [PATCH v3 3/7] ARM: OMAP3xxx: hwmod: Convert SHAM crypto device data to hwmod
From: Mark A. Greer @ 2012-11-07 2:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352257033-32495-1-git-send-email-mgreer@animalcreek.com>
From: "Mark A. Greer" <mgreer@animalcreek.com>
Convert the device data for the OMAP3 SHAM2 (SHA1/MD5) crypto IP
from explicit platform_data to hwmod.
CC: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
---
arch/arm/mach-omap2/clock3xxx_data.c | 1 +
arch/arm/mach-omap2/devices.c | 42 ++-------------------
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 60 ++++++++++++++++++++++++++++++
3 files changed, 64 insertions(+), 39 deletions(-)
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 1f42c9d..6f14d9b 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -3342,6 +3342,7 @@ static struct omap_clk omap3xxx_clks[] = {
CLK(NULL, "icr_ick", &icr_ick, CK_34XX | CK_36XX),
CLK("omap-aes", "ick", &aes2_ick, CK_34XX | CK_36XX),
CLK("omap-sham", "ick", &sha12_ick, CK_34XX | CK_36XX),
+ CLK(NULL, "sha12_ick", &sha12_ick, CK_34XX | CK_36XX),
CLK(NULL, "des2_ick", &des2_ick, CK_34XX | CK_36XX),
CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_3XXX),
CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_3XXX),
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index f18fa50..f38ac9d 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -36,6 +36,7 @@
#include "devices.h"
#include "cm2xxx_3xxx.h"
#include "cm-regbits-24xx.h"
+#include "cm-regbits-34xx.h"
#define L3_MODULES_MAX_LEN 12
#define L3_MODULES 3
@@ -453,38 +454,9 @@ static void omap_init_rng(void)
WARN(IS_ERR(pdev), "Can't build omap_device for omap_rng\n");
}
-#if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE)
-
-#ifdef CONFIG_ARCH_OMAP3
-static struct resource omap3_sham_resources[] = {
- {
- .start = OMAP34XX_SEC_SHA1MD5_BASE,
- .end = OMAP34XX_SEC_SHA1MD5_BASE + 0x64,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = 49 + OMAP_INTC_START,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = OMAP34XX_DMA_SHA1MD5_RX,
- .flags = IORESOURCE_DMA,
- }
-};
-static int omap3_sham_resources_sz = ARRAY_SIZE(omap3_sham_resources);
-#else
-#define omap3_sham_resources NULL
-#define omap3_sham_resources_sz 0
-#endif
-
-static struct platform_device sham_device = {
- .name = "omap-sham",
- .id = -1,
-};
-
-static void omap_init_sham(void)
+static void __init omap_init_sham(void)
{
- if (cpu_is_omap24xx()) {
+ if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
struct omap_hwmod *oh;
struct platform_device *pdev;
@@ -495,18 +467,10 @@ static void omap_init_sham(void)
pdev = omap_device_build("omap-sham", -1, oh, NULL, 0, NULL,
0, 0);
WARN(IS_ERR(pdev), "Can't build omap_device for omap-sham\n");
- } else if (cpu_is_omap34xx()) {
- sham_device.resource = omap3_sham_resources;
- sham_device.num_resources = omap3_sham_resources_sz;
- platform_device_register(&sham_device);
} else {
pr_err("%s: platform not supported\n", __func__);
- return;
}
}
-#else
-static inline void omap_init_sham(void) { }
-#endif
#if defined(CONFIG_CRYPTO_DEV_OMAP_AES) || defined(CONFIG_CRYPTO_DEV_OMAP_AES_MODULE)
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index f67b7ee..785a0c5 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -3543,6 +3543,65 @@ static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+/* l4_core -> SHAM2 (SHA1/MD5) (similar to omap24xx) */
+static struct omap_hwmod_class_sysconfig omap3_sham_sysc = {
+ .rev_offs = 0x5c,
+ .sysc_offs = 0x60,
+ .syss_offs = 0x64,
+ .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+ SYSS_HAS_RESET_STATUS),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap3xxx_sham_class = {
+ .name = "sham",
+ .sysc = &omap3_sham_sysc,
+};
+
+struct omap_hwmod_irq_info omap3_sham_mpu_irqs[] = {
+ { .irq = 49 + OMAP_INTC_START, },
+ { .irq = -1 }
+};
+
+struct omap_hwmod_dma_info omap3_sham_sdma_reqs[] = {
+ { .name = "rx", .dma_req = OMAP34XX_DMA_SHA1MD5_RX, },
+ { .dma_req = -1 }
+};
+
+struct omap_hwmod omap3xxx_sham_hwmod = {
+ .name = "sham",
+ .mpu_irqs = omap3_sham_mpu_irqs,
+ .sdma_reqs = omap3_sham_sdma_reqs,
+ .main_clk = "sha12_ick",
+ .prcm = {
+ .omap2 = {
+ .module_offs = CORE_MOD,
+ .prcm_reg_id = 1,
+ .module_bit = OMAP3430_EN_SHA12_SHIFT,
+ .idlest_reg_id = 1,
+ .idlest_idle_bit = OMAP3430_ST_SHA12_SHIFT,
+ },
+ },
+ .class = &omap3xxx_sham_class,
+};
+
+static struct omap_hwmod_addr_space omap3xxx_sham_addrs[] = {
+ {
+ .pa_start = 0x480c3000,
+ .pa_end = 0x480c3000 + 0x64 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__sham = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap3xxx_sham_hwmod,
+ .clk = "sha12_ick",
+ .addr = omap3xxx_sham_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
&omap3xxx_l3_main__l4_core,
&omap3xxx_l3_main__l4_per,
@@ -3596,6 +3655,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
/* GP-only hwmod links */
static struct omap_hwmod_ocp_if *omap3xxx_gp_hwmod_ocp_ifs[] __initdata = {
&omap3xxx_l4_sec__timer12,
+ &omap3xxx_l4_core__sham,
NULL
};
--
1.7.12
^ permalink raw reply related
* [PATCH v3 4/7] ARM: OMAP2+: Remove unnecessary message when no SHA IP is present
From: Mark A. Greer @ 2012-11-07 2:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352257033-32495-1-git-send-email-mgreer@animalcreek.com>
From: "Mark A. Greer" <mgreer@animalcreek.com>
Remove the error message that prints when there is no SHA IP
present to make it consistent with all the other IPs.
CC: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
---
arch/arm/mach-omap2/devices.c | 19 +++++++------------
1 file changed, 7 insertions(+), 12 deletions(-)
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index f38ac9d..f41c793 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -456,20 +456,15 @@ static void omap_init_rng(void)
static void __init omap_init_sham(void)
{
- if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
- struct omap_hwmod *oh;
- struct platform_device *pdev;
+ struct omap_hwmod *oh;
+ struct platform_device *pdev;
- oh = omap_hwmod_lookup("sham");
- if (!oh)
- return;
+ oh = omap_hwmod_lookup("sham");
+ if (!oh)
+ return;
- pdev = omap_device_build("omap-sham", -1, oh, NULL, 0, NULL,
- 0, 0);
- WARN(IS_ERR(pdev), "Can't build omap_device for omap-sham\n");
- } else {
- pr_err("%s: platform not supported\n", __func__);
- }
+ pdev = omap_device_build("omap-sham", -1, oh, NULL, 0, NULL, 0, 0);
+ WARN(IS_ERR(pdev), "Can't build omap_device for omap-sham\n");
}
#if defined(CONFIG_CRYPTO_DEV_OMAP_AES) || defined(CONFIG_CRYPTO_DEV_OMAP_AES_MODULE)
--
1.7.12
^ permalink raw reply related
* [PATCH v3 5/7] crypto: omap-sham: Convert to use pm_runtime API
From: Mark A. Greer @ 2012-11-07 2:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352257033-32495-1-git-send-email-mgreer@animalcreek.com>
From: "Mark A. Greer" <mgreer@animalcreek.com>
Convert the omap-sham crypto driver to use the
pm_runtime API instead of the clk API.
CC: Kevin Hilman <khilman@deeprootsystems.com>
CC: Paul Walmsley <paul@pwsan.com>
CC: Dmitry Kasatkin <dmitry.kasatkin@intel.com>
Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
---
drivers/crypto/omap-sham.c | 28 +++++++++++-----------------
1 file changed, 11 insertions(+), 17 deletions(-)
diff --git a/drivers/crypto/omap-sham.c b/drivers/crypto/omap-sham.c
index a3fd6fc..85d43b2 100644
--- a/drivers/crypto/omap-sham.c
+++ b/drivers/crypto/omap-sham.c
@@ -22,12 +22,12 @@
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
-#include <linux/clk.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/scatterlist.h>
#include <linux/dma-mapping.h>
+#include <linux/pm_runtime.h>
#include <linux/delay.h>
#include <linux/crypto.h>
#include <linux/cryptohash.h>
@@ -141,7 +141,6 @@ struct omap_sham_dev {
struct device *dev;
void __iomem *io_base;
int irq;
- struct clk *iclk;
spinlock_t lock;
int err;
int dma;
@@ -238,7 +237,7 @@ static void omap_sham_copy_ready_hash(struct ahash_request *req)
static int omap_sham_hw_init(struct omap_sham_dev *dd)
{
- clk_enable(dd->iclk);
+ pm_runtime_get_sync(dd->dev);
if (!test_bit(FLAGS_INIT, &dd->flags)) {
omap_sham_write_mask(dd, SHA_REG_MASK,
@@ -653,7 +652,8 @@ static void omap_sham_finish_req(struct ahash_request *req, int err)
/* atomic operation is not needed here */
dd->flags &= ~(BIT(FLAGS_BUSY) | BIT(FLAGS_FINAL) | BIT(FLAGS_CPU) |
BIT(FLAGS_DMA_READY) | BIT(FLAGS_OUTPUT_READY));
- clk_disable(dd->iclk);
+
+ pm_runtime_put_sync(dd->dev);
if (req->base.complete)
req->base.complete(&req->base, err);
@@ -1198,14 +1198,6 @@ static int __devinit omap_sham_probe(struct platform_device *pdev)
if (err)
goto dma_err;
- /* Initializing the clock */
- dd->iclk = clk_get(dev, "ick");
- if (IS_ERR(dd->iclk)) {
- dev_err(dev, "clock intialization failed.\n");
- err = PTR_ERR(dd->iclk);
- goto clk_err;
- }
-
dd->io_base = ioremap(dd->phys_base, SZ_4K);
if (!dd->io_base) {
dev_err(dev, "can't ioremap\n");
@@ -1213,11 +1205,14 @@ static int __devinit omap_sham_probe(struct platform_device *pdev)
goto io_err;
}
- clk_enable(dd->iclk);
+ pm_runtime_enable(dev);
+ pm_runtime_get_sync(dev);
+
dev_info(dev, "hw accel on OMAP rev %u.%u\n",
(omap_sham_read(dd, SHA_REG_REV) & SHA_REG_REV_MAJOR) >> 4,
omap_sham_read(dd, SHA_REG_REV) & SHA_REG_REV_MINOR);
- clk_disable(dd->iclk);
+
+ pm_runtime_put_sync(&pdev->dev);
spin_lock(&sham.lock);
list_add_tail(&dd->list, &sham.dev_list);
@@ -1235,9 +1230,8 @@ err_algs:
for (j = 0; j < i; j++)
crypto_unregister_ahash(&algs[j]);
iounmap(dd->io_base);
+ pm_runtime_disable(dev);
io_err:
- clk_put(dd->iclk);
-clk_err:
omap_sham_dma_cleanup(dd);
dma_err:
if (dd->irq >= 0)
@@ -1266,7 +1260,7 @@ static int __devexit omap_sham_remove(struct platform_device *pdev)
crypto_unregister_ahash(&algs[i]);
tasklet_kill(&dd->done_task);
iounmap(dd->io_base);
- clk_put(dd->iclk);
+ pm_runtime_disable(&pdev->dev);
omap_sham_dma_cleanup(dd);
if (dd->irq >= 0)
free_irq(dd->irq, dd);
--
1.7.12
^ permalink raw reply related
* [PATCH v3 6/7] crypto: omap-sham: Add code to use dmaengine API
From: Mark A. Greer @ 2012-11-07 2:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352257033-32495-1-git-send-email-mgreer@animalcreek.com>
From: "Mark A. Greer" <mgreer@animalcreek.com>
Add code to use the new dmaengine API alongside
the existing DMA code that uses the private
OMAP DMA API. The API to use is chosen by
defining or undefining 'OMAP_SHAM_DMA_PRIVATE'.
CC: Russell King <rmk+kernel@arm.linux.org.uk>
CC: Dmitry Kasatkin <dmitry.kasatkin@intel.com>
Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
---
drivers/crypto/omap-sham.c | 150 +++++++++++++++++++++++++++++++++++++++++++--
1 file changed, 145 insertions(+), 5 deletions(-)
diff --git a/drivers/crypto/omap-sham.c b/drivers/crypto/omap-sham.c
index 85d43b2..b57277c 100644
--- a/drivers/crypto/omap-sham.c
+++ b/drivers/crypto/omap-sham.c
@@ -13,6 +13,8 @@
* Some ideas are from old omap-sha1-md5.c driver.
*/
+#define OMAP_SHAM_DMA_PRIVATE
+
#define pr_fmt(fmt) "%s: " fmt, __func__
#include <linux/err.h>
@@ -27,6 +29,10 @@
#include <linux/platform_device.h>
#include <linux/scatterlist.h>
#include <linux/dma-mapping.h>
+#ifndef OMAP_SHAM_DMA_PRIVATE
+#include <linux/dmaengine.h>
+#include <linux/omap-dma.h>
+#endif
#include <linux/pm_runtime.h>
#include <linux/delay.h>
#include <linux/crypto.h>
@@ -37,9 +43,11 @@
#include <crypto/hash.h>
#include <crypto/internal/hash.h>
+#ifdef OMAP_SHAM_DMA_PRIVATE
#include <plat/cpu.h>
#include <plat/dma.h>
#include <mach/irqs.h>
+#endif
#define SHA_REG_DIGEST(x) (0x00 + ((x) * 0x04))
#define SHA_REG_DIN(x) (0x1C + ((x) * 0x04))
@@ -47,6 +55,8 @@
#define SHA1_MD5_BLOCK_SIZE SHA1_BLOCK_SIZE
#define MD5_DIGEST_SIZE 16
+#define DST_MAXBURST 16 /* Really element number (en) */
+
#define SHA_REG_DIGCNT 0x14
#define SHA_REG_CTRL 0x18
@@ -110,6 +120,9 @@ struct omap_sham_reqctx {
/* walk state */
struct scatterlist *sg;
+#ifndef OMAP_SHAM_DMA_PRIVATE
+ struct scatterlist sgl;
+#endif
unsigned int offset; /* offset in current sg */
unsigned int total; /* total request */
@@ -143,8 +156,12 @@ struct omap_sham_dev {
int irq;
spinlock_t lock;
int err;
+#ifdef OMAP_SHAM_DMA_PRIVATE
int dma;
int dma_lch;
+#else
+ struct dma_chan *dma_lch;
+#endif
struct tasklet_struct done_task;
unsigned long flags;
@@ -314,15 +331,32 @@ static int omap_sham_xmit_cpu(struct omap_sham_dev *dd, const u8 *buf,
return -EINPROGRESS;
}
+#ifndef OMAP_SHAM_DMA_PRIVATE
+static void omap_sham_dma_callback(void *param)
+{
+ struct omap_sham_dev *dd = param;
+
+ set_bit(FLAGS_DMA_READY, &dd->flags);
+ tasklet_schedule(&dd->done_task);
+}
+#endif
+
static int omap_sham_xmit_dma(struct omap_sham_dev *dd, dma_addr_t dma_addr,
- size_t length, int final)
+ size_t length, int final, int is_sg)
{
struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
+#ifdef OMAP_SHAM_DMA_PRIVATE
int len32;
+#else
+ struct dma_async_tx_descriptor *tx;
+ struct dma_slave_config cfg;
+ int ret;
+#endif
dev_dbg(dd->dev, "xmit_dma: digcnt: %d, length: %d, final: %d\n",
ctx->digcnt, length, final);
+#ifdef OMAP_SHAM_DMA_PRIVATE
len32 = DIV_ROUND_UP(length, sizeof(u32));
omap_set_dma_transfer_params(dd->dma_lch, OMAP_DMA_DATA_TYPE_S32, len32,
@@ -332,6 +366,48 @@ static int omap_sham_xmit_dma(struct omap_sham_dev *dd, dma_addr_t dma_addr,
omap_set_dma_src_params(dd->dma_lch, 0, OMAP_DMA_AMODE_POST_INC,
dma_addr, 0, 0);
+#else
+ memset(&cfg, 0, sizeof(cfg));
+
+ cfg.dst_addr = dd->phys_base + SHA_REG_DIN(0);
+ cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+ cfg.dst_maxburst = DST_MAXBURST;
+
+ ret = dmaengine_slave_config(dd->dma_lch, &cfg);
+ if (ret) {
+ pr_err("omap-sham: can't configure dmaengine slave: %d\n", ret);
+ return ret;
+ }
+
+ if (is_sg) {
+ /*
+ * The SG entry passed in may not have the 'length' member
+ * set correctly so use a local SG entry (sgl) with the
+ * proper value for 'length' instead. If this is not done,
+ * the dmaengine may try to DMA the incorrect amount of data.
+ */
+ sg_init_table(&ctx->sgl, 1);
+ ctx->sgl.page_link = ctx->sg->page_link;
+ ctx->sgl.offset = ctx->sg->offset;
+ sg_dma_len(&ctx->sgl) = length;
+ sg_dma_address(&ctx->sgl) = sg_dma_address(ctx->sg);
+
+ tx = dmaengine_prep_slave_sg(dd->dma_lch, &ctx->sgl, 1,
+ DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+ } else {
+ tx = dmaengine_prep_slave_single(dd->dma_lch, dma_addr, length,
+ DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+ }
+
+ if (!tx) {
+ dev_err(dd->dev, "prep_slave_sg/single() failed\n");
+ return -EINVAL;
+ }
+
+ tx->callback = omap_sham_dma_callback;
+ tx->callback_param = dd;
+#endif
+
omap_sham_write_ctrl(dd, length, final, 1);
ctx->digcnt += length;
@@ -341,7 +417,12 @@ static int omap_sham_xmit_dma(struct omap_sham_dev *dd, dma_addr_t dma_addr,
set_bit(FLAGS_DMA_ACTIVE, &dd->flags);
+#ifdef OMAP_SHAM_DMA_PRIVATE
omap_start_dma(dd->dma_lch);
+#else
+ dmaengine_submit(tx);
+ dma_async_issue_pending(dd->dma_lch);
+#endif
return -EINPROGRESS;
}
@@ -388,6 +469,8 @@ static int omap_sham_xmit_dma_map(struct omap_sham_dev *dd,
struct omap_sham_reqctx *ctx,
size_t length, int final)
{
+ int ret;
+
ctx->dma_addr = dma_map_single(dd->dev, ctx->buffer, ctx->buflen,
DMA_TO_DEVICE);
if (dma_mapping_error(dd->dev, ctx->dma_addr)) {
@@ -397,8 +480,12 @@ static int omap_sham_xmit_dma_map(struct omap_sham_dev *dd,
ctx->flags &= ~BIT(FLAGS_SG);
- /* next call does not fail... so no unmap in the case of error */
- return omap_sham_xmit_dma(dd, ctx->dma_addr, length, final);
+ ret = omap_sham_xmit_dma(dd, ctx->dma_addr, length, final, 0);
+ if (ret)
+ dma_unmap_single(dd->dev, ctx->dma_addr, ctx->buflen,
+ DMA_TO_DEVICE);
+
+ return ret;
}
static int omap_sham_update_dma_slow(struct omap_sham_dev *dd)
@@ -433,6 +520,7 @@ static int omap_sham_update_dma_start(struct omap_sham_dev *dd)
struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
unsigned int length, final, tail;
struct scatterlist *sg;
+ int ret;
if (!ctx->total)
return 0;
@@ -440,6 +528,17 @@ static int omap_sham_update_dma_start(struct omap_sham_dev *dd)
if (ctx->bufcnt || ctx->offset)
return omap_sham_update_dma_slow(dd);
+#ifndef OMAP_SHAM_DMA_PRIVATE
+ /*
+ * Don't use the sg interface when the transfer size is less
+ * than the number of elements in a DMA frame. Otherwise,
+ * the dmaengine infrastructure will calculate that it needs
+ * to transfer 0 frames which ultimately fails.
+ */
+ if (ctx->total < (DST_MAXBURST * sizeof(u32)))
+ return omap_sham_update_dma_slow(dd);
+#endif
+
dev_dbg(dd->dev, "fast: digcnt: %d, bufcnt: %u, total: %u\n",
ctx->digcnt, ctx->bufcnt, ctx->total);
@@ -477,8 +576,11 @@ static int omap_sham_update_dma_start(struct omap_sham_dev *dd)
final = (ctx->flags & BIT(FLAGS_FINUP)) && !ctx->total;
- /* next call does not fail... so no unmap in the case of error */
- return omap_sham_xmit_dma(dd, sg_dma_address(ctx->sg), length, final);
+ ret = omap_sham_xmit_dma(dd, sg_dma_address(ctx->sg), length, final, 1);
+ if (ret)
+ dma_unmap_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE);
+
+ return ret;
}
static int omap_sham_update_cpu(struct omap_sham_dev *dd)
@@ -497,7 +599,12 @@ static int omap_sham_update_dma_stop(struct omap_sham_dev *dd)
{
struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
+#ifdef OMAP_SHAM_DMA_PRIVATE
omap_stop_dma(dd->dma_lch);
+#else
+ dmaengine_terminate_all(dd->dma_lch);
+#endif
+
if (ctx->flags & BIT(FLAGS_SG)) {
dma_unmap_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE);
if (ctx->sg->length == ctx->offset) {
@@ -700,6 +807,7 @@ static int omap_sham_handle_queue(struct omap_sham_dev *dd,
if (err)
goto err1;
+#ifdef OMAP_SHAM_DMA_PRIVATE
omap_set_dma_dest_params(dd->dma_lch, 0,
OMAP_DMA_AMODE_CONSTANT,
dd->phys_base + SHA_REG_DIN(0), 0, 16);
@@ -709,6 +817,7 @@ static int omap_sham_handle_queue(struct omap_sham_dev *dd,
omap_set_dma_src_burst_mode(dd->dma_lch,
OMAP_DMA_DATA_BURST_4);
+#endif
if (ctx->digcnt)
/* request has changed - restore hash */
@@ -1100,6 +1209,7 @@ static irqreturn_t omap_sham_irq(int irq, void *dev_id)
return IRQ_HANDLED;
}
+#ifdef OMAP_SHAM_DMA_PRIVATE
static void omap_sham_dma_callback(int lch, u16 ch_status, void *data)
{
struct omap_sham_dev *dd = data;
@@ -1137,12 +1247,17 @@ static void omap_sham_dma_cleanup(struct omap_sham_dev *dd)
dd->dma_lch = -1;
}
}
+#endif
static int __devinit omap_sham_probe(struct platform_device *pdev)
{
struct omap_sham_dev *dd;
struct device *dev = &pdev->dev;
struct resource *res;
+#ifndef OMAP_SHAM_DMA_PRIVATE
+ dma_cap_mask_t mask;
+ unsigned dma_chan;
+#endif
int err, i, j;
dd = kzalloc(sizeof(struct omap_sham_dev), GFP_KERNEL);
@@ -1177,7 +1292,11 @@ static int __devinit omap_sham_probe(struct platform_device *pdev)
err = -ENODEV;
goto res_err;
}
+#ifdef OMAP_SHAM_DMA_PRIVATE
dd->dma = res->start;
+#else
+ dma_chan = res->start;
+#endif
/* Get the IRQ */
dd->irq = platform_get_irq(pdev, 0);
@@ -1194,9 +1313,22 @@ static int __devinit omap_sham_probe(struct platform_device *pdev)
goto res_err;
}
+#ifdef OMAP_SHAM_DMA_PRIVATE
err = omap_sham_dma_init(dd);
if (err)
goto dma_err;
+#else
+ dma_cap_zero(mask);
+ dma_cap_set(DMA_SLAVE, mask);
+
+ dd->dma_lch = dma_request_channel(mask, omap_dma_filter_fn, &dma_chan);
+ if (!dd->dma_lch) {
+ dev_err(dev, "unable to obtain RX DMA engine channel %u\n",
+ dma_chan);
+ err = -ENXIO;
+ goto dma_err;
+ }
+#endif
dd->io_base = ioremap(dd->phys_base, SZ_4K);
if (!dd->io_base) {
@@ -1232,7 +1364,11 @@ err_algs:
iounmap(dd->io_base);
pm_runtime_disable(dev);
io_err:
+#ifdef OMAP_SHAM_DMA_PRIVATE
omap_sham_dma_cleanup(dd);
+#else
+ dma_release_channel(dd->dma_lch);
+#endif
dma_err:
if (dd->irq >= 0)
free_irq(dd->irq, dd);
@@ -1261,7 +1397,11 @@ static int __devexit omap_sham_remove(struct platform_device *pdev)
tasklet_kill(&dd->done_task);
iounmap(dd->io_base);
pm_runtime_disable(&pdev->dev);
+#ifdef OMAP_SHAM_DMA_PRIVATE
omap_sham_dma_cleanup(dd);
+#else
+ dma_release_channel(dd->dma_lch);
+#endif
if (dd->irq >= 0)
free_irq(dd->irq, dd);
kfree(dd);
--
1.7.12
^ permalink raw reply related
* [PATCH v3 7/7] crypto: omap_sham: Remove usage of private DMA API
From: Mark A. Greer @ 2012-11-07 2:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352257033-32495-1-git-send-email-mgreer@animalcreek.com>
From: "Mark A. Greer" <mgreer@animalcreek.com>
Remove usage of the private OMAP DMA API.
The dmaengine API will be used instead.
CC: Russell King <rmk+kernel@arm.linux.org.uk>
CC: Dmitry Kasatkin <dmitry.kasatkin@intel.com>
Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
---
drivers/crypto/omap-sham.c | 117 ---------------------------------------------
1 file changed, 117 deletions(-)
diff --git a/drivers/crypto/omap-sham.c b/drivers/crypto/omap-sham.c
index b57277c..ebb5255 100644
--- a/drivers/crypto/omap-sham.c
+++ b/drivers/crypto/omap-sham.c
@@ -13,8 +13,6 @@
* Some ideas are from old omap-sha1-md5.c driver.
*/
-#define OMAP_SHAM_DMA_PRIVATE
-
#define pr_fmt(fmt) "%s: " fmt, __func__
#include <linux/err.h>
@@ -29,10 +27,8 @@
#include <linux/platform_device.h>
#include <linux/scatterlist.h>
#include <linux/dma-mapping.h>
-#ifndef OMAP_SHAM_DMA_PRIVATE
#include <linux/dmaengine.h>
#include <linux/omap-dma.h>
-#endif
#include <linux/pm_runtime.h>
#include <linux/delay.h>
#include <linux/crypto.h>
@@ -43,12 +39,6 @@
#include <crypto/hash.h>
#include <crypto/internal/hash.h>
-#ifdef OMAP_SHAM_DMA_PRIVATE
-#include <plat/cpu.h>
-#include <plat/dma.h>
-#include <mach/irqs.h>
-#endif
-
#define SHA_REG_DIGEST(x) (0x00 + ((x) * 0x04))
#define SHA_REG_DIN(x) (0x1C + ((x) * 0x04))
@@ -120,9 +110,7 @@ struct omap_sham_reqctx {
/* walk state */
struct scatterlist *sg;
-#ifndef OMAP_SHAM_DMA_PRIVATE
struct scatterlist sgl;
-#endif
unsigned int offset; /* offset in current sg */
unsigned int total; /* total request */
@@ -156,12 +144,7 @@ struct omap_sham_dev {
int irq;
spinlock_t lock;
int err;
-#ifdef OMAP_SHAM_DMA_PRIVATE
- int dma;
- int dma_lch;
-#else
struct dma_chan *dma_lch;
-#endif
struct tasklet_struct done_task;
unsigned long flags;
@@ -331,7 +314,6 @@ static int omap_sham_xmit_cpu(struct omap_sham_dev *dd, const u8 *buf,
return -EINPROGRESS;
}
-#ifndef OMAP_SHAM_DMA_PRIVATE
static void omap_sham_dma_callback(void *param)
{
struct omap_sham_dev *dd = param;
@@ -339,34 +321,18 @@ static void omap_sham_dma_callback(void *param)
set_bit(FLAGS_DMA_READY, &dd->flags);
tasklet_schedule(&dd->done_task);
}
-#endif
static int omap_sham_xmit_dma(struct omap_sham_dev *dd, dma_addr_t dma_addr,
size_t length, int final, int is_sg)
{
struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
-#ifdef OMAP_SHAM_DMA_PRIVATE
- int len32;
-#else
struct dma_async_tx_descriptor *tx;
struct dma_slave_config cfg;
int ret;
-#endif
dev_dbg(dd->dev, "xmit_dma: digcnt: %d, length: %d, final: %d\n",
ctx->digcnt, length, final);
-#ifdef OMAP_SHAM_DMA_PRIVATE
- len32 = DIV_ROUND_UP(length, sizeof(u32));
-
- omap_set_dma_transfer_params(dd->dma_lch, OMAP_DMA_DATA_TYPE_S32, len32,
- 1, OMAP_DMA_SYNC_PACKET, dd->dma,
- OMAP_DMA_DST_SYNC_PREFETCH);
-
- omap_set_dma_src_params(dd->dma_lch, 0, OMAP_DMA_AMODE_POST_INC,
- dma_addr, 0, 0);
-
-#else
memset(&cfg, 0, sizeof(cfg));
cfg.dst_addr = dd->phys_base + SHA_REG_DIN(0);
@@ -406,7 +372,6 @@ static int omap_sham_xmit_dma(struct omap_sham_dev *dd, dma_addr_t dma_addr,
tx->callback = omap_sham_dma_callback;
tx->callback_param = dd;
-#endif
omap_sham_write_ctrl(dd, length, final, 1);
@@ -417,12 +382,8 @@ static int omap_sham_xmit_dma(struct omap_sham_dev *dd, dma_addr_t dma_addr,
set_bit(FLAGS_DMA_ACTIVE, &dd->flags);
-#ifdef OMAP_SHAM_DMA_PRIVATE
- omap_start_dma(dd->dma_lch);
-#else
dmaengine_submit(tx);
dma_async_issue_pending(dd->dma_lch);
-#endif
return -EINPROGRESS;
}
@@ -528,7 +489,6 @@ static int omap_sham_update_dma_start(struct omap_sham_dev *dd)
if (ctx->bufcnt || ctx->offset)
return omap_sham_update_dma_slow(dd);
-#ifndef OMAP_SHAM_DMA_PRIVATE
/*
* Don't use the sg interface when the transfer size is less
* than the number of elements in a DMA frame. Otherwise,
@@ -537,7 +497,6 @@ static int omap_sham_update_dma_start(struct omap_sham_dev *dd)
*/
if (ctx->total < (DST_MAXBURST * sizeof(u32)))
return omap_sham_update_dma_slow(dd);
-#endif
dev_dbg(dd->dev, "fast: digcnt: %d, bufcnt: %u, total: %u\n",
ctx->digcnt, ctx->bufcnt, ctx->total);
@@ -599,11 +558,7 @@ static int omap_sham_update_dma_stop(struct omap_sham_dev *dd)
{
struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
-#ifdef OMAP_SHAM_DMA_PRIVATE
- omap_stop_dma(dd->dma_lch);
-#else
dmaengine_terminate_all(dd->dma_lch);
-#endif
if (ctx->flags & BIT(FLAGS_SG)) {
dma_unmap_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE);
@@ -807,18 +762,6 @@ static int omap_sham_handle_queue(struct omap_sham_dev *dd,
if (err)
goto err1;
-#ifdef OMAP_SHAM_DMA_PRIVATE
- omap_set_dma_dest_params(dd->dma_lch, 0,
- OMAP_DMA_AMODE_CONSTANT,
- dd->phys_base + SHA_REG_DIN(0), 0, 16);
-
- omap_set_dma_dest_burst_mode(dd->dma_lch,
- OMAP_DMA_DATA_BURST_16);
-
- omap_set_dma_src_burst_mode(dd->dma_lch,
- OMAP_DMA_DATA_BURST_4);
-#endif
-
if (ctx->digcnt)
/* request has changed - restore hash */
omap_sham_copy_hash(req, 0);
@@ -1209,55 +1152,13 @@ static irqreturn_t omap_sham_irq(int irq, void *dev_id)
return IRQ_HANDLED;
}
-#ifdef OMAP_SHAM_DMA_PRIVATE
-static void omap_sham_dma_callback(int lch, u16 ch_status, void *data)
-{
- struct omap_sham_dev *dd = data;
-
- if (ch_status != OMAP_DMA_BLOCK_IRQ) {
- pr_err("omap-sham DMA error status: 0x%hx\n", ch_status);
- dd->err = -EIO;
- clear_bit(FLAGS_INIT, &dd->flags);/* request to re-initialize */
- }
-
- set_bit(FLAGS_DMA_READY, &dd->flags);
- tasklet_schedule(&dd->done_task);
-}
-
-static int omap_sham_dma_init(struct omap_sham_dev *dd)
-{
- int err;
-
- dd->dma_lch = -1;
-
- err = omap_request_dma(dd->dma, dev_name(dd->dev),
- omap_sham_dma_callback, dd, &dd->dma_lch);
- if (err) {
- dev_err(dd->dev, "Unable to request DMA channel\n");
- return err;
- }
-
- return 0;
-}
-
-static void omap_sham_dma_cleanup(struct omap_sham_dev *dd)
-{
- if (dd->dma_lch >= 0) {
- omap_free_dma(dd->dma_lch);
- dd->dma_lch = -1;
- }
-}
-#endif
-
static int __devinit omap_sham_probe(struct platform_device *pdev)
{
struct omap_sham_dev *dd;
struct device *dev = &pdev->dev;
struct resource *res;
-#ifndef OMAP_SHAM_DMA_PRIVATE
dma_cap_mask_t mask;
unsigned dma_chan;
-#endif
int err, i, j;
dd = kzalloc(sizeof(struct omap_sham_dev), GFP_KERNEL);
@@ -1292,11 +1193,7 @@ static int __devinit omap_sham_probe(struct platform_device *pdev)
err = -ENODEV;
goto res_err;
}
-#ifdef OMAP_SHAM_DMA_PRIVATE
- dd->dma = res->start;
-#else
dma_chan = res->start;
-#endif
/* Get the IRQ */
dd->irq = platform_get_irq(pdev, 0);
@@ -1313,11 +1210,6 @@ static int __devinit omap_sham_probe(struct platform_device *pdev)
goto res_err;
}
-#ifdef OMAP_SHAM_DMA_PRIVATE
- err = omap_sham_dma_init(dd);
- if (err)
- goto dma_err;
-#else
dma_cap_zero(mask);
dma_cap_set(DMA_SLAVE, mask);
@@ -1328,7 +1220,6 @@ static int __devinit omap_sham_probe(struct platform_device *pdev)
err = -ENXIO;
goto dma_err;
}
-#endif
dd->io_base = ioremap(dd->phys_base, SZ_4K);
if (!dd->io_base) {
@@ -1364,11 +1255,7 @@ err_algs:
iounmap(dd->io_base);
pm_runtime_disable(dev);
io_err:
-#ifdef OMAP_SHAM_DMA_PRIVATE
- omap_sham_dma_cleanup(dd);
-#else
dma_release_channel(dd->dma_lch);
-#endif
dma_err:
if (dd->irq >= 0)
free_irq(dd->irq, dd);
@@ -1397,11 +1284,7 @@ static int __devexit omap_sham_remove(struct platform_device *pdev)
tasklet_kill(&dd->done_task);
iounmap(dd->io_base);
pm_runtime_disable(&pdev->dev);
-#ifdef OMAP_SHAM_DMA_PRIVATE
- omap_sham_dma_cleanup(dd);
-#else
dma_release_channel(dd->dma_lch);
-#endif
if (dd->irq >= 0)
free_irq(dd->irq, dd);
kfree(dd);
--
1.7.12
^ permalink raw reply related
* linux-next: manual merge of the arm-soc tree with the l2-mtd and pinctrl trees
From: Stephen Rothwell @ 2012-11-07 3:29 UTC (permalink / raw)
To: linux-arm-kernel
Hi all,
Today's linux-next merge of the arm-soc tree got a conflict in
arch/arm/mach-nomadik/board-nhk8815.c between commit 1cd2fc449091 ("ARM:
nomadik: fixup some FSMC merge problems") from the l2-mtd tree, commits
bb16bd9b9da4 ("pinctrl/nomadik: move the platform data header") from the
pinctrl and commit 44e47ccf8ab6 ("Merge branch 'next/multiplatform' into
for-next") from the arm-soc tree.
I fixed it up (see below) and can carry the fix as necessary (no action
is required).
--
Cheers,
Stephen Rothwell sfr at canb.auug.org.au
diff --cc arch/arm/mach-nomadik/board-nhk8815.c
index ab7104f,5ccdf53..0000000
--- a/arch/arm/mach-nomadik/board-nhk8815.c
+++ b/arch/arm/mach-nomadik/board-nhk8815.c
@@@ -30,11 -31,10 +32,9 @@@
#include <asm/sizes.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
- #include <asm/mach/irq.h>
#include <asm/mach/flash.h>
#include <asm/mach/time.h>
-
- #include <plat/mtu.h>
-#include <mach/fsmc.h>
+ #include <mach/irqs.h>
#include "cpu-8815.h"
-------------- next part --------------
A non-text attachment was scrubbed...
Name: not available
Type: application/pgp-signature
Size: 836 bytes
Desc: not available
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20121107/e075bca6/attachment.sig>
^ permalink raw reply
* [Resend PATCH v3 2/4] ARM: at91: atmel-ssc: add device tree support
From: Bo Shen @ 2012-11-07 3:41 UTC (permalink / raw)
To: linux-arm-kernel
Add atmel-ssc for device tree support
Match "atmel,at91rm9200-ssc" for using pdc for data transfer
Match "atmel,at91sam9g45-ssc" for using dma for data transfer
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
---
Resend
Fix a error find by Fengguang Yu
Although there is a NACK from Jean-Christophe PLAGNIOL-VILLARD,
however the pinctrl for at91 is not in mainline. So, plan to add
pinctrl support after the pinctrl driver for at91 is merged.
Change since v2
No change
Change since v1
change the underscore to dash in atmel-ssc binding document
---
.../devicetree/bindings/misc/atmel-ssc.txt | 15 ++++++
arch/arm/boot/dts/at91sam9260.dtsi | 8 ++++
arch/arm/boot/dts/at91sam9263.dtsi | 16 +++++++
arch/arm/boot/dts/at91sam9g45.dtsi | 16 +++++++
arch/arm/boot/dts/at91sam9x5.dtsi | 8 ++++
arch/arm/mach-at91/at91rm9200.c | 3 ++
arch/arm/mach-at91/at91sam9260.c | 1 +
arch/arm/mach-at91/at91sam9261.c | 3 ++
arch/arm/mach-at91/at91sam9263.c | 2 +
arch/arm/mach-at91/at91sam9g45.c | 2 +
arch/arm/mach-at91/at91sam9rl.c | 2 +
arch/arm/mach-at91/at91sam9x5.c | 1 +
drivers/misc/atmel-ssc.c | 49 ++++++++++++++++++--
13 files changed, 123 insertions(+), 3 deletions(-)
create mode 100644 Documentation/devicetree/bindings/misc/atmel-ssc.txt
diff --git a/Documentation/devicetree/bindings/misc/atmel-ssc.txt b/Documentation/devicetree/bindings/misc/atmel-ssc.txt
new file mode 100644
index 0000000..38e51ad
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/atmel-ssc.txt
@@ -0,0 +1,15 @@
+* Atmel SSC driver.
+
+Required properties:
+- compatible: "atmel,at91rm9200-ssc" or "atmel,at91sam9g45-ssc"
+ - atmel,at91rm9200-ssc: support pdc transfer
+ - atmel,at91sam9g45-ssc: support dma transfer
+- reg: Should contain SSC registers location and length
+- interrupts: Should contain SSC interrupt
+
+Example:
+ssc0: ssc at fffbc000 {
+ compatible = "atmel,at91rm9200-ssc";
+ reg = <0xfffbc000 0x4000>;
+ interrupts = <14 4 5>;
+};
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index d410581..aaa42d8 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -29,6 +29,7 @@
tcb0 = &tcb0;
tcb1 = &tcb1;
i2c0 = &i2c0;
+ ssc0 = &ssc0;
};
cpus {
cpu at 0 {
@@ -212,6 +213,13 @@
status = "disabled";
};
+ ssc0: ssc at fffbc000 {
+ compatible = "atmel,at91rm9200-ssc";
+ reg = <0xfffbc000 0x4000>;
+ interrupts = <14 4 5>;
+ status = "disable";
+ };
+
adc0: adc at fffe0000 {
compatible = "atmel,at91sam9260-adc";
reg = <0xfffe0000 0x100>;
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index 3e6e5c1..3b721ee 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -25,6 +25,8 @@
gpio4 = &pioE;
tcb0 = &tcb0;
i2c0 = &i2c0;
+ ssc0 = &ssc0;
+ ssc1 = &ssc1;
};
cpus {
cpu at 0 {
@@ -173,6 +175,20 @@
status = "disabled";
};
+ ssc0: ssc at fff98000 {
+ compatible = "atmel,at91rm9200-ssc";
+ reg = <0xfff98000 0x4000>;
+ interrupts = <16 4 5>;
+ status = "disable";
+ };
+
+ ssc1: ssc at fff9c000 {
+ compatible = "atmel,at91rm9200-ssc";
+ reg = <0xfff9c000 0x4000>;
+ interrupts = <17 4 5>;
+ status = "disable";
+ };
+
macb0: ethernet at fffbc000 {
compatible = "cdns,at32ap7000-macb", "cdns,macb";
reg = <0xfffbc000 0x100>;
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index 3add030..acfa207 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -31,6 +31,8 @@
tcb1 = &tcb1;
i2c0 = &i2c0;
i2c1 = &i2c1;
+ ssc0 = &ssc0;
+ ssc1 = &ssc1;
};
cpus {
cpu at 0 {
@@ -226,6 +228,20 @@
status = "disabled";
};
+ ssc0: ssc at fff9c000 {
+ compatible = "atmel,at91sam9g45-ssc";
+ reg = <0xfff9c000 0x4000>;
+ interrupts = <16 4 5>;
+ status = "disable";
+ };
+
+ ssc1: ssc at fffa0000 {
+ compatible = "atmel,at91sam9g45-ssc";
+ reg = <0xfffa0000 0x4000>;
+ interrupts = <17 4 5>;
+ status = "disable";
+ };
+
adc0: adc at fffb0000 {
compatible = "atmel,at91sam9260-adc";
reg = <0xfffb0000 0x100>;
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 03fc136..69667d0 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -30,6 +30,7 @@
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
+ ssc0 = &ssc0;
};
cpus {
cpu at 0 {
@@ -87,6 +88,13 @@
interrupts = <1 4 7>;
};
+ ssc0: ssc at f0010000 {
+ compatible = "atmel,at91sam9g45-ssc";
+ reg = <0xf0010000 0x4000>;
+ interrupts = <28 4 5>;
+ status = "disable";
+ };
+
tcb0: timer at f8008000 {
compatible = "atmel,at91sam9x5-tcb";
reg = <0xf8008000 0x100>;
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index 400d1a3..af47c75 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -187,6 +187,9 @@ static struct clk_lookup periph_clocks_lookups[] = {
CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.2", &ssc2_clk),
+ CLKDEV_CON_DEV_ID("pclk", "fffd0000.ssc", &ssc0_clk),
+ CLKDEV_CON_DEV_ID("pclk", "fffd4000.ssc", &ssc1_clk),
+ CLKDEV_CON_DEV_ID("pclk", "fffd8000.ssc", &ssc2_clk),
CLKDEV_CON_DEV_ID(NULL, "i2c-at91rm9200.0", &twi_clk),
/* fake hclk clock */
CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index d14ab6a..a41eb3d 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -211,6 +211,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk),
CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk),
CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc_clk),
+ CLKDEV_CON_DEV_ID("pclk", "fffbc000.ssc", &ssc_clk),
CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9260.0", &twi_clk),
CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.0", &twi_clk),
/* more usart lookup table for DT entries */
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index c7b6057..7fcbe05 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -177,6 +177,9 @@ static struct clk_lookup periph_clocks_lookups[] = {
CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.2", &ssc2_clk),
+ CLKDEV_CON_DEV_ID("pclk", "fffbc000.ssc", &ssc0_clk),
+ CLKDEV_CON_DEV_ID("pclk", "fffc0000.ssc", &ssc1_clk),
+ CLKDEV_CON_DEV_ID("pclk", "fffc4000.ssc", &ssc2_clk),
CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &hck0),
CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9261.0", &twi_clk),
CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.0", &twi_clk),
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index b87be18..c0f4c8c 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -188,6 +188,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
CLKDEV_CON_ID("hclk", &macb_clk),
CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
+ CLKDEV_CON_DEV_ID("pclk", "fff98000.ssc", &ssc0_clk),
+ CLKDEV_CON_DEV_ID("pclk", "fff9c000.ssc", &ssc1_clk),
CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index f4f96a6..a4282d3 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -241,6 +241,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.1", &twi1_clk),
CLKDEV_CON_DEV_ID("pclk", "at91sam9g45_ssc.0", &ssc0_clk),
CLKDEV_CON_DEV_ID("pclk", "at91sam9g45_ssc.1", &ssc1_clk),
+ CLKDEV_CON_DEV_ID("pclk", "fff9c000.ssc", &ssc0_clk),
+ CLKDEV_CON_DEV_ID("pclk", "fffa0000.ssc", &ssc1_clk),
CLKDEV_CON_DEV_ID(NULL, "atmel-trng", &trng_clk),
CLKDEV_CON_DEV_ID(NULL, "atmel_sha", &aestdessha_clk),
CLKDEV_CON_DEV_ID(NULL, "atmel_tdes", &aestdessha_clk),
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index 4110b54..b683fdc 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -186,6 +186,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
+ CLKDEV_CON_DEV_ID("pclk", "fffc0000.ssc", &ssc0_clk),
+ CLKDEV_CON_DEV_ID("pclk", "fffc4000.ssc", &ssc1_clk),
CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.0", &twi0_clk),
CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.1", &twi1_clk),
CLKDEV_CON_ID("pioA", &pioA_clk),
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index e503538..18fbbb2 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -231,6 +231,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb0_clk),
CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma0_clk),
CLKDEV_CON_DEV_ID("dma_clk", "ffffee00.dma-controller", &dma1_clk),
+ CLKDEV_CON_DEV_ID("pclk", "f0010000.ssc", &ssc_clk),
CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk),
CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk),
CLKDEV_CON_DEV_ID(NULL, "f8018000.i2c", &twi2_clk),
diff --git a/drivers/misc/atmel-ssc.c b/drivers/misc/atmel-ssc.c
index f40abd8..a769719 100644
--- a/drivers/misc/atmel-ssc.c
+++ b/drivers/misc/atmel-ssc.c
@@ -18,6 +18,8 @@
#include <linux/slab.h>
#include <linux/module.h>
+#include <linux/of.h>
+
/* Serialize access to ssc_list and user count */
static DEFINE_SPINLOCK(user_lock);
static LIST_HEAD(ssc_list);
@@ -29,7 +31,13 @@ struct ssc_device *ssc_request(unsigned int ssc_num)
spin_lock(&user_lock);
list_for_each_entry(ssc, &ssc_list, list) {
- if (ssc->pdev->id == ssc_num) {
+ if (ssc->pdev->dev.of_node) {
+ if (of_alias_get_id(ssc->pdev->dev.of_node, "ssc")
+ == ssc_num) {
+ ssc_valid = 1;
+ break;
+ }
+ } else if (ssc->pdev->id == ssc_num) {
ssc_valid = 1;
break;
}
@@ -88,10 +96,41 @@ static const struct platform_device_id atmel_ssc_devtypes[] = {
}
};
+#ifdef CONFIG_OF
+static const struct of_device_id atmel_ssc_dt_ids[] = {
+ {
+ .compatible = "atmel,at91rm9200-ssc",
+ .data = &at91rm9200_config,
+ }, {
+ .compatible = "atmel,at91sam9g45-ssc",
+ .data = &at91sam9g45_config,
+ }, {
+ /* sentinel */
+ }
+};
+MODULE_DEVICE_TABLE(of, atmel_ssc_dt_ids);
+#endif
+
+static inline const struct atmel_ssc_platform_data * __init
+ atmel_ssc_get_driver_data(struct platform_device *pdev)
+{
+ if (pdev->dev.of_node) {
+ const struct of_device_id *match;
+ match = of_match_node(atmel_ssc_dt_ids, pdev->dev.of_node);
+ if (match == NULL)
+ return NULL;
+ return match->data;
+ }
+
+ return (struct atmel_ssc_platform_data *)
+ platform_get_device_id(pdev)->driver_data;
+}
+
static int ssc_probe(struct platform_device *pdev)
{
struct resource *regs;
struct ssc_device *ssc;
+ const struct atmel_ssc_platform_data *plat_dat;
ssc = devm_kzalloc(&pdev->dev, sizeof(struct ssc_device), GFP_KERNEL);
if (!ssc) {
@@ -100,8 +139,11 @@ static int ssc_probe(struct platform_device *pdev)
}
ssc->pdev = pdev;
- ssc->pdata = (struct atmel_ssc_platform_data *)
- platform_get_device_id(pdev)->driver_data;
+
+ plat_dat = atmel_ssc_get_driver_data(pdev);
+ if (!plat_dat)
+ return -ENODEV;
+ ssc->pdata = (struct atmel_ssc_platform_data *)plat_dat;
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!regs) {
@@ -160,6 +202,7 @@ static struct platform_driver ssc_driver = {
.driver = {
.name = "ssc",
.owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(atmel_ssc_dt_ids),
},
.id_table = atmel_ssc_devtypes,
.probe = ssc_probe,
--
1.7.9.5
^ permalink raw reply related
* [PATCH RFC] ARM: EXYNOS5: Setup legacy i2c controller interrupts on SMDK5250
From: Abhilash Kesavan @ 2012-11-07 3:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAJuYYwSka_-w+_hJQivu6M2tUDtD-9zH-4YtLeSoTwPODODQMw@mail.gmail.com>
Hi Thomas,
Thanks for the suggestions.
On Tue, Nov 6, 2012 at 1:45 PM, Thomas Abraham
<thomas.abraham@linaro.org> wrote:
> On 6 November 2012 11:48, Abhilash Kesavan <a.kesavan@samsung.com> wrote:
>> On Exynos5 we have a new high-speed i2c controller. The interrupt
>> sources for the legacy and new controller are muxed and are controlled
>> via the SYSCON I2C_CFG register.
>> At reset the interrupt source is configured for the high-speed controller,
>> to continue using the old i2c controller we need to modify the I2C_CFG
>> register.
>
> If the high-speed i2c controllers are not used, can this configuration
> be moved into the bootloader?
>
> The other option could be, in the exynos5250_dt_machine_init()
> function, first check if the platform is compatible with
> "samsung,exynos5250" and if so search for a high-speed i2c controller
> compatible node. If a high-speed controller node is found and if that
> node is not disabled, then do not change the reset value of I2C_CFG
> register.
>
I'd like to try this out. Do we have to a scenario where both hs-i2c and legacy
i2c nodes are added to the dts file without disabling either of them or is it
expected that one of these will always be disabled in the board-specific
dts file (as only one can work at a time) ?
> Thanks,
> Thomas.
>
^ permalink raw reply
* [PATCH RFC] ARM: EXYNOS5: Setup legacy i2c controller interrupts on SMDK5250
From: Thomas Abraham @ 2012-11-07 4:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAM4voaki_t=AMNZ4g8-aWTCATNYQTSBSjxiH0jPX2dddMoj+jw@mail.gmail.com>
On 7 November 2012 09:12, Abhilash Kesavan <kesavan.abhilash@gmail.com> wrote:
> Hi Thomas,
>
> Thanks for the suggestions.
>
> On Tue, Nov 6, 2012 at 1:45 PM, Thomas Abraham
> <thomas.abraham@linaro.org> wrote:
>> On 6 November 2012 11:48, Abhilash Kesavan <a.kesavan@samsung.com> wrote:
>>> On Exynos5 we have a new high-speed i2c controller. The interrupt
>>> sources for the legacy and new controller are muxed and are controlled
>>> via the SYSCON I2C_CFG register.
>>> At reset the interrupt source is configured for the high-speed controller,
>>> to continue using the old i2c controller we need to modify the I2C_CFG
>>> register.
>>
>> If the high-speed i2c controllers are not used, can this configuration
>> be moved into the bootloader?
>>
>> The other option could be, in the exynos5250_dt_machine_init()
>> function, first check if the platform is compatible with
>> "samsung,exynos5250" and if so search for a high-speed i2c controller
>> compatible node. If a high-speed controller node is found and if that
>> node is not disabled, then do not change the reset value of I2C_CFG
>> register.
>>
> I'd like to try this out. Do we have to a scenario where both hs-i2c and legacy
> i2c nodes are added to the dts file without disabling either of them or is it
> expected that one of these will always be disabled in the board-specific
> dts file (as only one can work at a time) ?
I would expect only one of the two types of i2c controller to be
enabled in the board dts file. I don't think there will be use case
where we have to switch between low-speed and high-speed controllers
at runtime.
And, since there are four interrupt configuration bits in I2C_CFG,
alias id would be required to determine which bit in the I2C_CFG
register has be setup.
Thanks,
Thomas.
^ permalink raw reply
* [PATCH RFC] ARM: EXYNOS5: Setup legacy i2c controller interrupts on SMDK5250
From: Abhilash Kesavan @ 2012-11-07 4:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAJuYYwQzBU0=L_dFLj8=hSPremnOKPocF7oS68X1tCBDXuKLYw@mail.gmail.com>
Thanks for the clarification.
On Wed, Nov 7, 2012 at 9:35 AM, Thomas Abraham
<thomas.abraham@linaro.org> wrote:
> On 7 November 2012 09:12, Abhilash Kesavan <kesavan.abhilash@gmail.com> wrote:
>> Hi Thomas,
>>
>> Thanks for the suggestions.
>>
>> On Tue, Nov 6, 2012 at 1:45 PM, Thomas Abraham
>> <thomas.abraham@linaro.org> wrote:
>>> On 6 November 2012 11:48, Abhilash Kesavan <a.kesavan@samsung.com> wrote:
>>>> On Exynos5 we have a new high-speed i2c controller. The interrupt
>>>> sources for the legacy and new controller are muxed and are controlled
>>>> via the SYSCON I2C_CFG register.
>>>> At reset the interrupt source is configured for the high-speed controller,
>>>> to continue using the old i2c controller we need to modify the I2C_CFG
>>>> register.
>>>
>>> If the high-speed i2c controllers are not used, can this configuration
>>> be moved into the bootloader?
>>>
>>> The other option could be, in the exynos5250_dt_machine_init()
>>> function, first check if the platform is compatible with
>>> "samsung,exynos5250" and if so search for a high-speed i2c controller
>>> compatible node. If a high-speed controller node is found and if that
>>> node is not disabled, then do not change the reset value of I2C_CFG
>>> register.
>>>
>> I'd like to try this out. Do we have to a scenario where both hs-i2c and legacy
>> i2c nodes are added to the dts file without disabling either of them or is it
>> expected that one of these will always be disabled in the board-specific
>> dts file (as only one can work at a time) ?
>
> I would expect only one of the two types of i2c controller to be
> enabled in the board dts file. I don't think there will be use case
> where we have to switch between low-speed and high-speed controllers
> at runtime.
>
> And, since there are four interrupt configuration bits in I2C_CFG,
> alias id would be required to determine which bit in the I2C_CFG
> register has be setup.
>
> Thanks,
> Thomas.
^ permalink raw reply
* [PATCH 2/4] gpio: samsung: Skip registration if pinctrl driver is present on Exynos4x12
From: Kukjin Kim @ 2012-11-07 4:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACRpkdYNDSp0K3wpvUem9ecsW-JQ9L6aKqaOmHNUR65DQTMNHA@mail.gmail.com>
Linus Walleij wrote:
>
> On Wed, Oct 24, 2012 at 4:37 PM, Tomasz Figa <t.figa@samsung.com> wrote:
>
> > This patch modifies the Samsung GPIO driver to check for pinctrl driver
> > presence earlier and use generic matching instead of a single compatible
> > value.
> >
> > This allows us to fix warning about unrecognized SoC in case of
> > Exynos4x12, which is not supported by this driver.
> >
> > Signed-off-by: Tomasz Figa <t.figa@samsung.com>
> > Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
>
> Acked-by: Linus Walleij <linus.walleij@linaro.org>
>
> Tell me if there is something you want merged through
> the GPIO or pinctrl tree. I have this Samsung branch on the
> pinctrl tree...
>
Hi Linus,
A commit 1b6056d6 ("pinctrl: samsung: Include bank-specific eint offset in
bank struct") which is in your pinctrl tree (samsung branch) changed
macro(EXYNOS_PIN_BANK_EINTG) to add offset. Eventually, this series(due to
3rd patch, pinctrl: samsung: Add support for Exynos4x12) breaks compilation
without the commit. So if you don't have a plan to rebase samsung branch of
your pinctrl tree, I'd like to merge it in my tree. Is it ok to you?
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply
* [PATCH 1/5] gpiolib: fix up function prototypes etc
From: Viresh Kumar @ 2012-11-07 5:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352214994-30232-1-git-send-email-linus.walleij@stericsson.com>
On 6 November 2012 20:46, Linus Walleij <linus.walleij@stericsson.com>wrote:
> diff --git a/include/linux/gpio.h b/include/linux/gpio.h
>
> -void gpiochip_add_pin_range(struct gpio_chip *chip, const char
> *pinctl_name,
> - unsigned int pin_base, unsigned int npins);
> -void gpiochip_remove_pin_ranges(struct gpio_chip *chip);
> -#endif
> +#ifdef CONFIG_PINCTRL
>
Shouldn't this be ifndef??
> +static inline void
> +gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,
> + unsigned int pin_base, unsigned int npins)
> +{
> +}
> +
> +static inline void
> +gpiochip_remove_pin_ranges(struct gpio_chip *chip)
> +{
> +}
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20121107/e384fe03/attachment-0001.html>
^ permalink raw reply
* [PATCH 2/5] gpiolib-of: staticize the pin range calls
From: viresh kumar @ 2012-11-07 5:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352215003-30268-1-git-send-email-linus.walleij@stericsson.com>
On 6 November 2012 20:46, Linus Walleij <linus.walleij@stericsson.com> wrote:
diff --git a/drivers/gpio/gpiolib-of.c b/drivers/gpio/gpiolib-of.c
#ifdef CONFIG_PINCTRL
-void of_gpiochip_add_pin_range(struct gpio_chip *chip)
+static void of_gpiochip_add_pin_range(struct gpio_chip *chip)
{
struct device_node *np = chip->of_node;
struct gpio_pin_range *pin_range;
@@ -254,7 +254,7 @@ void of_gpiochip_add_pin_range(struct gpio_chip *chip)
} while (index++);
}
-void of_gpiochip_remove_pin_range(struct gpio_chip *chip)
+static void of_gpiochip_remove_pin_range(struct gpio_chip *chip)
{
struct gpio_pin_range *pin_range, *tmp;
@@ -265,8 +265,8 @@ void of_gpiochip_remove_pin_range(struct gpio_chip *chip)
}
}
#else
-void of_gpiochip_add_pin_range(struct gpio_chip *chip) {}
-void of_gpiochip_remove_pin_range(struct gpio_chip *chip) {}
+static void of_gpiochip_add_pin_range(struct gpio_chip *chip) {}
+static void of_gpiochip_remove_pin_range(struct gpio_chip *chip) {}
Maybe static inline??
Reviewed-by: Viresh Kumar <viresh.kumar@linaro.org>
^ permalink raw reply
* [PATCH 3/5] gpiolib: remove duplicate pin range code
From: viresh kumar @ 2012-11-07 5:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352215014-30305-1-git-send-email-linus.walleij@stericsson.com>
On Tue, Nov 6, 2012 at 8:46 PM, Linus Walleij
<linus.walleij@stericsson.com> wrote:
> From: Linus Walleij <linus.walleij@linaro.org>
>
> Commit 69e1601bca88809dc118abd1becb02c15a02ec71
> "gpiolib: provide provision to register pin ranges"
>
> Introduced both of_gpiochip_remove_pin_range() and
> gpiochip_remove_pin_ranges(). But the contents are exactly
> the same so remove the OF one and rely on the range deletion
> in the core.
>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
I can't believe that i did this :(
Reviewed-by: Viresh Kumar <viresh.kumar@linaro.org>
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox