* [PATCH v4 1/9] ARM: mmp: select pinctrl driver
From: Tony Lindgren @ 2012-11-08 1:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352301582-12244-2-git-send-email-haojian.zhuang@gmail.com>
* Haojian Zhuang <haojian.zhuang@gmail.com> [121107 07:21]:
> Pinctrl driver is necessary for MMP DT & MMP2 DT platforms.
>
> Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
> Acked-by: Linus Walleij <linus.walleij@linaro.org>
> ---
> arch/arm/mach-mmp/Kconfig | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig
> index 178d4da..ebdda83 100644
> --- a/arch/arm/mach-mmp/Kconfig
> +++ b/arch/arm/mach-mmp/Kconfig
> @@ -89,6 +89,8 @@ config MACH_MMP_DT
> select CPU_PXA168
> select CPU_PXA910
> select USE_OF
> + select PINCTRL
> + select PINCTRL_SINGLE
> help
> Include support for Marvell MMP2 based platforms using
> the device tree. Needn't select any other machine while
> @@ -99,6 +101,8 @@ config MACH_MMP2_DT
> depends on !CPU_MOHAWK
> select CPU_MMP2
> select USE_OF
> + select PINCTRL
> + select PINCTRL_SINGLE
> help
> Include support for Marvell MMP2 based platforms using
> the device tree.
I don't think you want to select PINCTRL_SINGLE here, you may want
to have it built as a module too in some cases.
Regards,
Tony
^ permalink raw reply
* [PATCH v4 5/9] document: devicetree: bind pinconf with pin-single
From: Tony Lindgren @ 2012-11-08 1:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352301582-12244-6-git-send-email-haojian.zhuang@gmail.com>
Hi,
* Haojian Zhuang <haojian.zhuang@gmail.com> [121107 07:22]:
> --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
> +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
> @@ -14,9 +16,33 @@ Optional properties:
> - pinctrl-single,function-off : function off mode for disabled state if
> available and same for all registers; if not specified, disabling of
> pin functions is ignored
> +
> - pinctrl-single,bit-per-mux : boolean to indicate that one register controls
> more than one pin
>
> +- pinctrl-single,power-source-mask : mask of setting power source in
> + the pinmux register
My non-native english suggests:
- pinctrl-single,power-source-mask : mask for setting the power source in
the pinmux register
> +- pinctrl-single,power-source : value of setting power source field
> + in the pinmux register
- pinctrl-single,power-source : value for setting the power source field
in the pinmux register
> +- pinctrl-single,bias-mask : mask of setting bias value in the pinmux
> + register
> +
> +- pinctrl-single,bias-disable : value of disabling bias in the pinmux
> + register
> +
> +- pinctrl-single,bias-pull-down : value of setting bias pull down in
> + the pinmux register
> +
> +- pinctrl-single,bias-pull-up : value of setting bias pull up in the
> + pinmux register
> +
> +- pinctrl-single,bias : value of setting bias in the pinmux register
> +
> +- pinctrl-single,input-schmitt-mask : mask of setting input schmitt
> + in the pinmux register
And the same for the rest.
> @@ -42,6 +68,25 @@ Where 0xdc is the offset from the pinctrl register base address for the
> device pinctrl register, 0x18 is the desired value, and 0xff is the sub mask to
> be used when applying this change to the register.
>
> +
> +Optional sub-node: In case some pins could be configured as GPIO in the pinmux
> +register. If both GPIO nubmer and pin base of those pins are in ascending order,
> +those pins could be defined as a GPIO range. The sub-node should be defined in
> +.dtsi files of those silicons.
I suggest you update the above to say:
Optional sub-node: In case some pins can be configured as GPIO in the pinmux
register. If both the GPIO number and pin base of those pins are in ascending
order, these pins can be defined as a GPIO range.
Then maybe clarify the sub-node part a bit, or just leave it out? Actually the
"ascending order" part is a bit unclear to me too..
Regards,
Tony
^ permalink raw reply
* [PATCH] ARM: SAMSUNG: Fix typo in definition of VIDCON1_VSTATUS_FRONTPORCH value
From: Jingoo Han @ 2012-11-08 1:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1429686.vBaRDnu5Be@amdc1227>
On Wednesday, November 07, 2012 9:31 PM Jingoo Han wrote
>
> The correct value for VIDCON1_VSTATUS_FRONTPORCH is 3, not 0.
>
> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
According to the datasheet, 3 is right value.
Acked-by: Jingoo Han <jg1.han@samsung.com>
> ---
> include/video/samsung_fimd.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/include/video/samsung_fimd.h b/include/video/samsung_fimd.h
> index 7ae6c07..263ed4b 100644
> --- a/include/video/samsung_fimd.h
> +++ b/include/video/samsung_fimd.h
> @@ -82,7 +82,7 @@
> #define VIDCON1_VSTATUS_VSYNC (0x0 << 13)
> #define VIDCON1_VSTATUS_BACKPORCH (0x1 << 13)
> #define VIDCON1_VSTATUS_ACTIVE (0x2 << 13)
> -#define VIDCON1_VSTATUS_FRONTPORCH (0x0 << 13)
> +#define VIDCON1_VSTATUS_FRONTPORCH (0x3 << 13)
> #define VIDCON1_VCLK_MASK (0x3 << 9)
> #define VIDCON1_VCLK_HOLD (0x0 << 9)
> #define VIDCON1_VCLK_RUN (0x1 << 9)
> --
> 1.8.0
>
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* [PATCH v2 00/26] Move OMAP2+ over to common clk framework
From: Mike Turquette @ 2012-11-08 1:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352337181-29427-1-git-send-email-mturquette@ti.com>
Doh, I got the LAKML address wrong...
Thankfully it's already up on some archives:
http://article.gmane.org/gmane.linux.ports.arm.omap/88824
For anyone interested in testing:
git://git.linaro.org/people/mturquette/linux.git clk-omap-3.8
Regards,
Mike
Quoting Mike Turquette (2012-11-07 17:12:35)
> From: Mike Turquette <mturquette@linaro.org>
>
> Hi all,
>
> This series is based on top of Paul's PRM/CM clean-up work. It is a
> refresh of the patches Rajendra sent out a while back[1], with the
> addition of several fixes for PM regressions[2] across several
> platforms.
>
> I have tested on OMAP4430 Panda including PRCM diffing against pre-CCF
> patches (delta is zero) and also suspend/resume.
>
> I also tested on OMAP4460 Panda-ES. Boot is fine and PRCM programming
> appears sane. However Panda-ES never comes back from suspend/resume.
> This problem exists on the PRM/CM branch I based on and was not
> introduced by this series. I am investigating that independently of
> this series.
>
> Anyone wanting to pull the work can find it at:
> git://git.linaro.org/people/mturquette/linux.git clk-omap-3.8
>
> [1] http://article.gmane.org/gmane.linux.ports.arm.omap/78771
> [2] http://article.gmane.org/gmane.linux.ports.arm.omap/84015
>
> Mike Turquette (3):
> ARM: OMAP4: clock: Convert to common clk
> ARM: OMAP2+: clock: remove unnecessary declarations
> ARM: OMAP2+: clock: Cleanup !CONFIG_COMMON_CLK parts
>
> Paul Walmsley (7):
> ARM: OMAP2xxx: clock: add APLL rate recalculation functions
> ARM: OMAP2+: clock: add OMAP CCF convenience macros to
> mach-omap2/clock.h
> ARM: AM33XX: clock: add clock data in common clock format
> ARM: OMAP44xx: clock: drop obsolete clock data
> ARM: OMAP3xxx: clk: drop obsolete clock data
> ARM: AM33xx: clock: drop obsolete clock data
> ARM: OMAP2xxx: clock: drop obsolete clock data
>
> Rajendra Nayak (15):
> ARM: OMAP: clock: Nuke plat/clock.c & reuse struct clk as clk_hw_omap
> ARM: OMAP: hwmod: Fix up hwmod based clkdm accesses
> ARM: OMAP3: clock: Convert to common clk
> ARM: OMAP2: clock: Convert to common clk
> ARM: OMAP: clock: list all clk_hw_omap clks to enable/disable
> autoidle
> ARM: OMAP: clock: Define a function to enable clocks at init
> ARM: OMAP: clock: Get rid of some clkdm assocations within clks
> ARM: OMAP4: clock: Add 44xx data using common struct clk
> ARM: OMAP3: clock: Add 3xxx data using common struct clk
> ARM: omap2: clock: Add 24xx data using common struct clk
> ARM: OMAP: clock: Switch to COMMON clk
> ARM: OMAP: hwmod: Cleanup !CONFIG_COMMON_CLK parts
> ARM: OMAP4: clock: Cleanup !CONFIG_COMMON_CLK parts
> ARM: omap3: clock: Cleanup !CONFIG_COMMON_CLK parts
> ARM: omap2: clock: Cleanup !CONFIG_COMMON_CLK parts
>
> Vaibhav Hiremath (1):
> ARM: OMAP2+: hwmod: Invoke init_clkdm before other init functions
>
> arch/arm/mach-omap2/Kconfig | 5 +
> arch/arm/mach-omap2/Makefile | 10 +-
> arch/arm/mach-omap2/cclock2420_data.c | 1959 ++++++++++++++
> arch/arm/mach-omap2/cclock2430_data.c | 2073 +++++++++++++++
> arch/arm/mach-omap2/cclock33xx_data.c | 961 +++++++
> arch/arm/mach-omap2/cclock3xxx_data.c | 3595 +++++++++++++++++++++++++
> arch/arm/mach-omap2/cclock44xx_data.c | 1991 ++++++++++++++
> arch/arm/mach-omap2/clkt2xxx_apll.c | 66 +-
> arch/arm/mach-omap2/clkt2xxx_dpll.c | 8 +-
> arch/arm/mach-omap2/clkt2xxx_dpllcore.c | 12 +-
> arch/arm/mach-omap2/clkt2xxx_osc.c | 13 +-
> arch/arm/mach-omap2/clkt2xxx_sys.c | 7 +-
> arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c | 11 +-
> arch/arm/mach-omap2/clkt34xx_dpll3m2.c | 8 +-
> arch/arm/mach-omap2/clkt_clksel.c | 194 +-
> arch/arm/mach-omap2/clkt_dpll.c | 28 +-
> arch/arm/mach-omap2/clkt_iclk.c | 31 +-
> arch/arm/mach-omap2/clock.c | 845 ++----
> arch/arm/mach-omap2/clock.h | 356 ++-
> arch/arm/mach-omap2/clock2420_data.c | 1986 --------------
> arch/arm/mach-omap2/clock2430.c | 8 +-
> arch/arm/mach-omap2/clock2430_data.c | 2085 ---------------
> arch/arm/mach-omap2/clock2xxx.c | 1 +
> arch/arm/mach-omap2/clock2xxx.h | 47 +-
> arch/arm/mach-omap2/clock33xx_data.c | 1107 --------
> arch/arm/mach-omap2/clock34xx.c | 51 +-
> arch/arm/mach-omap2/clock3517.c | 24 +-
> arch/arm/mach-omap2/clock36xx.c | 22 +-
> arch/arm/mach-omap2/clock36xx.h | 2 +-
> arch/arm/mach-omap2/clock3xxx.c | 6 +-
> arch/arm/mach-omap2/clock3xxx.h | 6 +-
> arch/arm/mach-omap2/clock3xxx_data.c | 3613 --------------------------
> arch/arm/mach-omap2/clock44xx_data.c | 3398 ------------------------
> arch/arm/mach-omap2/clock_common_data.c | 22 +-
> arch/arm/mach-omap2/cm-regbits-24xx.h | 5 +
> arch/arm/mach-omap2/cm-regbits-34xx.h | 31 +
> arch/arm/mach-omap2/cm2xxx_3xxx.h | 1 +
> arch/arm/mach-omap2/dpll3xxx.c | 226 +-
> arch/arm/mach-omap2/dpll44xx.c | 21 +-
> arch/arm/mach-omap2/io.c | 25 +
> arch/arm/mach-omap2/omap_hwmod.c | 63 +-
> arch/arm/mach-omap2/pm24xx.c | 4 +-
> arch/arm/mach-omap2/prm-regbits-24xx.h | 2 +
> arch/arm/mach-omap2/prm-regbits-34xx.h | 1 +
> arch/arm/mach-omap2/prm2xxx_3xxx.h | 1 +
> arch/arm/mach-omap2/scrm44xx.h | 2 +
> 46 files changed, 11539 insertions(+), 13394 deletions(-)
> create mode 100644 arch/arm/mach-omap2/cclock2420_data.c
> create mode 100644 arch/arm/mach-omap2/cclock2430_data.c
> create mode 100644 arch/arm/mach-omap2/cclock33xx_data.c
> create mode 100644 arch/arm/mach-omap2/cclock3xxx_data.c
> create mode 100644 arch/arm/mach-omap2/cclock44xx_data.c
> delete mode 100644 arch/arm/mach-omap2/clock2420_data.c
> delete mode 100644 arch/arm/mach-omap2/clock2430_data.c
> delete mode 100644 arch/arm/mach-omap2/clock33xx_data.c
> delete mode 100644 arch/arm/mach-omap2/clock3xxx_data.c
> delete mode 100644 arch/arm/mach-omap2/clock44xx_data.c
>
> --
> 1.7.9.5
^ permalink raw reply
* [PATCH net-next 2/2] ARM: net: bpf_jit_32: add VLAN instructions for BPF JIT
From: Daniel Borkmann @ 2012-11-08 1:31 UTC (permalink / raw)
To: linux-arm-kernel
This patch is a follow-up for patch "net: filter: add vlan tag access"
to support the new VLAN_TAG/VLAN_TAG_PRESENT accessors in BPF JIT.
Signed-off-by: Daniel Borkmann <daniel.borkmann@tik.ee.ethz.ch>
Cc: Mircea Gherzan <mgherzan@gmail.com>
Cc: Arnd Bergmann <arnd@arndb.de>
---
arch/arm/net/bpf_jit_32.c | 14 ++++++++++++++
1 files changed, 14 insertions(+), 0 deletions(-)
diff --git a/arch/arm/net/bpf_jit_32.c b/arch/arm/net/bpf_jit_32.c
index 8be702d..9af9a69 100644
--- a/arch/arm/net/bpf_jit_32.c
+++ b/arch/arm/net/bpf_jit_32.c
@@ -16,6 +16,7 @@
#include <linux/netdevice.h>
#include <linux/string.h>
#include <linux/slab.h>
+#include <linux/if_vlan.h>
#include <asm/cacheflush.h>
#include <asm/hwcap.h>
@@ -168,6 +169,8 @@ static inline bool is_load_to_a(u16 inst)
case BPF_S_ANC_MARK:
case BPF_S_ANC_PROTOCOL:
case BPF_S_ANC_RXHASH:
+ case BPF_S_ANC_VLAN_TAG:
+ case BPF_S_ANC_VLAN_TAG_PRESENT:
case BPF_S_ANC_QUEUE:
return true;
default:
@@ -815,6 +818,17 @@ b_epilogue:
off = offsetof(struct sk_buff, rxhash);
emit(ARM_LDR_I(r_A, r_skb, off), ctx);
break;
+ case BPF_S_ANC_VLAN_TAG:
+ case BPF_S_ANC_VLAN_TAG_PRESENT:
+ ctx->seen |= SEEN_SKB;
+ BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, vlan_tci) != 2);
+ off = offsetof(struct sk_buff, vlan_tci);
+ emit(ARM_LDRH_I(r_A, r_skb, off), ctx);
+ if (inst->code == BPF_S_ANC_VLAN_TAG)
+ OP_IMM3(ARM_AND, r_A, r_A, VLAN_VID_MASK, ctx);
+ else
+ OP_IMM3(ARM_AND, r_A, r_A, VLAN_TAG_PRESENT, ctx);
+ break;
case BPF_S_ANC_QUEUE:
ctx->seen |= SEEN_SKB;
BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff,
^ permalink raw reply related
* [PATCH net-next 1/2] ARM: net: bpf_jit_32: add XOR instruction for BPF JIT
From: Daniel Borkmann @ 2012-11-08 1:28 UTC (permalink / raw)
To: linux-arm-kernel
This patch is a follow-up for patch "filter: add XOR instruction for use
with X/K" that implements BPF ARM JIT parts for the BPF XOR operation.
Signed-off-by: Daniel Borkmann <daniel.borkmann@tik.ee.ethz.ch>
Cc: Mircea Gherzan <mgherzan@gmail.com>
Cc: Arnd Bergmann <arnd@arndb.de>
---
arch/arm/net/bpf_jit_32.c | 15 ++++++++++-----
arch/arm/net/bpf_jit_32.h | 2 ++
2 files changed, 12 insertions(+), 5 deletions(-)
diff --git a/arch/arm/net/bpf_jit_32.c b/arch/arm/net/bpf_jit_32.c
index c641fb6..8be702d 100644
--- a/arch/arm/net/bpf_jit_32.c
+++ b/arch/arm/net/bpf_jit_32.c
@@ -646,6 +646,16 @@ load_ind:
update_on_xread(ctx);
emit(ARM_ORR_R(r_A, r_A, r_X), ctx);
break;
+ case BPF_S_ALU_XOR_K:
+ /* A ^= K; */
+ OP_IMM3(ARM_EOR, r_A, r_A, k, ctx);
+ break;
+ case BPF_S_ANC_ALU_XOR_X:
+ case BPF_S_ALU_XOR_X:
+ /* A ^= X */
+ update_on_xread(ctx);
+ emit(ARM_EOR_R(r_A, r_A, r_X), ctx);
+ break;
case BPF_S_ALU_AND_K:
/* A &= K */
OP_IMM3(ARM_AND, r_A, r_A, k, ctx);
@@ -762,11 +772,6 @@ b_epilogue:
update_on_xread(ctx);
emit(ARM_MOV_R(r_A, r_X), ctx);
break;
- case BPF_S_ANC_ALU_XOR_X:
- /* A ^= X */
- update_on_xread(ctx);
- emit(ARM_EOR_R(r_A, r_A, r_X), ctx);
- break;
case BPF_S_ANC_PROTOCOL:
/* A = ntohs(skb->protocol) */
ctx->seen |= SEEN_SKB;
diff --git a/arch/arm/net/bpf_jit_32.h b/arch/arm/net/bpf_jit_32.h
index 7fa2f7d..afb8462 100644
--- a/arch/arm/net/bpf_jit_32.h
+++ b/arch/arm/net/bpf_jit_32.h
@@ -69,6 +69,7 @@
#define ARM_INST_CMP_I 0x03500000
#define ARM_INST_EOR_R 0x00200000
+#define ARM_INST_EOR_I 0x02200000
#define ARM_INST_LDRB_I 0x05d00000
#define ARM_INST_LDRB_R 0x07d00000
@@ -135,6 +136,7 @@
#define ARM_CMP_I(rn, imm) _AL3_I(ARM_INST_CMP, 0, rn, imm)
#define ARM_EOR_R(rd, rn, rm) _AL3_R(ARM_INST_EOR, rd, rn, rm)
+#define ARM_EOR_I(rd, rn, imm) _AL3_I(ARM_INST_EOR, rd, rn, imm)
#define ARM_LDR_I(rt, rn, off) (ARM_INST_LDR_I | (rt) << 12 | (rn) << 16 \
| (off))
^ permalink raw reply related
* [PATCH 7/7] ARM: shmobile: r8a7740: add FSI-DVI clocks
From: Simon Horman @ 2012-11-08 1:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352338056-21107-1-git-send-email-horms@verge.net.au>
From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms@verge.net.au>
---
arch/arm/mach-shmobile/clock-r8a7740.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
index 6729e00..71ee224 100644
--- a/arch/arm/mach-shmobile/clock-r8a7740.c
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -65,6 +65,9 @@
#define SMSTPCR3 IOMEM(0xe615013c)
#define SMSTPCR4 IOMEM(0xe6150140)
+#define FSIDIVA IOMEM(0xFE1F8000)
+#define FSIDIVB IOMEM(0xFE1F8008)
+
/* Fixed 32 KHz root clock from EXTALR pin */
static struct clk extalr_clk = {
.rate = 32768,
@@ -427,6 +430,14 @@ static struct clk *late_main_clks[] = {
&hdmi2_clk,
};
+/* FSI DIV */
+enum { FSIDIV_A, FSIDIV_B, FSIDIV_REPARENT_NR };
+
+static struct clk fsidivs[] = {
+ [FSIDIV_A] = SH_CLK_FSIDIV(FSIDIVA, &div6_reparent_clks[DIV6_FSIA]),
+ [FSIDIV_B] = SH_CLK_FSIDIV(FSIDIVB, &div6_reparent_clks[DIV6_FSIB]),
+};
+
/* MSTP */
enum {
DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_HP,
@@ -596,6 +607,8 @@ static struct clk_lookup lookups[] = {
CLKDEV_ICK_ID("icka", "sh_fsi2", &div6_reparent_clks[DIV6_FSIA]),
CLKDEV_ICK_ID("ickb", "sh_fsi2", &div6_reparent_clks[DIV6_FSIB]),
+ CLKDEV_ICK_ID("diva", "sh_fsi2", &fsidivs[FSIDIV_A]),
+ CLKDEV_ICK_ID("divb", "sh_fsi2", &fsidivs[FSIDIV_B]),
};
void __init r8a7740_clock_init(u8 md_ck)
@@ -641,6 +654,9 @@ void __init r8a7740_clock_init(u8 md_ck)
for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)
ret = clk_register(late_main_clks[k]);
+ if (!ret)
+ ret = sh_clk_fsidiv_register(fsidivs, FSIDIV_REPARENT_NR);
+
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
if (!ret)
--
1.7.10.4
^ permalink raw reply related
* [PATCH 6/7] ARM: shmobile: sh7372: use sh_clk_fsidiv_register() for FSI-DIV clocks
From: Simon Horman @ 2012-11-08 1:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352338056-21107-1-git-send-email-horms@verge.net.au>
From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Now, sh7372 can use sh_clk_fsidiv_register() for FSI-DIV clocks.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms@verge.net.au>
---
arch/arm/mach-shmobile/clock-sh7372.c | 94 ++++-----------------------------
1 file changed, 10 insertions(+), 84 deletions(-)
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
index 18dcff7..bee2d05 100644
--- a/arch/arm/mach-shmobile/clock-sh7372.c
+++ b/arch/arm/mach-shmobile/clock-sh7372.c
@@ -420,87 +420,11 @@ static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
};
/* FSI DIV */
-static unsigned long fsidiv_recalc(struct clk *clk)
-{
- unsigned long value;
-
- value = __raw_readl(clk->mapping->base);
-
- value >>= 16;
- if (value < 2)
- return 0;
-
- return clk->parent->rate / value;
-}
-
-static long fsidiv_round_rate(struct clk *clk, unsigned long rate)
-{
- return clk_rate_div_range_round(clk, 2, 0xffff, rate);
-}
-
-static void fsidiv_disable(struct clk *clk)
-{
- __raw_writel(0, clk->mapping->base);
-}
-
-static int fsidiv_enable(struct clk *clk)
-{
- unsigned long value;
-
- value = __raw_readl(clk->mapping->base) >> 16;
- if (value < 2)
- return -EIO;
-
- __raw_writel((value << 16) | 0x3, clk->mapping->base);
-
- return 0;
-}
+enum { FSIDIV_A, FSIDIV_B, FSIDIV_REPARENT_NR };
-static int fsidiv_set_rate(struct clk *clk, unsigned long rate)
-{
- int idx;
-
- idx = (clk->parent->rate / rate) & 0xffff;
- if (idx < 2)
- return -EINVAL;
-
- __raw_writel(idx << 16, clk->mapping->base);
- return 0;
-}
-
-static struct sh_clk_ops fsidiv_clk_ops = {
- .recalc = fsidiv_recalc,
- .round_rate = fsidiv_round_rate,
- .set_rate = fsidiv_set_rate,
- .enable = fsidiv_enable,
- .disable = fsidiv_disable,
-};
-
-static struct clk_mapping fsidiva_clk_mapping = {
- .phys = FSIDIVA,
- .len = 8,
-};
-
-static struct clk fsidiva_clk = {
- .ops = &fsidiv_clk_ops,
- .parent = &div6_reparent_clks[DIV6_FSIA], /* late install */
- .mapping = &fsidiva_clk_mapping,
-};
-
-static struct clk_mapping fsidivb_clk_mapping = {
- .phys = FSIDIVB,
- .len = 8,
-};
-
-static struct clk fsidivb_clk = {
- .ops = &fsidiv_clk_ops,
- .parent = &div6_reparent_clks[DIV6_FSIB], /* late install */
- .mapping = &fsidivb_clk_mapping,
-};
-
-static struct clk *late_main_clks[] = {
- &fsidiva_clk,
- &fsidivb_clk,
+static struct clk fsidivs[] = {
+ [FSIDIV_A] = SH_CLK_FSIDIV(FSIDIVA, &div6_reparent_clks[DIV6_FSIA]),
+ [FSIDIV_B] = SH_CLK_FSIDIV(FSIDIVB, &div6_reparent_clks[DIV6_FSIB]),
};
enum { MSTP001, MSTP000,
@@ -583,8 +507,8 @@ static struct clk_lookup lookups[] = {
CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
CLKDEV_CON_ID("pllc2_clk", &sh7372_pllc2_clk),
- CLKDEV_CON_ID("fsidiva", &fsidiva_clk),
- CLKDEV_CON_ID("fsidivb", &fsidivb_clk),
+ CLKDEV_CON_ID("fsidiva", &fsidivs[FSIDIV_A]),
+ CLKDEV_CON_ID("fsidivb", &fsidivs[FSIDIV_B]),
/* DIV4 clocks */
CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
@@ -680,6 +604,8 @@ static struct clk_lookup lookups[] = {
CLKDEV_ICK_ID("icka", "sh_fsi2", &div6_reparent_clks[DIV6_FSIA]),
CLKDEV_ICK_ID("ickb", "sh_fsi2", &div6_reparent_clks[DIV6_FSIB]),
CLKDEV_ICK_ID("spu2", "sh_fsi2", &mstp_clks[MSTP223]),
+ CLKDEV_ICK_ID("diva", "sh_fsi2", &fsidivs[FSIDIV_A]),
+ CLKDEV_ICK_ID("divb", "sh_fsi2", &fsidivs[FSIDIV_B]),
};
void __init sh7372_clock_init(void)
@@ -708,8 +634,8 @@ void __init sh7372_clock_init(void)
if (!ret)
ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
- for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)
- ret = clk_register(late_main_clks[k]);
+ if (!ret)
+ ret = sh_clk_fsidiv_register(fsidivs, FSIDIV_REPARENT_NR);
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
--
1.7.10.4
^ permalink raw reply related
* [PATCH 5/7] ARM: shmobile: sh7372: sh7372_fsidivX_clk become non-global
From: Simon Horman @ 2012-11-08 1:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352338056-21107-1-git-send-email-horms@verge.net.au>
From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Not only sh7372 but also many Renesas chip has FSI-DIV clock,
and we can share its sh_clk_ops.
To support common FSI-DIV clock, sh7372_fsidivX_clk
becomes non-global by this patch.
This is preparation for FSI DT support.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms@verge.net.au>
---
arch/arm/mach-shmobile/board-ap4evb.c | 2 +-
arch/arm/mach-shmobile/board-mackerel.c | 2 +-
arch/arm/mach-shmobile/clock-sh7372.c | 10 ++++++----
arch/arm/mach-shmobile/include/mach/sh7372.h | 2 --
4 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index 790dc68..cefdd03 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -728,7 +728,7 @@ fsia_ick_out:
static int fsi_hdmi_set_rate(struct device *dev, int rate, int enable)
{
struct clk *fsib_clk;
- struct clk *fdiv_clk = &sh7372_fsidivb_clk;
+ struct clk *fdiv_clk = clk_get(NULL, "fsidivb");
long fsib_rate = 0;
long fdiv_rate = 0;
int ackmd_bpfmd;
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index 39b8f2e..f274252 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -882,7 +882,7 @@ static int __fsi_set_round_rate(struct clk *clk, long rate, int enable)
static int fsi_b_set_rate(struct device *dev, int rate, int enable)
{
struct clk *fsib_clk;
- struct clk *fdiv_clk = &sh7372_fsidivb_clk;
+ struct clk *fdiv_clk = clk_get(NULL, "fsidivb");
long fsib_rate = 0;
long fdiv_rate = 0;
int ackmd_bpfmd;
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
index 430a90f..18dcff7 100644
--- a/arch/arm/mach-shmobile/clock-sh7372.c
+++ b/arch/arm/mach-shmobile/clock-sh7372.c
@@ -481,7 +481,7 @@ static struct clk_mapping fsidiva_clk_mapping = {
.len = 8,
};
-struct clk sh7372_fsidiva_clk = {
+static struct clk fsidiva_clk = {
.ops = &fsidiv_clk_ops,
.parent = &div6_reparent_clks[DIV6_FSIA], /* late install */
.mapping = &fsidiva_clk_mapping,
@@ -492,15 +492,15 @@ static struct clk_mapping fsidivb_clk_mapping = {
.len = 8,
};
-struct clk sh7372_fsidivb_clk = {
+static struct clk fsidivb_clk = {
.ops = &fsidiv_clk_ops,
.parent = &div6_reparent_clks[DIV6_FSIB], /* late install */
.mapping = &fsidivb_clk_mapping,
};
static struct clk *late_main_clks[] = {
- &sh7372_fsidiva_clk,
- &sh7372_fsidivb_clk,
+ &fsidiva_clk,
+ &fsidivb_clk,
};
enum { MSTP001, MSTP000,
@@ -583,6 +583,8 @@ static struct clk_lookup lookups[] = {
CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
CLKDEV_CON_ID("pllc2_clk", &sh7372_pllc2_clk),
+ CLKDEV_CON_ID("fsidiva", &fsidiva_clk),
+ CLKDEV_CON_ID("fsidivb", &fsidivb_clk),
/* DIV4 clocks */
CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h
index eb98b45..bf93a86 100644
--- a/arch/arm/mach-shmobile/include/mach/sh7372.h
+++ b/arch/arm/mach-shmobile/include/mach/sh7372.h
@@ -475,8 +475,6 @@ extern struct clk sh7372_dv_clki_div2_clk;
extern struct clk sh7372_pllc2_clk;
extern struct clk sh7372_fsiack_clk;
extern struct clk sh7372_fsibck_clk;
-extern struct clk sh7372_fsidiva_clk;
-extern struct clk sh7372_fsidivb_clk;
extern void sh7372_intcs_suspend(void);
extern void sh7372_intcs_resume(void);
--
1.7.10.4
^ permalink raw reply related
* [PATCH 4/7] sh: clkfwk: add sh_clk_fsidiv_register()
From: Simon Horman @ 2012-11-08 1:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352338056-21107-1-git-send-email-horms@verge.net.au>
From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
This patch adds sh_clk_fsidiv_register() to share FSI-DIV clock code
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms@verge.net.au>
---
drivers/sh/clk/cpg.c | 86 ++++++++++++++++++++++++++++++++++++++++++++++++
include/linux/sh_clk.h | 9 +++++
2 files changed, 95 insertions(+)
diff --git a/drivers/sh/clk/cpg.c b/drivers/sh/clk/cpg.c
index 07e9fb4..b3dc441 100644
--- a/drivers/sh/clk/cpg.c
+++ b/drivers/sh/clk/cpg.c
@@ -361,3 +361,89 @@ int __init sh_clk_div4_reparent_register(struct clk *clks, int nr,
return sh_clk_div_register_ops(clks, nr, table,
&sh_clk_div4_reparent_clk_ops);
}
+
+/* FSI-DIV */
+static unsigned long fsidiv_recalc(struct clk *clk)
+{
+ u32 value;
+
+ value = __raw_readl(clk->mapping->base);
+
+ value >>= 16;
+ if (value < 2)
+ return clk->parent->rate;
+
+ return clk->parent->rate / value;
+}
+
+static long fsidiv_round_rate(struct clk *clk, unsigned long rate)
+{
+ return clk_rate_div_range_round(clk, 1, 0xffff, rate);
+}
+
+static void fsidiv_disable(struct clk *clk)
+{
+ __raw_writel(0, clk->mapping->base);
+}
+
+static int fsidiv_enable(struct clk *clk)
+{
+ u32 value;
+
+ value = __raw_readl(clk->mapping->base) >> 16;
+ if (value < 2)
+ return 0;
+
+ __raw_writel((value << 16) | 0x3, clk->mapping->base);
+
+ return 0;
+}
+
+static int fsidiv_set_rate(struct clk *clk, unsigned long rate)
+{
+ u32 val;
+ int idx;
+
+ idx = (clk->parent->rate / rate) & 0xffff;
+ if (idx < 2)
+ __raw_writel(0, clk->mapping->base);
+ else
+ __raw_writel(idx << 16, clk->mapping->base);
+
+ return 0;
+}
+
+static struct sh_clk_ops fsidiv_clk_ops = {
+ .recalc = fsidiv_recalc,
+ .round_rate = fsidiv_round_rate,
+ .set_rate = fsidiv_set_rate,
+ .enable = fsidiv_enable,
+ .disable = fsidiv_disable,
+};
+
+int __init sh_clk_fsidiv_register(struct clk *clks, int nr)
+{
+ struct clk_mapping *map;
+ int i;
+
+ for (i = 0; i < nr; i++) {
+
+ map = kzalloc(sizeof(struct clk_mapping), GFP_KERNEL);
+ if (!map) {
+ pr_err("%s: unable to alloc memory\n", __func__);
+ return -ENOMEM;
+ }
+
+ /* clks[i].enable_reg came from SH_CLK_FSIDIV() */
+ map->phys = (phys_addr_t)clks[i].enable_reg;
+ map->len = 8;
+
+ clks[i].enable_reg = 0; /* remove .enable_reg */
+ clks[i].ops = &fsidiv_clk_ops;
+ clks[i].mapping = map;
+
+ clk_register(&clks[i]);
+ }
+
+ return 0;
+}
diff --git a/include/linux/sh_clk.h b/include/linux/sh_clk.h
index 5091091..60c7239 100644
--- a/include/linux/sh_clk.h
+++ b/include/linux/sh_clk.h
@@ -199,4 +199,13 @@ int sh_clk_div6_reparent_register(struct clk *clks, int nr);
#define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
#define CLKDEV_ICK_ID(_cid, _did, _clk) { .con_id = _cid, .dev_id = _did, .clk = _clk }
+/* .enable_reg will be updated to .mapping on sh_clk_fsidiv_register() */
+#define SH_CLK_FSIDIV(_reg, _parent) \
+{ \
+ .enable_reg = (void __iomem *)_reg, \
+ .parent = _parent, \
+}
+
+int sh_clk_fsidiv_register(struct clk *clks, int nr);
+
#endif /* __SH_CLOCK_H */
--
1.7.10.4
^ permalink raw reply related
* [PATCH 3/7] ARM: shmobile: marzen: add USB OHCI driver support
From: Simon Horman @ 2012-11-08 1:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352338056-21107-1-git-send-email-horms@verge.net.au>
From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
This patch supports CN21/CN22 USB 1.x (port 0/1/2),
and enable input event on defconfig
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms@verge.net.au>
---
arch/arm/configs/marzen_defconfig | 5 +--
arch/arm/mach-shmobile/Kconfig | 1 +
arch/arm/mach-shmobile/board-marzen.c | 57 +++++++++++++++++++++++++++++++++
3 files changed, 61 insertions(+), 2 deletions(-)
diff --git a/arch/arm/configs/marzen_defconfig b/arch/arm/configs/marzen_defconfig
index 6540dfb..728a43c 100644
--- a/arch/arm/configs/marzen_defconfig
+++ b/arch/arm/configs/marzen_defconfig
@@ -61,9 +61,8 @@ CONFIG_SMSC911X=y
# CONFIG_NET_VENDOR_STMICRO is not set
# CONFIG_WLAN is not set
# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_KEYBOARD is not set
+CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
# CONFIG_VT is not set
# CONFIG_LEGACY_PTYS is not set
# CONFIG_DEVKMEM is not set
@@ -86,6 +85,8 @@ CONFIG_MMC=y
CONFIG_MMC_SDHI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
CONFIG_USB_EHCI_HCD_PLATFORM=y
CONFIG_USB_STORAGE=y
CONFIG_UIO=y
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index c03aeec..64db252 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -42,6 +42,7 @@ config ARCH_R8A7779
select CPU_V7
select SH_CLK_CPG
select USB_ARCH_HAS_EHCI
+ select USB_ARCH_HAS_OHCI
config ARCH_EMEV2
bool "Emma Mobile EV2"
diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
index 707b3bd..449f928 100644
--- a/arch/arm/mach-shmobile/board-marzen.c
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -36,6 +36,7 @@
#include <linux/mfd/tmio.h>
#include <linux/usb/otg.h>
#include <linux/usb/ehci_pdriver.h>
+#include <linux/usb/ohci_pdriver.h>
#include <linux/pm_runtime.h>
#include <mach/hardware.h>
#include <mach/r8a7779.h>
@@ -255,9 +256,65 @@ static struct platform_device ehci1_device = {
.resource = ehci1_resources,
};
+static struct usb_ohci_pdata ohcix_pdata = {
+ .power_on = usb_power_on,
+ .power_off = usb_power_off,
+ .power_suspend = usb_power_off,
+};
+
+static struct resource ohci0_resources[] = {
+ [0] = {
+ .start = 0xffe70400,
+ .end = 0xffe70800 - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = gic_spi(44),
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device ohci0_device = {
+ .name = "ohci-platform",
+ .id = 0,
+ .dev = {
+ .dma_mask = &ohci0_device.dev.coherent_dma_mask,
+ .coherent_dma_mask = 0xffffffff,
+ .platform_data = &ohcix_pdata,
+ },
+ .num_resources = ARRAY_SIZE(ohci0_resources),
+ .resource = ohci0_resources,
+};
+
+static struct resource ohci1_resources[] = {
+ [0] = {
+ .start = 0xfff70400,
+ .end = 0xfff70800 - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = gic_spi(45),
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device ohci1_device = {
+ .name = "ohci-platform",
+ .id = 1,
+ .dev = {
+ .dma_mask = &ohci1_device.dev.coherent_dma_mask,
+ .coherent_dma_mask = 0xffffffff,
+ .platform_data = &ohcix_pdata,
+ },
+ .num_resources = ARRAY_SIZE(ohci1_resources),
+ .resource = ohci1_resources,
+};
+
static struct platform_device *marzen_late_devices[] __initdata = {
&ehci0_device,
&ehci1_device,
+ &ohci0_device,
+ &ohci1_device,
};
void __init marzen_init_late(void)
--
1.7.10.4
^ permalink raw reply related
* [PATCH 2/7] ARM: shmobile: marzen: add USB EHCI driver support
From: Simon Horman @ 2012-11-08 1:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352338056-21107-1-git-send-email-horms@verge.net.au>
From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
This patch supports CN21/CN22 USB 2.0 (port 0/1/2),
and enable USB momery on defconfig
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms@verge.net.au>
---
arch/arm/configs/marzen_defconfig | 6 ++
arch/arm/mach-shmobile/Kconfig | 1 +
arch/arm/mach-shmobile/board-marzen.c | 108 ++++++++++++++++++++++++++++++++-
3 files changed, 114 insertions(+), 1 deletion(-)
diff --git a/arch/arm/configs/marzen_defconfig b/arch/arm/configs/marzen_defconfig
index 8a861b7..6540dfb 100644
--- a/arch/arm/configs/marzen_defconfig
+++ b/arch/arm/configs/marzen_defconfig
@@ -47,6 +47,8 @@ CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_STANDALONE is not set
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
# CONFIG_FW_LOADER is not set
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
CONFIG_NETDEVICES=y
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_FARADAY is not set
@@ -82,6 +84,10 @@ CONFIG_USB=y
CONFIG_USB_RCAR_PHY=y
CONFIG_MMC=y
CONFIG_MMC_SDHI=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_STORAGE=y
CONFIG_UIO=y
CONFIG_UIO_PDRV_GENIRQ=y
# CONFIG_IOMMU_SUPPORT is not set
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index f58c3ea..c03aeec 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -41,6 +41,7 @@ config ARCH_R8A7779
select ARM_GIC
select CPU_V7
select SH_CLK_CPG
+ select USB_ARCH_HAS_EHCI
config ARCH_EMEV2
bool "Emma Mobile EV2"
diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
index 74c7f0b..707b3bd 100644
--- a/arch/arm/mach-shmobile/board-marzen.c
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -34,6 +34,9 @@
#include <linux/spi/sh_hspi.h>
#include <linux/mmc/sh_mobile_sdhi.h>
#include <linux/mfd/tmio.h>
+#include <linux/usb/otg.h>
+#include <linux/usb/ehci_pdriver.h>
+#include <linux/pm_runtime.h>
#include <mach/hardware.h>
#include <mach/r8a7779.h>
#include <mach/common.h>
@@ -172,6 +175,101 @@ static struct platform_device *marzen_devices[] __initdata = {
&usb_phy_device,
};
+/* USB */
+static struct usb_phy *phy;
+static int usb_power_on(struct platform_device *pdev)
+{
+ if (!phy)
+ return -EIO;
+
+ pm_runtime_enable(&pdev->dev);
+ pm_runtime_get_sync(&pdev->dev);
+
+ usb_phy_init(phy);
+
+ return 0;
+}
+
+static void usb_power_off(struct platform_device *pdev)
+{
+ if (!phy)
+ return;
+
+ usb_phy_shutdown(phy);
+
+ pm_runtime_put_sync(&pdev->dev);
+ pm_runtime_disable(&pdev->dev);
+}
+
+static struct usb_ehci_pdata ehcix_pdata = {
+ .power_on = usb_power_on,
+ .power_off = usb_power_off,
+ .power_suspend = usb_power_off,
+};
+
+static struct resource ehci0_resources[] = {
+ [0] = {
+ .start = 0xffe70000,
+ .end = 0xffe70400 - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = gic_spi(44),
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device ehci0_device = {
+ .name = "ehci-platform",
+ .id = 0,
+ .dev = {
+ .dma_mask = &ehci0_device.dev.coherent_dma_mask,
+ .coherent_dma_mask = 0xffffffff,
+ .platform_data = &ehcix_pdata,
+ },
+ .num_resources = ARRAY_SIZE(ehci0_resources),
+ .resource = ehci0_resources,
+};
+
+static struct resource ehci1_resources[] = {
+ [0] = {
+ .start = 0xfff70000,
+ .end = 0xfff70400 - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = gic_spi(45),
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device ehci1_device = {
+ .name = "ehci-platform",
+ .id = 1,
+ .dev = {
+ .dma_mask = &ehci1_device.dev.coherent_dma_mask,
+ .coherent_dma_mask = 0xffffffff,
+ .platform_data = &ehcix_pdata,
+ },
+ .num_resources = ARRAY_SIZE(ehci1_resources),
+ .resource = ehci1_resources,
+};
+
+static struct platform_device *marzen_late_devices[] __initdata = {
+ &ehci0_device,
+ &ehci1_device,
+};
+
+void __init marzen_init_late(void)
+{
+ /* get usb phy */
+ phy = usb_get_phy(USB_PHY_TYPE_USB2);
+
+ shmobile_init_late();
+ platform_add_devices(marzen_late_devices,
+ ARRAY_SIZE(marzen_late_devices));
+}
+
static void __init marzen_init(void)
{
regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
@@ -209,6 +307,14 @@ static void __init marzen_init(void)
gpio_request(GPIO_FN_HSPI_TX0, NULL);
gpio_request(GPIO_FN_HSPI_RX0, NULL);
+ /* USB (CN21) */
+ gpio_request(GPIO_FN_USB_OVC0, NULL);
+ gpio_request(GPIO_FN_USB_OVC1, NULL);
+ gpio_request(GPIO_FN_USB_OVC2, NULL);
+
+ /* USB (CN22) */
+ gpio_request(GPIO_FN_USB_PENC2, NULL);
+
r8a7779_add_standard_devices();
platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices));
}
@@ -221,6 +327,6 @@ MACHINE_START(MARZEN, "marzen")
.init_irq = r8a7779_init_irq,
.handle_irq = gic_handle_irq,
.init_machine = marzen_init,
- .init_late = shmobile_init_late,
+ .init_late = marzen_init_late,
.timer = &shmobile_timer,
MACHINE_END
--
1.7.10.4
^ permalink raw reply related
* [PATCH 1/7] ARM: shmobile: marzen: add USB phy support
From: Simon Horman @ 2012-11-08 1:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352338056-21107-1-git-send-email-horms@verge.net.au>
From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms@verge.net.au>
---
arch/arm/configs/marzen_defconfig | 3 ++-
arch/arm/mach-shmobile/board-marzen.c | 21 +++++++++++++++++++++
2 files changed, 23 insertions(+), 1 deletion(-)
diff --git a/arch/arm/configs/marzen_defconfig b/arch/arm/configs/marzen_defconfig
index 5b8215f..8a861b7 100644
--- a/arch/arm/configs/marzen_defconfig
+++ b/arch/arm/configs/marzen_defconfig
@@ -78,7 +78,8 @@ CONFIG_GPIO_SYSFS=y
CONFIG_THERMAL=y
CONFIG_RCAR_THERMAL=y
CONFIG_SSB=y
-# CONFIG_USB_SUPPORT is not set
+CONFIG_USB=y
+CONFIG_USB_RCAR_PHY=y
CONFIG_MMC=y
CONFIG_MMC_SDHI=y
CONFIG_UIO=y
diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
index 69f7f46..74c7f0b 100644
--- a/arch/arm/mach-shmobile/board-marzen.c
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -144,11 +144,32 @@ static struct platform_device hspi_device = {
.num_resources = ARRAY_SIZE(hspi_resources),
};
+/* USB PHY */
+static struct resource usb_phy_resources[] = {
+ [0] = {
+ .start = 0xffe70000,
+ .end = 0xffe70900 - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = 0xfff70000,
+ .end = 0xfff70900 - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device usb_phy_device = {
+ .name = "rcar_usb_phy",
+ .resource = usb_phy_resources,
+ .num_resources = ARRAY_SIZE(usb_phy_resources),
+};
+
static struct platform_device *marzen_devices[] __initdata = {
ð_device,
&sdhi0_device,
&thermal_device,
&hspi_device,
+ &usb_phy_device,
};
static void __init marzen_init(void)
--
1.7.10.4
^ permalink raw reply related
* [GIT PULL v2] Renesas ARM-based SoC boards for v3.8 #2
From: Simon Horman @ 2012-11-08 1:27 UTC (permalink / raw)
To: linux-arm-kernel
Hi Olof, Hi Arnd,
please consider the following board enhancements for 3.8.
* This pull-request is based on an earlier request which I
posted on the 1st and was merged yesterday: [GIT PULL v3] Renesas
ARM-based SoC boards for v3.8
* This pull request replaces the one that I sent yesterday:
[GIT PULL] Renesas ARM-based SoC boards for v3.8 #2
* Patch #2 of this series has a build-time dependency on
the soc pull request that I sent a few minutes ago:
[GIT PULL] Renesas ARM-based SoC for v3.8 #2
In particular, "ARM: shmobile: marzen: add USB EHCI driver support"
depends on "[PATCH 1/7] ARM: shmobile: r8a7779: PFC rename PENCx -> USB_PENCx"
* Patch 4 of this pull-request is a driver patch which is a dependency
of patches 6 and 7 of this pull-request. I have spoken to the driver
maintainer, Paul Mundt, and he has indicated that he thinks it
is best to merge all in one go.
In more detail:
"sh: clkfwk: add sh_clk_fsidiv_register()" is a dependency of
- "ARM: shmobile: sh7372: use sh_clk_fsidiv_register() for FSI-DIV clocks"
- "ARM: shmobile: r8a7740: add FSI-DVI clocks"
----------------------------------------------------------------
The following changes since commit 631a7b5d958d2ef2c2333b105794c693642f0641:
ARM: shmobile: Remove G4EVM machine support (2012-10-30 15:25:59 +0800)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git boards
for you to fetch changes up to 32ce635f0251bf5b2232cc59151d344303b73718:
ARM: shmobile: r8a7740: add FSI-DVI clocks (2012-11-08 10:16:13 +0900)
----------------------------------------------------------------
Kuninori Morimoto (7):
ARM: shmobile: marzen: add USB phy support
ARM: shmobile: marzen: add USB EHCI driver support
ARM: shmobile: marzen: add USB OHCI driver support
sh: clkfwk: add sh_clk_fsidiv_register()
ARM: shmobile: sh7372: sh7372_fsidivX_clk become non-global
ARM: shmobile: sh7372: use sh_clk_fsidiv_register() for FSI-DIV clocks
ARM: shmobile: r8a7740: add FSI-DVI clocks
arch/arm/configs/marzen_defconfig | 14 +-
arch/arm/mach-shmobile/Kconfig | 2 +
arch/arm/mach-shmobile/board-ap4evb.c | 2 +-
arch/arm/mach-shmobile/board-mackerel.c | 2 +-
arch/arm/mach-shmobile/board-marzen.c | 186 +++++++++++++++++++++++++-
arch/arm/mach-shmobile/clock-r8a7740.c | 16 +++
arch/arm/mach-shmobile/clock-sh7372.c | 92 ++-----------
arch/arm/mach-shmobile/include/mach/sh7372.h | 2 -
drivers/sh/clk/cpg.c | 86 ++++++++++++
include/linux/sh_clk.h | 9 ++
10 files changed, 321 insertions(+), 90 deletions(-)
^ permalink raw reply
* [PATCH v4 9/9] pinctrl: single: dump pinmux register value
From: Tony Lindgren @ 2012-11-08 1:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352301582-12244-10-git-send-email-haojian.zhuang@gmail.com>
* Haojian Zhuang <haojian.zhuang@gmail.com> [121107 07:22]:
> Dump pinmux register value, not only function part in the pinmux
> register.
>
> Also fix the issue on caluclating pin offset. The last parameter
> should be pin number, not register offset.
Acked-by: Tony Lindgren <tony@atomide.com>
> Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
> ---
> drivers/pinctrl/pinctrl-single.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
> index 77aec05..243a9ca 100644
> --- a/drivers/pinctrl/pinctrl-single.c
> +++ b/drivers/pinctrl/pinctrl-single.c
> @@ -286,15 +286,15 @@ static int pcs_get_group_pins(struct pinctrl_dev *pctldev,
>
> static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev,
> struct seq_file *s,
> - unsigned offset)
> + unsigned pin)
> {
> struct pcs_device *pcs;
> - unsigned val;
> + unsigned val, mux_bytes;
>
> pcs = pinctrl_dev_get_drvdata(pctldev);
>
> - val = pcs->read(pcs->base + offset);
> - val &= pcs->fmask;
> + mux_bytes = pcs->width / BITS_PER_BYTE;
> + val = pcs->read(pcs->base + pin * mux_bytes);
>
> seq_printf(s, "%08x %s " , val, DRIVER_NAME);
> }
> --
> 1.7.10.4
>
^ permalink raw reply
* [PATCH 06/15] ARM: shmobile: Add DT table of INTC for sh73a0
From: Nobuhiro Iwamatsu @ 2012-11-08 0:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <509A3E02.3050507@kmckk.co.jp>
Hi,
Tetsuyuki Kobayashi ????????:
> Hello, Iwamatsu-san, Simon-san
>
> (2012/11/07 17:50), Simon Horman wrote:
>> From: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
>>
>> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
>> Signed-off-by: Simon Horman <horms@verge.net.au>
>> ---
>> arch/arm/boot/dts/sh73a0.dtsi | 810 +++++++++++++++++++++++++++++++++++++++++
>> 1 file changed, 810 insertions(+)
>> create mode 100644 arch/arm/boot/dts/sh73a0.dtsi
>>
>> diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
>> new file mode 100644
>> index 0000000..b0c55e1
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/sh73a0.dtsi
>> @@ -0,0 +1,810 @@
>> +/*
>> + * Device Tree Source for the SH73A0
>> + *
>> + * Copyright (C) 2012 Renesas Solutions Corp.
>> + *
>> + * This file is licensed under the terms of the GNU General Public License
>> + * version 2. This program is licensed "as is" without any warranty of any
>> + * kind, whether express or implied.
>> + */
>> +
>> +/include/ "skeleton.dtsi"
>> +
>> +/ {
>> + compatible = "renesas,sh73a0";
>> +
>> + cpus {
>> + cpu at 0 {
>> + compatible = "arm,cortex-a8";
>> + };
>> + };
>
> SH73A0 is dual core cortex-a9.
>
Thanks, I will fix.
^ permalink raw reply
* [PATCH 06/15] ARM: shmobile: Add DT table of INTC for sh73a0
From: Simon Horman @ 2012-11-08 0:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <509A3E02.3050507@kmckk.co.jp>
On Wed, Nov 07, 2012 at 07:54:58PM +0900, Tetsuyuki Kobayashi wrote:
> Hello, Iwamatsu-san, Simon-san
>
> (2012/11/07 17:50), Simon Horman wrote:
> > From: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
> >
> > Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
> > Signed-off-by: Simon Horman <horms@verge.net.au>
> > ---
> > arch/arm/boot/dts/sh73a0.dtsi | 810 +++++++++++++++++++++++++++++++++++++++++
> > 1 file changed, 810 insertions(+)
> > create mode 100644 arch/arm/boot/dts/sh73a0.dtsi
> >
> > diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
> > new file mode 100644
> > index 0000000..b0c55e1
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/sh73a0.dtsi
> > @@ -0,0 +1,810 @@
> > +/*
> > + * Device Tree Source for the SH73A0
> > + *
> > + * Copyright (C) 2012 Renesas Solutions Corp.
> > + *
> > + * This file is licensed under the terms of the GNU General Public License
> > + * version 2. This program is licensed "as is" without any warranty of any
> > + * kind, whether express or implied.
> > + */
> > +
> > +/include/ "skeleton.dtsi"
> > +
> > +/ {
> > + compatible = "renesas,sh73a0";
> > +
> > + cpus {
> > + cpu at 0 {
> > + compatible = "arm,cortex-a8";
> > + };
> > + };
>
> SH73A0 is dual core cortex-a9.
Thanks, I have changed the patch to use "arm,cortex-a9"
^ permalink raw reply
* [PATCH] ARM: cache-l2x0: move 'l2_wt_override' variable to proper place
From: Jingoo Han @ 2012-11-08 0:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121107093419.GS28327@n2100.arm.linux.org.uk>
On Wednesday, November 07, 2012 6:34 PM Russell King wrote
>
> On Wed, Nov 07, 2012 at 03:03:36PM +0900, Jingoo Han wrote:
> > Fixed build warning as below:
> >
> > arch/arm/mm/cache-l2x0.c:37:12: warning: 'l2_wt_override' defined but not used [-Wunused-variable]
>
> You're too late with this; it's already been resolved.
OK, I see. :)
^ permalink raw reply
* [PATCH v4 1/5] zynq: use GIC device tree bindings
From: John Linn @ 2012-11-08 0:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121107141759.GA1718@beefymiracle.amer.corp.natinst.com>
> -----Original Message-----
> From: Josh Cartwright [mailto:josh.cartwright at ni.com]
> Sent: Wednesday, November 07, 2012 6:18 AM
> To: Michal Simek
> Cc: arm at kernel.org; Arnd Bergmann; linux-kernel at vger.kernel.org; linux-arm-kernel at lists.infradead.org;
> John Linn; Nick Bowler
> Subject: Re: [PATCH v4 1/5] zynq: use GIC device tree bindings
>
> On Wed, Nov 07, 2012 at 01:05:57PM +0100, Michal Simek wrote:
> > 2012/11/5 Josh Cartwright <josh.cartwright@ni.com>:
> [..]
> > > Our usecase may admittedly be a bit weird, because what logic is in the
> > > PL is ultimately determined (and even implemented) by the end user and
> > > is loaded at runtime. There is a lot of machinery to make that happen,
> > > but the point is that I don't have sufficient knowledge upfront to
> > > generate appropriate bindings for what's in the PL.
> >
> > ok. It means that you need to use just the part of DTS without PL logic at all.
> > Does it mean that PL will be connected with any DTS fragment?
>
> Yes. For the time being, this is true. We have our own mechanisms for
> enumerating IP at runtime.
>
> > > > > Having a dtsi allows for easy extension of the zynq-7000
> > > > > platform for our boards, without having to carry duplicate data.
> > > >
> > > > ok. I think that make sense if you send the next your series as
> > > > RFC to see how exactly you would like to use it.
> > >
> > > It seems like you caught a glimpse of this in my COMMON_CLK
> > > patchset. :)
> >
> > Yes. Just need to get some time to analyze it.
> >
> [..]
> > > I wouldn't be as opposed to device tree generation if the device tree
> > > generator was in tree.
> >
> > Which tree do you exactly mean? Linux kernel or just any git tree?
>
> No, I mean in the upstream Linux kernel tree. I don't think this is
> likely to happen. My point here is that the generator necessarily has a
> dependency on how the bindings are written. If those bindings change
> (or new bindings are added), the generator must be updated to generate
> device trees according to the new bindings.
>
> I fail to see how these changes are handled with your generator.
>
> > Let me give you more information about the generator. It uses TCL in SDK
> > where it provides all structure from the system. It means device-tree generator
> > will read all information from design tool and based on that will generate
> > DTS file. It also means if user will setup specific irq lines in design, special
> > paramters setting in registers then all these values will be added to DTS.
> >
> > > Device tree bindings change, how would/could an out-of-tree
> > > generator possibly handle changes in bindings?
> >
> > What do you mean by that? Any example?
>
> Yes, I have a real life example. In 3.2 (?), GIC bindings were added to
> the kernel. It was necessary for us to update our board descriptions to
> reflect the new #interrupt-cells = <3>; and figure out the appropriate
> interrupt numbers (which differed from how they were specified before).
>
> How would your generator have known whether or not I was targetting a
> kernel with the GIC bindings, and appropriately generate the GIC node,
> and generate interruptspecs for all children with #interrupt-cells = <3>?
>
Hi Josh,
Yes we see this problem coming too.
> Or, maybe another example: say clk bindings are added to the upstream
> kernel, and I would like to use a kernel that contains them on my board.
> Say this has all happened before Xilinx has even released a new version
> of their SDK. How could I use your dts generator to output proper clk
> nodes in my dts?
>
> It seems the only way that Xilinx can possibly handle this is to tightly
> couple the version of the kernel and their generator.
>
> With increasing support for Zynq in the mainline kernel tree, it may
> become more palatable for some existing users to switch to using the
> upstream kernel instead of the Xilinx tree for their boards, and
> coupling between the generator and target kernel version will be broken.
>
> [..]
> > > It is odd to me that the use of a generator would be required to create
> > > what is completely static data. What I'm referring to here is the
> > > collection of peripherals on the zynq-7000 that are not in the PL. For
> > > me, this requirement adds an unnecessary dependency on the Xilinx EDK
> > > that I would like to avoid.
> >
> > I am not saying that you need to use it. If you want to write your DTS
> > by hand, you still can but I expect that the most of zynq users will
> > use generator and generate it because it is just easier than to
> > describe it by hand and they can be sure that all parameters are
> > correctly generated.
>
> Again, you can only make this assurance _for a specific version of the
> kernel_. If a user is not using the version of the kernel that came
> with the SDK (and, maybe instead using a vanilla upstream kernel), all
> bets are off.
>
> > If you are using any non-standard solution where you will load pl
> > logic at runtime then you can use just generated DTS for hardblock or
> > write it by hand.
>
> I choose 'write it by hand'. I want what I write by hand to also be
> useful to others by including the zynq-7000.dtsi in the upstream kernel.
Yes agreed.
>
> [..]
> > If you want to use solution with several dtsi files and compose it as
> > you describe then it is completely fine but forcing others to use this
> > structure and write dts by hand will be big pain for a lot of users.
>
> Using a composed model in the upstream kernel doesn't force anything
> upon the existing users of your generator. They can still use whatever
> gets spit out of your generator (assuming it generates nodes with
> appropriate bindings). Unless I'm missing something here.
>
> > Also in design tools you can setup if you use qspi,nor,nand flash
> > memory interface.
> > memory interface, baudrates, dma, ports to PL logic, connections, etc.
> > and from my point of view is very complicated to describe it by
> >
> > There are a lot of combination which you can have on one reference
> > board. You can't enable all hard IPs at one time and use all of them
> > that's why you shouldn't list all of them in the kernel.
>
> I disagree with this. In my opinion, all of the "hard IPs" should be
> described in the zynq-7000.dtsi, and those nodes which aren't available
> explicitly disabled in the board-specific file.
It looks like most everyone is doing this in their device trees.
>
> > From my point of view make sense to have one DTS file in the kernel
> > and one defconfig for the most popular zynq board where will be
> > exactly written that this DTS is connected to this reference hw
> > design. If you want to get more reference design go to this page and
> > download it. Adding all DTSes for zynq boards to the kernel is
> > overkill. If you want to use your hw design you can use this
> > generator and generate it or write it by hand.
>
> All I'm asking for is for there to be a common zynq-7000.dtsi that
> describes all of the static PS logic ("hard IPs") in the upstream kernel
> source that I can include in my own (hand maintained) board
> descriptions. It would be nice if there was an example of its use, like
> with a zc702 board file also upstream, but it is not really important to
> me.
>
Yes I understand and see the benefits too.
> I do not want a dependency on the EDK.
>
Understood and it makes sense what you're saying.
> My request does not sound unreasonable to me and is what other platforms
> are doing.
>
Agreed. We'll wrestle with this some more within Xilinx.
Thanks,
John
> Josh
^ permalink raw reply
* [PATCH v4 3/9] pinctrl: single: support pinconf generic
From: Tony Lindgren @ 2012-11-08 0:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352301582-12244-4-git-send-email-haojian.zhuang@gmail.com>
Hi,
* Haojian Zhuang <haojian.zhuang@gmail.com> [121107 07:21]:
> diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
> index a7c5fdd..77aec05 100644
> --- a/drivers/pinctrl/pinctrl-single.c
> +++ b/drivers/pinctrl/pinctrl-single.c
> static int pcs_pinconf_get(struct pinctrl_dev *pctldev,
> unsigned pin, unsigned long *config)
> {
> + struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
> + enum pin_config_param param = pinconf_to_config_param(*config);
> + unsigned data;
> + u32 offset;
Do you need a check here (and also in other pinconf related functions)
for driver instances that don't have pinconf enabled?
Something like:
if (!pcs->pinconf)
return -ENOTSUPP;
...
> @@ -806,34 +1000,27 @@ static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
>
> pcs = pinctrl_dev_get_drvdata(pctldev);
>
> - *map = devm_kzalloc(pcs->dev, sizeof(**map), GFP_KERNEL);
> - if (!map)
> - return -ENOMEM;
> + if (!pcs->conf.nconfs)
> + *num_maps = 1;
> + else
> + *num_maps = 2;
>
> - *num_maps = 0;
> + *map = devm_kzalloc(pcs->dev, sizeof(**map) * (*num_maps), GFP_KERNEL);
> + if (!*map)
> + return -ENOMEM;
>
> pgnames = devm_kzalloc(pcs->dev, sizeof(*pgnames), GFP_KERNEL);
> - if (!pgnames) {
> - ret = -ENOMEM;
> - goto free_map;
> - }
> + if (!pgnames)
> + return -ENOMEM;
>
> ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map, pgnames);
> if (ret < 0) {
> dev_err(pcs->dev, "no pins entries for %s\n",
> np_config->name);
> - goto free_pgnames;
> + return ret;
> }
> - *num_maps = 1;
>
> return 0;
> -
> -free_pgnames:
> - devm_kfree(pcs->dev, pgnames);
> -free_map:
> - devm_kfree(pcs->dev, *map);
> -
> - return ret;
> }
Here looks like you're changing the behaviour to not free entries in cases
where parsing with cs_parse_one_pinctrl_entry() fails. I'd prefer the freeing
it in case of parsing errors so we don't waste memory when the system is
running. Also there's a tiny chance that *num_maps will be wrong if the
second devm_kzalloc fails.. But it's more likely that we get a broken device
tree to parse and end up potentially hogging hundreds of maps.
Regards,
Tony
^ permalink raw reply
* [PATCH] ARM: highbank: use common debug_ll_io_init
From: Rob Herring @ 2012-11-08 0:09 UTC (permalink / raw)
To: linux-arm-kernel
From: Rob Herring <rob.herring@calxeda.com>
Remove the platform static mapping code for uart and use the common
debug_ll_io_init function.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
---
This is dependent on arm-soc/devel/debug_ll_init and
arm-soc/calxeda/ecx-2000 branches.
Rob
arch/arm/mach-highbank/Makefile | 1 -
arch/arm/mach-highbank/core.h | 5 -----
arch/arm/mach-highbank/highbank.c | 8 ++------
arch/arm/mach-highbank/lluart.c | 34 ----------------------------------
4 files changed, 2 insertions(+), 46 deletions(-)
delete mode 100644 arch/arm/mach-highbank/lluart.c
diff --git a/arch/arm/mach-highbank/Makefile b/arch/arm/mach-highbank/Makefile
index 3ec8bdd..8a1ef57 100644
--- a/arch/arm/mach-highbank/Makefile
+++ b/arch/arm/mach-highbank/Makefile
@@ -3,7 +3,6 @@ obj-y := highbank.o system.o smc.o
plus_sec := $(call as-instr,.arch_extension sec,+sec)
AFLAGS_smc.o :=-Wa,-march=armv7-a$(plus_sec)
-obj-$(CONFIG_DEBUG_HIGHBANK_UART) += lluart.o
obj-$(CONFIG_SMP) += platsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
obj-$(CONFIG_PM_SLEEP) += pm.o
diff --git a/arch/arm/mach-highbank/core.h b/arch/arm/mach-highbank/core.h
index 286ec82..603b536 100644
--- a/arch/arm/mach-highbank/core.h
+++ b/arch/arm/mach-highbank/core.h
@@ -2,11 +2,6 @@ extern void highbank_set_cpu_jump(int cpu, void *jump_addr);
extern void highbank_clocks_init(void);
extern void highbank_restart(char, const char *);
extern void __iomem *scu_base_addr;
-#ifdef CONFIG_DEBUG_HIGHBANK_UART
-extern void highbank_lluart_map_io(void);
-#else
-static inline void highbank_lluart_map_io(void) {}
-#endif
#ifdef CONFIG_PM_SLEEP
extern void highbank_pm_init(void);
diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c
index 3e60e57..dc24816 100644
--- a/arch/arm/mach-highbank/highbank.c
+++ b/arch/arm/mach-highbank/highbank.c
@@ -35,6 +35,7 @@
#include <asm/hardware/gic.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include "core.h"
@@ -53,11 +54,6 @@ static void __init highbank_scu_map_io(void)
scu_base_addr = ioremap(base, SZ_4K);
}
-static void __init highbank_map_io(void)
-{
- highbank_lluart_map_io();
-}
-
#define HB_JUMP_TABLE_PHYS(cpu) (0x40 + (0x10 * (cpu)))
#define HB_JUMP_TABLE_VIRT(cpu) phys_to_virt(HB_JUMP_TABLE_PHYS(cpu))
@@ -211,7 +207,7 @@ static const char *highbank_match[] __initconst = {
DT_MACHINE_START(HIGHBANK, "Highbank")
.smp = smp_ops(highbank_smp_ops),
- .map_io = highbank_map_io,
+ .map_io = debug_ll_io_init,
.init_irq = highbank_init_irq,
.timer = &highbank_timer,
.handle_irq = gic_handle_irq,
diff --git a/arch/arm/mach-highbank/lluart.c b/arch/arm/mach-highbank/lluart.c
deleted file mode 100644
index 3715750..0000000
--- a/arch/arm/mach-highbank/lluart.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright 2011 Calxeda, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
- */
-#include <linux/init.h>
-#include <asm/page.h>
-#include <asm/sizes.h>
-#include <asm/mach/map.h>
-
-#define HB_DEBUG_LL_PHYS_BASE 0xfff36000
-#define HB_DEBUG_LL_VIRT_BASE 0xfee36000
-
-static struct map_desc lluart_io_desc __initdata = {
- .virtual = HB_DEBUG_LL_VIRT_BASE,
- .pfn = __phys_to_pfn(HB_DEBUG_LL_PHYS_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
-};
-
-void __init highbank_lluart_map_io(void)
-{
- iotable_init(&lluart_io_desc, 1);
-}
--
1.7.10.4
^ permalink raw reply related
* struct sys_timer .suspend/.resume ignored for ARCH_SA1100/ARCH_PXA?
From: Stephen Warren @ 2012-11-08 0:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121107232341.GY28327@n2100.arm.linux.org.uk>
On 11/07/2012 04:23 PM, Russell King - ARM Linux wrote:
> On Wed, Nov 07, 2012 at 04:06:12PM -0700, Stephen Warren wrote:
>> Russell, Kevin,
>>
>> In commit 9e4559d "[ARM] 4258/2: Support for dynticks in idle loop" in
>> 2007, Kevin applied the following change:
>>
>>> diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c
>>
>>> -#ifdef CONFIG_PM
>>> +#if defined(CONFIG_PM) && !defined(CONFIG_GENERIC_CLOCKEVENTS)
>>> static int timer_suspend(struct sys_device *dev, pm_message_t state)
>>
>> This means that for any architecture that enables GENERIC_CLOCKEVENTS,
>> the .suspend/.resume fields of struct sys_timer will be ignored, since
>> timer_suspend()/timer_resume() won't be filled into
>> arch/arm/kernel/time.c's struct syscore_ops timer_syscore_ops.
>
> Correct.
>
>> Later, in commit 3e238be "[ARM] sa1100: add clock event support" in
>> 2008, Russell modified ARCH_SA1100 to select GENERIC_CLOCKEVENTS. I
>> believe this means that sa1100_timer_suspend()/resume() haven't been
>> used since.
>
> Also correct.
>
>> A similar issue exists for ARCH_PXA.
>>
>> Should sa1100_timer_suspend(), sa1100_timer_resume(),
>> pxa_timer_suspend(), pxa_timer_suspend() simply be deleted since they
>> are dead code, or should they be revived somehow; is the ifdef from
>> Kevin's change incorrect?
>
> Hmm, that's probably not good for either of those two platforms; it means
> that the OSCR and match registers get lost over a suspend/resume. That's
> not a real big problem for the clocksource code, but if its being used
> for something else (eg, rtc) then it probably means we have a failure
> there.
OK, so it sounds like the correct approach here is to re-enable those
functions. The local patches I have right now do this, and hook them
into e.g. ckevt_sa1100_osmr0's suspend/resume rather than sys_timer's. I
assume that will work fine?
>> As background, I'm working on a patch series that will remove all fields
>> from struct sys_timer except for .init, and will then replace the ARM
>> machine descriptor's .timer struct pointer with a .init_timer function
>> pointer. This will allow machines, on an opt-in basis, to call into a
>> central function in drivers/clocksource to initialize the required
>> timer, as determined by searching device tree for a known device type,
>> in much the same way as has been proposed to use a single implementation
>> for for the machine descriptor's .init_irq. As part of this, I've been
>> looking at moving any use of struct sys_timer .suspend/.resume into e.g.
>> struct clock_event_device .suspend/.resume, and found this issue.
>
> Don't forget we still have a number of platforms not converted to
> the generic event/clocksource stuff (because they lack the necessary
> counters/timers for this 'new' infrastructure.)
I believe the only user of struct sys_timer .suspend/.resume that does
use struct clock_event_device is s3c2410. I'd missed that before since
I'd only searched for .suspend and not .resume alone. Perhaps this one
should just register its own syscore_ops instead of having the ARM core
do that on its behalf.
^ permalink raw reply
* [GIT PULL] ARM: OMAP: Timer and Counter DT Updates for v3.8
From: Tony Lindgren @ 2012-11-07 23:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121107004703.GS6801@atomide.com>
Hi Jon,
* Tony Lindgren <tony@atomide.com> [121106 16:48]:
> * Jon Hunter <jon-hunter@ti.com> [121102 12:01]:
> >
> > git at github.com:jonhunter/linux.git dev-dt-timer
>
> Thanks pulling into omap-for-v3.8/dt branch.
Looks like omap-for-v3.8/dt boots OK on blaze when booted
with device tree, but then current omap-for-v3.8/tmp-merge
oopses.
I guess we should apply the following fix somewhere or
do we need to check other places too?
Regards,
Tony
[<c04e3d30>] (omap_dm_timer_probe+0x110/0x310) from [<c0334a18>] (platform_drv_probe+0x1c/0x24)
[<c0334a18>] (platform_drv_probe+0x1c/0x24) from [<c03335d4>] (really_probe+0x60/0x1f4)
[<c03335d4>] (really_probe+0x60/0x1f4) from [<c033379c>] (driver_probe_device+0x34/0x50)
[<c033379c>] (driver_probe_device+0x34/0x50) from [<c033384c>] (__driver_attach+0x94/0x98)
[<c033384c>] (__driver_attach+0x94/0x98) from [<c0331df8>] (bus_for_each_dev+0x60/0x8c)
[<c0331df8>] (bus_for_each_dev+0x60/0x8c) from [<c03326c4>] (bus_add_driver+0x18c/0x254)
[<c03326c4>] (bus_add_driver+0x18c/0x254) from [<c0333e44>] (driver_register+0x5c/0x150)
[<c0333e44>] (driver_register+0x5c/0x150) from [<c0008868>] (do_one_initcall+0x2c/0x178)
[<c0008868>] (do_one_initcall+0x2c/0x178) from [<c06df2a0>] (do_basic_setup+0x94/0xd0)
[<c06df2a0>] (do_basic_setup+0x94/0xd0) from [<c06df358>] (kernel_init_freeable+0x7c/0x124)
[<c06df358>] (kernel_init_freeable+0x7c/0x124) from [<c04e1810>] (kernel_init+0x8/0x1a8)
[<c04e1810>] (kernel_init+0x8/0x1a8) from [<c0014410>] (ret_from_fork+0x14/0x24)
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -803,8 +803,11 @@ static int __devinit omap_dm_timer_probe(struct platform_device *pdev)
timer->irq = irq->start;
timer->pdev = pdev;
- timer->capability = pdata->timer_capability;
- timer->get_context_loss_count = pdata->get_context_loss_count;
+
+ if (pdata) {
+ timer->capability = pdata->timer_capability;
+ timer->get_context_loss_count = pdata->get_context_loss_count;
+ }
/* Skip pm_runtime_enable for OMAP1 */
if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) {
^ permalink raw reply
* [PATCH V2 03/14] ARM: OMAP3+: Implement timer workaround for errata i103 and i767
From: Santosh Shilimkar @ 2012-11-07 23:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <509AEEA4.80804@ti.com>
On Wednesday 07 November 2012 05:28 PM, Jon Hunter wrote:
>
> On 11/07/2012 04:14 PM, Santosh Shilimkar wrote:
>
>> Looks sensible considering alternative WAs.
>>
>> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
>
> Thanks. With further thought I think that it would be best to combine
> patches #2 and #3. Really the main motivation here is the errata
> workaround and without actually benchmarking the timer read I should
> not claim the improvement in overhead as stated in patch #2. So I
> have combined #2 and #3 and updated the changelog/comments
> appropriately. Let me know if you guys are ok with this.
>
Yep. Sounds good.
Regards
Santosh
^ permalink raw reply
* [PATCH V2 03/14] ARM: OMAP3+: Implement timer workaround for errata i103 and i767
From: Jon Hunter @ 2012-11-07 23:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <509ADD28.20707@ti.com>
On 11/07/2012 04:14 PM, Santosh Shilimkar wrote:
> Looks sensible considering alternative WAs.
>
> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Thanks. With further thought I think that it would be best to combine
patches #2 and #3. Really the main motivation here is the errata
workaround and without actually benchmarking the timer read I should
not claim the improvement in overhead as stated in patch #2. So I
have combined #2 and #3 and updated the changelog/comments
appropriately. Let me know if you guys are ok with this.
Cheers
Jon
>From 0143aa216ef4c4b7554588bd72c417bc8c614525 Mon Sep 17 00:00:00 2001
From: Jon Hunter <jon-hunter@ti.com>
Date: Thu, 27 Sep 2012 12:47:43 -0500
Subject: [PATCH] ARM: OMAP3+: Implement timer workaround for errata i103 and
i767
Errata Titles:
i103: Delay needed to read some GP timer, WD timer and sync timer
registers after wakeup (OMAP3/4)
i767: Delay needed to read some GP timer registers after wakeup (OMAP5)
Description (i103/i767):
If a General Purpose Timer (GPTimer) is in posted mode
(TSICR [2].POSTED=1), due to internal resynchronizations, values read in
TCRR, TCAR1 and TCAR2 registers right after the timer interface clock
(L4) goes from stopped to active may not return the expected values. The
most common event leading to this situation occurs upon wake up from
idle.
GPTimer non-posted synchronization mode is not impacted by this
limitation.
Workarounds:
1). Disable posted mode
2). Use static dependency between timer clock domain and MPUSS clock
domain
3). Use no-idle mode when the timer is active
Workarounds #2 and #3 are not pratical from a power standpoint and so
workaround #1 has been implemented. Disabling posted mode adds some CPU
overhead for configuring and reading the timers as the CPU has to wait
for accesses to be re-synchronised within the timer. However, disabling
posted mode guarantees correct operation.
Please note that it is safe to use posted mode for timers if the counter
(TCRR) and capture (TCARx) registers will never be read. An example of
this is the clock-event system timer. This is used by the kernel to
schedule events however, the timers counter is never read and capture
registers are not used. Given that the kernel configures this timer
often yet never reads the counter register it is safe to enable posted
mode in this case. Hence, for the timer used for kernel clock-events,
posted mode is enabled by overriding the errata for devices that are
impacted by this defect.
For drivers using the timers that do not read the counter or capture
registers and wish to use posted mode, can override the errata and
enable posted mode by making the following function calls.
omap_dm_timer_override_errata(timer, OMAP_TIMER_ERRATA_I103_I767);
omap_dm_timer_enable_posted(timer);
Both dmtimers and watchdogs are impacted by this defect this patch only
implements the workaround for the dmtimer. Currently the watchdog driver
does not read the counter register and so no workaround is necessary.
Posted mode will be disabled for all OMAP2+ devices (including AM33xx)
using a GP timer as a clock-source timer to guarantee correct operation.
This is not necessary for OMAP24xx devices but the default clock-source
timer for OMAP24xx devices is the 32k-sync timer and not the GP timer
and so should not have any impact. This should be re-visited for future
devices if this errata is fixed.
Confirmed with Vaibhav Hiremath that this bug also impacts AM33xx
devices.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
---
arch/arm/mach-omap2/timer.c | 44 +++++++++++++++++----
arch/arm/plat-omap/dmtimer.c | 59 ++++++++++++++++++++++++++++-
arch/arm/plat-omap/include/plat/dmtimer.h | 19 ++++++++--
3 files changed, 109 insertions(+), 13 deletions(-)
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 28c6078..37e3089 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -83,11 +83,20 @@
#define NUMERATOR_DENUMERATOR_MASK 0xfffff000
/*
- * For clock-events timer, always use posted mode to
- * minimise CPU overhead for configuring the timer.
+ * For the clock-events timer, always use posted mode to
+ * minimise CPU overhead for configuring the timer. This timer
+ * is never read and so overhead of reading the timer in posted
+ * mode is not applicable.
*/
#define OMAP_CLKEVT_POSTEDMODE OMAP_TIMER_POSTED
-#define OMAP_CLKSRC_POSTEDMODE OMAP_TIMER_POSTED
+
+/*
+ * For the clock-source timer, use non-posted mode default due to
+ * errata i103/i767 that can cause the timer to return an incorrect
+ * counter value for OMAP3/4/5 devices. REVISIT this to see what is
+ * the optimal way to handle for future devices.
+ */
+#define OMAP_CLKSRC_POSTEDMODE OMAP_TIMER_NONPOSTED
/* Clockevent code */
@@ -233,7 +242,8 @@ void __init omap_dmtimer_init(void)
static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
int gptimer_id,
const char *fck_source,
- const char *property)
+ const char *property,
+ int posted)
{
char name[10]; /* 10 = sizeof("gptXX_Xck0") */
const char *oh_name;
@@ -319,10 +329,15 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
}
__omap_dm_timer_init_regs(timer);
__omap_dm_timer_reset(timer, 1, 1);
- timer->posted = 1;
- timer->rate = clk_get_rate(timer->fclk);
+ if (posted)
+ omap_dm_timer_enable_posted(timer);
+
+ /* Check that the intended posted configuration matches the actual */
+ if (posted != timer->posted)
+ return -EINVAL;
+ timer->rate = clk_get_rate(timer->fclk);
timer->reserved = 1;
return res;
@@ -334,7 +349,17 @@ static void __init omap2_gp_clockevent_init(int gptimer_id,
{
int res;
- res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source, property);
+ omap_dm_timer_populate_errata(&clkev);
+
+ /*
+ * For clock-event timers we never read the timer counter and
+ * so we are not impacted by errata i103 and i767. Therefore,
+ * we can safely ignore this errata for clock-event timers.
+ */
+ omap_dm_timer_override_errata(&clkev, OMAP_TIMER_ERRATA_I103_I767);
+
+ res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source, property,
+ OMAP_CLKEVT_POSTEDMODE);
BUG_ON(res);
omap2_gp_timer_irq.dev_id = &clkev;
@@ -461,7 +486,10 @@ static void __init omap2_gptimer_clocksource_init(int gptimer_id,
{
int res;
- res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source, NULL);
+ omap_dm_timer_populate_errata(&clksrc);
+
+ res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source, NULL,
+ OMAP_CLKSRC_POSTEDMODE);
BUG_ON(res);
__omap_dm_timer_load_start(&clksrc,
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index b09e556..4abbbe5 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -131,8 +131,8 @@ static void omap_dm_timer_reset(struct omap_dm_timer *timer)
}
__omap_dm_timer_reset(timer, 0, 0);
+ omap_dm_timer_enable_posted(timer);
omap_dm_timer_disable(timer);
- timer->posted = 1;
}
int omap_dm_timer_prepare(struct omap_dm_timer *timer)
@@ -176,6 +176,61 @@ int omap_dm_timer_reserve_systimer(int id)
return 0;
}
+/**
+ * omap_dm_timer_populate_errata - populate errata flags for a timer
+ * @timer: pointer to timer handle
+ *
+ * For a given timer, populate the timer errata flags that are specific to the
+ * OMAP device being used.
+ */
+void omap_dm_timer_populate_errata(struct omap_dm_timer *timer)
+{
+ timer->errata = 0;
+
+ if (cpu_class_is_omap1() || cpu_is_omap24xx())
+ return;
+
+ timer->errata = OMAP_TIMER_ERRATA_I103_I767;
+}
+
+/**
+ * omap_dm_timer_override_errata - override errata flags for a timer
+ * @timer: pointer to timer handle
+ * @errata: errata flags to be ignored
+ *
+ * For a given timer, override a timer errata by clearing the flags specified
+ * by the errata argument. A specific erratum should only be overridden for a
+ * timer if the timer is used in such a way the erratum has no impact.
+ */
+void omap_dm_timer_override_errata(struct omap_dm_timer *timer, u32 errata)
+{
+ timer->errata &= ~errata;
+}
+
+/*
+ * omap_dm_timer_enable_posted - enables write posted mode
+ * @timer: pointer to timer instance handle
+ *
+ * Enables the write posted mode for the timer. When posted mode is enabled
+ * writes to certain timer registers are immediately acknowledged by the
+ * internal bus and hence prevents stalling the CPU waiting for the write to
+ * complete. Enabling this feature can improve performance for writing to the
+ * timer registers.
+ */
+void omap_dm_timer_enable_posted(struct omap_dm_timer *timer)
+{
+ if (timer->posted)
+ return;
+
+ if (timer->errata & OMAP_TIMER_ERRATA_I103_I767)
+ return;
+
+ omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG,
+ OMAP_TIMER_CTRL_POSTED);
+ timer->context.tsicr = OMAP_TIMER_CTRL_POSTED;
+ timer->posted = OMAP_TIMER_POSTED;
+}
+
struct omap_dm_timer *omap_dm_timer_request(void)
{
struct omap_dm_timer *timer = NULL, *t;
@@ -803,6 +858,8 @@ static int __devinit omap_dm_timer_probe(struct platform_device *pdev)
timer->irq = irq->start;
timer->pdev = pdev;
+ omap_dm_timer_populate_errata(timer);
+
/* Skip pm_runtime_enable for OMAP1 */
if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) {
pm_runtime_enable(dev);
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index 835c3bdf..ef93017 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -36,6 +36,7 @@
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/platform_device.h>
+#include <plat/cpu.h>
#ifndef __ASM_ARCH_DMTIMER_H
#define __ASM_ARCH_DMTIMER_H
@@ -66,6 +67,16 @@
#define OMAP_TIMER_NEEDS_RESET 0x10000000
#define OMAP_TIMER_HAS_DSP_IRQ 0x08000000
+/*
+ * timer errata flags
+ *
+ * Errata i103/i767 impacts all OMAP3/4/5 devices including AM33xx. This
+ * errata prevents us from using posted mode on these devices, unless the
+ * timer counter register is never read. For more details please refer to
+ * the OMAP3/4/5 errata documents.
+ */
+#define OMAP_TIMER_ERRATA_I103_I767 0x80000000
+
struct omap_timer_capability_dev_attr {
u32 timer_capability;
};
@@ -101,6 +112,9 @@ struct dmtimer_platform_data {
};
int omap_dm_timer_reserve_systimer(int id);
+void omap_dm_timer_populate_errata(struct omap_dm_timer *timer);
+void omap_dm_timer_override_errata(struct omap_dm_timer *timer, u32 errata);
+void omap_dm_timer_enable_posted(struct omap_dm_timer *timer);
struct omap_dm_timer *omap_dm_timer_request(void);
struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id);
struct omap_dm_timer *omap_dm_timer_request_by_cap(u32 cap);
@@ -271,6 +285,7 @@ struct omap_dm_timer {
int ctx_loss_count;
int revision;
u32 capability;
+ u32 errata;
struct platform_device *pdev;
struct list_head node;
};
@@ -342,10 +357,6 @@ static inline void __omap_dm_timer_reset(struct omap_dm_timer *timer,
l |= 1 << 2;
__raw_writel(l, timer->io_base + OMAP_TIMER_OCP_CFG_OFFSET);
-
- /* Match hardware reset default of posted mode */
- __omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG,
- OMAP_TIMER_CTRL_POSTED, 0);
}
static inline int __omap_dm_timer_set_source(struct clk *timer_fck,
--
1.7.9.5
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