* [PATCH 01/14] pinctrl: SPEAr: add spi chipselect control driver
From: Linus Walleij @ 2012-11-15 14:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4a92290e8a3b1a19c3a5e864edfa7badfc2af5d0.1352608333.git.viresh.kumar@linaro.org>
On Sun, Nov 11, 2012 at 5:39 AM, Viresh Kumar <viresh.kumar@linaro.org> wrote:
> From: Shiraz Hashim <shiraz.hashim@st.com>
>
> SPEAr platform provides a provision to control chipselects of ARM PL022
> Prime Cell spi controller through its system registers, which otherwise
> remains under PL022 control which some protocols do not want.
>
> This commit intends to provide the spi chipselect control in software
> over gpiolib interface. Since it is tied to pinctrl, we place it under
> 'drivers/pinctrl/spear/' directory.
>
> spi chip drivers can use the exported gpiolib interface to define their
> chipselect through DT or platform data.
>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
> Reviewed-by: Vipin Kumar <vipin.kumar@st.com>
> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
This sure looks good, sorry for the delay.
Just one question: since this driver is not using any
pinctrl interfaces, why is it under drivers/pinctrl/*?
Shouldn't it be under drivers/gpio from a technical
point of view?
I think I'd accept it under drivers/pinctrl/spear/*
if you just want this to keep everything SPEAr-related
in one place though, so enlighten me.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH v4 9/9] pinctrl: single: dump pinmux register value
From: Linus Walleij @ 2012-11-15 14:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAN1soZxSQb2RN41v64SuOaQ6eLcV5NEZWSsMBBb_84dd5xks6Q@mail.gmail.com>
On Wed, Nov 14, 2012 at 2:45 AM, Haojian Zhuang
<haojian.zhuang@gmail.com> wrote:
> On Wed, Nov 14, 2012 at 1:34 AM, Tony Lindgren <tony@atomide.com> wrote:
>> * Linus Walleij <linus.walleij@linaro.org> [121113 05:10]:
>>> On Thu, Nov 8, 2012 at 2:25 AM, Tony Lindgren <tony@atomide.com> wrote:
>>>
>>> > * Haojian Zhuang <haojian.zhuang@gmail.com> [121107 07:22]:
>>> >> Dump pinmux register value, not only function part in the pinmux
>>> >> register.
>>> >>
>>> >> Also fix the issue on caluclating pin offset. The last parameter
>>> >> should be pin number, not register offset.
>>> >
>>> > Acked-by: Tony Lindgren <tony@atomide.com>
>>>
>>> Acked-by: Linus Walleij <linus.walleij@linaro.org>
>>>
>>> Shall I apply this to the pinctrl tree?
>>
>> Yes please.
>>
>> Regards,
>>
>> Tony
>
> Yes, this patch doesn't impact others. Please help to merge.
OK patch applied to the pinctrl tree.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH 1/2] arm/mm: L2CC shared mutex with ARM TZ
From: Etienne CARRIERE ST @ 2012-11-15 14:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121115135555.GC25985@arm.com>
If I understood well, you stated that on-going background operations on L2 can jeopardize PA operations.
So the secure code must insure other CPUs do not perform other L2 operations, including non-PA based operations.
Linux protects both PA and WAY operations using the very same spinlock.
We must hold this lock while performing any PA operations from secure world.
I am right ?
etienne
-----Original Message-----
From: Catalin Marinas [mailto:catalin.marinas at arm.com]
Sent: Thursday, November 15, 2012 2:56 PM
To: Etienne CARRIERE ST
Cc: Abhimanyu Kapur; Dave Martin; Rabin VINCENT; Russell King; Srinidhi KASAGAR; Marc Zyngier; Linus Walleij (linus.walleij at linaro.org); Will Deacon; linux-arm-kernel at lists.infradead.org
Subject: Re: [PATCH 1/2] arm/mm: L2CC shared mutex with ARM TZ
On Thu, Nov 15, 2012 at 01:46:29PM +0000, Etienne CARRIERE ST wrote:
> I think we will internally use our hack in l2x0 spin locking to
> prevent collision, based on old arch_spinlock support.
Or just handle the collision in the secure code and make sure you don't start background operations. If you don't use background operations, you don't need any locking.
--
Catalin
^ permalink raw reply
* [PATCH] ARM i.MX dts: Consistently add labels to devicenodes
From: Shawn Guo @ 2012-11-15 14:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121115133034.GD10369@pengutronix.de>
On Thu, Nov 15, 2012 at 02:30:34PM +0100, Sascha Hauer wrote:
> On Thu, Nov 15, 2012 at 09:48:33PM +0800, Shawn Guo wrote:
> > On Thu, Nov 15, 2012 at 09:31:52AM +0100, Sascha Hauer wrote:
> > > Having labels before each node allows board bindings to reference
> > > to nodes by using the &nodename {} notation.
> >
> > I can understand this part.
> >
> > > This way boards do not
> > > have to resemble the whole devicetree layout. Due to less indention
> > > needed the board files also get better readability.
> >
> > I do not understand it. Don't we have to always maintain the device
> > tree layout defined by <soc>.dtsi in <board>.dts, do we?
>
> Have a look at for example arch/arm/boot/dts/omap5-evm.dts, it is
> written like this:
>
> ...
>
> &mmc1 {
> vmmc-supply = <&vmmcsd_fixed>;
> bus-width = <4>;
> };
>
> &mmc2 {
> vmmc-supply = <&vmmcsd_fixed>;
> bus-width = <8>;
> ti,non-removable;
> };
>
> &mmc3 {
> bus-width = <4>;
> ti,non-removable;
> };
>
> ...
>
> I've written some board dts from scratch yesterday and this is much
> easier to write (and I think also easier to read as I don't have to
> care about the tree layout when writing a dts).
>
Ah, ok. I do not know this syntax before. Thanks. Just applied the
patch.
Shawn
^ permalink raw reply
* [PATCH 02/14] ARM: SPEAr13xx: DT: Add spics gpio controller nodes
From: Viresh Kumar @ 2012-11-15 14:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACRpkdaJ2kCYfSP=xCRQAG2wDnkMKX9fey+ByhDDiOS==u+XwA@mail.gmail.com>
On 15 November 2012 19:36, Linus Walleij <linus.walleij@linaro.org> wrote:
>>> > ahb {
>>> > + spics: spics at e0700000{
>>> > + compatible = "st,spear-spics-gpio";
>>> > + reg = <0xe0700000 0x1000>;
>>> > + st-spics,peripcfg-reg = <0x3b0>;
>>> > + st-spics,sw-enable-bit = <12>;
>>> > + st-spics,cs-value-bit = <11>;
>>> > + st-spics,cs-enable-mask = <3>;
>>> > + st-spics,cs-enable-shift = <8>;
>>> > + gpio-controller;
>>> > + #gpio-cells = <2>;
>>> > + };
>>> > +
>>>
>>> Are these bindings documented?
>>
>> The main patch waiting for ur comments is 1/14.
>
> I seldom comment on individual DT bindings, I just want
> to know that they're there :-)
Its not that simple. You are required to Ack it, as we have added it in
drivers/pinctrl/spear because we are controlling pins here :)
--
viresh
^ permalink raw reply
* [PATCH 02/14] ARM: SPEAr13xx: DT: Add spics gpio controller nodes
From: Linus Walleij @ 2012-11-15 14:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAKohpon=AVGZmR_cwUZ4=buw0kr3JVtXh51BtXteWkJ7E-f_bQ@mail.gmail.com>
On Tue, Nov 13, 2012 at 3:34 PM, Viresh Kumar <viresh.kumar@linaro.org> wrote:
> On Nov 13, 2012 7:38 PM, "Linus Walleij" <linus.walleij@linaro.org> wrote:
>> On Sun, Nov 11, 2012 at 5:39 AM, Viresh Kumar <viresh.kumar@linaro.org>
>> wrote:
>> > ahb {
>> > + spics: spics at e0700000{
>> > + compatible = "st,spear-spics-gpio";
>> > + reg = <0xe0700000 0x1000>;
>> > + st-spics,peripcfg-reg = <0x3b0>;
>> > + st-spics,sw-enable-bit = <12>;
>> > + st-spics,cs-value-bit = <11>;
>> > + st-spics,cs-enable-mask = <3>;
>> > + st-spics,cs-enable-shift = <8>;
>> > + gpio-controller;
>> > + #gpio-cells = <2>;
>> > + };
>> > +
>>
>> Are these bindings documented?
>
> The main patch waiting for ur comments is 1/14.
I seldom comment on individual DT bindings, I just want
to know that they're there :-)
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH] RFC: pinctrl: grab default handler with bus notifiers
From: Linus Walleij @ 2012-11-15 14:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121113063546.GD18224@opensource.wolfsonmicro.com>
On Tue, Nov 13, 2012 at 7:35 AM, Mark Brown
<broonie@opensource.wolfsonmicro.com> wrote:
> On Mon, Nov 12, 2012 at 01:21:40PM -0700, Stephen Warren wrote:
>> On 11/11/2012 05:22 AM, Linus Walleij wrote:
>
>> > Another solution that was discussed was whether to move
>> > the default pinctrl handle and state grab to the device
>> > core as an optional field in struct device itself, but
>> > I'd like to first propose this less intrusive mechanism.
>
>> I think doing that approach makes a lot more sense; wouldn't it
>> completely avoid the issues with deferred probe that this notifier-based
>> method can't solve? It would also be very much in line with e.g.
>> dev_get_regmap() - if every resource that a driver required were handled
>> like that, then deferred probe could be significantly isolated into the
>> driver core rather than in every driver...
>
> I have to say that I agree with this, notifiers seem to make life more
> complicated for limited gain. Otherwise I guess we could enhance
> notifiers so that they're able to trigger deferrals?
OK I'll have to come up with a patch to the device core
instead... it'll be much simpler anyway and if both of you guys
can back it I guess Greg might be OK with it too.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH 4/4] ARM: dts: imx: add imx5x phy-mode entries
From: Michael Grzeschik @ 2012-11-15 14:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352988014-14769-1-git-send-email-m.grzeschik@pengutronix.de>
Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
---
arch/arm/boot/dts/imx51.dtsi | 2 ++
arch/arm/boot/dts/imx53.dtsi | 2 ++
2 files changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 366b8d3..ffc6bc8 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -145,6 +145,7 @@
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
reg = <0x73f80200 0x0200>;
interrupts = <14>;
+ phy-mode = "utmiw";
status = "disabled";
};
@@ -152,6 +153,7 @@
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
reg = <0x73f80400 0x0200>;
interrupts = <16>;
+ phy-mode = "utmi";
status = "disabled";
};
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 2faa193..1da8e12 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -143,6 +143,7 @@
compatible = "fsl,imx53-usb", "fsl,imx27-usb";
reg = <0x53f80000 0x0200>;
interrupts = <18>;
+ phy-mode = "utmiw";
status = "disabled";
};
@@ -150,6 +151,7 @@
compatible = "fsl,imx53-usb", "fsl,imx27-usb";
reg = <0x53f80200 0x0200>;
interrupts = <14>;
+ phy-mode = "utmi";
status = "disabled";
};
--
1.7.10.4
^ permalink raw reply related
* [PATCH 3/4] ARM: dts: imx: rename imx5x usb entries as in imx6q.dtsi
From: Michael Grzeschik @ 2012-11-15 14:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352988014-14769-1-git-send-email-m.grzeschik@pengutronix.de>
Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
---
arch/arm/boot/dts/imx51.dtsi | 12 ++++++++----
arch/arm/boot/dts/imx53.dtsi | 12 ++++++++----
2 files changed, 16 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 75d069f..366b8d3 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -21,6 +21,10 @@
gpio1 = &gpio2;
gpio2 = &gpio3;
gpio3 = &gpio4;
+ usb0 = &usbotg;
+ usb1 = &usbhost1;
+ usb2 = &usbhost2;
+ usb3 = &usbhost3;
};
tzic: tz-interrupt-controller at e0000000 {
@@ -130,28 +134,28 @@
};
};
- usb at 73f80000 {
+ usbotg: usb at 73f80000 {
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
reg = <0x73f80000 0x0200>;
interrupts = <18>;
status = "disabled";
};
- usb at 73f80200 {
+ usbhost1: usb at 73f80200 {
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
reg = <0x73f80200 0x0200>;
interrupts = <14>;
status = "disabled";
};
- usb at 73f80400 {
+ usbhost2: usb at 73f80400 {
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
reg = <0x73f80400 0x0200>;
interrupts = <16>;
status = "disabled";
};
- usb at 73f80600 {
+ usbhost3: usb at 73f80600 {
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
reg = <0x73f80600 0x0200>;
interrupts = <17>;
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 76ebb1a..2faa193 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -26,6 +26,10 @@
gpio4 = &gpio5;
gpio5 = &gpio6;
gpio6 = &gpio7;
+ usb0 = &usbotg;
+ usb1 = &usbhost1;
+ usb2 = &usbhost2;
+ usb3 = &usbhost3;
};
tzic: tz-interrupt-controller at 0fffc000 {
@@ -135,28 +139,28 @@
};
};
- usb at 53f80000 {
+ usbotg: usb at 53f80000 {
compatible = "fsl,imx53-usb", "fsl,imx27-usb";
reg = <0x53f80000 0x0200>;
interrupts = <18>;
status = "disabled";
};
- usb at 53f80200 {
+ usbhost1: usb at 53f80200 {
compatible = "fsl,imx53-usb", "fsl,imx27-usb";
reg = <0x53f80200 0x0200>;
interrupts = <14>;
status = "disabled";
};
- usb at 53f80400 {
+ usbhost2: usb at 53f80400 {
compatible = "fsl,imx53-usb", "fsl,imx27-usb";
reg = <0x53f80400 0x0200>;
interrupts = <16>;
status = "disabled";
};
- usb at 53f80600 {
+ usbhost3: usb at 53f80600 {
compatible = "fsl,imx53-usb", "fsl,imx27-usb";
reg = <0x53f80600 0x0200>;
interrupts = <17>;
--
1.7.10.4
^ permalink raw reply related
* [PATCH 2/4] ARM: imx: add imx5x usbmisc clock lookups
From: Michael Grzeschik @ 2012-11-15 14:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352988014-14769-1-git-send-email-m.grzeschik@pengutronix.de>
Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
---
arch/arm/mach-imx/clk-imx51-imx53.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index 3edd11c..33c3c9b 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -365,6 +365,9 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
clk_register_clkdev(clk[usboh3_per_gate], "per", "73f80000.usb");
clk_register_clkdev(clk[usboh3_gate], "ipg", "73f80000.usb");
clk_register_clkdev(clk[usboh3_gate], "ahb", "73f80000.usb");
+ clk_register_clkdev(clk[usboh3_per_gate], "per", "73f80800.usbmisc");
+ clk_register_clkdev(clk[usboh3_gate], "ipg", "73f80800.usbmisc");
+ clk_register_clkdev(clk[usboh3_gate], "ahb", "73f80800.usbmisc");
clk_register_clkdev(clk[usb_phy_gate], "phy", "mxc-ehci.0");
clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx51.0");
clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.0");
@@ -470,6 +473,9 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
clk_register_clkdev(clk[usboh3_per_gate], "per", "53f80000.usb");
clk_register_clkdev(clk[usboh3_gate], "ipg", "53f80000.usb");
clk_register_clkdev(clk[usboh3_gate], "ahb", "53f80000.usb");
+ clk_register_clkdev(clk[usboh3_per_gate], "per", "53f80800.usbmisc");
+ clk_register_clkdev(clk[usboh3_gate], "ipg", "53f80800.usbmisc");
+ clk_register_clkdev(clk[usboh3_gate], "ahb", "53f80800.usbmisc");
clk_register_clkdev(clk[usb_phy1_gate], "usb_phy1", "mxc-ehci.0");
clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx53.0");
clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.0");
--
1.7.10.4
^ permalink raw reply related
* [PATCH 1/4] ARM: imx: add imx5x usb controller clock lookups
From: Michael Grzeschik @ 2012-11-15 14:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352988014-14769-1-git-send-email-m.grzeschik@pengutronix.de>
Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
---
arch/arm/mach-imx/clk-imx51-imx53.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index a0bf848..3edd11c 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -353,6 +353,18 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
clk_register_clkdev(clk[ipu_di0_gate], "di0", "imx51-ipu");
clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx51-ipu");
clk_register_clkdev(clk[ipu_gate], "hsp", "imx51-ipu");
+ clk_register_clkdev(clk[usboh3_per_gate], "per", "73f80600.usb");
+ clk_register_clkdev(clk[usboh3_gate], "ipg", "73f80600.usb");
+ clk_register_clkdev(clk[usboh3_gate], "ahb", "73f80600.usb");
+ clk_register_clkdev(clk[usboh3_per_gate], "per", "73f80400.usb");
+ clk_register_clkdev(clk[usboh3_gate], "ipg", "73f80400.usb");
+ clk_register_clkdev(clk[usboh3_gate], "ahb", "73f80400.usb");
+ clk_register_clkdev(clk[usboh3_per_gate], "per", "73f80200.usb");
+ clk_register_clkdev(clk[usboh3_gate], "ipg", "73f80200.usb");
+ clk_register_clkdev(clk[usboh3_gate], "ahb", "73f80200.usb");
+ clk_register_clkdev(clk[usboh3_per_gate], "per", "73f80000.usb");
+ clk_register_clkdev(clk[usboh3_gate], "ipg", "73f80000.usb");
+ clk_register_clkdev(clk[usboh3_gate], "ahb", "73f80000.usb");
clk_register_clkdev(clk[usb_phy_gate], "phy", "mxc-ehci.0");
clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx51.0");
clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.0");
@@ -446,6 +458,18 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
clk_register_clkdev(clk[ipu_di0_gate], "di0", "imx53-ipu");
clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx53-ipu");
clk_register_clkdev(clk[ipu_gate], "hsp", "imx53-ipu");
+ clk_register_clkdev(clk[usboh3_per_gate], "per", "53f80600.usb");
+ clk_register_clkdev(clk[usboh3_gate], "ipg", "53f80600.usb");
+ clk_register_clkdev(clk[usboh3_gate], "ahb", "53f80600.usb");
+ clk_register_clkdev(clk[usboh3_per_gate], "per", "53f80400.usb");
+ clk_register_clkdev(clk[usboh3_gate], "ipg", "53f80400.usb");
+ clk_register_clkdev(clk[usboh3_gate], "ahb", "53f80400.usb");
+ clk_register_clkdev(clk[usboh3_per_gate], "per", "53f80200.usb");
+ clk_register_clkdev(clk[usboh3_gate], "ipg", "53f80200.usb");
+ clk_register_clkdev(clk[usboh3_gate], "ahb", "53f80200.usb");
+ clk_register_clkdev(clk[usboh3_per_gate], "per", "53f80000.usb");
+ clk_register_clkdev(clk[usboh3_gate], "ipg", "53f80000.usb");
+ clk_register_clkdev(clk[usboh3_gate], "ahb", "53f80000.usb");
clk_register_clkdev(clk[usb_phy1_gate], "usb_phy1", "mxc-ehci.0");
clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx53.0");
clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.0");
--
1.7.10.4
^ permalink raw reply related
* [PATCH 0/4] mx5x usb{misc} devictree bindings and clocks
From: Michael Grzeschik @ 2012-11-15 14:00 UTC (permalink / raw)
To: linux-arm-kernel
Michael Grzeschik (4):
ARM: imx: add imx5x usb controller clock lookups
ARM: imx: add imx5x usbmisc clock lookups
ARM: dts: imx: rename imx5x usb entries as in imx6q.dtsi
ARM: dts: imx: add imx5x phy-mode entries
arch/arm/boot/dts/imx51.dtsi | 14 ++++++++++----
arch/arm/boot/dts/imx53.dtsi | 14 ++++++++++----
arch/arm/mach-imx/clk-imx51-imx53.c | 30 ++++++++++++++++++++++++++++++
3 files changed, 50 insertions(+), 8 deletions(-)
--
1.7.10.4
^ permalink raw reply
* [PATCH 1/4] pinctrl: dove: Prevent NULL dereference if of_match_device returns NULL
From: Thomas Petazzoni @ 2012-11-15 13:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAFRkauCybE+UcBD17u3J6hoxEA88GM0tatxkrKtWqVNvDPC9dA@mail.gmail.com>
Dear Axel Lin,
On Thu, 15 Nov 2012 21:44:07 +0800, Axel Lin wrote:
> BTW, I found there is no way to compile the dove and kirkwood pinctrl
> drivers.
> I need add below patch to compile these two drivers, how do you think about
> below patch?
> ( In dove, the USE_OF is optional, it is selected only when MACH_DOVE_DT is
> enabled )
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 14f8160..dda6785 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -531,6 +531,8 @@ config ARCH_DOVE
> select CPU_V7
> select GENERIC_CLOCKEVENTS
> select MIGHT_HAVE_PCI
> + select PINCTRL
> + select PINCTRL_DOVE if USE_OF
> select PLAT_ORION_LEGACY
> select USB_ARCH_HAS_EHCI
> help
> @@ -542,6 +544,8 @@ config ARCH_KIRKWOOD
> select CPU_FEROCEON
> select GENERIC_CLOCKEVENTS
> select PCI
> + select PINCTRL
> + select PINCTRL_KIRKWOOD
> select PLAT_ORION_LEGACY
> help
> Support for the following Marvell Kirkwood series SoCs:
See "[PATCH 1/5] ARM: Kirkwood: Allow use of pinctrl" and "[PATCH 4/5]
ARM: Dove: Make use of pinctrl driver" which have been posted by Andrew
Lunn on October, 24th.
Best regards,
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply
* [PATCH 1/2] arm/mm: L2CC shared mutex with ARM TZ
From: Catalin Marinas @ 2012-11-15 13:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <0154077FE026E54BB093CA7EB3FD1AE32DB6A63266@SAFEX1MAIL3.st.com>
On Thu, Nov 15, 2012 at 01:46:29PM +0000, Etienne CARRIERE ST wrote:
> I think we will internally use our hack in l2x0 spin locking to
> prevent collision, based on old arch_spinlock support.
Or just handle the collision in the secure code and make sure you don't
start background operations. If you don't use background operations, you
don't need any locking.
--
Catalin
^ permalink raw reply
* [PATCH 2/2] clocksource/mtu-nomadik: use apb_pclk
From: Linus Walleij @ 2012-11-15 13:55 UTC (permalink / raw)
To: linux-arm-kernel
From: Ulf Hansson <ulf.hansson@linaro.org>
After improving the clock tree we need to make sure the the
MTU timer explicitly grabs and enables it silicon clock
(pclk).
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Mike Turquette <mturquette@ti.com>
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
---
This version of the patch is based upon the ux500
SPARSE_IRQ commit and is intended to be merged after [1/2]
so as to avoid conflicts between the clk and ARM SoC trees.
---
drivers/clocksource/nomadik-mtu.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/clocksource/nomadik-mtu.c b/drivers/clocksource/nomadik-mtu.c
index 23c780b..8914c3c 100644
--- a/drivers/clocksource/nomadik-mtu.c
+++ b/drivers/clocksource/nomadik-mtu.c
@@ -177,9 +177,15 @@ void nmdk_clksrc_reset(void)
void __init nmdk_timer_init(void __iomem *base, int irq)
{
unsigned long rate;
- struct clk *clk0;
+ struct clk *clk0, *pclk0;
mtu_base = base;
+
+ pclk0 = clk_get_sys("mtu0", "apb_pclk");
+ BUG_ON(IS_ERR(pclk0));
+ BUG_ON(clk_prepare(pclk0) < 0);
+ BUG_ON(clk_enable(pclk0) < 0);
+
clk0 = clk_get_sys("mtu0", NULL);
BUG_ON(IS_ERR(clk0));
BUG_ON(clk_prepare(clk0) < 0);
--
1.7.11.3
^ permalink raw reply related
* [PATCH 1/2] clk: ux500: Register mtu apb_pclocks
From: Linus Walleij @ 2012-11-15 13:55 UTC (permalink / raw)
To: linux-arm-kernel
From: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Mike Turquette <mturquette@ti.com>
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
---
drivers/clk/ux500/u8500_clk.c | 9 +++------
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/ux500/u8500_clk.c b/drivers/clk/ux500/u8500_clk.c
index ab30ce8..1f6bfb8 100644
--- a/drivers/clk/ux500/u8500_clk.c
+++ b/drivers/clk/ux500/u8500_clk.c
@@ -160,12 +160,6 @@ void u8500_clk_init(void)
clk = clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, CLK_IS_ROOT);
clk_register_clkdev(clk, NULL, "uicc");
- /*
- * FIXME: The MTU clocks might need some kind of "parent muxed join"
- * and these have no K-clocks. For now, we ignore the missing
- * connection to the corresponding P-clocks, p6_mtu0_clk and
- * p6_mtu1_clk. Instead timclk is used which is the valid parent.
- */
clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, CLK_IS_ROOT);
clk_register_clkdev(clk, NULL, "mtu0");
clk_register_clkdev(clk, NULL, "mtu1");
@@ -379,8 +373,11 @@ void u8500_clk_init(void)
clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", U8500_CLKRST6_BASE,
BIT(6), 0);
+ clk_register_clkdev(clk, "apb_pclk", "mtu0");
+
clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", U8500_CLKRST6_BASE,
BIT(7), 0);
+ clk_register_clkdev(clk, "apb_pclk", "mtu1");
/* PRCC K-clocks
*
--
1.7.11.3
^ permalink raw reply related
* [PATCH 6/6] usb: chipidea: usbmisc: add post handling and errata fix for mx25
From: Marc Kleine-Budde @ 2012-11-15 13:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CALBypN7-NKFmoPXWA0utFhUjLOWjvzwJ7ZSuQBa+W5edNQA_OA@mail.gmail.com>
On 11/15/2012 02:51 PM, Martin Fuzzey wrote:
>> This is because that series is based on Peter Chen's work. I should have
>> mentioned this in the cover-letter mail. You can merge his master branch
>> before adding my series:
>
> Ok thanks for the very rapid reply.
>
> I've now built this together with patch 2 "ci13xxx_imx: add 2nd and
> 3rd clock to support imx5x and newer" from your other series.
> But it hangs because the usb-phy clock is not being enabled.
> If I add a clock enable for that clock too to usbmisc_imx.c it works
> but that can't be the right way.
>
> Who is supposed to enable the phy clock?
> [I'm using the OTG port in host only mode on i.MX53 with "nop-usbphy"]
>
> Here's what I did (illustration only, probably white space broken):
We've have a patch that the missing clock handling to the nop phy
driver, which isn't much better. What are other possible options?
Marc
--
Pengutronix e.K. | Marc Kleine-Budde |
Industrial Linux Solutions | Phone: +49-231-2826-924 |
Vertretung West/Dortmund | Fax: +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686 | http://www.pengutronix.de |
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^ permalink raw reply
* [PATCH] ARM: Fix errata 751472 handling on Cortex-A9 r1p*
From: Catalin Marinas @ 2012-11-15 13:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACY+gR3PurUofCbUeG40B6vXqXAoHrMmbOQSuwAGoc1LS8XXJQ@mail.gmail.com>
On Thu, Nov 15, 2012 at 12:41:43PM +0000, Siarhei Siamashka wrote:
> On Thu, Nov 15, 2012 at 1:01 PM, Catalin Marinas
> <catalin.marinas@arm.com> wrote:
> > On Thu, Nov 15, 2012 at 12:54:48AM +0000, Rob Herring wrote:
> >> On 11/14/2012 04:21 PM, Tony Lindgren wrote:
> >> > * Rob Herring <robherring2@gmail.com> [121114 13:59]:
> >> >> On 11/14/2012 02:32 PM, Tony Lindgren wrote:
> >> >>>
> >> >>> Checking for the bit already set should work in this case, I'll post
> >> >>> a patch for that shortly.
> >> >>
> >> >> Can you actually read the state of the diagnostic register in non-secure
> >> >> mode? If you can on the A9, is the same true on A8 or others?
> >> >
> >> > Looks like it can be read on at least TI omap 4430 which is A9.
> >> > But it reads as zero, so the below patch is what I came up with.
> >> >
> >> > No idea if assuming that zero value for the diagnostic register
> >> > is safe.. What's the default value of the diagnostic register supposed
> >> > to be?
> >>
> >> RTFM. Oh, wait it's a super secret, undocumented register. We shouldn't
> >> even be talking about it.
> >>
> >> It could vary by rev, but I see 0 for the reset value, so this would not
> >> work if the bootloader did not do any setup of the diagnostic register.
> >>
> >> One way to determine secure mode on the A9 would be seeing if you can
> >> change the auxcr register. Something like this (untested):
> >>
> >> mrc p15, 0, r0, c1, c0, 1; Read ACTLR
> >> eor r1, r0, #0x100 ; Modify alloc in 1 way
> >> mcr p15, 0, r1, c1, c0, 1
> >> mrc p15, 0, r2, c1, c0, 1; Read ACTLR
> >> mcr p15, 0, r0, c1, c0, 1 ; Restore original value
> >> cmp r1, r2
> >> bne skip_errata
> >
> > This would fail on platforms where Linux runs in non-secure mode. What
> > we do for some errata workarounds is to test whether the bit was already
> > set and avoid writing the register. But this assumes that, for a given
> > workaround in the kernel, there is a corresponding workaround in the
> > code running before the kernel (boot-loader, firmware) which sets that
> > bit.
> >
> > Since the kernel will run more often in non-secure mode (on Cortex-A15
> > you need this for the virtualisation extensions) I strongly suggest that
> > the workaround (usually undocumented bit setting) is done before the
> > kernel is started and we simply remove it from Linux (or add a clear
> > comment that it only works if running in secure mode; if unsure say
> > 'N').
> >
> > I don't think it's worth the hassle detecting whether the kernel runs in
> > secure or non-secure mode, just assume the latter and get SoC vendors to
> > update the boot loaders or firmware (if possible) with any errata
> > workarounds.
> >
> > Having a common SMC API for errata workarounds is not feasible since not
> > all registers are public, most are implementation specific and it could
> > have secure implications with exposing them.
>
> BTW, I always wondered about what could be preventing TI and the other
> silicon vendors from using something like an SMC API based on
> asymmetric cryptography? My understanding is that for OMAP4 GP chips,
> ROM code switches to non-secure mode before passing control to the
> bootloader and there is simply no way to workaround bugs like this.
AFAIK, there are some SMCs to the OMAP secure firmware that allow such
bits to be set (see omap4_l2x0_set_debug() for example). I'm not sure
they are documented.
But we can't have a standard SMC API since the registers affected are
not standard (nor documented). Which means that such workarounds must be
applied in the bootloader specific to that platform. Even if it is
running in non-secure mode, it can be made aware of the SMC API provided
by the secure firmware.
--
Catalin
^ permalink raw reply
* [PATCH 1/2] Boottime: A tool for automatic measurement of kernel/bootloader boot time
From: Andrew Murray @ 2012-11-15 13:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352973847-21605-2-git-send-email-lee.jones@linaro.org>
On 15 November 2012 10:04, Lee Jones <lee.jones@linaro.org> wrote:
> The overhead is very low and the results will be found under
> sysfs/bootime, as well as detailed results in debugfs under
> boottime/. The bootgraph* files are compatible with
> scripts/bootgraph.pl. The reason for this patch is to provide
> data (sysfs/boottime) suitable for automatic test-cases as
> well as help for developers to reduce the boot time (debugfs).
>
> Based heavily on the original driver by Jonas Aaberg.
>
> +
> +static LIST_HEAD(boottime_list);
> +static DEFINE_SPINLOCK(boottime_list_lock);
> +static struct boottime_timer boottime_timer;
> +static int num_const_boottime_list;
> +static struct boottime_list const_boottime_list[NUM_STATIC_BOOTTIME_ENTRIES];
> +static unsigned long time_kernel_done;
> +static unsigned long time_bootloader_done;
> +static bool system_up;
> +static bool boottime_done;
> +
> +int __attribute__((weak)) boottime_arch_startup(void)
> +{
> + return 0;
> +}
> +
> +int __attribute__((weak)) boottime_bootloader_idle(void)
> +{
> + return 0;
> +}
You may wish to use the __weak macro (include/linux/compiler*) instead
of directly using GCC attributes here.
Andrew Murray
^ permalink raw reply
* [PATCH 6/6] usb: chipidea: usbmisc: add post handling and errata fix for mx25
From: Martin Fuzzey @ 2012-11-15 13:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121115102525.GA16118@pengutronix.de>
> This is because that series is based on Peter Chen's work. I should have
> mentioned this in the cover-letter mail. You can merge his master branch
> before adding my series:
Ok thanks for the very rapid reply.
I've now built this together with patch 2 "ci13xxx_imx: add 2nd and
3rd clock to support imx5x and newer" from your other series.
But it hangs because the usb-phy clock is not being enabled.
If I add a clock enable for that clock too to usbmisc_imx.c it works
but that can't be the right way.
Who is supposed to enable the phy clock?
[I'm using the OTG port in host only mode on i.MX53 with "nop-usbphy"]
Here's what I did (illustration only, probably white space broken):
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c
b/arch/arm/mach-imx/clk-imx51-imx53.c
index cd6d7a0..2f0687a 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -492,6 +492,7 @@ int __init mx53_clocks_init(unsigned long
rate_ckil, unsigned long rate_osc,
clk_register_clkdev(clk[usboh3_per_gate], "per", "53f80800.usbmisc");
clk_register_clkdev(clk[usboh3_gate], "ipg", "53f80800.usbmisc");
clk_register_clkdev(clk[usboh3_gate], "ahb", "53f80800.usbmisc");
+ clk_register_clkdev(clk[usb_phy1_gate], "phy1",
"53f80800.usbmisc"); // MF
clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx53.0");
clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.0");
clk_register_clkdev(clk[esdhc1_per_gate], "per", "sdhci-esdhc-imx53.0");
diff --git a/drivers/usb/chipidea/usbmisc_imx.c
b/drivers/usb/chipidea/usbmisc_imx.c
index acca109..a59093a 100644
--- a/drivers/usb/chipidea/usbmisc_imx.c
+++ b/drivers/usb/chipidea/usbmisc_imx.c
@@ -197,6 +197,24 @@ static int __devinit usbmisc_imx_probe(struct
platform_device *pdev)
if (ret)
goto err_per_failed;
+
+ { /* Temp Hack by MF awaiting reply on mailing list */
+ struct clk *phy_clk;
+
+ dev_info(&pdev->dev, "@MF@ hacking phy clock enable\n");
+ phy_clk = devm_clk_get(&pdev->dev, "phy1");
+ if (IS_ERR(phy_clk)) {
+ dev_err(&pdev->dev, "failed to get PHY clock,
err=%ld\n", PTR_ERR(phy_clk));
+ goto err_per_failed;
+ }
+
+ ret = clk_prepare_enable(phy_clk);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to enable PHY
clock, err=%d\n", ret);
+ goto err_per_failed;
+ }
+ }
+
tmp_dev = (struct of_device_id *)
of_match_device(usbmisc_imx_dt_ids, &pdev->dev);
data->ops = (const struct usbmisc_ops *)tmp_dev->data;
^ permalink raw reply related
* [PATCH v3 1/5] ARM: kernel: smp_setup_processor_id() updates
From: Will Deacon @ 2012-11-15 13:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352983614-22924-2-git-send-email-lorenzo.pieralisi@arm.com>
On Thu, Nov 15, 2012 at 12:46:50PM +0000, Lorenzo Pieralisi wrote:
> This patch applies some basic changes to the smp_setup_processor_id()
> ARM implementation to make the code that builds cpu_logical_map more
> uniform across the kernel.
>
> The function now prints the full extent of the boot CPU MPIDR[23:0] and
> initializes the cpu_logical_map for CPUs up to nr_cpu_ids.
>
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> ---
> arch/arm/kernel/setup.c | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
> index da1d1aa..d0df6c8 100644
> --- a/arch/arm/kernel/setup.c
> +++ b/arch/arm/kernel/setup.c
> @@ -426,13 +426,14 @@ int __cpu_logical_map[NR_CPUS];
> void __init smp_setup_processor_id(void)
> {
> int i;
> - u32 cpu = is_smp() ? read_cpuid_mpidr() & 0xff : 0;
> + u32 mpidr = is_smp() ? read_cpuid_mpidr() & 0xffffff : 0;
> + u32 cpu = mpidr & 0xff;
Can we move the #defines out of topology.c and use those instead of magic
masks please? You could use MPIDR_HWID_BITMASK, although the LEVEL mask
definitions over there don't look right to me (MPIDR_LEVEL0_MASK is 0x3?)
Will
^ permalink raw reply
* [PATCH] ARM i.MX dts: Consistently add labels to devicenodes
From: Shawn Guo @ 2012-11-15 13:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352968312-8321-1-git-send-email-s.hauer@pengutronix.de>
On Thu, Nov 15, 2012 at 09:31:52AM +0100, Sascha Hauer wrote:
> Having labels before each node allows board bindings to reference
> to nodes by using the &nodename {} notation.
I can understand this part.
> This way boards do not
> have to resemble the whole devicetree layout. Due to less indention
> needed the board files also get better readability.
I do not understand it. Don't we have to always maintain the device
tree layout defined by <soc>.dtsi in <board>.dts, do we?
> Since the label
> make the documentation behind the nodes unnecessary it is removed.
>
I can also understand this part.
Shawn
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
> arch/arm/boot/dts/imx27.dtsi | 5 ++-
> arch/arm/boot/dts/imx51.dtsi | 40 +++++++++----------
> arch/arm/boot/dts/imx53.dtsi | 42 ++++++++++----------
> arch/arm/boot/dts/imx6q.dtsi | 88 +++++++++++++++++++++---------------------
> 4 files changed, 88 insertions(+), 87 deletions(-)
>
> diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
> index 3e54f14..4192e87 100644
> --- a/arch/arm/boot/dts/imx27.dtsi
> +++ b/arch/arm/boot/dts/imx27.dtsi
> @@ -58,7 +58,7 @@
> reg = <0x10000000 0x10000000>;
> ranges;
>
> - wdog at 10002000 {
> + wdog: wdog at 10002000 {
> compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
> reg = <0x10002000 0x4000>;
> interrupts = <27>;
> @@ -218,7 +218,8 @@
> status = "disabled";
> };
> };
> - nand at d8000000 {
> +
> + nfc: nand at d8000000 {
> #address-cells = <1>;
> #size-cells = <1>;
>
> diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
> index 75d069f..9fd7657 100644
> --- a/arch/arm/boot/dts/imx51.dtsi
> +++ b/arch/arm/boot/dts/imx51.dtsi
> @@ -76,14 +76,14 @@
> reg = <0x70000000 0x40000>;
> ranges;
>
> - esdhc at 70004000 { /* ESDHC1 */
> + esdhc1: esdhc at 70004000 {
> compatible = "fsl,imx51-esdhc";
> reg = <0x70004000 0x4000>;
> interrupts = <1>;
> status = "disabled";
> };
>
> - esdhc at 70008000 { /* ESDHC2 */
> + esdhc2: esdhc at 70008000 {
> compatible = "fsl,imx51-esdhc";
> reg = <0x70008000 0x4000>;
> interrupts = <2>;
> @@ -97,7 +97,7 @@
> status = "disabled";
> };
>
> - ecspi at 70010000 { /* ECSPI1 */
> + ecspi1: ecspi at 70010000 {
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "fsl,imx51-ecspi";
> @@ -115,14 +115,14 @@
> status = "disabled";
> };
>
> - esdhc at 70020000 { /* ESDHC3 */
> + esdhc3: esdhc at 70020000 {
> compatible = "fsl,imx51-esdhc";
> reg = <0x70020000 0x4000>;
> interrupts = <3>;
> status = "disabled";
> };
>
> - esdhc at 70024000 { /* ESDHC4 */
> + esdhc4: esdhc at 70024000 {
> compatible = "fsl,imx51-esdhc";
> reg = <0x70024000 0x4000>;
> interrupts = <4>;
> @@ -130,28 +130,28 @@
> };
> };
>
> - usb at 73f80000 {
> + usbotg: usb at 73f80000 {
> compatible = "fsl,imx51-usb", "fsl,imx27-usb";
> reg = <0x73f80000 0x0200>;
> interrupts = <18>;
> status = "disabled";
> };
>
> - usb at 73f80200 {
> + usbh1: usb at 73f80200 {
> compatible = "fsl,imx51-usb", "fsl,imx27-usb";
> reg = <0x73f80200 0x0200>;
> interrupts = <14>;
> status = "disabled";
> };
>
> - usb at 73f80400 {
> + usbh2: usb at 73f80400 {
> compatible = "fsl,imx51-usb", "fsl,imx27-usb";
> reg = <0x73f80400 0x0200>;
> interrupts = <16>;
> status = "disabled";
> };
>
> - usb at 73f80600 {
> + usbh3: usb at 73f80600 {
> compatible = "fsl,imx51-usb", "fsl,imx27-usb";
> reg = <0x73f80600 0x0200>;
> interrupts = <17>;
> @@ -198,20 +198,20 @@
> #interrupt-cells = <2>;
> };
>
> - wdog at 73f98000 { /* WDOG1 */
> + wdog1: wdog at 73f98000 {
> compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
> reg = <0x73f98000 0x4000>;
> interrupts = <58>;
> };
>
> - wdog at 73f9c000 { /* WDOG2 */
> + wdog2: wdog at 73f9c000 {
> compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
> reg = <0x73f9c000 0x4000>;
> interrupts = <59>;
> status = "disabled";
> };
>
> - iomuxc at 73fa8000 {
> + iomuxc: iomuxc at 73fa8000 {
> compatible = "fsl,imx51-iomuxc";
> reg = <0x73fa8000 0x4000>;
>
> @@ -349,7 +349,7 @@
> reg = <0x80000000 0x10000000>;
> ranges;
>
> - ecspi at 83fac000 { /* ECSPI2 */
> + ecspi2: ecspi at 83fac000 {
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "fsl,imx51-ecspi";
> @@ -358,14 +358,14 @@
> status = "disabled";
> };
>
> - sdma at 83fb0000 {
> + sdma: sdma at 83fb0000 {
> compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
> reg = <0x83fb0000 0x4000>;
> interrupts = <6>;
> fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
> };
>
> - cspi at 83fc0000 {
> + cspi: cspi at 83fc0000 {
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
> @@ -374,7 +374,7 @@
> status = "disabled";
> };
>
> - i2c at 83fc4000 { /* I2C2 */
> + i2c2: i2c at 83fc4000 {
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "fsl,imx51-i2c", "fsl,imx1-i2c";
> @@ -383,7 +383,7 @@
> status = "disabled";
> };
>
> - i2c at 83fc8000 { /* I2C1 */
> + i2c1: i2c at 83fc8000 {
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "fsl,imx51-i2c", "fsl,imx1-i2c";
> @@ -401,13 +401,13 @@
> status = "disabled";
> };
>
> - audmux at 83fd0000 {
> + audmux: audmux at 83fd0000 {
> compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
> reg = <0x83fd0000 0x4000>;
> status = "disabled";
> };
>
> - nand at 83fdb000 {
> + nfc: nand at 83fdb000 {
> compatible = "fsl,imx51-nand";
> reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
> interrupts = <8>;
> @@ -423,7 +423,7 @@
> status = "disabled";
> };
>
> - ethernet at 83fec000 {
> + fec: ethernet at 83fec000 {
> compatible = "fsl,imx51-fec", "fsl,imx27-fec";
> reg = <0x83fec000 0x4000>;
> interrupts = <87>;
> diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
> index 76ebb1a..08effd1 100644
> --- a/arch/arm/boot/dts/imx53.dtsi
> +++ b/arch/arm/boot/dts/imx53.dtsi
> @@ -81,14 +81,14 @@
> reg = <0x50000000 0x40000>;
> ranges;
>
> - esdhc at 50004000 { /* ESDHC1 */
> + esdhc1: esdhc at 50004000 {
> compatible = "fsl,imx53-esdhc";
> reg = <0x50004000 0x4000>;
> interrupts = <1>;
> status = "disabled";
> };
>
> - esdhc at 50008000 { /* ESDHC2 */
> + esdhc2: esdhc at 50008000 {
> compatible = "fsl,imx53-esdhc";
> reg = <0x50008000 0x4000>;
> interrupts = <2>;
> @@ -102,7 +102,7 @@
> status = "disabled";
> };
>
> - ecspi at 50010000 { /* ECSPI1 */
> + ecspi1: ecspi at 50010000 {
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
> @@ -120,14 +120,14 @@
> status = "disabled";
> };
>
> - esdhc at 50020000 { /* ESDHC3 */
> + esdhc3: esdhc at 50020000 {
> compatible = "fsl,imx53-esdhc";
> reg = <0x50020000 0x4000>;
> interrupts = <3>;
> status = "disabled";
> };
>
> - esdhc at 50024000 { /* ESDHC4 */
> + esdhc4: esdhc at 50024000 {
> compatible = "fsl,imx53-esdhc";
> reg = <0x50024000 0x4000>;
> interrupts = <4>;
> @@ -135,28 +135,28 @@
> };
> };
>
> - usb at 53f80000 {
> + usbotg: usb at 53f80000 {
> compatible = "fsl,imx53-usb", "fsl,imx27-usb";
> reg = <0x53f80000 0x0200>;
> interrupts = <18>;
> status = "disabled";
> };
>
> - usb at 53f80200 {
> + usbh1: usb at 53f80200 {
> compatible = "fsl,imx53-usb", "fsl,imx27-usb";
> reg = <0x53f80200 0x0200>;
> interrupts = <14>;
> status = "disabled";
> };
>
> - usb at 53f80400 {
> + usbh2: usb at 53f80400 {
> compatible = "fsl,imx53-usb", "fsl,imx27-usb";
> reg = <0x53f80400 0x0200>;
> interrupts = <16>;
> status = "disabled";
> };
>
> - usb at 53f80600 {
> + usbh3: usb at 53f80600 {
> compatible = "fsl,imx53-usb", "fsl,imx27-usb";
> reg = <0x53f80600 0x0200>;
> interrupts = <17>;
> @@ -203,20 +203,20 @@
> #interrupt-cells = <2>;
> };
>
> - wdog at 53f98000 { /* WDOG1 */
> + wdog1: wdog at 53f98000 {
> compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
> reg = <0x53f98000 0x4000>;
> interrupts = <58>;
> };
>
> - wdog at 53f9c000 { /* WDOG2 */
> + wdog2: wdog at 53f9c000 {
> compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
> reg = <0x53f9c000 0x4000>;
> interrupts = <59>;
> status = "disabled";
> };
>
> - iomuxc at 53fa8000 {
> + iomuxc: iomuxc at 53fa8000 {
> compatible = "fsl,imx53-iomuxc";
> reg = <0x53fa8000 0x4000>;
>
> @@ -429,7 +429,7 @@
> #interrupt-cells = <2>;
> };
>
> - i2c at 53fec000 { /* I2C3 */
> + i2c3: i2c at 53fec000 {
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
> @@ -460,7 +460,7 @@
> status = "disabled";
> };
>
> - ecspi at 63fac000 { /* ECSPI2 */
> + ecspi2: ecspi at 63fac000 {
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
> @@ -469,14 +469,14 @@
> status = "disabled";
> };
>
> - sdma at 63fb0000 {
> + sdma: sdma at 63fb0000 {
> compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
> reg = <0x63fb0000 0x4000>;
> interrupts = <6>;
> fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
> };
>
> - cspi at 63fc0000 {
> + cspi: cspi at 63fc0000 {
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
> @@ -485,7 +485,7 @@
> status = "disabled";
> };
>
> - i2c at 63fc4000 { /* I2C2 */
> + i2c2: i2c at 63fc4000 {
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
> @@ -494,7 +494,7 @@
> status = "disabled";
> };
>
> - i2c at 63fc8000 { /* I2C1 */
> + i2c1: i2c at 63fc8000 {
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
> @@ -512,13 +512,13 @@
> status = "disabled";
> };
>
> - audmux at 63fd0000 {
> + audmux: audmux at 63fd0000 {
> compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
> reg = <0x63fd0000 0x4000>;
> status = "disabled";
> };
>
> - nand at 63fdb000 {
> + nfc: nand at 63fdb000 {
> compatible = "fsl,imx53-nand";
> reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
> interrupts = <8>;
> @@ -534,7 +534,7 @@
> status = "disabled";
> };
>
> - ethernet at 63fec000 {
> + fec: ethernet at 63fec000 {
> compatible = "fsl,imx53-fec", "fsl,imx25-fec";
> reg = <0x63fec000 0x4000>;
> interrupts = <87>;
> diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
> index f3990b0..56772b9 100644
> --- a/arch/arm/boot/dts/imx6q.dtsi
> +++ b/arch/arm/boot/dts/imx6q.dtsi
> @@ -100,7 +100,7 @@
> clocks = <&clks 106>;
> };
>
> - gpmi-nand at 00112000 {
> + nfc: gpmi-nand at 00112000 {
> compatible = "fsl,imx6q-gpmi-nand";
> #address-cells = <1>;
> #size-cells = <1>;
> @@ -144,12 +144,12 @@
> reg = <0x02000000 0x40000>;
> ranges;
>
> - spdif at 02004000 {
> + spdif: spdif at 02004000 {
> reg = <0x02004000 0x4000>;
> interrupts = <0 52 0x04>;
> };
>
> - ecspi at 02008000 { /* eCSPI1 */
> + ecspi1: ecspi at 02008000 {
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
> @@ -160,7 +160,7 @@
> status = "disabled";
> };
>
> - ecspi at 0200c000 { /* eCSPI2 */
> + ecspi2: ecspi at 0200c000 {
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
> @@ -171,7 +171,7 @@
> status = "disabled";
> };
>
> - ecspi at 02010000 { /* eCSPI3 */
> + ecspi3: ecspi at 02010000 {
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
> @@ -182,7 +182,7 @@
> status = "disabled";
> };
>
> - ecspi at 02014000 { /* eCSPI4 */
> + ecspi4: ecspi at 02014000 {
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
> @@ -193,7 +193,7 @@
> status = "disabled";
> };
>
> - ecspi at 02018000 { /* eCSPI5 */
> + ecspi5: ecspi at 02018000 {
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
> @@ -213,7 +213,7 @@
> status = "disabled";
> };
>
> - esai at 02024000 {
> + esai: esai at 02024000 {
> reg = <0x02024000 0x4000>;
> interrupts = <0 51 0x04>;
> };
> @@ -248,7 +248,7 @@
> status = "disabled";
> };
>
> - asrc at 02034000 {
> + asrc: asrc at 02034000 {
> reg = <0x02034000 0x4000>;
> interrupts = <0 50 0x04>;
> };
> @@ -258,7 +258,7 @@
> };
> };
>
> - vpu at 02040000 {
> + vpu: vpu at 02040000 {
> reg = <0x02040000 0x3c000>;
> interrupts = <0 3 0x04 0 12 0x04>;
> };
> @@ -267,37 +267,37 @@
> reg = <0x0207c000 0x4000>;
> };
>
> - pwm at 02080000 { /* PWM1 */
> + pwm1: pwm at 02080000 {
> reg = <0x02080000 0x4000>;
> interrupts = <0 83 0x04>;
> };
>
> - pwm at 02084000 { /* PWM2 */
> + pwm2: pwm at 02084000 {
> reg = <0x02084000 0x4000>;
> interrupts = <0 84 0x04>;
> };
>
> - pwm at 02088000 { /* PWM3 */
> + pwm3: pwm at 02088000 {
> reg = <0x02088000 0x4000>;
> interrupts = <0 85 0x04>;
> };
>
> - pwm at 0208c000 { /* PWM4 */
> + pwm4: pwm at 0208c000 {
> reg = <0x0208c000 0x4000>;
> interrupts = <0 86 0x04>;
> };
>
> - flexcan at 02090000 { /* CAN1 */
> + can1: flexcan at 02090000 {
> reg = <0x02090000 0x4000>;
> interrupts = <0 110 0x04>;
> };
>
> - flexcan at 02094000 { /* CAN2 */
> + can2: flexcan at 02094000 {
> reg = <0x02094000 0x4000>;
> interrupts = <0 111 0x04>;
> };
>
> - gpt at 02098000 {
> + gpt: gpt at 02098000 {
> compatible = "fsl,imx6q-gpt";
> reg = <0x02098000 0x4000>;
> interrupts = <0 55 0x04>;
> @@ -373,19 +373,19 @@
> #interrupt-cells = <2>;
> };
>
> - kpp at 020b8000 {
> + kpp: kpp at 020b8000 {
> reg = <0x020b8000 0x4000>;
> interrupts = <0 82 0x04>;
> };
>
> - wdog at 020bc000 { /* WDOG1 */
> + wdog1: wdog at 020bc000 {
> compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
> reg = <0x020bc000 0x4000>;
> interrupts = <0 80 0x04>;
> clocks = <&clks 0>;
> };
>
> - wdog at 020c0000 { /* WDOG2 */
> + wdog2: wdog at 020c0000 {
> compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
> reg = <0x020c0000 0x4000>;
> interrupts = <0 81 0x04>;
> @@ -509,23 +509,23 @@
> interrupts = <0 19 0x04 0 20 0x04>;
> };
>
> - epit at 020d0000 { /* EPIT1 */
> + epit1: epit at 020d0000 { /* EPIT1 */
> reg = <0x020d0000 0x4000>;
> interrupts = <0 56 0x04>;
> };
>
> - epit at 020d4000 { /* EPIT2 */
> + epit2: epit at 020d4000 { /* EPIT2 */
> reg = <0x020d4000 0x4000>;
> interrupts = <0 57 0x04>;
> };
>
> - src at 020d8000 {
> + src: src at 020d8000 {
> compatible = "fsl,imx6q-src";
> reg = <0x020d8000 0x4000>;
> interrupts = <0 91 0x04 0 96 0x04>;
> };
>
> - gpc at 020dc000 {
> + gpc: gpc at 020dc000 {
> compatible = "fsl,imx6q-gpc";
> reg = <0x020dc000 0x4000>;
> interrupts = <0 89 0x04 0 90 0x04>;
> @@ -536,7 +536,7 @@
> reg = <0x020e0000 0x38>;
> };
>
> - iomuxc at 020e0000 {
> + iomuxc: iomuxc at 020e0000 {
> compatible = "fsl,imx6q-iomuxc";
> reg = <0x020e0000 0x4000>;
>
> @@ -748,17 +748,17 @@
> };
> };
>
> - dcic at 020e4000 { /* DCIC1 */
> + dcic1: dcic at 020e4000 {
> reg = <0x020e4000 0x4000>;
> interrupts = <0 124 0x04>;
> };
>
> - dcic at 020e8000 { /* DCIC2 */
> + dcic2: dcic at 020e8000 {
> reg = <0x020e8000 0x4000>;
> interrupts = <0 125 0x04>;
> };
>
> - sdma at 020ec000 {
> + sdma: sdma at 020ec000 {
> compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
> reg = <0x020ec000 0x4000>;
> interrupts = <0 2 0x04>;
> @@ -784,7 +784,7 @@
> reg = <0x0217c000 0x4000>;
> };
>
> - usb at 02184000 { /* USB OTG */
> + usbotg: usb at 02184000 {
> compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
> reg = <0x02184000 0x200>;
> interrupts = <0 43 0x04>;
> @@ -794,7 +794,7 @@
> status = "disabled";
> };
>
> - usb at 02184200 { /* USB1 */
> + usbh1: usb at 02184200 {
> compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
> reg = <0x02184200 0x200>;
> interrupts = <0 40 0x04>;
> @@ -804,7 +804,7 @@
> status = "disabled";
> };
>
> - usb at 02184400 { /* USB2 */
> + usbh2: usb at 02184400 {
> compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
> reg = <0x02184400 0x200>;
> interrupts = <0 41 0x04>;
> @@ -813,7 +813,7 @@
> status = "disabled";
> };
>
> - usb at 02184600 { /* USB3 */
> + usbh3: usb at 02184600 {
> compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
> reg = <0x02184600 0x200>;
> interrupts = <0 42 0x04>;
> @@ -822,14 +822,14 @@
> status = "disabled";
> };
>
> - usbmisc: usbmisc at 02184800 {
> + usbmisc: usbmisc: usbmisc at 02184800 {
> #index-cells = <1>;
> compatible = "fsl,imx6q-usbmisc";
> reg = <0x02184800 0x200>;
> clocks = <&clks 162>;
> };
>
> - ethernet at 02188000 {
> + fec: ethernet at 02188000 {
> compatible = "fsl,imx6q-fec";
> reg = <0x02188000 0x4000>;
> interrupts = <0 118 0x04 0 119 0x04>;
> @@ -843,7 +843,7 @@
> interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
> };
>
> - usdhc at 02190000 { /* uSDHC1 */
> + usdhc1: usdhc at 02190000 {
> compatible = "fsl,imx6q-usdhc";
> reg = <0x02190000 0x4000>;
> interrupts = <0 22 0x04>;
> @@ -852,7 +852,7 @@
> status = "disabled";
> };
>
> - usdhc at 02194000 { /* uSDHC2 */
> + usdhc2: usdhc at 02194000 {
> compatible = "fsl,imx6q-usdhc";
> reg = <0x02194000 0x4000>;
> interrupts = <0 23 0x04>;
> @@ -861,7 +861,7 @@
> status = "disabled";
> };
>
> - usdhc at 02198000 { /* uSDHC3 */
> + usdhc3: usdhc at 02198000 {
> compatible = "fsl,imx6q-usdhc";
> reg = <0x02198000 0x4000>;
> interrupts = <0 24 0x04>;
> @@ -870,7 +870,7 @@
> status = "disabled";
> };
>
> - usdhc at 0219c000 { /* uSDHC4 */
> + usdhc4: usdhc at 0219c000 {
> compatible = "fsl,imx6q-usdhc";
> reg = <0x0219c000 0x4000>;
> interrupts = <0 25 0x04>;
> @@ -879,7 +879,7 @@
> status = "disabled";
> };
>
> - i2c at 021a0000 { /* I2C1 */
> + i2c1: i2c at 021a0000 {
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
> @@ -889,7 +889,7 @@
> status = "disabled";
> };
>
> - i2c at 021a4000 { /* I2C2 */
> + i2c2: i2c at 021a4000 {
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
> @@ -899,7 +899,7 @@
> status = "disabled";
> };
>
> - i2c at 021a8000 { /* I2C3 */
> + i2c3: i2c at 021a8000 {
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
> @@ -913,12 +913,12 @@
> reg = <0x021ac000 0x4000>;
> };
>
> - mmdc at 021b0000 { /* MMDC0 */
> + mmdc0: mmdc at 021b0000 { /* MMDC0 */
> compatible = "fsl,imx6q-mmdc";
> reg = <0x021b0000 0x4000>;
> };
>
> - mmdc at 021b4000 { /* MMDC1 */
> + mmdc1: mmdc at 021b4000 { /* MMDC1 */
> reg = <0x021b4000 0x4000>;
> };
>
> @@ -946,7 +946,7 @@
> interrupts = <0 109 0x04>;
> };
>
> - audmux at 021d8000 {
> + audmux: audmux at 021d8000 {
> compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
> reg = <0x021d8000 0x4000>;
> status = "disabled";
> --
> 1.7.10.4
>
^ permalink raw reply
* [PATCH 1/2] arm/mm: L2CC shared mutex with ARM TZ
From: Etienne CARRIERE ST @ 2012-11-15 13:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121114172216.GG16215@arm.com>
Thanks for the details.
I think we will internally use our hack in l2x0 spin locking to prevent collision, based on old arch_spinlock support.
For a definitive outer cache support in TZ, I think we will go into a RPC/SMC based architecture.
I mean a basic SMC to request secured outer cache maintenance, called from linux L2 cache driver based on its native spinlock, whatever it is.
This will indeed require some modification in L2 cache driver (cache-l2x0.c).
We will work on that once our TZ implementation support such RPC/SMC features for L2 cache maintenance.
Thanks to all for the feedbacks.
Regards,
etienne
-----Original Message-----
From: Catalin Marinas [mailto:catalin.marinas at arm.com]
Sent: Wednesday, November 14, 2012 6:22 PM
To: Etienne CARRIERE ST
Cc: Abhimanyu Kapur; Dave Martin; Rabin VINCENT; Russell King; Srinidhi KASAGAR; Marc Zyngier; Linus Walleij (linus.walleij at linaro.org); Will Deacon; linux-arm-kernel at lists.infradead.org
Subject: Re: [PATCH 1/2] arm/mm: L2CC shared mutex with ARM TZ
On Wed, Nov 14, 2012 at 10:15:46AM +0000, Etienne CARRIERE ST wrote:
> > Tue 11-13-2012 8:23 PM
> > From: Abhimanyu Kapur <abhimanyu.kapur@outlook.com>
> >
> > > Secure code in TrustZone space may need to perform L2 cache
> > > maintenance operations. A shared mutex is required to synchronize
> > > linux l2cc maintenance and TZ l2cc maintenance.
> >
> > If you are using PL310 with thrustzone support then the L2 cache
> > lines are secure bit tagged ; your design should be such that the
> > secure (TZ) side only does operations on secure cache lines and
> > non-secure side does operations only on non-secure cache lines. So
> > each entity (TZ and nonTZ) if maintains their own cache and ensures
> > integrity before switching over via monitor, this might not be needed.
>
> I don't think 2 cores can safely write the LX20_CLEAN/INV_LINE_PA
> registers of the PL310 at the same time, even if targeting different
> lines.
Actually for the clean/invalidate operations by PA you can safely write the registers from two different processors as they get serialised by the hardware. What you don't get is protection around the background operations (clean/inv by way). I think it depends on how the PL310 is wired on your hardware but trying to do a PA operation while a background one is in progress would trigger an external abort.
So the NS world could simply start a background cache operation without taking the lock while the secure world thinks that it has the lock and tries to do a PA operation which would abort.
My advise is to simply ignore the shared locking and only do atomic PA operations on the secure side. The secure side also needs to poll for the completion of any background operation that was started in non-secure world. Of course, there is still a race, in which case, depending on the hardware implementation, you would need to trap any possible aborts while in secure mode when writing the PL310 registers.
--
Catalin
^ permalink raw reply
* [PATCH] ARM: add get_user() support for 8 byte types
From: Rob Clark @ 2012-11-15 13:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <201211151339.08016.arnd@arndb.de>
On Thu, Nov 15, 2012 at 7:39 AM, Arnd Bergmann <arnd@arndb.de> wrote:
> On Thursday 15 November 2012, Rob Clark wrote:
>> On Thu, Nov 15, 2012 at 3:19 AM, Arnd Bergmann <arnd@arndb.de> wrote:
>> > On Tuesday 13 November 2012, Russell King - ARM Linux wrote:
>> >> You're missing something; that is one of the greatest powers of open
>> >> source. The many eyes (and minds) effect. Someone out there probably
>> >> has a solution to whatever problem, the trick is to find that person. :)
>> >>
>> >> I think we have a working solution for this for ARM. It won't be suitable
>> >> for every arch, where they have 8-bit and 16-bit registers able to be
>> >> allocated by the compiler, but for architectures where the minimum register
>> >> size is 32-bit, what we have below should work.
>> >
>> > I don't mind at all adding the extension to ARM, and I think it's pretty
>> > cool that you guys actually found a working solution.
>> >
>> > The part that worries me is that we are making architecture independent
>> > code depend on a clever hack that may or may not be possible to implement
>> > on a given architecture, and that most architecture maintainers wouldn't
>> > know how to implement correctly even if it's possible.
>>
>> I could always send a 3rd version with a comment smashed on about why
>> that works if you think this is a problem..
>
> Comments are always good, so I'd surely like to see those get added.
> As I said, I don't have any objections to the addition of your patch to
> the ARM code, which sounds useful to have.
ok, I'll send a v3 w/ some additional comments
> I still haven't heard a conclusive argument why we need to use get_user()
> rather than copy_from_user() in the DRM code. Is this about a fast path
> where you want to shave off a few cycles for each call, or does this
> simplify the code structure, or something else?
well, it is mostly because it seemed like a good idea to first try to
solve the root issue, rather than having to fix things up in each
driver when someone from x86-world introduces a 64b get_user()..
There are some other arch's that don't have 64b get_user(), but I
don't think any that have any DRM drivers. If 64b get_user() is
really not intended to be supported by all archs, it is better to
remove it from x86 and the other arch's that do currently support it,
rather than making it possible to write drivers that are broken on
some archs.
BR,
-R
> Arnd
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^ permalink raw reply
* [PATCH v2 1/2] ARM: mx27: Add VPU support
From: Sascha Hauer @ 2012-11-15 13:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAOMZO5BrzD5okmRMcY3X3aquMpmxV5Pn2k2upsQNhsmq_Pi5-A@mail.gmail.com>
On Thu, Nov 15, 2012 at 11:38:01AM -0200, Fabio Estevam wrote:
> On Thu, Nov 15, 2012 at 6:12 AM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
>
> > As Eric mentioned this may lead to problems on the i.MX27L without VPU.
> > Do you have the possibility to test this?
>
> I do not have any board with a MX27L variant. Maybe we could try
> reading the SREV info register to distinguish between MX27 and MX27L.
> MX27RM does not provide any info on this though.
If that works I would prefer this, but I also have no i.MX27L to test
it. Otherwise doing it like v1 is the best we can do.
You should probably put the changes to Javiers board into a separate
patch so that Javier can Ack it indepently of what we are coming up
with.
Sascha
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