* [PATCH V2 2/2] ARM: dts: OMAP2+: Add PMU nodes
From: Jon Hunter @ 2013-01-11 13:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50F01256.7030701@ti.com>
Hi Benoit,
On 01/11/2013 07:23 AM, Benoit Cousson wrote:
> Hi Jon,
>
> On 12/17/2012 06:49 PM, Jon Hunter wrote:
>> Add PMU nodes for OMAP2, OMAP3 and OMAP4460 devices.
>>
>> Please note that the node for OMAP4460 has been placed in a separate
>> header file for OMAP4460, because the node is not compatible with
>> OMAP4430. The node for OMAP4430 is not included because PMU is not
>> currently supported on OMAP4430 due to the absence of a cross-trigger
>> interface driver.
>>
>> Signed-off-by: Jon Hunter <jon-hunter@ti.com>
>
> I've just applied this patch in my for_3.9/dts branch.
>
> I'm wondering if there is any dependency with the previous patch? If
> Tony ack it I can take it as well.
I have been thinking about the best way to handle that. May be best for
you to take both if Tony can ack the first.
Cheers
Jon
^ permalink raw reply
* [PATCHv2 02/11] arm: arch_timer: remove redundant available check
From: Mark Rutland @ 2013-01-11 14:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50F00F8D.3050904@ti.com>
On Fri, Jan 11, 2013 at 01:11:41PM +0000, Santosh Shilimkar wrote:
> On Wednesday 09 January 2013 09:37 PM, Mark Rutland wrote:
> > This check is a holdover from the pre-devicetree days. As the timer
> > is not probed except by platforms which register it via devicetree,
> > it's not strictly necessary.
> >
> > Signed-off-by: Mark Rutland <mark.rutland@arm.com>
> > Acked-by: Catalin Marinas <catalin.marinas@arm.com>
> > Acked-by: Marc Zyngier <marc.zyngier@arm.com>
> > ---
> Multi-platform build without DT could still benefit from the
> check but I guess the most of the A15 based platform are DT
> only, so its should be good to get rid of the check.
Indeed. I'm under the impression that all platforms which might have an
architected timer are devicetree only.
>
> Regards,
> Santosh
>
Thanks,
Mark.
^ permalink raw reply
* [PATCH 0/2 v2] at91/ssc: fixes on ASoC tree for 3.8
From: Nicolas Ferre @ 2013-01-11 14:08 UTC (permalink / raw)
To: linux-arm-kernel
Hi Mark, Olof, Arnd,
This series goes on top of Linus' v3.8-rc3 and fixes an error that
we have while compiling DTBs for AT91:
ERROR (phandle_references): Reference to non-existent node or label
"pinctrl_ssc0_tx"
ERROR: Input tree has errors, aborting (use -f to force output)
make[3]: *** [arch/arm/boot/dts/at91sam9g20ek.dtb] Error 2
I have included pending material that is dealing with SSC and pinctrl. The
pinctrl part can be merged more easily now that the big pinctrl update for AT91
has been merged upstream.
This material was designed to enter Mark's fixes queue, but as discussed with
Olof, we can imagine merging everything through arm-soc or split the series (of
2 patches) and let them progress upstream separated (option that I do not like
even if I know that the consequences are not so dramatic).
So please, Olof, if you feel confortable with this series, tell us what you
prefer and we will make our best to make this material go forward...
Thanks for your help, best regards,
v2: - remove the fix for typo in SSC status property: already merged upstream
Bo Shen (2):
ARM: at91/dts: add pinctrl support for SSC peripheral
ASoC: atmel-ssc: add pinctrl selection to driver
arch/arm/boot/dts/at91sam9260.dtsi | 18 ++++++++++++++++++
arch/arm/boot/dts/at91sam9263.dtsi | 36 ++++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/at91sam9g45.dtsi | 36 ++++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/at91sam9n12.dtsi | 26 ++++++++++++++++++++++++++
arch/arm/boot/dts/at91sam9x5.dtsi | 32 +++++++++++++++++++++++++-------
drivers/misc/atmel-ssc.c | 8 ++++++++
6 files changed, 149 insertions(+), 7 deletions(-)
--
1.8.0
^ permalink raw reply
* [PATCH 1/2 v2] ARM: at91/dts: add pinctrl support for SSC peripheral
From: Nicolas Ferre @ 2013-01-11 14:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1357912706.git.nicolas.ferre@atmel.com>
From: Bo Shen <voice.shen@atmel.com>
Add pinctrl support for SSC on AT91 dtsi files.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
[nicolas.ferre at atmel.com: split dtsi and driver changes]
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
---
arch/arm/boot/dts/at91sam9260.dtsi | 18 ++++++++++++++++++
arch/arm/boot/dts/at91sam9263.dtsi | 36 ++++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/at91sam9g45.dtsi | 36 ++++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/at91sam9n12.dtsi | 26 ++++++++++++++++++++++++++
arch/arm/boot/dts/at91sam9x5.dtsi | 32 +++++++++++++++++++++++++-------
5 files changed, 141 insertions(+), 7 deletions(-)
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index 68bccf4..cb7bcc5 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -306,6 +306,22 @@
};
};
+ ssc0 {
+ pinctrl_ssc0_tx: ssc0_tx-0 {
+ atmel,pins =
+ <1 16 0x1 0x0 /* PB16 periph A */
+ 1 17 0x1 0x0 /* PB17 periph A */
+ 1 18 0x1 0x0>; /* PB18 periph A */
+ };
+
+ pinctrl_ssc0_rx: ssc0_rx-0 {
+ atmel,pins =
+ <1 19 0x1 0x0 /* PB19 periph A */
+ 1 20 0x1 0x0 /* PB20 periph A */
+ 1 21 0x1 0x0>; /* PB21 periph A */
+ };
+ };
+
pioA: gpio at fffff400 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x200>;
@@ -450,6 +466,8 @@
compatible = "atmel,at91rm9200-ssc";
reg = <0xfffbc000 0x4000>;
interrupts = <14 4 5>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index 32ec62c..271d4de 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -271,6 +271,38 @@
};
};
+ ssc0 {
+ pinctrl_ssc0_tx: ssc0_tx-0 {
+ atmel,pins =
+ <1 0 0x2 0x0 /* PB0 periph B */
+ 1 1 0x2 0x0 /* PB1 periph B */
+ 1 2 0x2 0x0>; /* PB2 periph B */
+ };
+
+ pinctrl_ssc0_rx: ssc0_rx-0 {
+ atmel,pins =
+ <1 3 0x2 0x0 /* PB3 periph B */
+ 1 4 0x2 0x0 /* PB4 periph B */
+ 1 5 0x2 0x0>; /* PB5 periph B */
+ };
+ };
+
+ ssc1 {
+ pinctrl_ssc1_tx: ssc1_tx-0 {
+ atmel,pins =
+ <1 6 0x1 0x0 /* PB6 periph A */
+ 1 7 0x1 0x0 /* PB7 periph A */
+ 1 8 0x1 0x0>; /* PB8 periph A */
+ };
+
+ pinctrl_ssc1_rx: ssc1_rx-0 {
+ atmel,pins =
+ <1 9 0x1 0x0 /* PB9 periph A */
+ 1 10 0x1 0x0 /* PB10 periph A */
+ 1 11 0x1 0x0>; /* PB11 periph A */
+ };
+ };
+
pioA: gpio at fffff200 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff200 0x200>;
@@ -368,6 +400,8 @@
compatible = "atmel,at91rm9200-ssc";
reg = <0xfff98000 0x4000>;
interrupts = <16 4 5>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
status = "disabled";
};
@@ -375,6 +409,8 @@
compatible = "atmel,at91rm9200-ssc";
reg = <0xfff9c000 0x4000>;
interrupts = <17 4 5>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index 231858f..6b1d4ca 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -290,6 +290,38 @@
};
};
+ ssc0 {
+ pinctrl_ssc0_tx: ssc0_tx-0 {
+ atmel,pins =
+ <3 0 0x1 0x0 /* PD0 periph A */
+ 3 1 0x1 0x0 /* PD1 periph A */
+ 3 2 0x1 0x0>; /* PD2 periph A */
+ };
+
+ pinctrl_ssc0_rx: ssc0_rx-0 {
+ atmel,pins =
+ <3 3 0x1 0x0 /* PD3 periph A */
+ 3 4 0x1 0x0 /* PD4 periph A */
+ 3 5 0x1 0x0>; /* PD5 periph A */
+ };
+ };
+
+ ssc1 {
+ pinctrl_ssc1_tx: ssc1_tx-0 {
+ atmel,pins =
+ <3 10 0x1 0x0 /* PD10 periph A */
+ 3 11 0x1 0x0 /* PD11 periph A */
+ 3 12 0x1 0x0>; /* PD12 periph A */
+ };
+
+ pinctrl_ssc1_rx: ssc1_rx-0 {
+ atmel,pins =
+ <3 13 0x1 0x0 /* PD13 periph A */
+ 3 14 0x1 0x0 /* PD14 periph A */
+ 3 15 0x1 0x0>; /* PD15 periph A */
+ };
+ };
+
pioA: gpio at fffff200 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff200 0x200>;
@@ -425,6 +457,8 @@
compatible = "atmel,at91sam9g45-ssc";
reg = <0xfff9c000 0x4000>;
interrupts = <16 4 5>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
status = "disabled";
};
@@ -432,6 +466,8 @@
compatible = "atmel,at91sam9g45-ssc";
reg = <0xfffa0000 0x4000>;
interrupts = <17 4 5>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index e9efb34..80e29c6 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -28,6 +28,7 @@
tcb1 = &tcb1;
i2c0 = &i2c0;
i2c1 = &i2c1;
+ ssc0 = &ssc0;
};
cpus {
cpu at 0 {
@@ -244,6 +245,22 @@
};
};
+ ssc0 {
+ pinctrl_ssc0_tx: ssc0_tx-0 {
+ atmel,pins =
+ <0 24 0x2 0x0 /* PA24 periph B */
+ 0 25 0x2 0x0 /* PA25 periph B */
+ 0 26 0x2 0x0>; /* PA26 periph B */
+ };
+
+ pinctrl_ssc0_rx: ssc0_rx-0 {
+ atmel,pins =
+ <0 27 0x2 0x0 /* PA27 periph B */
+ 0 28 0x2 0x0 /* PA28 periph B */
+ 0 29 0x2 0x0>; /* PA29 periph B */
+ };
+ };
+
pioA: gpio at fffff400 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x200>;
@@ -294,6 +311,15 @@
status = "disabled";
};
+ ssc0: ssc at f0010000 {
+ compatible = "atmel,at91sam9g45-ssc";
+ reg = <0xf0010000 0x4000>;
+ interrupts = <28 4 5>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
+ status = "disabled";
+ };
+
usart0: serial at f801c000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xf801c000 0x4000>;
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 40ac3a4..3a47cf9 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -88,13 +88,6 @@
interrupts = <1 4 7>;
};
- ssc0: ssc at f0010000 {
- compatible = "atmel,at91sam9g45-ssc";
- reg = <0xf0010000 0x4000>;
- interrupts = <28 4 5>;
- status = "disabled";
- };
-
tcb0: timer at f8008000 {
compatible = "atmel,at91sam9x5-tcb";
reg = <0xf8008000 0x100>;
@@ -290,6 +283,22 @@
};
};
+ ssc0 {
+ pinctrl_ssc0_tx: ssc0_tx-0 {
+ atmel,pins =
+ <0 24 0x2 0x0 /* PA24 periph B */
+ 0 25 0x2 0x0 /* PA25 periph B */
+ 0 26 0x2 0x0>; /* PA26 periph B */
+ };
+
+ pinctrl_ssc0_rx: ssc0_rx-0 {
+ atmel,pins =
+ <0 27 0x2 0x0 /* PA27 periph B */
+ 0 28 0x2 0x0 /* PA28 periph B */
+ 0 29 0x2 0x0>; /* PA29 periph B */
+ };
+ };
+
pioA: gpio at fffff400 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x200>;
@@ -333,6 +342,15 @@
};
};
+ ssc0: ssc at f0010000 {
+ compatible = "atmel,at91sam9g45-ssc";
+ reg = <0xf0010000 0x4000>;
+ interrupts = <28 4 5>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
+ status = "disabled";
+ };
+
mmc0: mmc at f0008000 {
compatible = "atmel,hsmci";
reg = <0xf0008000 0x600>;
--
1.8.0
^ permalink raw reply related
* [PATCH 2/2 v2] ASoC: atmel-ssc: add pinctrl selection to driver
From: Nicolas Ferre @ 2013-01-11 14:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1357912706.git.nicolas.ferre@atmel.com>
From: Bo Shen <voice.shen@atmel.com>
Add default pinctrl selection to atmel-ssc driver. The pinctrl
is mandatory.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
[nicolas.ferre at atmel.com: split dtsi and driver changes]
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
---
drivers/misc/atmel-ssc.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/misc/atmel-ssc.c b/drivers/misc/atmel-ssc.c
index 158da5a..3c09cbb 100644
--- a/drivers/misc/atmel-ssc.c
+++ b/drivers/misc/atmel-ssc.c
@@ -19,6 +19,7 @@
#include <linux/module.h>
#include <linux/of.h>
+#include <linux/pinctrl/consumer.h>
/* Serialize access to ssc_list and user count */
static DEFINE_SPINLOCK(user_lock);
@@ -131,6 +132,13 @@ static int ssc_probe(struct platform_device *pdev)
struct resource *regs;
struct ssc_device *ssc;
const struct atmel_ssc_platform_data *plat_dat;
+ struct pinctrl *pinctrl;
+
+ pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
+ if (IS_ERR(pinctrl)) {
+ dev_err(&pdev->dev, "Failed to request pinctrl\n");
+ return PTR_ERR(pinctrl);
+ }
ssc = devm_kzalloc(&pdev->dev, sizeof(struct ssc_device), GFP_KERNEL);
if (!ssc) {
--
1.8.0
^ permalink raw reply related
* [PATCHv2 05/11] arm: arch_timer: split cntfrq accessor
From: Mark Rutland @ 2013-01-11 14:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50F01350.4040107@ti.com>
On Fri, Jan 11, 2013 at 01:27:44PM +0000, Santosh Shilimkar wrote:
> On Wednesday 09 January 2013 09:37 PM, Mark Rutland wrote:
> > The CNTFRQ register is not duplicated for physical and virtual timers,
> > and accessing it as if it were is confusing.
> >
> > Instead, use a separate accessor which doesn't take the access type
> > as a parameter.
> >
> > Signed-off-by: Mark Rutland <mark.rutland@arm.com>
> > Acked-by: Catalin Marinas <catalin.marinas@arm.com>
> > Acked-by: Marc Zyngier <marc.zyngier@arm.com>
> > ---
> > arch/arm/kernel/arch_timer.c | 17 +++++++++--------
> > 1 files changed, 9 insertions(+), 8 deletions(-)
> >
> > diff --git a/arch/arm/kernel/arch_timer.c b/arch/arm/kernel/arch_timer.c
> > index 0d2681c..fc87d3d 100644
> > --- a/arch/arm/kernel/arch_timer.c
> > +++ b/arch/arm/kernel/arch_timer.c
> > @@ -51,8 +51,7 @@ static bool arch_timer_use_virtual = true;
> > #define ARCH_TIMER_CTRL_IT_STAT (1 << 2)
> >
> > #define ARCH_TIMER_REG_CTRL 0
> > -#define ARCH_TIMER_REG_FREQ 1
> > -#define ARCH_TIMER_REG_TVAL 2
> > +#define ARCH_TIMER_REG_TVAL 1
> >
> > #define ARCH_TIMER_PHYS_ACCESS 0
> > #define ARCH_TIMER_VIRT_ACCESS 1
> > @@ -101,9 +100,6 @@ static inline u32 arch_timer_reg_read(const int access, const int reg)
> > case ARCH_TIMER_REG_TVAL:
> > asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val));
> > break;
> > - case ARCH_TIMER_REG_FREQ:
> > - asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (val));
> > - break;
> > }
> > }
> >
> > @@ -121,6 +117,13 @@ static inline u32 arch_timer_reg_read(const int access, const int reg)
> > return val;
> > }
> >
> > +static inline u32 arch_timer_get_cntfrq(void)
> > +{
> > + u32 val;
> > + asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (val));
> > + return val;
> > +}
> > +
> > static inline u64 arch_counter_get_cntpct(void)
> > {
> > u64 cval;
> > @@ -253,9 +256,7 @@ static int arch_timer_available(void)
> > u32 freq;
> >
> > if (arch_timer_rate == 0) {
> > - freq = arch_timer_reg_read(ARCH_TIMER_PHYS_ACCESS,
> > - ARCH_TIMER_REG_FREQ);
> > -
> > + freq = arch_timer_get_cntfrq();
> Not related to this patch a new line here will be good.
Whoops. I hadn't intended to alter the line spacing here. I'll fix that up.
> > /* Check the timer frequency. */
> > if (freq == 0) {
> > pr_warn("Architected timer frequency not available\n");
> >
> Otherwise patch looks fine to me.
> Acked-by: Santosh Shilimkar<santosh.shilimkar@ti.com>
>
Thanks,
Mark.
^ permalink raw reply
* [PATCH] ARM: imx: fix build error with !CONFIG_SMP
From: Shawn Guo @ 2013-01-11 14:20 UTC (permalink / raw)
To: linux-arm-kernel
Commit 68b2532 (ARM: imx: select HAVE_IMX_SRC when SMP is enabled)
introduces a build error with imx_v6_v7_defconfig when CONFIG_SMP is
deselected.
LINK vmlinux
LD vmlinux.o
MODPOST vmlinux.o
GEN .version
CHK include/generated/compile.h
UPD include/generated/compile.h
CC init/version.o
LD init/built-in.o
arch/arm/mach-imx/built-in.o: In function `imx6q_restart':
platform-ahci-imx.c:(.text+0x448c): undefined reference to `imx_src_prepare_restart'
arch/arm/mach-imx/built-in.o: In function `imx6q_pm_enter':
platform-ahci-imx.c:(.text+0x4544): undefined reference to `imx_set_cpu_jump'
arch/arm/mach-imx/built-in.o: In function `imx6q_init_irq':
platform-ahci-imx.c:(.init.text+0xbef0): undefined reference to `imx_src_init'
make[1]: *** [vmlinux] Error 1
While the commit adds 'def_bool y if SMP' for HAVE_IMX_SRC, it should
not remove 'select HAVE_IMX_SRC' from SOC_IMX6Q, as the IMX6Q UP build
also needs HAVE_IMX_SRC. Add the HAVE_IMX_SRC select back for SOC_IMX6Q
to fix above build error.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
arch/arm/mach-imx/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 1ad0d76..8e2f292 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -853,6 +853,7 @@ config SOC_IMX6Q
select HAVE_CAN_FLEXCAN if CAN
select HAVE_IMX_GPC
select HAVE_IMX_MMDC
+ select HAVE_IMX_SRC
select HAVE_SMP
select MFD_SYSCON
select PINCTRL
--
1.7.9.5
^ permalink raw reply related
* [PATCH v4 01/14] ARM: davinci: move private EDMA API to arm/common
From: Matt Porter @ 2013-01-11 14:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1BAFE6F6C881BF42822005164F1491C33EB3EAB6@DBDE01.ent.ti.com>
On Fri, Jan 11, 2013 at 06:15:06AM +0000, Hebbar, Gururaja wrote:
> On Fri, Jan 11, 2013 at 11:18:37, Porter, Matt wrote:
> > Move mach-davinci/dma.c to common/edma.c so it can be used
> > by OMAP (specifically AM33xx) as well. This just moves the
> > private EDMA API and enables it to build on OMAP.
> >
> > Signed-off-by: Matt Porter <mporter@ti.com>
> > ---
> > arch/arm/Kconfig | 1 +
> > arch/arm/common/Kconfig | 3 +
> > arch/arm/common/Makefile | 1 +
> > arch/arm/{mach-davinci/dma.c => common/edma.c} | 2 +-
> > arch/arm/mach-davinci/Makefile | 2 +-
> > arch/arm/mach-davinci/board-tnetv107x-evm.c | 2 +-
> > arch/arm/mach-davinci/davinci.h | 2 +-
> > arch/arm/mach-davinci/devices-tnetv107x.c | 2 +-
> > arch/arm/mach-davinci/devices.c | 7 +-
> > arch/arm/mach-davinci/dm355.c | 2 +-
> > arch/arm/mach-davinci/dm365.c | 2 +-
> > arch/arm/mach-davinci/dm644x.c | 2 +-
> > arch/arm/mach-davinci/dm646x.c | 2 +-
> > arch/arm/mach-davinci/include/mach/da8xx.h | 2 +-
> > arch/arm/mach-davinci/include/mach/edma.h | 267 ------------------------
> > arch/arm/plat-omap/Kconfig | 1 +
> > drivers/dma/edma.c | 2 +-
> > drivers/mmc/host/davinci_mmc.c | 1 +
> > include/linux/mfd/davinci_voicecodec.h | 3 +-
> > include/linux/platform_data/edma.h | 182 ++++++++++++++++
>
> Headers file are just moved here. So "git mv file1 flie2; and the git
> format-patch -C" on commit should just generate few lines of patch.
Ok, good catch.
>
> > include/linux/platform_data/spi-davinci.h | 2 +-
> > sound/soc/davinci/davinci-evm.c | 1 +
> > sound/soc/davinci/davinci-pcm.c | 1 +
> > sound/soc/davinci/davinci-pcm.h | 2 +-
> > sound/soc/davinci/davinci-sffsdr.c | 6 +-
> > 25 files changed, 212 insertions(+), 288 deletions(-)
> > rename arch/arm/{mach-davinci/dma.c => common/edma.c} (99%)
> > delete mode 100644 arch/arm/mach-davinci/include/mach/edma.h
> > create mode 100644 include/linux/platform_data/edma.h
> >
> > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> > index 67874b8..7637d31 100644
> > --- a/arch/arm/Kconfig
> > +++ b/arch/arm/Kconfig
> > @@ -932,6 +932,7 @@ config ARCH_DAVINCI
> > select GENERIC_IRQ_CHIP
> > select HAVE_IDE
> > select NEED_MACH_GPIO_H
> > + select TI_PRIV_EDMA
> > select USE_OF
> > select ZONE_DMA
> > help
> > diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig
> > index 45ceeb0..9e32d0d 100644
> > --- a/arch/arm/common/Kconfig
> > +++ b/arch/arm/common/Kconfig
> > @@ -40,3 +40,6 @@ config SHARP_PARAM
> >
> > config SHARP_SCOOP
> > bool
> > +
> > +config TI_PRIV_EDMA
> > + bool
> > diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
> > index e8a4e58..d09a39b 100644
> > --- a/arch/arm/common/Makefile
> > +++ b/arch/arm/common/Makefile
> > @@ -13,3 +13,4 @@ obj-$(CONFIG_SHARP_PARAM) += sharpsl_param.o
> > obj-$(CONFIG_SHARP_SCOOP) += scoop.o
> > obj-$(CONFIG_PCI_HOST_ITE8152) += it8152.o
> > obj-$(CONFIG_ARM_TIMER_SP804) += timer-sp.o
> > +obj-$(CONFIG_TI_PRIV_EDMA) += edma.o
> > diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/common/edma.c
> > similarity index 99%
> > rename from arch/arm/mach-davinci/dma.c
> > rename to arch/arm/common/edma.c
> > index a685e97..4411087 100644
> > --- a/arch/arm/mach-davinci/dma.c
> > +++ b/arch/arm/common/edma.c
> > @@ -25,7 +25,7 @@
> > #include <linux/io.h>
> > #include <linux/slab.h>
> >
> > -#include <mach/edma.h>
> > +#include <linux/platform_data/edma.h>
> >
> > /* Offsets matching "struct edmacc_param" */
> > #define PARM_OPT 0x00
> > diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
> > index fb5c1aa..493a36b 100644
> > --- a/arch/arm/mach-davinci/Makefile
> > +++ b/arch/arm/mach-davinci/Makefile
> > @@ -5,7 +5,7 @@
> >
> > # Common objects
> > obj-y := time.o clock.o serial.o psc.o \
> > - dma.o usb.o common.o sram.o aemif.o
> > + usb.o common.o sram.o aemif.o
> >
> > obj-$(CONFIG_DAVINCI_MUX) += mux.o
> >
> > diff --git a/arch/arm/mach-davinci/board-tnetv107x-evm.c b/arch/arm/mach-davinci/board-tnetv107x-evm.c
> > index be30997..86f55ba 100644
> > --- a/arch/arm/mach-davinci/board-tnetv107x-evm.c
> > +++ b/arch/arm/mach-davinci/board-tnetv107x-evm.c
> > @@ -26,12 +26,12 @@
> > #include <linux/input.h>
> > #include <linux/input/matrix_keypad.h>
> > #include <linux/spi/spi.h>
> > +#include <linux/platform_data/edma.h>
> >
> > #include <asm/mach/arch.h>
> > #include <asm/mach-types.h>
> >
> > #include <mach/irqs.h>
> > -#include <mach/edma.h>
> > #include <mach/mux.h>
> > #include <mach/cp_intc.h>
> > #include <mach/tnetv107x.h>
> > diff --git a/arch/arm/mach-davinci/davinci.h b/arch/arm/mach-davinci/davinci.h
> > index 12d544b..d26a6bc 100644
> > --- a/arch/arm/mach-davinci/davinci.h
> > +++ b/arch/arm/mach-davinci/davinci.h
> > @@ -23,9 +23,9 @@
> > #include <linux/platform_device.h>
> > #include <linux/spi/spi.h>
> > #include <linux/platform_data/davinci_asp.h>
> > +#include <linux/platform_data/edma.h>
> > #include <linux/platform_data/keyscan-davinci.h>
> > #include <mach/hardware.h>
> > -#include <mach/edma.h>
> >
> > #include <media/davinci/vpfe_capture.h>
> > #include <media/davinci/vpif_types.h>
> > diff --git a/arch/arm/mach-davinci/devices-tnetv107x.c b/arch/arm/mach-davinci/devices-tnetv107x.c
> > index 773ab07..ba37760 100644
> > --- a/arch/arm/mach-davinci/devices-tnetv107x.c
> > +++ b/arch/arm/mach-davinci/devices-tnetv107x.c
> > @@ -18,10 +18,10 @@
> > #include <linux/dma-mapping.h>
> > #include <linux/clk.h>
> > #include <linux/slab.h>
> > +#include <linux/platform_data/edma.h>
> >
> > #include <mach/common.h>
> > #include <mach/irqs.h>
> > -#include <mach/edma.h>
> > #include <mach/tnetv107x.h>
> >
> > #include "clock.h"
> > diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
> > index 4c48a36..3bdf9f7 100644
> > --- a/arch/arm/mach-davinci/devices.c
> > +++ b/arch/arm/mach-davinci/devices.c
> > @@ -19,9 +19,10 @@
> > #include <mach/irqs.h>
> > #include <mach/cputype.h>
> > #include <mach/mux.h>
> > -#include <mach/edma.h>
> > #include <linux/platform_data/mmc-davinci.h>
> > #include <mach/time.h>
> > +#include <linux/platform_data/edma.h>
> > +
> >
> > #include "davinci.h"
> > #include "clock.h"
> > @@ -141,10 +142,10 @@ static struct resource mmcsd0_resources[] = {
> > },
> > /* DMA channels: RX, then TX */
> > {
> > - .start = EDMA_CTLR_CHAN(0, DAVINCI_DMA_MMCRXEVT),
> > + .start = EDMA_CTLR_CHAN(0, 26), /* MMCRXEVT */
> > .flags = IORESOURCE_DMA,
> > }, {
> > - .start = EDMA_CTLR_CHAN(0, DAVINCI_DMA_MMCTXEVT),
> > + .start = EDMA_CTLR_CHAN(0, 27), /* MMCTXEVT */
> > .flags = IORESOURCE_DMA,
> > },
> > };
> > diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
> > index b49c3b7..53998d8 100644
> > --- a/arch/arm/mach-davinci/dm355.c
> > +++ b/arch/arm/mach-davinci/dm355.c
> > @@ -19,7 +19,6 @@
> > #include <asm/mach/map.h>
> >
> > #include <mach/cputype.h>
> > -#include <mach/edma.h>
> > #include <mach/psc.h>
> > #include <mach/mux.h>
> > #include <mach/irqs.h>
> > @@ -28,6 +27,7 @@
> > #include <mach/common.h>
> > #include <linux/platform_data/spi-davinci.h>
> > #include <mach/gpio-davinci.h>
> > +#include <linux/platform_data/edma.h>
> >
> > #include "davinci.h"
> > #include "clock.h"
> > diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
> > index 6c39805..9b41d33 100644
> > --- a/arch/arm/mach-davinci/dm365.c
> > +++ b/arch/arm/mach-davinci/dm365.c
> > @@ -18,11 +18,11 @@
> > #include <linux/platform_device.h>
> > #include <linux/dma-mapping.h>
> > #include <linux/spi/spi.h>
> > +#include <linux/platform_data/edma.h>
> >
> > #include <asm/mach/map.h>
> >
> > #include <mach/cputype.h>
> > -#include <mach/edma.h>
> > #include <mach/psc.h>
> > #include <mach/mux.h>
> > #include <mach/irqs.h>
> > diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
> > index 11c79a3..a08910e 100644
> > --- a/arch/arm/mach-davinci/dm644x.c
> > +++ b/arch/arm/mach-davinci/dm644x.c
> > @@ -12,11 +12,11 @@
> > #include <linux/clk.h>
> > #include <linux/serial_8250.h>
> > #include <linux/platform_device.h>
> > +#include <linux/platform_data/edma.h>
> >
> > #include <asm/mach/map.h>
> >
> > #include <mach/cputype.h>
> > -#include <mach/edma.h>
> > #include <mach/irqs.h>
> > #include <mach/psc.h>
> > #include <mach/mux.h>
> > diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
> > index ac7b431..6d52a32 100644
> > --- a/arch/arm/mach-davinci/dm646x.c
> > +++ b/arch/arm/mach-davinci/dm646x.c
> > @@ -13,11 +13,11 @@
> > #include <linux/clk.h>
> > #include <linux/serial_8250.h>
> > #include <linux/platform_device.h>
> > +#include <linux/platform_data/edma.h>
> >
> > #include <asm/mach/map.h>
> >
> > #include <mach/cputype.h>
> > -#include <mach/edma.h>
> > #include <mach/irqs.h>
> > #include <mach/psc.h>
> > #include <mach/mux.h>
> > diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
> > index 700d311..9d77f9b 100644
> > --- a/arch/arm/mach-davinci/include/mach/da8xx.h
> > +++ b/arch/arm/mach-davinci/include/mach/da8xx.h
> > @@ -20,8 +20,8 @@
> > #include <linux/videodev2.h>
> >
> > #include <mach/serial.h>
> > -#include <mach/edma.h>
> > #include <mach/pm.h>
> > +#include <linux/platform_data/edma.h>
> > #include <linux/platform_data/i2c-davinci.h>
> > #include <linux/platform_data/mmc-davinci.h>
> > #include <linux/platform_data/usb-davinci.h>
> > diff --git a/arch/arm/mach-davinci/include/mach/edma.h b/arch/arm/mach-davinci/include/mach/edma.h
> > deleted file mode 100644
> > index 7e84c90..0000000
> > --- a/arch/arm/mach-davinci/include/mach/edma.h
> > +++ /dev/null
> > @@ -1,267 +0,0 @@
> > -/*
> > - * TI DAVINCI dma definitions
> > - *
> > - * Copyright (C) 2006-2009 Texas Instruments.
> > - *
> > - * This program is free software; you can redistribute it and/or modify it
> > - * under the terms of the GNU General Public License as published by the
> > - * Free Software Foundation; either version 2 of the License, or (at your
> > - * option) any later version.
> > - *
> > - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
> > - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
> > - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
> > - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
> > - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
> > - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
> > - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
> > - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
> > - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
> > - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> > - *
> > - * You should have received a copy of the GNU General Public License along
> > - * with this program; if not, write to the Free Software Foundation, Inc.,
> > - * 675 Mass Ave, Cambridge, MA 02139, USA.
> > - *
> > - */
> > -
> > -/*
> > - * This EDMA3 programming framework exposes two basic kinds of resource:
> > - *
> > - * Channel Triggers transfers, usually from a hardware event but
> > - * also manually or by "chaining" from DMA completions.
> > - * Each channel is coupled to a Parameter RAM (PaRAM) slot.
> > - *
> > - * Slot Each PaRAM slot holds a DMA transfer descriptor (PaRAM
> > - * "set"), source and destination addresses, a link to a
> > - * next PaRAM slot (if any), options for the transfer, and
> > - * instructions for updating those addresses. There are
> > - * more than twice as many slots as event channels.
> > - *
> > - * Each PaRAM set describes a sequence of transfers, either for one large
> > - * buffer or for several discontiguous smaller buffers. An EDMA transfer
> > - * is driven only from a channel, which performs the transfers specified
> > - * in its PaRAM slot until there are no more transfers. When that last
> > - * transfer completes, the "link" field may be used to reload the channel's
> > - * PaRAM slot with a new transfer descriptor.
> > - *
> > - * The EDMA Channel Controller (CC) maps requests from channels into physical
> > - * Transfer Controller (TC) requests when the channel triggers (by hardware
> > - * or software events, or by chaining). The two physical DMA channels provided
> > - * by the TCs are thus shared by many logical channels.
> > - *
> > - * DaVinci hardware also has a "QDMA" mechanism which is not currently
> > - * supported through this interface. (DSP firmware uses it though.)
> > - */
> > -
> > -#ifndef EDMA_H_
> > -#define EDMA_H_
> > -
> > -/* PaRAM slots are laid out like this */
> > -struct edmacc_param {
> > - unsigned int opt;
> > - unsigned int src;
> > - unsigned int a_b_cnt;
> > - unsigned int dst;
> > - unsigned int src_dst_bidx;
> > - unsigned int link_bcntrld;
> > - unsigned int src_dst_cidx;
> > - unsigned int ccnt;
> > -};
> > -
> > -#define CCINT0_INTERRUPT 16
> > -#define CCERRINT_INTERRUPT 17
> > -#define TCERRINT0_INTERRUPT 18
> > -#define TCERRINT1_INTERRUPT 19
> > -
> > -/* fields in edmacc_param.opt */
> > -#define SAM BIT(0)
> > -#define DAM BIT(1)
> > -#define SYNCDIM BIT(2)
> > -#define STATIC BIT(3)
> > -#define EDMA_FWID (0x07 << 8)
> > -#define TCCMODE BIT(11)
> > -#define EDMA_TCC(t) ((t) << 12)
> > -#define TCINTEN BIT(20)
> > -#define ITCINTEN BIT(21)
> > -#define TCCHEN BIT(22)
> > -#define ITCCHEN BIT(23)
> > -
> > -#define TRWORD (0x7<<2)
> > -#define PAENTRY (0x1ff<<5)
> > -
> > -/* Drivers should avoid using these symbolic names for dm644x
> > - * channels, and use platform_device IORESOURCE_DMA resources
> > - * instead. (Other DaVinci chips have different peripherals
> > - * and thus have different DMA channel mappings.)
> > - */
> > -#define DAVINCI_DMA_MCBSP_TX 2
> > -#define DAVINCI_DMA_MCBSP_RX 3
> > -#define DAVINCI_DMA_VPSS_HIST 4
> > -#define DAVINCI_DMA_VPSS_H3A 5
> > -#define DAVINCI_DMA_VPSS_PRVU 6
> > -#define DAVINCI_DMA_VPSS_RSZ 7
> > -#define DAVINCI_DMA_IMCOP_IMXINT 8
> > -#define DAVINCI_DMA_IMCOP_VLCDINT 9
> > -#define DAVINCI_DMA_IMCO_PASQINT 10
> > -#define DAVINCI_DMA_IMCOP_DSQINT 11
> > -#define DAVINCI_DMA_SPI_SPIX 16
> > -#define DAVINCI_DMA_SPI_SPIR 17
> > -#define DAVINCI_DMA_UART0_URXEVT0 18
> > -#define DAVINCI_DMA_UART0_UTXEVT0 19
> > -#define DAVINCI_DMA_UART1_URXEVT1 20
> > -#define DAVINCI_DMA_UART1_UTXEVT1 21
> > -#define DAVINCI_DMA_UART2_URXEVT2 22
> > -#define DAVINCI_DMA_UART2_UTXEVT2 23
> > -#define DAVINCI_DMA_MEMSTK_MSEVT 24
> > -#define DAVINCI_DMA_MMCRXEVT 26
> > -#define DAVINCI_DMA_MMCTXEVT 27
> > -#define DAVINCI_DMA_I2C_ICREVT 28
> > -#define DAVINCI_DMA_I2C_ICXEVT 29
> > -#define DAVINCI_DMA_GPIO_GPINT0 32
> > -#define DAVINCI_DMA_GPIO_GPINT1 33
> > -#define DAVINCI_DMA_GPIO_GPINT2 34
> > -#define DAVINCI_DMA_GPIO_GPINT3 35
> > -#define DAVINCI_DMA_GPIO_GPINT4 36
> > -#define DAVINCI_DMA_GPIO_GPINT5 37
> > -#define DAVINCI_DMA_GPIO_GPINT6 38
> > -#define DAVINCI_DMA_GPIO_GPINT7 39
> > -#define DAVINCI_DMA_GPIO_GPBNKINT0 40
> > -#define DAVINCI_DMA_GPIO_GPBNKINT1 41
> > -#define DAVINCI_DMA_GPIO_GPBNKINT2 42
> > -#define DAVINCI_DMA_GPIO_GPBNKINT3 43
> > -#define DAVINCI_DMA_GPIO_GPBNKINT4 44
> > -#define DAVINCI_DMA_TIMER0_TINT0 48
> > -#define DAVINCI_DMA_TIMER1_TINT1 49
> > -#define DAVINCI_DMA_TIMER2_TINT2 50
> > -#define DAVINCI_DMA_TIMER3_TINT3 51
> > -#define DAVINCI_DMA_PWM0 52
> > -#define DAVINCI_DMA_PWM1 53
> > -#define DAVINCI_DMA_PWM2 54
> > -
> > -/* DA830 specific EDMA3 information */
> > -#define EDMA_DA830_NUM_DMACH 32
> > -#define EDMA_DA830_NUM_TCC 32
> > -#define EDMA_DA830_NUM_PARAMENTRY 128
> > -#define EDMA_DA830_NUM_EVQUE 2
> > -#define EDMA_DA830_NUM_TC 2
> > -#define EDMA_DA830_CHMAP_EXIST 0
> > -#define EDMA_DA830_NUM_REGIONS 4
> > -#define DA830_DMACH2EVENT_MAP0 0x000FC03Fu
> > -#define DA830_DMACH2EVENT_MAP1 0x00000000u
> > -#define DA830_EDMA_ARM_OWN 0x30FFCCFFu
> > -
> > -/*ch_status paramater of callback function possible values*/
> > -#define DMA_COMPLETE 1
> > -#define DMA_CC_ERROR 2
> > -#define DMA_TC1_ERROR 3
> > -#define DMA_TC2_ERROR 4
> > -
> > -enum address_mode {
> > - INCR = 0,
> > - FIFO = 1
> > -};
> > -
> > -enum fifo_width {
> > - W8BIT = 0,
> > - W16BIT = 1,
> > - W32BIT = 2,
> > - W64BIT = 3,
> > - W128BIT = 4,
> > - W256BIT = 5
> > -};
> > -
> > -enum dma_event_q {
> > - EVENTQ_0 = 0,
> > - EVENTQ_1 = 1,
> > - EVENTQ_2 = 2,
> > - EVENTQ_3 = 3,
> > - EVENTQ_DEFAULT = -1
> > -};
> > -
> > -enum sync_dimension {
> > - ASYNC = 0,
> > - ABSYNC = 1
> > -};
> > -
> > -#define EDMA_CTLR_CHAN(ctlr, chan) (((ctlr) << 16) | (chan))
> > -#define EDMA_CTLR(i) ((i) >> 16)
> > -#define EDMA_CHAN_SLOT(i) ((i) & 0xffff)
> > -
> > -#define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */
> > -#define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */
> > -#define EDMA_CONT_PARAMS_ANY 1001
> > -#define EDMA_CONT_PARAMS_FIXED_EXACT 1002
> > -#define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003
> > -
> > -#define EDMA_MAX_CC 2
> > -
> > -/* alloc/free DMA channels and their dedicated parameter RAM slots */
> > -int edma_alloc_channel(int channel,
> > - void (*callback)(unsigned channel, u16 ch_status, void *data),
> > - void *data, enum dma_event_q);
> > -void edma_free_channel(unsigned channel);
> > -
> > -/* alloc/free parameter RAM slots */
> > -int edma_alloc_slot(unsigned ctlr, int slot);
> > -void edma_free_slot(unsigned slot);
> > -
> > -/* alloc/free a set of contiguous parameter RAM slots */
> > -int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count);
> > -int edma_free_cont_slots(unsigned slot, int count);
> > -
> > -/* calls that operate on part of a parameter RAM slot */
> > -void edma_set_src(unsigned slot, dma_addr_t src_port,
> > - enum address_mode mode, enum fifo_width);
> > -void edma_set_dest(unsigned slot, dma_addr_t dest_port,
> > - enum address_mode mode, enum fifo_width);
> > -void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst);
> > -void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx);
> > -void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx);
> > -void edma_set_transfer_params(unsigned slot, u16 acnt, u16 bcnt, u16 ccnt,
> > - u16 bcnt_rld, enum sync_dimension sync_mode);
> > -void edma_link(unsigned from, unsigned to);
> > -void edma_unlink(unsigned from);
> > -
> > -/* calls that operate on an entire parameter RAM slot */
> > -void edma_write_slot(unsigned slot, const struct edmacc_param *params);
> > -void edma_read_slot(unsigned slot, struct edmacc_param *params);
> > -
> > -/* channel control operations */
> > -int edma_start(unsigned channel);
> > -void edma_stop(unsigned channel);
> > -void edma_clean_channel(unsigned channel);
> > -void edma_clear_event(unsigned channel);
> > -void edma_pause(unsigned channel);
> > -void edma_resume(unsigned channel);
> > -
> > -struct edma_rsv_info {
> > -
> > - const s16 (*rsv_chans)[2];
> > - const s16 (*rsv_slots)[2];
> > -};
> > -
> > -/* platform_data for EDMA driver */
> > -struct edma_soc_info {
> > -
> > - /* how many dma resources of each type */
> > - unsigned n_channel;
> > - unsigned n_region;
> > - unsigned n_slot;
> > - unsigned n_tc;
> > - unsigned n_cc;
> > - /*
> > - * Default queue is expected to be a low-priority queue.
> > - * This way, long transfers on the default queue started
> > - * by the codec engine will not cause audio defects.
> > - */
> > - enum dma_event_q default_queue;
> > -
> > - /* Resource reservation for other cores */
> > - struct edma_rsv_info *rsv;
> > -
> > - const s8 (*queue_tc_mapping)[2];
> > - const s8 (*queue_priority_mapping)[2];
> > -};
> > -
> > -#endif
> > diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
> > index 665870d..0b81d6c 100644
> > --- a/arch/arm/plat-omap/Kconfig
> > +++ b/arch/arm/plat-omap/Kconfig
> > @@ -29,6 +29,7 @@ config ARCH_OMAP2PLUS
> > select PINCTRL
> > select PROC_DEVICETREE if PROC_FS
> > select SPARSE_IRQ
> > + select TI_PRIV_EDMA
> > select USE_OF
> > help
> > "Systems based on OMAP2, OMAP3, OMAP4 or OMAP5"
> > diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
> > index 023c8f2..e57cce3 100644
> > --- a/drivers/dma/edma.c
> > +++ b/drivers/dma/edma.c
> > @@ -24,7 +24,7 @@
> > #include <linux/slab.h>
> > #include <linux/spinlock.h>
> >
> > -#include <mach/edma.h>
> > +#include <linux/platform_data/edma.h>
> >
> > #include "dmaengine.h"
> > #include "virt-dma.h"
> > diff --git a/drivers/mmc/host/davinci_mmc.c b/drivers/mmc/host/davinci_mmc.c
> > index 17e186d..d1efacc 100644
> > --- a/drivers/mmc/host/davinci_mmc.c
> > +++ b/drivers/mmc/host/davinci_mmc.c
> > @@ -35,6 +35,7 @@
> > #include <linux/edma.h>
> > #include <linux/mmc/mmc.h>
> >
> > +#include <linux/platform_data/edma.h>
> > #include <linux/platform_data/mmc-davinci.h>
> >
> > /*
> > diff --git a/include/linux/mfd/davinci_voicecodec.h b/include/linux/mfd/davinci_voicecodec.h
> > index 0ab6132..7dd6524 100644
> > --- a/include/linux/mfd/davinci_voicecodec.h
> > +++ b/include/linux/mfd/davinci_voicecodec.h
> > @@ -26,8 +26,7 @@
> > #include <linux/kernel.h>
> > #include <linux/platform_device.h>
> > #include <linux/mfd/core.h>
> > -
> > -#include <mach/edma.h>
> > +#include <linux/platform_data/edma.h>
> >
> > /*
> > * Register values.
> > diff --git a/include/linux/platform_data/edma.h b/include/linux/platform_data/edma.h
> > new file mode 100644
> > index 0000000..2344ea2
> > --- /dev/null
> > +++ b/include/linux/platform_data/edma.h
> > @@ -0,0 +1,182 @@
> > +/*
> > + * TI EDMA definitions
> > + *
> > + * Copyright (C) 2006-2013 Texas Instruments.
> > + *
> > + * This program is free software; you can redistribute it and/or modify it
> > + * under the terms of the GNU General Public License as published by the
> > + * Free Software Foundation; either version 2 of the License, or (at your
> > + * option) any later version.
> > + */
> > +
> > +/*
> > + * This EDMA3 programming framework exposes two basic kinds of resource:
> > + *
> > + * Channel Triggers transfers, usually from a hardware event but
> > + * also manually or by "chaining" from DMA completions.
> > + * Each channel is coupled to a Parameter RAM (PaRAM) slot.
> > + *
> > + * Slot Each PaRAM slot holds a DMA transfer descriptor (PaRAM
> > + * "set"), source and destination addresses, a link to a
> > + * next PaRAM slot (if any), options for the transfer, and
> > + * instructions for updating those addresses. There are
> > + * more than twice as many slots as event channels.
> > + *
> > + * Each PaRAM set describes a sequence of transfers, either for one large
> > + * buffer or for several discontiguous smaller buffers. An EDMA transfer
> > + * is driven only from a channel, which performs the transfers specified
> > + * in its PaRAM slot until there are no more transfers. When that last
> > + * transfer completes, the "link" field may be used to reload the channel's
> > + * PaRAM slot with a new transfer descriptor.
> > + *
> > + * The EDMA Channel Controller (CC) maps requests from channels into physical
> > + * Transfer Controller (TC) requests when the channel triggers (by hardware
> > + * or software events, or by chaining). The two physical DMA channels provided
> > + * by the TCs are thus shared by many logical channels.
> > + *
> > + * DaVinci hardware also has a "QDMA" mechanism which is not currently
> > + * supported through this interface. (DSP firmware uses it though.)
> > + */
> > +
> > +#ifndef EDMA_H_
> > +#define EDMA_H_
> > +
> > +/* PaRAM slots are laid out like this */
> > +struct edmacc_param {
> > + unsigned int opt;
> > + unsigned int src;
> > + unsigned int a_b_cnt;
> > + unsigned int dst;
> > + unsigned int src_dst_bidx;
> > + unsigned int link_bcntrld;
> > + unsigned int src_dst_cidx;
> > + unsigned int ccnt;
> > +};
> > +
> > +/* fields in edmacc_param.opt */
> > +#define SAM BIT(0)
> > +#define DAM BIT(1)
> > +#define SYNCDIM BIT(2)
> > +#define STATIC BIT(3)
> > +#define EDMA_FWID (0x07 << 8)
> > +#define TCCMODE BIT(11)
> > +#define EDMA_TCC(t) ((t) << 12)
> > +#define TCINTEN BIT(20)
> > +#define ITCINTEN BIT(21)
> > +#define TCCHEN BIT(22)
> > +#define ITCCHEN BIT(23)
> > +
> > +/*ch_status paramater of callback function possible values*/
> > +#define DMA_COMPLETE 1
> > +#define DMA_CC_ERROR 2
> > +#define DMA_TC1_ERROR 3
> > +#define DMA_TC2_ERROR 4
> > +
> > +enum address_mode {
> > + INCR = 0,
> > + FIFO = 1
> > +};
> > +
> > +enum fifo_width {
> > + W8BIT = 0,
> > + W16BIT = 1,
> > + W32BIT = 2,
> > + W64BIT = 3,
> > + W128BIT = 4,
> > + W256BIT = 5
> > +};
> > +
> > +enum dma_event_q {
> > + EVENTQ_0 = 0,
> > + EVENTQ_1 = 1,
> > + EVENTQ_2 = 2,
> > + EVENTQ_3 = 3,
> > + EVENTQ_DEFAULT = -1
> > +};
> > +
> > +enum sync_dimension {
> > + ASYNC = 0,
> > + ABSYNC = 1
> > +};
> > +
> > +#define EDMA_CTLR_CHAN(ctlr, chan) (((ctlr) << 16) | (chan))
> > +#define EDMA_CTLR(i) ((i) >> 16)
> > +#define EDMA_CHAN_SLOT(i) ((i) & 0xffff)
> > +
> > +#define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */
> > +#define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */
> > +#define EDMA_CONT_PARAMS_ANY 1001
> > +#define EDMA_CONT_PARAMS_FIXED_EXACT 1002
> > +#define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003
> > +
> > +#define EDMA_MAX_CC 2
> > +
> > +/* alloc/free DMA channels and their dedicated parameter RAM slots */
> > +int edma_alloc_channel(int channel,
> > + void (*callback)(unsigned channel, u16 ch_status, void *data),
> > + void *data, enum dma_event_q);
> > +void edma_free_channel(unsigned channel);
> > +
> > +/* alloc/free parameter RAM slots */
> > +int edma_alloc_slot(unsigned ctlr, int slot);
> > +void edma_free_slot(unsigned slot);
> > +
> > +/* alloc/free a set of contiguous parameter RAM slots */
> > +int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count);
> > +int edma_free_cont_slots(unsigned slot, int count);
> > +
> > +/* calls that operate on part of a parameter RAM slot */
> > +void edma_set_src(unsigned slot, dma_addr_t src_port,
> > + enum address_mode mode, enum fifo_width);
> > +void edma_set_dest(unsigned slot, dma_addr_t dest_port,
> > + enum address_mode mode, enum fifo_width);
> > +void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst);
> > +void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx);
> > +void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx);
> > +void edma_set_transfer_params(unsigned slot, u16 acnt, u16 bcnt, u16 ccnt,
> > + u16 bcnt_rld, enum sync_dimension sync_mode);
> > +void edma_link(unsigned from, unsigned to);
> > +void edma_unlink(unsigned from);
> > +
> > +/* calls that operate on an entire parameter RAM slot */
> > +void edma_write_slot(unsigned slot, const struct edmacc_param *params);
> > +void edma_read_slot(unsigned slot, struct edmacc_param *params);
> > +
> > +/* channel control operations */
> > +int edma_start(unsigned channel);
> > +void edma_stop(unsigned channel);
> > +void edma_clean_channel(unsigned channel);
> > +void edma_clear_event(unsigned channel);
> > +void edma_pause(unsigned channel);
> > +void edma_resume(unsigned channel);
> > +
> > +struct edma_rsv_info {
> > +
> > + const s16 (*rsv_chans)[2];
> > + const s16 (*rsv_slots)[2];
> > +};
> > +
> > +/* platform_data for EDMA driver */
> > +struct edma_soc_info {
> > +
> > + /* how many dma resources of each type */
> > + unsigned n_channel;
> > + unsigned n_region;
> > + unsigned n_slot;
> > + unsigned n_tc;
> > + unsigned n_cc;
> > + /*
> > + * Default queue is expected to be a low-priority queue.
> > + * This way, long transfers on the default queue started
> > + * by the codec engine will not cause audio defects.
> > + */
> > + enum dma_event_q default_queue;
> > +
> > + /* Resource reservation for other cores */
> > + struct edma_rsv_info *rsv;
> > +
> > + const s8 (*queue_tc_mapping)[2];
> > + const s8 (*queue_priority_mapping)[2];
> > +};
> > +
> > +#endif
> > diff --git a/include/linux/platform_data/spi-davinci.h b/include/linux/platform_data/spi-davinci.h
> > index 7af305b..8dc2fa47 100644
> > --- a/include/linux/platform_data/spi-davinci.h
> > +++ b/include/linux/platform_data/spi-davinci.h
> > @@ -19,7 +19,7 @@
> > #ifndef __ARCH_ARM_DAVINCI_SPI_H
> > #define __ARCH_ARM_DAVINCI_SPI_H
> >
> > -#include <mach/edma.h>
> > +#include <linux/platform_data/edma.h>
> >
> > #define SPI_INTERN_CS 0xFF
> >
> > diff --git a/sound/soc/davinci/davinci-evm.c b/sound/soc/davinci/davinci-evm.c
> > index d55e647..591f547 100644
> > --- a/sound/soc/davinci/davinci-evm.c
> > +++ b/sound/soc/davinci/davinci-evm.c
> > @@ -14,6 +14,7 @@
> > #include <linux/timer.h>
> > #include <linux/interrupt.h>
> > #include <linux/platform_device.h>
> > +#include <linux/platform_data/edma.h>
> > #include <linux/i2c.h>
> > #include <sound/core.h>
> > #include <sound/pcm.h>
> > diff --git a/sound/soc/davinci/davinci-pcm.c b/sound/soc/davinci/davinci-pcm.c
> > index afab81f..9bdd71b 100644
> > --- a/sound/soc/davinci/davinci-pcm.c
> > +++ b/sound/soc/davinci/davinci-pcm.c
> > @@ -17,6 +17,7 @@
> > #include <linux/dma-mapping.h>
> > #include <linux/kernel.h>
> > #include <linux/genalloc.h>
> > +#include <linux/platform_data/edma.h>
> >
> > #include <sound/core.h>
> > #include <sound/pcm.h>
> > diff --git a/sound/soc/davinci/davinci-pcm.h b/sound/soc/davinci/davinci-pcm.h
> > index b6ef703..fbb710c 100644
> > --- a/sound/soc/davinci/davinci-pcm.h
> > +++ b/sound/soc/davinci/davinci-pcm.h
> > @@ -14,7 +14,7 @@
> >
> > #include <linux/genalloc.h>
> > #include <linux/platform_data/davinci_asp.h>
> > -#include <mach/edma.h>
> > +#include <linux/platform_data/edma.h>
> >
> > struct davinci_pcm_dma_params {
> > int channel; /* sync dma channel ID */
> > diff --git a/sound/soc/davinci/davinci-sffsdr.c b/sound/soc/davinci/davinci-sffsdr.c
> > index 5be65aa..074fc5d 100644
> > --- a/sound/soc/davinci/davinci-sffsdr.c
> > +++ b/sound/soc/davinci/davinci-sffsdr.c
> > @@ -17,6 +17,7 @@
> > #include <linux/timer.h>
> > #include <linux/interrupt.h>
> > #include <linux/platform_device.h>
> > +#include <linux/platform_data/edma.h>
> > #include <linux/gpio.h>
> > #include <sound/core.h>
> > #include <sound/pcm.h>
> > @@ -28,7 +29,6 @@
> > #include <asm/plat-sffsdr/sffsdr-fpga.h>
> > #endif
> >
> > -#include <mach/edma.h>
> >
> > #include "../codecs/pcm3008.h"
> > #include "davinci-pcm.h"
> > @@ -123,8 +123,8 @@ static struct resource sffsdr_snd_resources[] = {
> > };
> >
> > static struct evm_snd_platform_data sffsdr_snd_data = {
> > - .tx_dma_ch = DAVINCI_DMA_MCBSP_TX,
> > - .rx_dma_ch = DAVINCI_DMA_MCBSP_RX,
> > + .tx_dma_ch = 2, /* MCBSP_TX */
> > + .rx_dma_ch = 3, /* MCBSP_RX */
> > };
> >
> > static struct platform_device *sffsdr_snd_device;
> > --
> > 1.7.9.5
> >
> > _______________________________________________
> > Davinci-linux-open-source mailing list
> > Davinci-linux-open-source at linux.davincidsp.com
> > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
> >
>
>
> Regards,
> Gururaja
> _______________________________________________
> Davinci-linux-open-source mailing list
> Davinci-linux-open-source at linux.davincidsp.com
> http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
^ permalink raw reply
* [PATCH v4 05/14] dmaengine: edma: Add TI EDMA device tree binding
From: Matt Porter @ 2013-01-11 14:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <06e6ba0bd8984e1797c84d2926584909@DFLE72.ent.ti.com>
On Fri, Jan 11, 2013 at 07:54:05AM +0000, Hebbar, Gururaja wrote:
> On Fri, Jan 11, 2013 at 11:18:41, Porter, Matt wrote:
> > The binding definition is based on the generic DMA controller
> > binding.
> >
> > Signed-off-by: Matt Porter <mporter@ti.com>
> > ---
> > Documentation/devicetree/bindings/dma/ti-edma.txt | 51 +++++++++++++++++++++
> > 1 file changed, 51 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/dma/ti-edma.txt
> >
> > diff --git a/Documentation/devicetree/bindings/dma/ti-edma.txt b/Documentation/devicetree/bindings/dma/ti-edma.txt
> > new file mode 100644
> > index 0000000..3344345
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/dma/ti-edma.txt
> > @@ -0,0 +1,51 @@
> > +TI EDMA
> > +
> > +Required properties:
> > +- compatible : "ti,edma3"
> > +- ti,hwmods: Name of the hwmods associated to the EDMA
> > +- ti,edma-regions: Number of regions
> > +- ti,edma-slots: Number of slots
> > +- ti,edma-queue-tc-map: List of transfer control to queue mappings
> > +- ti,edma-queue-priority-map: List of queue priority mappings
> > +- ti,edma-default-queue: Default queue value
> > +
> > +Optional properties:
> > +- ti,edma-reserved-channels: List of reserved channel regions
> > +- ti,edma-reserved-slots: List of reserved slot regions
> > +- ti,edma-xbar-event-map: Crossbar event to channel map
> > +
> > +Example:
> > +
> > +edma: edma at 49000000 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
>
> address-cells & size-cells are only required when current node is a parent
> node & it has sibling/child nodes (that too if the child node uses "reg"
> property).
Yes, agreed. I addressed this in the actual dts but failed to update the
binding itself. Will update.
>
> > + reg = <0x49000000 0x10000>;
> > + interrupt-parent = <&intc>;
> > + interrupts = <12 13 14>;
> > + compatible = "ti,edma3";
> > + ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
> > + #dma-cells = <1>;
> > + dma-channels = <64>;
> > + ti,edma-regions = <4>;
> > + ti,edma-slots = <256>;
> > + ti,edma-reserved-channels = <0 2
> > + 14 2
> > + 26 6
> > + 48 4
> > + 56 8>;
> > + ti,edma-reserved-slots = <0 2
> > + 14 2
> > + 26 6
> > + 48 4
> > + 56 8
> > + 64 127>;
> > + ti,edma-queue-tc-map = <0 0
> > + 1 1
> > + 2 2>;
> > + ti,edma-queue-priority-map = <0 0
> > + 1 1
> > + 2 2>;
> > + ti,edma-default-queue = <0>;
> > + ti,edma-xbar-event-map = <1 12
> > + 2 13>;
> > +};
> > --
> > 1.7.9.5
> >
> > _______________________________________________
> > Davinci-linux-open-source mailing list
> > Davinci-linux-open-source at linux.davincidsp.com
> > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
> >
>
>
> Regards,
> Gururaja
^ permalink raw reply
* [PATCHv2 06/11] arm: arch_timer: factor out register accessors
From: Mark Rutland @ 2013-01-11 14:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50F01456.3030001@ti.com>
On Fri, Jan 11, 2013 at 01:32:06PM +0000, Santosh Shilimkar wrote:
> On Wednesday 09 January 2013 09:37 PM, Mark Rutland wrote:
> > Currently the arch_timer register accessors are thrown together with
> > the main driver, preventing us from porting the driver to other
> > architectures.
> >
> > This patch moves the register accessors into a header file, as with
> > the arm64 version. Constants required by the accessors are also moved.
> >
> > Additionally isbs are added in arch_timer_get_cnt{v,p}ct to prevent
> > the cpu from speculating the reads and returning stale values.
> >
> > Signed-off-by: Mark Rutland <mark.rutland@arm.com>
> > Acked-by: Catalin Marinas <catalin.marinas@arm.com>
> > Acked-by: Marc Zyngier <marc.zyngier@arm.com>
> > ---
> > arch/arm/include/asm/arch_timer.h | 101 +++++++++++++++++++++++++++++++++++++
> > arch/arm/kernel/arch_timer.c | 92 ---------------------------------
> > 2 files changed, 101 insertions(+), 92 deletions(-)
> >
> > diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h
> > index d40229d..701f2b7 100644
> > --- a/arch/arm/include/asm/arch_timer.h
> > +++ b/arch/arm/include/asm/arch_timer.h
> > @@ -1,13 +1,114 @@
> > #ifndef __ASMARM_ARCH_TIMER_H
> > #define __ASMARM_ARCH_TIMER_H
> >
> > +#include <asm/barrier.h>
> > #include <asm/errno.h>
> > +
> > #include <linux/clocksource.h>
> > +#include <linux/types.h>
> >
> > #ifdef CONFIG_ARM_ARCH_TIMER
> > int arch_timer_of_register(void);
> > int arch_timer_sched_clock_init(void);
> > struct timecounter *arch_timer_get_timecounter(void);
> > +
> > +#define ARCH_TIMER_CTRL_ENABLE (1 << 0)
> > +#define ARCH_TIMER_CTRL_IT_MASK (1 << 1)
> > +#define ARCH_TIMER_CTRL_IT_STAT (1 << 2)
> > +
> > +#define ARCH_TIMER_REG_CTRL 0
> > +#define ARCH_TIMER_REG_TVAL 1
> > +
> > +#define ARCH_TIMER_PHYS_ACCESS 0
> > +#define ARCH_TIMER_VIRT_ACCESS 1
> > +
> > +/*
> > + * These register accessors are marked inline so the compiler can
> > + * nicely work out which register we want, and chuck away the rest of
> > + * the code. At least it does so with a recent GCC (4.6.3).
> > + */
> > +static inline void arch_timer_reg_write(const int access, const int reg, u32 val)
> > +{
> > + if (access == ARCH_TIMER_PHYS_ACCESS) {
> > + switch (reg) {
> > + case ARCH_TIMER_REG_CTRL:
> > + asm volatile("mcr p15, 0, %0, c14, c2, 1" : : "r" (val));
> > + break;
> > + case ARCH_TIMER_REG_TVAL:
> > + asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val));
> > + break;
> > + }
> > + }
> > +
> > + if (access == ARCH_TIMER_VIRT_ACCESS) {
> > + switch (reg) {
> > + case ARCH_TIMER_REG_CTRL:
> > + asm volatile("mcr p15, 0, %0, c14, c3, 1" : : "r" (val));
> > + break;
> > + case ARCH_TIMER_REG_TVAL:
> > + asm volatile("mcr p15, 0, %0, c14, c3, 0" : : "r" (val));
> > + break;
> > + }
> > + }
> > +
> > + isb();
> > +}
> The isb() additions is actually a sepoerate fix. I suggest you to split
> the subject patch into 1) Movement of header data 2) isb() additions.
>
> Feel free to add my ack on updated patches if you agree.
Thanks, will do.
> Regards,
> Santosh
>
>
Mark.
^ permalink raw reply
* [PATCH 1/4 v10] arm: use devicetree to get smp_twd clock
From: Rob Herring @ 2013-01-11 14:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130110233442.GA30875@n2100.arm.linux.org.uk>
On 01/10/2013 05:34 PM, Russell King - ARM Linux wrote:
> Mark,
>
> Rafael just asked me to look at this patch, though I guess these comments
> should be directed to Rob who was the original patch author.
>
> On Fri, Jan 04, 2013 at 10:35:43AM -0600, Mark Langsdorf wrote:
>> diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c
>> index 49f335d..dad2d81 100644
>> --- a/arch/arm/kernel/smp_twd.c
>> +++ b/arch/arm/kernel/smp_twd.c
>> @@ -239,12 +239,15 @@ static irqreturn_t twd_handler(int irq, void *dev_id)
>> return IRQ_NONE;
>> }
>>
>> -static struct clk *twd_get_clock(void)
>> +static struct clk *twd_get_clock(struct device_node *np)
>> {
>> struct clk *clk;
>> int err;
>>
>> - clk = clk_get_sys("smp_twd", NULL);
>> + if (np)
>> + clk = of_clk_get(np, 0);
>> + else
>> + clk = clk_get_sys("smp_twd", NULL);
>> if (IS_ERR(clk)) {
>> pr_err("smp_twd: clock not found: %d\n", (int)PTR_ERR(clk));
>> return clk;
>> @@ -257,6 +260,7 @@ static struct clk *twd_get_clock(void)
>> return ERR_PTR(err);
>> }
>>
>> + twd_timer_rate = clk_get_rate(clk);
>
> Hmm, so this overrides the later clk_get_rate() in twd_timer_setup(), making
> the later one redundant. However...
>
>> return clk;
>> }
>>
>> @@ -285,7 +289,7 @@ static int __cpuinit twd_timer_setup(struct clock_event_device *clk)
>> * during the runtime of the system.
>> */
>> if (!common_setup_called) {
>> - twd_clk = twd_get_clock();
>> + twd_clk = twd_get_clock(NULL);
>>
>> /*
>> * We use IS_ERR_OR_NULL() here, because if the clock stubs
>> @@ -373,6 +377,8 @@ int __init twd_local_timer_register(struct twd_local_timer *tlt)
>> if (!twd_base)
>> return -ENOMEM;
>>
>> + twd_clk = twd_get_clock(NULL);
>> +
>> return twd_local_timer_common_register();
>
> Ok, so this sets up twd_clk, and also twd_timer_rate, but
> twd_local_timer_common_register() just ends up registering the set of
> function pointers with the local timer code. Some point later, the
> ->setup function is called, and that will happen with common_setup_called
> false. The result will be another call to twd_get_clock().
>
>> }
>>
>> @@ -405,6 +411,8 @@ void __init twd_local_timer_of_register(void)
>> goto out;
>> }
>>
>> + twd_clk = twd_get_clock(np);
>> +
>> err = twd_local_timer_common_register();
>
> And a similar thing happens here. Except... the twd_clk gets overwritten
> by the call to twd_get_clock(NULL) from twd_timer_setup().
>
> I wonder if it would be much better to move twd_get_clock() out of
> twd_timer_setup() entirely, moving it into twd_local_timer_common_register().
> twd_local_timer_common_register() would have to take the dev node.
> Also, leave the setting of twd_timer_rate in twd_timer_setup().
>
> An alternative strategy would be to move the initialization of the
> timer rate also into twd_local_timer_common_register(), detect the
> NULL or error clock, and run the calibration from there (I don't think
> we can move the calibration). If that's chosen, then "common_setup_called"
> should probably be renamed to "twd_calibration_done".
>
> What do you think?
Yes, things can be simplified a bit. How about this patch? I moved the clk
setup to twd_local_timer_common_register. Then we just rely on twd_timer_rate
being 0 when there is no clock and we need to do calibration. Then we can get
rid of common_setup_called altogether.
diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c
index dc9bb01..2201e2d 100644
--- a/arch/arm/kernel/smp_twd.c
+++ b/arch/arm/kernel/smp_twd.c
@@ -30,7 +30,6 @@ static void __iomem *twd_base;
static struct clk *twd_clk;
static unsigned long twd_timer_rate;
-static bool common_setup_called;
static DEFINE_PER_CPU(bool, percpu_setup_called);
static struct clock_event_device __percpu **twd_evt;
@@ -238,25 +237,28 @@ static irqreturn_t twd_handler(int irq, void *dev_id)
return IRQ_NONE;
}
-static struct clk *twd_get_clock(void)
+static void twd_get_clock(struct device_node *np)
{
- struct clk *clk;
int err;
- clk = clk_get_sys("smp_twd", NULL);
- if (IS_ERR(clk)) {
- pr_err("smp_twd: clock not found: %d\n", (int)PTR_ERR(clk));
- return clk;
+ if (np)
+ twd_clk = of_clk_get(np, 0);
+ else
+ twd_clk = clk_get_sys("smp_twd", NULL);
+
+ if (IS_ERR(twd_clk)) {
+ pr_err("smp_twd: clock not found: %d\n", (int)PTR_ERR(twd_clk));
+ return;
}
- err = clk_prepare_enable(clk);
+ err = clk_prepare_enable(twd_clk);
if (err) {
pr_err("smp_twd: clock failed to prepare+enable: %d\n", err);
- clk_put(clk);
- return ERR_PTR(err);
+ clk_put(twd_clk);
+ return;
}
- return clk;
+ twd_timer_rate = clk_get_rate(twd_clk);
}
/*
@@ -279,26 +281,7 @@ static int __cpuinit twd_timer_setup(struct clock_event_device *clk)
}
per_cpu(percpu_setup_called, cpu) = true;
- /*
- * This stuff only need to be done once for the entire TWD cluster
- * during the runtime of the system.
- */
- if (!common_setup_called) {
- twd_clk = twd_get_clock();
-
- /*
- * We use IS_ERR_OR_NULL() here, because if the clock stubs
- * are active we will get a valid clk reference which is
- * however NULL and will return the rate 0. In that case we
- * need to calibrate the rate instead.
- */
- if (!IS_ERR_OR_NULL(twd_clk))
- twd_timer_rate = clk_get_rate(twd_clk);
- else
- twd_calibrate_rate();
-
- common_setup_called = true;
- }
+ twd_calibrate_rate();
/*
* The following is done once per CPU the first time .setup() is
@@ -329,7 +312,7 @@ static struct local_timer_ops twd_lt_ops __cpuinitdata = {
.stop = twd_timer_stop,
};
-static int __init twd_local_timer_common_register(void)
+static int __init twd_local_timer_common_register(struct device_node *np)
{
int err;
@@ -349,6 +332,8 @@ static int __init twd_local_timer_common_register(void)
if (err)
goto out_irq;
+ twd_get_clock(np);
+
return 0;
out_irq:
@@ -372,7 +357,7 @@ int __init twd_local_timer_register(struct twd_local_timer *tlt)
if (!twd_base)
return -ENOMEM;
- return twd_local_timer_common_register();
+ return twd_local_timer_common_register(NULL);
}
#ifdef CONFIG_OF
@@ -404,7 +389,7 @@ void __init twd_local_timer_of_register(void)
goto out;
}
- err = twd_local_timer_common_register();
+ err = twd_local_timer_common_register(np);
out:
WARN(err, "twd_local_timer_of_register failed (%d)\n", err);
^ permalink raw reply related
* [PATCH 0/2] ARM: tegra: Add cpu node in device tree
From: Lorenzo Pieralisi @ 2013-01-11 14:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1357909914-28994-1-git-send-email-hdoyu@nvidia.com>
On Fri, Jan 11, 2013 at 01:11:52PM +0000, Hiroshi Doyu wrote:
> Hi,
>
> From the discussion(*1) of CPU core# detection, DT cpu node will be
> the only way to do it right. So we need to add cpu nodes on the
> existing Tegra SoCs(T20/T30) first in order to remove the existing A9
> SCU detection later, where DT cpu# detection fails, we would consider
> a single cpu core avalable.
>
> Tested only with T30.
>
> Hiroshi Doyu (2):
> ARM: tegra20: Add cpu node
> ARM: tegra30: Add cpu node
>
> arch/arm/boot/dts/tegra20.dtsi | 29 +++++++++++++++++++++++++++++
> arch/arm/boot/dts/tegra30.dtsi | 29 +++++++++++++++++++++++++++++
> 2 files changed, 58 insertions(+)
>
> *1:
> http://lists.infradead.org/pipermail/linux-arm-kernel/2013-January/140209.html
Looks ok, but you should copy devicetree-discuss at lists.ozlabs.org for
any set DT related.
FWIW on the series:
Reviewed-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
^ permalink raw reply
* [PATCH v2] arm: mvebu: add DTS file for Marvell RD-A370-A1 board
From: Florian Fainelli @ 2013-01-11 14:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <3816648.2TVsTiMOWx@bender>
Thomas, Gregory,
Le 01/09/13 20:56, Florian Fainelli a ?crit :
> This patch adds the DTS file to support the Marvell RD-A370-A1
> (Reference Design board) also known as RD-88F6710 board. It is almost
> entirely similar to the DB-A370 board except that the first Ethernet PHY
> is SGMII-wired and the second is a switch which is RGMII-wired.
Who is going to take this patch? Since this is a new DTS file there are
little chances it breaks anything, could it be taken for an upcoming 3.8-rc?
Thanks.
--
Florian
^ permalink raw reply
* [PATCH v2] arm: mvebu: add DTS file for Marvell RD-A370-A1 board
From: Gregory CLEMENT @ 2013-01-11 14:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50F02570.9050208@openwrt.org>
Florian,
On 01/11/2013 03:45 PM, Florian Fainelli wrote:
> Thomas, Gregory,
>
> Le 01/09/13 20:56, Florian Fainelli a ?crit :
>> This patch adds the DTS file to support the Marvell RD-A370-A1
>> (Reference Design board) also known as RD-88F6710 board. It is almost
>> entirely similar to the DB-A370 board except that the first Ethernet PHY
>> is SGMII-wired and the second is a switch which is RGMII-wired.
>
> Who is going to take this patch? Since this is a new DTS file there are
> little chances it breaks anything, could it be taken for an upcoming 3.8-rc?
It is Jason who takes care of gathering all the patches for mvebu.
As it is not a fix for a bug but more a new "feature" (at least a support
for a new board), I doubt that it could be part of 3.8-rc.
But as far as I am concerned I am not against having this patch in 3.8-rc.
Regards
>
> Thanks.
> --
> Florian
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply
* [PATCHv2 08/11] arm: arch_timer: add arch_counter_set_user_access
From: Mark Rutland @ 2013-01-11 14:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50F01646.4010203@ti.com>
On Fri, Jan 11, 2013 at 01:40:22PM +0000, Santosh Shilimkar wrote:
> On Wednesday 09 January 2013 09:37 PM, Mark Rutland wrote:
> > Several bits in CNTKCTL reset to 0, including PL0VTEN. For platforms
> > using the generic timer which wish to have a fast gettimeofday vDSO
> > implementation, these bits must be set to 1 by the kernel. On other
> > platforms, the bootloader might enable userspace access when we don't
> > want it.
> >
> > This patch adds arch_counter_set_user_access, which sets the PL0 access
> > permissions to that required by the platform. For arm, this currently
> minor nit.
> s/arm/ARM
>
> > means disabling all userspace access.
> >
> > Signed-off-by: Mark Rutland <mark.rutland@arm.com>
> > ---
> > arch/arm/include/asm/arch_timer.h | 11 +++++++++++
> > arch/arm/kernel/arch_timer.c | 2 ++
> > 2 files changed, 13 insertions(+), 0 deletions(-)
> >
> > diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h
> > index 701f2b7..05e3593 100644
> > --- a/arch/arm/include/asm/arch_timer.h
> > +++ b/arch/arm/include/asm/arch_timer.h
> > @@ -108,6 +108,17 @@ static inline u64 arch_counter_get_cntvct(void)
> > return cval;
> > }
> >
> > +static inline void __cpuinit arch_counter_set_user_access(void)
> > +{
> > + u32 cntkctl;
> > +
> > + asm volatile("mrc p15, 0, %0, c14, c1, 0" : "=r" (cntkctl));
> > +
> > + /* disable user access to everything */
> > + cntkctl &= ~((3 << 8) | (7 << 0));
> > +
> > + asm volatile("mcr p15, 0, %0, c14, c1, 0" : : "r" (cntkctl));
> > +}
> >
> > #else
> > static inline int arch_timer_of_register(void)
> > diff --git a/arch/arm/kernel/arch_timer.c b/arch/arm/kernel/arch_timer.c
> > index 834d347..4f39e68 100644
> > --- a/arch/arm/kernel/arch_timer.c
> > +++ b/arch/arm/kernel/arch_timer.c
> > @@ -155,6 +155,8 @@ static int __cpuinit arch_timer_setup(struct clock_event_device *clk)
> > enable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI], 0);
> > }
> >
> > + arch_counter_set_user_access();
> So how do you expect platform to enabled the user-space access in case
> they want to access it for some cases.
Unlike AArch64, at the moment we don't have the infrastructure to map this for
userspace accesses, so it isn't much of a problem.
If in future we wish to map it on 32bit platforms, the arm implementation of
arch_counter_set_user_access can be modified to allow userspace access to
specific registers, and additional code would be required to actually map it
into the user address space, etc.
>
> Regards
> Santosh
>
Thanks,
Mark.
^ permalink raw reply
* [PATCH v2] arm: mvebu: add DTS file for Marvell RD-A370-A1 board
From: Jason Cooper @ 2013-01-11 14:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50F02570.9050208@openwrt.org>
Florian,
On Fri, Jan 11, 2013 at 03:45:04PM +0100, Florian Fainelli wrote:
> Le 01/09/13 20:56, Florian Fainelli a ?crit :
> >This patch adds the DTS file to support the Marvell RD-A370-A1
> >(Reference Design board) also known as RD-88F6710 board. It is almost
> >entirely similar to the DB-A370 board except that the first Ethernet PHY
> >is SGMII-wired and the second is a switch which is RGMII-wired.
>
> Who is going to take this patch? Since this is a new DTS file there
> are little chances it breaks anything, could it be taken for an
> upcoming 3.8-rc?
No, only fixes go in for the current -rc. It'll be included for v3.9, I
have it in my queue.
thx,
Jason.
^ permalink raw reply
* ERROR: "__aeabi_uldivmod" [drivers/pinctrl/pinctrl-single.ko] undefined!
From: Russell King - ARM Linux @ 2013-01-11 15:00 UTC (permalink / raw)
To: linux-arm-kernel
Linus,
The above error happens in builds including pinctrl-single - the reason
is this, where resource_size_t may be 64-bit.
gpio->range.pin_base = (r.start - pcs->res->start) / mux_bytes;
gpio->range.npins = (r.end - r.start) / mux_bytes + 1;
This leads to a 64-bit division by an extended 64-bit, resulting in the
call to our (unimplemented) 64-bit-by-64-bit division routines.
This needs fixing - you probably want to cast the difference down to an
'unsigned' first, and also maybe check that it does fit in an unsigned
too?
^ permalink raw reply
* [PATCHv2 09/11] arm: arch_timer: move core to drivers/clocksource
From: Mark Rutland @ 2013-01-11 15:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50F01830.5040205@ti.com>
On Fri, Jan 11, 2013 at 01:48:32PM +0000, Santosh Shilimkar wrote:
> On Wednesday 09 January 2013 09:37 PM, Mark Rutland wrote:
> > The core functionality of the arch_timer driver is not directly tied to
> > anything under arch/arm, and can be split out.
> >
> > This patch factors out the core of the arch_timer driver, so it can be
> > shared with other architectures. A couple of functions are added so
> > that architecture-specific code can interact with the driver without
> > needing to touch its internals.
> >
> > The ARM_ARCH_TIMER config variable is moved out to
> > drivers/clocksource/Kconfig, existing uses in arch/arm are replaced with
> > USE_ARM_ARCH_TIMER, which selects it.
> >
> > Signed-off-by: Mark Rutland <mark.rutland@arm.com>
> > Acked-by: Catalin Marinas <catalin.marinas@arm.com>
> > Acked-by: Marc Zyngier <marc.zyngier@arm.com>
> > ---
> > arch/arm/Kconfig | 3 +-
> > arch/arm/include/asm/arch_timer.h | 19 +--
> > arch/arm/kernel/arch_timer.c | 375 ++--------------------------------
> > arch/arm/mach-omap2/Kconfig | 2 +-
> > drivers/clocksource/Kconfig | 3 +
> > drivers/clocksource/Makefile | 1 +
> > drivers/clocksource/arm_arch_timer.c | 374 +++++++++++++++++++++++++++++++++
> > include/clocksource/arm_arch_timer.h | 63 ++++++
> > 8 files changed, 465 insertions(+), 375 deletions(-)
> > create mode 100644 drivers/clocksource/arm_arch_timer.c
> > create mode 100644 include/clocksource/arm_arch_timer.h
> >
> It would have been easy if you have formated the patch with -C option.
> That will just leave the delta changes only and hiding the file
> movement related diff.
Sorry, I'll make sure I do that next time.
> > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> > index f95ba14..487696a 100644
> > --- a/arch/arm/Kconfig
> > +++ b/arch/arm/Kconfig
> > @@ -1567,9 +1567,10 @@ config HAVE_ARM_SCU
> > help
> > This option enables support for the ARM system coherency unit
> >
> > -config ARM_ARCH_TIMER
> > +config USE_ARM_ARCH_TIMER
> > bool "Architected timer support"
> > depends on CPU_V7
> > + select ARM_ARCH_TIMER
> > help
> > This option enables support for the ARM architected timer
> >
> How about HAVE_ARM_ARCH_TIMER in-line with HAVE_ARM_TWD. No strong
> opinion though.
Sure. It'll also make it more consistent with HAVE_ARM_SCU.
>
> Regards
> Santosh
>
Thanks,
Mark.
^ permalink raw reply
* [PATCHv2 08/11] arm: arch_timer: add arch_counter_set_user_access
From: Will Deacon @ 2013-01-11 15:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130111145451.GD19765@e106331-lin.cambridge.arm.com>
On Fri, Jan 11, 2013 at 02:54:52PM +0000, Mark Rutland wrote:
> On Fri, Jan 11, 2013 at 01:40:22PM +0000, Santosh Shilimkar wrote:
> > So how do you expect platform to enabled the user-space access in case
> > they want to access it for some cases.
>
> Unlike AArch64, at the moment we don't have the infrastructure to map this for
> userspace accesses, so it isn't much of a problem.
>
> If in future we wish to map it on 32bit platforms, the arm implementation of
> arch_counter_set_user_access can be modified to allow userspace access to
> specific registers, and additional code would be required to actually map it
> into the user address space, etc.
I'd also add that it's not up to a platform to decide whether to expose
this to userspace: it needs to be an architecture-wide decision. Otherwise,
userspace becomes SoC-specific, which is a complete disaster.
So, if userspace people want these available, they need to convince us to
flip the switch. In the meantime, it should default to off so that if/when
we do enable it we can do it in a sane manner for ARM (perhaps via the
vectors page).
Will
^ permalink raw reply
* [PATCH] ARM: spinlock: avoid exclusive accesses on unlock() path
From: Will Deacon @ 2013-01-11 15:07 UTC (permalink / raw)
To: linux-arm-kernel
When unlocking a spinlock, all we need to do is increment the owner
field of the lock. Since only one CPU can be performing an unlock()
operation for a given lock, this doesn't need to be exclusive.
This patch simplifies arch_spin_unlock to use non-exclusive accesses
when updating the owner field of the lock.
Signed-off-by: Will Deacon <will.deacon@arm.com>
---
arch/arm/include/asm/spinlock.h | 16 +---------------
1 file changed, 1 insertion(+), 15 deletions(-)
diff --git a/arch/arm/include/asm/spinlock.h b/arch/arm/include/asm/spinlock.h
index b4ca707..6220e9f 100644
--- a/arch/arm/include/asm/spinlock.h
+++ b/arch/arm/include/asm/spinlock.h
@@ -119,22 +119,8 @@ static inline int arch_spin_trylock(arch_spinlock_t *lock)
static inline void arch_spin_unlock(arch_spinlock_t *lock)
{
- unsigned long tmp;
- u32 slock;
-
smp_mb();
-
- __asm__ __volatile__(
-" mov %1, #1\n"
-"1: ldrex %0, [%2]\n"
-" uadd16 %0, %0, %1\n"
-" strex %1, %0, [%2]\n"
-" teq %1, #0\n"
-" bne 1b"
- : "=&r" (slock), "=&r" (tmp)
- : "r" (&lock->slock)
- : "cc");
-
+ lock->tickets.owner++;
dsb_sev();
}
--
1.8.0
^ permalink raw reply related
* [PATCH] cpsw: Add support to read cpu MAC address
From: Michal Bachraty @ 2013-01-11 15:15 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Michal Bachraty <michal.bachraty@streamunlimited.com>
---
Documentation/devicetree/bindings/net/cpsw.txt | 10 +-
arch/arm/boot/dts/am33xx.dtsi | 5 +-
drivers/net/ethernet/ti/cpsw.c | 121 +++++++++++++++++++++---
include/linux/platform_data/cpsw.h | 8 ++
4 files changed, 128 insertions(+), 16 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/cpsw.txt b/Documentation/devicetree/bindings/net/cpsw.txt
index dcaabe9..432122c 100644
--- a/Documentation/devicetree/bindings/net/cpsw.txt
+++ b/Documentation/devicetree/bindings/net/cpsw.txt
@@ -4,7 +4,7 @@ TI SoC Ethernet Switch Controller Device Tree Bindings
Required properties:
- compatible : Should be "ti,cpsw"
- reg : physical base address and size of the cpsw
- registers map
+ registers map and mac-address cpu config registers
- interrupts : property with a value describing the interrupt
number
- interrupt-parent : The parent interrupt controller
@@ -25,17 +25,23 @@ Required properties:
- slave_reg_ofs : Specifies slave register offset
- sliver_reg_ofs : Specifies slave sliver register offset
- phy_id : Specifies slave phy id
-- mac-address : Specifies slave MAC address
Optional properties:
- ti,hwmods : Must be "cpgmac0"
- no_bd_ram : Must be 0 or 1
+- mac-address-source : Specifies source of MAC address ("user-defined-mac",
+ "cpu-id0-mac", "cpu-id01-mac", "random-mac"). If not
+ specified, "cpu-id0-mac" is selected
+- mac-address : Specifies slave MAC address for "user-defined-mac"
+ property value. When MAC address is not correct,
+ "cpu-id01-mac" is selected
Note: "ti,hwmods" field is used to fetch the base address and irq
resources from TI, omap hwmod data base during device registration.
Future plan is to migrate hwmod data base contents into device tree
blob so that, all the required data will be used from device tree dts
file.
+As default, MAC address is set from CPU (MAC_ID0 register)
Examples:
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 47fb059..f4845a3 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -307,7 +307,8 @@
slaves = <1>;
reg = <0x4a100000 0x800
0x4a101200 0x100
- 0x4a101000 0x100>;
+ 0x4a101000 0x100
+ 0x44e10630 0x0C>;
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&intc>;
@@ -317,7 +318,7 @@
cpsw_emac0: slave at 0 {
slave_reg_ofs = <0x208>;
sliver_reg_ofs = <0xd80>;
- mac-address = [ 00 00 00 00 00 00 ];
+ mac-address-source = "cpu-id0-mac";
};
davinci_mdio: mdio at 4a101000 {
diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index fb1a692..b777116 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -184,6 +184,13 @@ struct cpsw_sliver_regs {
u32 rx_pri_map;
};
+struct config_regs {
+ u32 mac_id0_lo;
+ u32 mac_id0_hi;
+ u32 mac_id1_lo;
+ u32 mac_id1_hi;
+};
+
struct cpsw_slave {
struct cpsw_slave_regs __iomem *regs;
struct cpsw_sliver_regs __iomem *sliver;
@@ -199,12 +206,14 @@ struct cpsw_priv {
struct net_device *ndev;
struct resource *cpsw_res;
struct resource *cpsw_ss_res;
+ struct resource *conf_res;
struct napi_struct napi;
struct device *dev;
struct cpsw_platform_data data;
struct cpsw_regs __iomem *regs;
struct cpsw_ss_regs __iomem *ss_regs;
struct cpsw_host_regs __iomem *host_port_regs;
+ struct config_regs __iomem *conf_regs;
u32 msg_enable;
struct net_device_stats stats;
int rx_packet_max;
@@ -363,6 +372,20 @@ static void cpsw_set_slave_mac(struct cpsw_slave *slave,
__raw_writel(mac_lo(priv->mac_addr), &slave->regs->sa_lo);
}
+static void cpsw_get_cpu_id0_mac(struct cpsw_priv *priv)
+{
+ *((u32 *)priv->mac_addr) = __raw_readl(&priv->conf_regs->mac_id0_hi);
+ *((u16 *)(priv->mac_addr + 4)) = __raw_readw(
+ &priv->conf_regs->mac_id0_lo);
+}
+
+static void cpsw_get_cpu_id1_mac(struct cpsw_priv *priv)
+{
+ *((u32 *)priv->mac_addr) = __raw_readl(&priv->conf_regs->mac_id1_hi);
+ *((u16 *)(priv->mac_addr + 4)) = __raw_readw(
+ &priv->conf_regs->mac_id1_lo);
+}
+
static void _cpsw_adjust_link(struct cpsw_slave *slave,
struct cpsw_priv *priv, bool *link)
{
@@ -831,6 +854,7 @@ static int cpsw_probe_dt(struct cpsw_platform_data *data,
struct cpsw_slave_data *slave_data = data->slave_data + i;
const char *phy_id = NULL;
const void *mac_addr = NULL;
+ const char *source_mac;
if (of_property_read_string(slave_node, "phy_id", &phy_id)) {
pr_err("Missing slave[%d] phy_id property\n", i);
@@ -855,9 +879,39 @@ static int cpsw_probe_dt(struct cpsw_platform_data *data,
}
slave_data->sliver_reg_ofs = prop;
+ /* set default mac address to CPU_ID0_MAC */
+ slave_data->mac_addr_source = CPU_ID0_MAC;
+
mac_addr = of_get_mac_address(slave_node);
- if (mac_addr)
- memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
+ if (mac_addr) {
+ if (is_valid_ether_addr(mac_addr)) {
+ slave_data->mac_addr_source = USER_DEFINED_MAC;
+ memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
+ } else {
+ pr_info("Bad user defined MACID.Using CPU "\
+ "MACID0\n");
+ }
+ }
+
+ source_mac = of_get_property(slave_node, "mac-address-source",
+ NULL);
+
+ if (source_mac) {
+ if (!strcmp(source_mac, "user-defined-mac"))
+ slave_data->mac_addr_source = USER_DEFINED_MAC;
+ else if (!strcmp(source_mac, "cpu-id0-mac"))
+ slave_data->mac_addr_source = CPU_ID0_MAC;
+ else if (!strcmp(source_mac, "cpu-id1-mac"))
+ slave_data->mac_addr_source = CPU_ID1_MAC;
+ else if (!strcmp(source_mac, "random-mac"))
+ slave_data->mac_addr_source = RANDOM_MAC;
+ else {
+ pr_err("Slave[%d] Bad mac-address-source"\
+ "proprerty value\n", i);
+ ret = -EINVAL;
+ goto error_ret;
+ }
+ }
i++;
}
@@ -915,16 +969,6 @@ static int __devinit cpsw_probe(struct platform_device *pdev)
}
data = &priv->data;
- if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
- memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
- pr_info("Detected MACID = %pM", priv->mac_addr);
- } else {
- eth_random_addr(priv->mac_addr);
- pr_info("Random MACID = %pM", priv->mac_addr);
- }
-
- memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
-
priv->slaves = kzalloc(sizeof(struct cpsw_slave) * data->slaves,
GFP_KERNEL);
if (!priv->slaves) {
@@ -986,6 +1030,54 @@ static int __devinit cpsw_probe(struct platform_device *pdev)
}
priv->ss_regs = regs;
+ /* configuration register registering*/
+ priv->conf_res = platform_get_resource(pdev, IORESOURCE_MEM, 3);
+ if (!priv->conf_res) {
+ dev_err(priv->dev, "error getting i/o resource\n");
+ ret = -ENOENT;
+ goto clean_clk_ret;
+ }
+
+ if (!request_mem_region(priv->conf_res->start,
+ resource_size(priv->conf_res), ndev->name)) {
+ dev_err(priv->dev, "failed request i/o region\n");
+ ret = -ENXIO;
+ goto clean_clk_ret;
+ }
+
+ regs = ioremap(priv->conf_res->start,
+ resource_size(priv->conf_res));
+ if (!regs) {
+ dev_err(priv->dev, "unable to map i/o region\n");
+ goto clean_configuration_iores_ret;
+ }
+ priv->conf_regs = regs;
+
+ switch (data->slave_data[0].mac_addr_source) {
+ case USER_DEFINED_MAC:
+ /* read MAC adddress from DT*/
+ memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
+ pr_info("User defined MACID = %pM", priv->mac_addr);
+ break;
+ case CPU_ID0_MAC:
+ /* read MAC adddress from CPU MACID0*/
+ cpsw_get_cpu_id0_mac(priv);
+ pr_info("CPU MACID0 = %pM\n", priv->mac_addr);
+ break;
+ case CPU_ID1_MAC:
+ /* read MAC adddress from CPU MACID1*/
+ cpsw_get_cpu_id1_mac(priv);
+ pr_info("CPU MACID1 = %pM\n", priv->mac_addr);
+ break;
+ case RANDOM_MAC:
+ /* random MAC*/
+ eth_random_addr(priv->mac_addr);
+ pr_info("Random MACID = %pM\n", priv->mac_addr);
+ break;
+ }
+
+ memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
+
for_each_slave(priv, cpsw_slave_init, priv);
memset(&dma_params, 0, sizeof(dma_params));
@@ -1099,6 +1191,9 @@ clean_dma_ret:
cpdma_ctlr_destroy(priv->dma);
clean_iomap_ret:
iounmap(priv->regs);
+clean_configuration_iores_ret:
+ release_mem_region(priv->conf_res->start,
+ resource_size(priv->conf_res));
clean_cpsw_ss_iores_ret:
release_mem_region(priv->cpsw_ss_res->start,
resource_size(priv->cpsw_ss_res));
@@ -1133,6 +1228,8 @@ static int __devexit cpsw_remove(struct platform_device *pdev)
resource_size(priv->cpsw_res));
release_mem_region(priv->cpsw_ss_res->start,
resource_size(priv->cpsw_ss_res));
+ release_mem_region(priv->conf_res->start,
+ resource_size(priv->conf_res));
pm_runtime_disable(&pdev->dev);
clk_put(priv->clk);
kfree(priv->slaves);
diff --git a/include/linux/platform_data/cpsw.h b/include/linux/platform_data/cpsw.h
index c4e23d0..ef064b0 100644
--- a/include/linux/platform_data/cpsw.h
+++ b/include/linux/platform_data/cpsw.h
@@ -17,12 +17,20 @@
#include <linux/if_ether.h>
+enum mac_address_source {
+ USER_DEFINED_MAC = 0,
+ CPU_ID0_MAC,
+ CPU_ID1_MAC,
+ RANDOM_MAC,
+};
+
struct cpsw_slave_data {
u32 slave_reg_ofs;
u32 sliver_reg_ofs;
const char *phy_id;
int phy_if;
u8 mac_addr[ETH_ALEN];
+ enum mac_address_source mac_addr_source;
};
struct cpsw_platform_data {
--
1.7.9.5
^ permalink raw reply related
* [PATCH 0/3] hw_breakpoint updates for 3.9
From: Will Deacon @ 2013-01-11 15:28 UTC (permalink / raw)
To: linux-arm-kernel
Hello,
I have a small handful of hw_breakpoint updates, all from Dietmar, that
I plan to send via Russell for 3.9.
Any comments, please shout.
Will
Dietmar Eggemann (3):
ARM: coresight: common definition for (OS) Lock Access Register key
value
ARM: hw_breakpoint: Check function for OS Save and Restore mechanism
ARM: hw_breakpoint: Debug powerdown support for self-hosted debug
arch/arm/include/asm/cti.h | 10 ++---
arch/arm/include/asm/hardware/coresight.h | 6 +--
arch/arm/include/asm/hw_breakpoint.h | 3 ++
arch/arm/kernel/hw_breakpoint.c | 61 +++++++++++++++++++++++++++----
4 files changed, 62 insertions(+), 18 deletions(-)
--
1.8.0
^ permalink raw reply
* [PATCH 1/3] ARM: coresight: common definition for (OS) Lock Access Register key value
From: Will Deacon @ 2013-01-11 15:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1357918138-20222-1-git-send-email-will.deacon@arm.com>
From: Dietmar Eggemann <dietmar.eggemann@arm.com>
Coresight components and debug are using a common lock control mechansim.
Writing 0xC5ACCE55 to the Lock Access Register (LAR) in case of a coresight
components enables further access to the coresight device registers. Writing
any other value to it removes the write access.
Writing 0xC5ACCE55 to the OS Lock Access Register (OSLAR) in case of debug
locks the debug register for further access to the debug registers. Writing
any other value to it unlocks the debug registers.
Unfortunately, the existing coresight code uses the terms lock and unlock the
other way around. Unlocking stands for enabling write access and locking for
removing write access.
That is why the definition of the LAR and OSLAR key value has been changed to
CS_LAR_KEY.
Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
---
arch/arm/include/asm/cti.h | 10 +++-------
arch/arm/include/asm/hardware/coresight.h | 6 +++---
arch/arm/kernel/hw_breakpoint.c | 5 +++--
3 files changed, 9 insertions(+), 12 deletions(-)
diff --git a/arch/arm/include/asm/cti.h b/arch/arm/include/asm/cti.h
index f2e5cad..2381199 100644
--- a/arch/arm/include/asm/cti.h
+++ b/arch/arm/include/asm/cti.h
@@ -2,6 +2,7 @@
#define __ASMARM_CTI_H
#include <asm/io.h>
+#include <asm/hardware/coresight.h>
/* The registers' definition is from section 3.2 of
* Embedded Cross Trigger Revision: r0p0
@@ -35,11 +36,6 @@
#define LOCKACCESS 0xFB0
#define LOCKSTATUS 0xFB4
-/* write this value to LOCKACCESS will unlock the module, and
- * other value will lock the module
- */
-#define LOCKCODE 0xC5ACCE55
-
/**
* struct cti - cross trigger interface struct
* @base: mapped virtual address for the cti base
@@ -146,7 +142,7 @@ static inline void cti_irq_ack(struct cti *cti)
*/
static inline void cti_unlock(struct cti *cti)
{
- __raw_writel(LOCKCODE, cti->base + LOCKACCESS);
+ __raw_writel(CS_LAR_KEY, cti->base + LOCKACCESS);
}
/**
@@ -158,6 +154,6 @@ static inline void cti_unlock(struct cti *cti)
*/
static inline void cti_lock(struct cti *cti)
{
- __raw_writel(~LOCKCODE, cti->base + LOCKACCESS);
+ __raw_writel(~CS_LAR_KEY, cti->base + LOCKACCESS);
}
#endif
diff --git a/arch/arm/include/asm/hardware/coresight.h b/arch/arm/include/asm/hardware/coresight.h
index 7ecd793..0cf7a6b 100644
--- a/arch/arm/include/asm/hardware/coresight.h
+++ b/arch/arm/include/asm/hardware/coresight.h
@@ -36,7 +36,7 @@
/* CoreSight Component Registers */
#define CSCR_CLASS 0xff4
-#define UNLOCK_MAGIC 0xc5acce55
+#define CS_LAR_KEY 0xc5acce55
/* ETM control register, "ETM Architecture", 3.3.1 */
#define ETMR_CTRL 0
@@ -147,11 +147,11 @@
#define etm_lock(t) do { etm_writel((t), 0, CSMR_LOCKACCESS); } while (0)
#define etm_unlock(t) \
- do { etm_writel((t), UNLOCK_MAGIC, CSMR_LOCKACCESS); } while (0)
+ do { etm_writel((t), CS_LAR_KEY, CSMR_LOCKACCESS); } while (0)
#define etb_lock(t) do { etb_writel((t), 0, CSMR_LOCKACCESS); } while (0)
#define etb_unlock(t) \
- do { etb_writel((t), UNLOCK_MAGIC, CSMR_LOCKACCESS); } while (0)
+ do { etb_writel((t), CS_LAR_KEY, CSMR_LOCKACCESS); } while (0)
#endif /* __ASM_HARDWARE_CORESIGHT_H */
diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c
index 5ff2e77..34e9375 100644
--- a/arch/arm/kernel/hw_breakpoint.c
+++ b/arch/arm/kernel/hw_breakpoint.c
@@ -35,6 +35,7 @@
#include <asm/hw_breakpoint.h>
#include <asm/kdebug.h>
#include <asm/traps.h>
+#include <asm/hardware/coresight.h>
/* Breakpoint currently in use for each BRP. */
static DEFINE_PER_CPU(struct perf_event *, bp_on_reg[ARM_MAX_BRP]);
@@ -955,9 +956,9 @@ static void reset_ctrl_regs(void *unused)
/*
* Unconditionally clear the OS lock by writing a value
- * other than 0xC5ACCE55 to the access register.
+ * other than CS_LAR_KEY to the access register.
*/
- ARM_DBG_WRITE(c1, c0, 4, 0);
+ ARM_DBG_WRITE(c1, c0, 4, ~CS_LAR_KEY);
isb();
/*
--
1.8.0
^ permalink raw reply related
* [PATCH 07/14] usb: ehci-omap: Instantiate PHY devices if required
From: Alan Stern @ 2013-01-11 15:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50EFF075.5090203@ti.com>
On Fri, 11 Jan 2013, Roger Quadros wrote:
> Alan,
>
> Thanks for the patch. I've pasted the version that builds and works and
> put you as the Author of the patch, hope it is fine.
As far as I can see, yours is the same as what I posted except that:
You altered the changes to ehci-hcd.c and Makefile to remove
the dependency on the ehci-mxc patch;
You made an unimportant whitespace change in ehci-omap.c
(moved a blank line before ehci_write()).
Right? It's hard to compare the patches directly because the one you
posted was whitespace-damaged.
Anyway, if this is okay and there's nothing wrong with the ehci-mxc
change (other than the comment for ehci->priv), I'll submit both of
them to Greg soon.
Alan Stern
^ permalink raw reply
* [PATCH 2/3] ARM: hw_breakpoint: Check function for OS Save and Restore mechanism
From: Will Deacon @ 2013-01-11 15:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1357918138-20222-1-git-send-email-will.deacon@arm.com>
From: Dietmar Eggemann <dietmar.eggemann@arm.com>
v7 debug introduced OS Save and Restore mechanism. On a v7 debug SinglePower
system, i.e a system without a separate core and debug power domain, which does
not support external debug over powerdown, it is implementation defined whether
OS Save and Restore is implemented.
v7.1 debug requires OS Save and Restore mechanism. v6 debug and v6.1 debug do
not implement it.
A new global variable bool has_ossr is introduced and is determined in
arch_hw_breakpoint_init() like debug_arch or the number of BRPs/WRPs.
The logic how to check if OS Save and Restore is supported has changed with
this patch. In reset_ctrl_regs() a mask consisting of OSLM[1] (OSLSR.3) and
OSLM[0] (OSLSR.0) was used to check if the system supports OS Save and
Restore. In the new function core_has_os_save_restore() only OSLM[0] is used.
It is not necessary to check OSLM[1] too since it is v7.1 debug specific and
v7.1 debug requires OS Save and Restore and thus OS Lock.
Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
---
arch/arm/include/asm/hw_breakpoint.h | 3 +++
arch/arm/kernel/hw_breakpoint.c | 28 +++++++++++++++++++++++-----
2 files changed, 26 insertions(+), 5 deletions(-)
diff --git a/arch/arm/include/asm/hw_breakpoint.h b/arch/arm/include/asm/hw_breakpoint.h
index 01169dd..eef55ea 100644
--- a/arch/arm/include/asm/hw_breakpoint.h
+++ b/arch/arm/include/asm/hw_breakpoint.h
@@ -85,6 +85,9 @@ static inline void decode_ctrl_reg(u32 reg,
#define ARM_DSCR_HDBGEN (1 << 14)
#define ARM_DSCR_MDBGEN (1 << 15)
+/* OSLSR os lock model bits */
+#define ARM_OSLSR_OSLM0 (1 << 0)
+
/* opcode2 numbers for the co-processor instructions. */
#define ARM_OP2_BVR 4
#define ARM_OP2_BCR 5
diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c
index 34e9375..201d440 100644
--- a/arch/arm/kernel/hw_breakpoint.c
+++ b/arch/arm/kernel/hw_breakpoint.c
@@ -50,6 +50,9 @@ static int core_num_wrps;
/* Debug architecture version. */
static u8 debug_arch;
+/* Does debug architecture support OS Save and Restore? */
+static bool has_ossr;
+
/* Maximum supported watchpoint length. */
static u8 max_watchpoint_len;
@@ -904,6 +907,23 @@ static struct undef_hook debug_reg_hook = {
.fn = debug_reg_trap,
};
+/* Does this core support OS Save and Restore? */
+static bool core_has_os_save_restore(void)
+{
+ u32 oslsr;
+
+ switch (get_debug_arch()) {
+ case ARM_DEBUG_ARCH_V7_1:
+ return true;
+ case ARM_DEBUG_ARCH_V7_ECP14:
+ ARM_DBG_READ(c1, c1, 4, oslsr);
+ if (oslsr & ARM_OSLSR_OSLM0)
+ return true;
+ default:
+ return false;
+ }
+}
+
static void reset_ctrl_regs(void *unused)
{
int i, raw_num_brps, err = 0, cpu = smp_processor_id();
@@ -931,11 +951,7 @@ static void reset_ctrl_regs(void *unused)
if ((val & 0x1) == 0)
err = -EPERM;
- /*
- * Check whether we implement OS save and restore.
- */
- ARM_DBG_READ(c1, c1, 4, val);
- if ((val & 0x9) == 0)
+ if (!has_ossr)
goto clear_vcr;
break;
case ARM_DEBUG_ARCH_V7_1:
@@ -1025,6 +1041,8 @@ static int __init arch_hw_breakpoint_init(void)
return 0;
}
+ has_ossr = core_has_os_save_restore();
+
/* Determine how many BRPs/WRPs are available. */
core_num_brps = get_num_brps();
core_num_wrps = get_num_wrps();
--
1.8.0
^ permalink raw reply related
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox