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* [PATCH] clk: tegra: use _clk_pll_disable from _program_pll
From: Mike Turquette @ 2013-01-22 18:31 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1358188572-13005-1-git-send-email-swarren@wwwdotorg.org>

Quoting Stephen Warren (2013-01-14 10:36:12)
> From: Stephen Warren <swarren@nvidia.com>
> 
> _program_pll() was dropping the PLL's lock and calling clk_pll_disable().
> clk_pll_disable() does nothing but acquire the same lock and call
> _clk_pll_disable(). So, remove the lock manipulation code, and just call
> _clk_pll_disable() directly instead.
> 
> Reported-by: Sivaram Nair <sivaramn@nvidia.com>
> Signed-off-by: Stephen Warren <swarren@nvidia.com>
> ---
> Mike, this also will need to go through the Tegra tree; just looking for
> any review/ack from you. Thanks.
> 

Stephen,

This change looks good to me, but should it not be rolled into the tegra
CCF series?  Several patches on top of that series have surfaced; do you
plan on posting a V6?

Regards,
Mike

>  drivers/clk/tegra/clk-pll.c |    8 +-------
>  1 file changed, 1 insertion(+), 7 deletions(-)
> 
> diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
> index 474ce1f..9f9bb73 100644
> --- a/drivers/clk/tegra/clk-pll.c
> +++ b/drivers/clk/tegra/clk-pll.c
> @@ -339,14 +339,8 @@ static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
>         state = clk_pll_is_enabled(hw);
>  
>         if (state) {
> -               if (pll->lock)
> -                       spin_unlock_irqrestore(pll->lock, flags);
> -
> -               clk_pll_disable(hw);
> +               _clk_pll_disable(hw);
>                 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
> -
> -               if (pll->lock)
> -                       spin_lock_irqsave(pll->lock, flags);
>         }
>         pll_writel_base(val, pll);
>  
> -- 
> 1.7.10.4

^ permalink raw reply

* [PATCH] clk: tegra: ensure all provided clock values are valid cookies
From: Mike Turquette @ 2013-01-22 18:29 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1358187400-6824-1-git-send-email-swarren@wwwdotorg.org>

Quoting Stephen Warren (2013-01-14 10:16:40)
> From: Stephen Warren <swarren@nvidia.com>
> 
> Tegra's clock implementation uses pointers as the clock cookies, and
> hence chooses to make NULL an invalid clock cookie. However, there are
> gaps in the assigned device tree clock IDs, and hence the array mapping
> DT clock ID contains entries with NULL values (uninitialized BSS) unless
> explicit action is taken. This patch enhances the Tegra clock code to
> detect this case and explicitly initialize those lookup table entries to
> an error value. This prevents clk_get() from ever returning NULL. Hence,
> Tegra's clock APIs don't have to check the clock cookie they're passed
> for NULL.
> 
> Signed-off-by: Stephen Warren <swarren@nvidia.com>
> ---
> Mike, this also will need to go through the Tegra tree; just looking for
> any review/ack from you. Thanks.
> 

Stephen,

I think this is a bit strange.  Will you have gaps in the DT clock id's
forever or is this a temporary issue?

Also it is important than any driver using the clock api does not
dereference the struct clk pointer and assume that a NULL clk is
invalid.  I know that this series doesn't imply any such thing but I
wanted to state that anyways.

Also are you planning to roll this into the existing tegra ccf series?

Regards,
Mike

>  drivers/clk/tegra/clk-tegra20.c |    5 ++++-
>  drivers/clk/tegra/clk-tegra30.c |    5 ++++-
>  2 files changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
> index 5847b5e..e59ac14 100644
> --- a/drivers/clk/tegra/clk-tegra20.c
> +++ b/drivers/clk/tegra/clk-tegra20.c
> @@ -1243,12 +1243,15 @@ void __init tegra20_clock_init(struct device_node *np)
>         tegra20_audio_clk_init();
>  
>  
> -       for (i = 0; i < ARRAY_SIZE(clks); i++)
> +       for (i = 0; i < ARRAY_SIZE(clks); i++) {
>                 if (IS_ERR(clks[i])) {
>                         pr_err("Tegra20 clk %d: register failed with %ld\n",
>                                i, PTR_ERR(clks[i]));
>                         BUG();
>                 }
> +               if (!clks[i])
> +                       clks[i] = ERR_PTR(-EINVAL);
> +       }
>  
>         tegra_init_dup_clks(tegra_clk_duplicates, clks, clk_max);
>  
> diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
> index 987312c..9c0b2ee 100644
> --- a/drivers/clk/tegra/clk-tegra30.c
> +++ b/drivers/clk/tegra/clk-tegra30.c
> @@ -2022,12 +2022,15 @@ void __init tegra30_clock_init(struct device_node *np)
>         tegra30_audio_clk_init();
>         tegra30_pmc_clk_init();
>  
> -       for (i = 0; i < ARRAY_SIZE(clks); i++)
> +       for (i = 0; i < ARRAY_SIZE(clks); i++) {
>                 if (IS_ERR(clks[i])) {
>                         pr_err("Tegra30 clk %d: register failed with %ld\n",
>                                i, PTR_ERR(clks[i]));
>                         BUG();
>                 }
> +               if (!clks[i])
> +                       clks[i] = ERR_PTR(-EINVAL);
> +       }
>  
>         tegra_init_dup_clks(tegra_clk_duplicates, clks, clk_max);
>  
> -- 
> 1.7.10.4

^ permalink raw reply

* [PATCH 1/2] clk: divider: prepare for minimum divider
From: Stephen Boyd @ 2013-01-22 18:28 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <d20165dfc67970c3429b9d95ac9631015f8b2396.1358870920.git.afzal@ti.com>

On 01/22/13 08:39, Afzal Mohammed wrote:
> diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
> index a9204c6..0b34992 100644
> --- a/drivers/clk/clk-divider.c
> +++ b/drivers/clk/clk-divider.c
> @@ -236,7 +236,7 @@ EXPORT_SYMBOL_GPL(clk_divider_ops);
>  
>  static struct clk *_register_divider(struct device *dev, const char *name,
>  		const char *parent_name, unsigned long flags,
> -		void __iomem *reg, u8 shift, u8 width,
> +		void __iomem *reg, u8 shift, u8 width, u8 min_div,
>  		u8 clk_divider_flags, const struct clk_div_table *table,
>  		spinlock_t *lock)
>  {
> @@ -261,6 +261,7 @@ static struct clk *_register_divider(struct device *dev, const char *name,
>  	div->reg = reg;
>  	div->shift = shift;
>  	div->width = width;
> +	div->min_div = min_div;
>  	div->flags = clk_divider_flags;
>  	div->lock = lock;
>  	div->hw.init = &init;
> @@ -284,16 +285,17 @@ static struct clk *_register_divider(struct device *dev, const char *name,
>   * @reg: register address to adjust divider
>   * @shift: number of bits to shift the bitfield
>   * @width: width of the bitfield
> + * @min_div: minimum allowable divider value
>   * @clk_divider_flags: divider-specific flags for this clock
>   * @lock: shared register lock for this clock
>   */
>  struct clk *clk_register_divider(struct device *dev, const char *name,
>  		const char *parent_name, unsigned long flags,
> -		void __iomem *reg, u8 shift, u8 width,
> +		void __iomem *reg, u8 shift, u8 width, u8 min_div,
>  		u8 clk_divider_flags, spinlock_t *lock)
>  {
>  	return _register_divider(dev, name, parent_name, flags, reg, shift,
> -			width, clk_divider_flags, NULL, lock);
> +			width, min_div, clk_divider_flags, NULL, lock);
>  }

Can you make a new function, clk_register_min_divider(), to avoid
disturbing all users of clock dividers that don't have a minimum? Then
the default can be put into the two registration functions in
clk-divider.c and you don't have to change all clock divider users
across the tree.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation

^ permalink raw reply

* [PATCH v2 3/3] arm: omap2: gpmc: add DT bindings for OneNAND
From: Tony Lindgren @ 2013-01-22 18:27 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <CALF0-+WvfyygnV5A=E8UGc=zp9pab79FzJRe1KywjPw-B4UGZA@mail.gmail.com>

* Ezequiel Garcia <elezegarcia@gmail.com> [130122 10:17]:
> On Mon, Jan 21, 2013 at 10:32 PM, Daniel Mack <zonque@gmail.com> wrote:
> >
> > I'm currently far away from my computer and can't prepare a patch for this, sorry. But I think you are right, so please just submit a patch for that, anyone :-)
> >
> 
> Ok, I'll try to submit a patch as soon as possible. If anyone wants to
> do it instead, fine by me.

No please go ahead as it seems that you can easily test it too.

Regards,

Tony

^ permalink raw reply

* [PATCH] clk: tegra: add KBC clock for Tegra20
From: Stephen Warren @ 2013-01-22 18:26 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20130122182340.24671.64241@quantum>

On 01/22/2013 11:23 AM, Mike Turquette wrote:
> Quoting Stephen Warren (2013-01-11 15:17:42)
>> From: Stephen Warren <swarren@nvidia.com>
>>
>> This clock has been missing from all our upstream clock drivers. Add it
>> by copying the tegra_clk_periph_gate() call from Tegra30; the data
>> matches what's in the ChromeOS kernel for this clock.
>>
>> Cc: Prashant Gaikwad <pgaikwad@nvidia.com>
>> Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
>> Signed-off-by: Stephen Warren <swarren@nvidia.com>
>> ---
>> Mike, I'd need to apply this to the Tegra tree as part of the common
>> clock framework conversion.
>>
> 
> Is this patch going to be rolled into patch 6/9 of the larger tegra ccf
> series?

In the latest Tegra CCF series that I posted, I've rolled all these
small fixes in already.

^ permalink raw reply

* [PATCH] arm: omap: Fix build break in drm.c
From: Tony Lindgren @ 2013-01-22 18:25 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1358843328-8178-1-git-send-email-archit@ti.com>

* Archit Taneja <archit@ti.com> [130122 00:32]:
> Building omapdrm leads to a build break because of a missing include needed
> for the macro GET_OMAP_REVISION(). Add the missing inlclude.

Thanks I already have a similar patch from Rob queued up.

Tony
 
> Signed-off-by: Archit Taneja <archit@ti.com>
> ---
>  arch/arm/mach-omap2/drm.c |    1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm/mach-omap2/drm.c b/arch/arm/mach-omap2/drm.c
> index 4c7566c..6b1a8df 100644
> --- a/arch/arm/mach-omap2/drm.c
> +++ b/arch/arm/mach-omap2/drm.c
> @@ -25,6 +25,7 @@
>  #include <linux/dma-mapping.h>
>  #include <linux/platform_data/omap_drm.h>
>  
> +#include "soc.h"
>  #include "omap_device.h"
>  #include "omap_hwmod.h"
>  
> -- 
> 1.7.9.5
> 

^ permalink raw reply

* [PATCH] ARM: Versatile Express: extend the MPIDR range used for pen release check
From: Nicolas Pitre @ 2013-01-22 18:25 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1358852200-4581-1-git-send-email-lorenzo.pieralisi@arm.com>

On Tue, 22 Jan 2013, Lorenzo Pieralisi wrote:

> In ARM multi-cluster systems the MPIDR affinity level 0 cannot be used as a
> single cpu identifier, affinity levels 1 and 2 must be taken into account as
> well.
> This patch extends the MPIDR usage to affinity levels 1 and 2 in versatile
> secondary cores start up code in order to compare the passed pen_release
> value with the full-blown affinity mask.
> 
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>

Note that my b.L series makes this patch obsolete.



> ---
>  arch/arm/plat-versatile/headsmp.S | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/plat-versatile/headsmp.S b/arch/arm/plat-versatile/headsmp.S
> index dd703ef..b178d44 100644
> --- a/arch/arm/plat-versatile/headsmp.S
> +++ b/arch/arm/plat-versatile/headsmp.S
> @@ -20,7 +20,7 @@
>   */
>  ENTRY(versatile_secondary_startup)
>  	mrc	p15, 0, r0, c0, c0, 5
> -	and	r0, r0, #15
> +	bic	r0, #0xff000000
>  	adr	r4, 1f
>  	ldmia	r4, {r5, r6}
>  	sub	r4, r4, r5
> -- 
> 1.7.12
> 
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 

^ permalink raw reply

* [PATCH] clk: tegra: add KBC clock for Tegra20
From: Mike Turquette @ 2013-01-22 18:23 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1357946262-25823-1-git-send-email-swarren@wwwdotorg.org>

Quoting Stephen Warren (2013-01-11 15:17:42)
> From: Stephen Warren <swarren@nvidia.com>
> 
> This clock has been missing from all our upstream clock drivers. Add it
> by copying the tegra_clk_periph_gate() call from Tegra30; the data
> matches what's in the ChromeOS kernel for this clock.
> 
> Cc: Prashant Gaikwad <pgaikwad@nvidia.com>
> Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
> Signed-off-by: Stephen Warren <swarren@nvidia.com>
> ---
> Mike, I'd need to apply this to the Tegra tree as part of the common
> clock framework conversion.
> 

Is this patch going to be rolled into patch 6/9 of the larger tegra ccf
series?

Thanks,
Mike

>  drivers/clk/tegra/clk-tegra20.c |    7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
> index f40b6f7..5847b5e 100644
> --- a/drivers/clk/tegra/clk-tegra20.c
> +++ b/drivers/clk/tegra/clk-tegra20.c
> @@ -896,6 +896,13 @@ static void __init tegra20_periph_clk_init(void)
>         clk_register_clkdev(clk, NULL, "timer");
>         clks[timer] = clk;
>  
> +       /* kbc */
> +       clk = tegra_clk_periph_gate("kbc", "clk_32k", TEGRA_PERIPH_NO_RESET |
> +                                   TEGRA_PERIPH_ON_APB, clk_base, 0,
> +                                   36, &periph_h_regs, periph_clk_enb_refcnt);
> +       clk_register_clkdev(clk, NULL, "tegra-kbc");
> +       clks[kbc] = clk;
> +
>         /* csus */
>         clk = tegra_clk_periph_gate("csus", "clk_m", TEGRA_PERIPH_NO_RESET,
>                                     clk_base, 0, 92, &periph_u_regs,
> -- 
> 1.7.10.4

^ permalink raw reply

* OMAP baseline test results for v3.8-rc4
From: Tony Lindgren @ 2013-01-22 18:23 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <50FE9692.2090001@mimc.co.uk>

* Mark Jackson <mpfj-list@mimc.co.uk> [130122 05:46]:
> On 22/01/13 13:32, Bedia, Vaibhav wrote:
> 
> <snip>
> 
> > Following works for me:
> > 
> > Kernel
> > ===
> > git checkout next-20130122
> > make distclean
> > make omap2plus_defconfig
> > <Enable the appended DTB related options via menuconfig>
> > make -j7
> > cat arch/arm/boot/zImage arch/arm/boot/dts/am335x-bone.dtb > arch/arm/boot/zImage-dtb.am335x-bone
> > mkimage -A arm -O linux -C none -T kernel -a 0x80008000 -e 0x80008000 -n 'Linux' -d arch/arm/boot/zImage-dtb.am335x-bone arch/arm/boot/uImage-dtb.am335x-bone
> > 
> > U-Boot
> > ===
> > Built from v2013.01
> 
> <snip>
> 
> > A dumb question... in your case what's the bootargs set? Note that the mainline
> > kernel for AM335x doesn't have MMC support yet and the default bootargs is set to
> > rootfs on MMC.
> 
> Yes ... I'm trying to boot from a rootfs on MMC:-
> 
> Kernel command line: console=ttyO0,115200n8 earlyprintk debug root=/dev/mmcblk0p2 ro rootfstype=ext2
> rootwait
> 
> But I should get *something* from the kernel before it starts trying to access the rootfs ?

Here's something Kevin fixed but did not send it out before going to
a vacation. Can you give it a try with earlyprintk enabled?

Note that this does not help with no output early on, that sounds
like a bug configuring the DEBUG_LL port somewhere.

Regards,

Tony



From: Kevin Hilman <khilman@deeprootsystems.com>
Date: Tue, 15 Jan 2013 14:12:24 -0800
Subject: [PATCH] Fix omap_serial as module with debug_ll and earlyprintk

Otherwise we can race with the earlyconsole getting turned off
which can cause a non-booting system with earlyprintk enabled.

[tony at atomide.com: updated description]
Signed-off-by: Tony Lindgren <tony@atomide.com>

---

Kevin, can I add your Signed-off-by to this one?

--- a/arch/arm/mach-omap2/omap_device.c
+++ b/arch/arm/mach-omap2/omap_device.c
@@ -1298,4 +1298,4 @@ static int __init omap_device_late_init(void)
 	bus_for_each_dev(&platform_bus_type, NULL, NULL, omap_device_late_idle);
 	return 0;
 }
-omap_late_initcall(omap_device_late_init);
+late_initcall_sync(omap_device_late_init);

^ permalink raw reply

* [PATCH 15/15] staging/omapdrm: don't build on multiplatform
From: Rob Clark @ 2013-01-22 18:16 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <201301221747.24618.arnd@arndb.de>

On 01/22/2013 11:47 AM, Arnd Bergmann wrote:
> On Tuesday 22 January 2013, Greg Kroah-Hartman wrote:
>>> Ie. I'd prefer to re-enable omapdss on multi-plat rather than
>>> disabling omapdrm.  With changes in drm core, it is a bit of a pain
>>> to compile test all the arm drivers by doing N different builds, so
>>> we've been trying to get to the point of all arm drm drivers
>>> supporting multi-plat
>> Ok, I'll let you and Arnd fight it out and drop this patch from my
>> to-apply queue for now...
> If Rob thinks there is no danger in allowing omap2_dss to be built
> on all platforms, and Tomi has no objections, I'm fine with that, too.
> In general, that is the right solution, I was just trying to be
> conservative for the 3.8 cycle.

I think it should be safe.. or at least it built fine for multi-plat in 
the recent past and shouldn't really do anything if there is no omapdss 
platform device.

Do you want me to make a patch or are you already doing this?

BR,
-R

> 	Arnd

^ permalink raw reply

* [PATCH] ARM: dts: add mshc controller node for Exynos4x12 SoCs
From: Dongjin Kim @ 2013-01-22 18:15 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1358764755-21470-1-git-send-email-thomas.abraham@linaro.org>

Hi Thomas,

Good to see your patch, actually I had sent similar one before but no
one care my patch. And now I feel it seems to be wrong.

But I have a couple of question if I use your patch to enable MSHC
controller work properly on Exynos4412.

What's the exact form of ".compatible" on board file?
With your patch, MSHC is not probed at all in my board. The
".compatible" has to be 'samsung,exynos5250-dw-mshc' and it works.

I also tried '.compatible = "samsung,exynos5250-dw-mshc",
"samsung,exynos4412-dw-mshc"', it probes the driver but in the
function 'dw_mci_exynos_priv_init', priv->ctrl_type always becomes
DW_MCI_TYPE_EXYNOS5250. Because there is a loop and returns each
compatible strings in alphanumeric order whatever it is ordered in the
board file.

I also tried below patch to add a compatible for Exynos4412 to
'dw_mci_exynos_match' with its specific data, and it works. What's the
right direction? If I am missing something or wrong, please correct
me. :)

Many thanks,
Dongjin.

@@ -184,6 +186,25 @@ static int dw_mci_exynos_setup_bus(struct dw_mci *host,
        return 0;
 }

+/* Exynos4412 controller specific capabilities */
+static unsigned long exynos4412_dwmmc_caps[4] = {
+       MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR |
+               MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
+       MMC_CAP_CMD23,
+       MMC_CAP_CMD23,
+       MMC_CAP_CMD23,
+};
+
+static const struct dw_mci_drv_data exynos4412_drv_data = {
+       .caps                   = exynos4412_dwmmc_caps,
+       .init                   = dw_mci_exynos_priv_init,
+       .setup_clock            = dw_mci_exynos_setup_clock,
+       .prepare_command        = dw_mci_exynos_prepare_command,
+       .set_ios                = dw_mci_exynos_set_ios,
+       .parse_dt               = dw_mci_exynos_parse_dt,
+       .setup_bus              = dw_mci_exynos_setup_bus,
+};
+
 /* Exynos5250 controller specific capabilities */
 static unsigned long exynos5250_dwmmc_caps[4] = {
        MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR |
@@ -204,6 +225,8 @@ static const struct dw_mci_drv_data exynos5250_drv_data = {
 };

 static const struct of_device_id dw_mci_exynos_match[] = {
+       { .compatible = "samsung,exynos4412-dw-mshc",
+                       .data = &exynos4412_drv_data, },
        { .compatible = "samsung,exynos5250-dw-mshc",
                        .data = &exynos5250_drv_data, },
        {},


On Mon, Jan 21, 2013 at 7:39 PM, Thomas Abraham
<thomas.abraham@linaro.org> wrote:
> Commit cea0f256 ("ARM: dts: Add board dts file for ODROID-X") includes a node
> to describe the board level properties for mshc controller. But the mshc
> controller node was not added in the Exynos4x12 dtsi file which resulted
> in the following warning when compiling the dtb files.
>
> Warning (reg_format): "reg" property in /mshc at 12550000/slot at 0 has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
> Warning (avoid_default_addr_size): Relying on default #address-cells value for /mshc at 12550000/slot at 0
> Warning (avoid_default_addr_size): Relying on default #size-cells value for /mshc at 12550000/slot at 0
>
> Fix this by adding the mshc controller node for Exynos4x12 SoCs.
>
> Cc: Dongjin Kim <tobetter@gmail.com>
> Cc: Kukjin Kim <kgene.kim@samsung.com>
> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
> ---
>  arch/arm/boot/dts/exynos4412.dtsi |    8 ++++++++
>  1 files changed, 8 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
> index 78ed377..96f5b66 100644
> --- a/arch/arm/boot/dts/exynos4412.dtsi
> +++ b/arch/arm/boot/dts/exynos4412.dtsi
> @@ -32,4 +32,12 @@
>                 interrupts = <0 57 0>, <0 0 0>, <0 0 0>, <0 0 0>,
>                              <1 12 0>, <1 12 0>, <1 12 0>, <1 12 0>;
>         };
> +
> +       mshc at 12550000 {
> +               compatible = "samsung,exynos4412-dw-mshc";
> +               reg = <0x12550000 0x1000>;
> +               interrupts = <0 77 0>;
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +       };
>  };
> --
> 1.7.5.4
>

^ permalink raw reply

* [PATCH v2] mm: dmapool: use provided gfp flags for all dma_alloc_coherent() calls
From: Arnd Bergmann @ 2013-01-22 18:13 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20130121210150.GA9184@kroah.com>

On Monday 21 January 2013, Greg KH wrote:
> > 
> > I don't know a lot about USB, but I always assumed that this was not
> > a normal condition and that there are only a couple of URBs per endpoint
> > used at a time. Maybe Greg or someone else with a USB background can
> > shed some light on this.
> 
> There's no restriction on how many URBs a driver can have outstanding at
> once, and if you have a system with a lot of USB devices running at the
> same time, there could be lots of URBs in flight depending on the number
> of host controllers and devices and drivers being used.

Ok, thanks for clarifying that. I read some more of the em28xx driver,
and while it does have a bunch of URBs in flight, there are only five
audio and five video URBs that I see simultaneously being submitted,
and then resubmitted from their completion handlers. I think this
means that there should be 10 URBs active at any given time in this
driver, which does not explain why we get 256 allocations.

I also noticed that the initial submissions are all atomic but don't
need to, so it may be worth trying the patch below, which should also
help in low-memory situations. We could also try moving the resubmission
into a workqueue in order to let those be GFP_KERNEL, but I don't think
that will help.

	Arnd

diff --git a/drivers/media/usb/em28xx/em28xx-audio.c b/drivers/media/usb/em28xx/em28xx-audio.c
index 2fdb66e..8b789f4 100644
--- a/drivers/media/usb/em28xx/em28xx-audio.c
+++ b/drivers/media/usb/em28xx/em28xx-audio.c
@@ -177,12 +177,12 @@ static int em28xx_init_audio_isoc(struct em28xx *dev)
 		struct urb *urb;
 		int j, k;
 
-		dev->adev.transfer_buffer[i] = kmalloc(sb_size, GFP_ATOMIC);
+		dev->adev.transfer_buffer[i] = kmalloc(sb_size, GFP_KERNEL);
 		if (!dev->adev.transfer_buffer[i])
 			return -ENOMEM;
 
 		memset(dev->adev.transfer_buffer[i], 0x80, sb_size);
-		urb = usb_alloc_urb(EM28XX_NUM_AUDIO_PACKETS, GFP_ATOMIC);
+		urb = usb_alloc_urb(EM28XX_NUM_AUDIO_PACKETS, GFP_KERNEL);
 		if (!urb) {
 			em28xx_errdev("usb_alloc_urb failed!\n");
 			for (j = 0; j < i; j++) {
@@ -212,7 +212,7 @@ static int em28xx_init_audio_isoc(struct em28xx *dev)
 	}
 
 	for (i = 0; i < EM28XX_AUDIO_BUFS; i++) {
-		errCode = usb_submit_urb(dev->adev.urb[i], GFP_ATOMIC);
+		errCode = usb_submit_urb(dev->adev.urb[i], GFP_KERNEL);
 		if (errCode) {
 			em28xx_errdev("submit of audio urb failed\n");
 			em28xx_deinit_isoc_audio(dev);
diff --git a/drivers/media/usb/em28xx/em28xx-core.c b/drivers/media/usb/em28xx/em28xx-core.c
index bed07a6..c5a2c4b 100644
--- a/drivers/media/usb/em28xx/em28xx-core.c
+++ b/drivers/media/usb/em28xx/em28xx-core.c
@@ -1166,7 +1166,7 @@ int em28xx_init_isoc(struct em28xx *dev, enum em28xx_mode mode,
 
 	/* submit urbs and enables IRQ */
 	for (i = 0; i < isoc_bufs->num_bufs; i++) {
-		rc = usb_submit_urb(isoc_bufs->urb[i], GFP_ATOMIC);
+		rc = usb_submit_urb(isoc_bufs->urb[i], GFP_KERNEL);
 		if (rc) {
 			em28xx_err("submit of urb %i failed (error=%i)\n", i,
 				   rc);

^ permalink raw reply related

* [PATCH v2 3/3] arm: omap2: gpmc: add DT bindings for OneNAND
From: Ezequiel Garcia @ 2013-01-22 18:13 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <af696cd0-8a7f-4839-9600-87d5b9172585@email.android.com>

On Mon, Jan 21, 2013 at 10:32 PM, Daniel Mack <zonque@gmail.com> wrote:
> Hi Tony, Mark, Ezequiel,
>
> Tony Lindgren <tony@atomide.com> wrote:
>
>>* Ezequiel Garcia <elezegarcia@gmail.com> [130121 09:00]:
>>> Hi Mark,
>>>
>>> On Mon, Jan 21, 2013 at 9:30 AM, Mark Rutland <mark.rutland@arm.com>
>>wrote:
>>> > [...]
>>> >
>>> >> diff --git a/arch/arm/mach-omap2/gpmc.c
>>b/arch/arm/mach-omap2/gpmc.c
>>> >> index 01ce462..f7de9eb 100644
>>> >> --- a/arch/arm/mach-omap2/gpmc.c
>>> >> +++ b/arch/arm/mach-omap2/gpmc.c
>>> >> @@ -39,6 +39,7 @@
>>> >>  #include "omap_device.h"
>>> >>  #include "gpmc.h"
>>> >>  #include "gpmc-nand.h"
>>> >> +#include "gpmc-onenand.h"
>>> >>
>>> >>  #define      DEVICE_NAME             "omap-gpmc"
>>> >>
>>> >> @@ -1259,6 +1260,43 @@ static int gpmc_probe_nand_child(struct
>>platform_device *pdev,
>>> >>  }
>>> >>  #endif
>>> >>
>>> >> +#ifdef CONFIG_MTD_ONENAND
>>> >> +static int gpmc_probe_onenand_child(struct platform_device *pdev,
>>> >> +                              struct device_node *child)
>>> >> +{
>>> >> +     u32 val;
>>> >> +     struct omap_onenand_platform_data *gpmc_onenand_data;
>>> >> +
>>> >> +     if (of_property_read_u32(child, "reg", &val) < 0) {
>>> >> +             dev_err(&pdev->dev, "%s has no 'reg' property\n",
>>> >> +                     child->full_name);
>>> >> +             return -ENODEV;
>>> >> +     }
>>> >> +
>>> >> +     gpmc_onenand_data = devm_kzalloc(&pdev->dev,
>>sizeof(*gpmc_onenand_data),
>>> >> +                                      GFP_KERNEL);
>>> >> +     if (!gpmc_onenand_data)
>>> >> +             return -ENOMEM;
>>> >> +
>>> >> +     gpmc_onenand_data->cs = val;
>>> >> +     gpmc_onenand_data->of_node = child;
>>> >> +     gpmc_onenand_data->dma_channel = -1;
>>> >> +
>>> >> +     if (!of_property_read_u32(child, "dma-channel", &val))
>>> >> +             gpmc_onenand_data->dma_channel = val;
>>> >> +
>>> >> +     gpmc_onenand_init(gpmc_onenand_data);
>>> >> +
>>> >> +     return 0;
>>> >> +}
>>> >> +#else
>>> >> +static int gpmc_probe_onenand_child(struct platform_device *pdev,
>>> >> +                                 struct device_node *child)
>>> >> +{
>>> >> +     return 0;
>>> >> +}
>>> >> +#endif
>>> >> +
>>> >>  static int gpmc_probe_dt(struct platform_device *pdev)
>>> >>  {
>>> >>       int ret;
>>> >> @@ -1276,6 +1314,12 @@ static int gpmc_probe_dt(struct
>>platform_device *pdev)
>>> >>                       return ret;
>>> >>       }
>>> >>
>>> >
>>> > This doesn't look right to me:
>>> >
>>> >> +     for_each_node_by_name(child, "onenand") {
>>> >> +             ret = gpmc_probe_onenand_child(pdev, child);
>>> >> +             of_node_put(child);
>>> >> +             if (ret < 0)
>>> >> +                     return ret;
>>> >> +     }
>>> >
>>> > for_each_node_by_name automatically calls of_node_put on each node
>>once passed,
>>> > and as far as I can tell, gpmc_probe_onenand_child doesn't do
>>anything that'd
>>> > increment a node's refcount.
>>> >
>>> > As far as I can see, you only need the of_node_put in the error
>>case:
>>> >
>>> > for_each_node_by_name(child, "onenand") {
>>> >         ret = gpmc_probe_onenand_child(pdev, child);
>>> >         if (ret < 0) {
>>> >                 of_node_put(child);
>>> >                 return ret;
>>> >         }
>>> > }
>>> >
>>> > Have I missed something here?
>>> >
>>>
>>> Mmm... perhaps I've overlooked that code.
>>>
>>> After some digging through source and reading for_each_node_by_name()
>>> it seems to me you're right.
>>>
>>> @Daniel: It seems this would also apply to the NAND binding.
>>> What do you think?
>>
>>Would prefer this done as a fix against the omap-for-v3.9/gpmc
>>branch before we apply Ezequiel's patches.
>
> I'm currently far away from my computer and can't prepare a patch for this, sorry. But I think you are right, so please just submit a patch for that, anyone :-)
>

Ok, I'll try to submit a patch as soon as possible. If anyone wants to
do it instead, fine by me.

-- 
    Ezequiel

^ permalink raw reply

* [PATCH] clk: Add axi-clkgen driver
From: Josh Cartwright @ 2013-01-22 18:08 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1357755120-32735-1-git-send-email-lars@metafoo.de>

On Wed, Jan 09, 2013 at 07:12:00PM +0100, Lars-Peter Clausen wrote:
> This driver adds support for the AXI clkgen pcore to the common clock framework.
> The AXI clkgen pcore is a AXI front-end to the MMCM_ADV frequency synthesizer
> commonly found in Xilinx FPGAs.
> 
> The AXI clkgen pcore is used in Analog Devices' reference designs targeting
> Xilinx FPGAs.
> 
> Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
> ---
>  .../devicetree/bindings/clock/axi-clkgen.txt       |  22 ++
>  drivers/clk/Kconfig                                |   8 +
>  drivers/clk/Makefile                               |   1 +
>  drivers/clk/clk-axi-clkgen.c                       | 326 +++++++++++++++++++++
>  4 files changed, 357 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/axi-clkgen.txt
>  create mode 100644 drivers/clk/clk-axi-clkgen.c
> 
[..]
> diff --git a/drivers/clk/clk-axi-clkgen.c b/drivers/clk/clk-axi-clkgen.c
> new file mode 100644
> index 0000000..e9db225
> --- /dev/null
> +++ b/drivers/clk/clk-axi-clkgen.c
> @@ -0,0 +1,326 @@
> +/*
> + * AXI clkgen driver
> + *
> + * Copyright 2012-2013 Analog Device Inc.
> + *  Author: Lars-Peter Clausen <lars@metafoo.de>
> + *
> + * Licensed under the GPL-2.
> + *
> + */
> +
> +#include <linux/platform_device.h>
> +#include <linux/clk-provider.h>
> +#include <linux/clk.h>
> +#include <linux/slab.h>
> +#include <linux/io.h>
> +#include <linux/of.h>
> +#include <linux/module.h>
> +#include <linux/err.h>
> +
> +#define AXI_CLKGEN_REG_UPDATE_ENABLE	0x04
> +#define AXI_CLKGEN_REG_CLK_OUT1		0x08
> +#define AXI_CLKGEN_REG_CLK_OUT2		0x0c
> +#define AXI_CLKGEN_REG_CLK_DIV		0x10
> +#define AXI_CLKGEN_REG_CLK_FB1		0x14
> +#define AXI_CLKGEN_REG_CLK_FB2		0x18
> +#define AXI_CLKGEN_REG_LOCK1		0x1c
> +#define AXI_CLKGEN_REG_LOCK2		0x20
> +#define AXI_CLKGEN_REG_LOCK3		0x24
> +#define AXI_CLKGEN_REG_FILTER1		0x28
> +#define AXI_CLKGEN_REG_FILTER2		0x2c
> +
> +struct axi_clkgen {
> +	void __iomem *base;
> +	struct clk_hw clk_hw;
> +};
> +
> +static uint32_t axi_clkgen_lookup_filter(unsigned int m)
> +{
> +	switch (m) {
> +	case 0:
> +		return 0x01001990;
> +	case 1:
> +		return 0x01001190;
> +	case 2:
> +		return 0x01009890;
> +	case 3:
> +		return 0x01001890;
> +	case 4:
> +		return 0x01008890;
> +	case 5 ... 8:
> +		return 0x01009090;
> +	case 9 ... 11:
> +		return 0x0100890;

Just checking to ensure this ^ entry is correct, since it looks
different then the others (it may very well be).

   Josh

^ permalink raw reply

* [PATCH V5] drivers/pinctrl: grab default handles from device core
From: Stephen Warren @ 2013-01-22 17:56 UTC (permalink / raw)
  To: linux-arm-kernel

From: Linus Walleij <linus.walleij@linaro.org>

This makes the device core auto-grab the pinctrl handle and set
the "default" (PINCTRL_STATE_DEFAULT) state for every device
that is present in the device model right before probe. This will
account for the lion's share of embedded silicon devcies.

A modification of the semantics for pinctrl_get() is also done:
previously if the pinctrl handle for a certain device was already
taken, the pinctrl core would return an error. Now, since the
core may have already default-grabbed the handle and set its
state to "default", if the handle was already taken, this will
be disregarded and the located, previously instanitated handle
will be returned to the caller.

This way all code in drivers explicitly requesting their pinctrl
handlers will still be functional, and drivers that want to
explicitly retrieve and switch their handles can still do that.
But if the desired functionality is just boilerplate of this
type in the probe() function:

struct pinctrl  *p;

p = devm_pinctrl_get_select_default(&dev);
if (IS_ERR(p)) {
   if (PTR_ERR(p) == -EPROBE_DEFER)
        return -EPROBE_DEFER;
        dev_warn(&dev, "no pinctrl handle\n");
}

The discussion began with the addition of such boilerplate
to the omap4 keypad driver:
http://marc.info/?l=linux-input&m=135091157719300&w=2

A previous approach using notifiers was discussed:
http://marc.info/?l=linux-kernel&m=135263661110528&w=2
This failed because it could not handle deferred probes.

This patch alone does not solve the entire dilemma faced:
whether code should be distributed into the drivers or
if it should be centralized to e.g. a PM domain. But it
solves the immediate issue of the addition of boilerplate
to a lot of drivers that just want to grab the default
state. As mentioned, they can later explicitly retrieve
the handle and set different states, and this could as
well be done by e.g. PM domains as it is only related
to a certain struct device * pointer.

Cc: Felipe Balbi <balbi@ti.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Mitch Bradley <wmb@firmworks.com>
Cc: Ulf Hansson <ulf.hansson@linaro.org>
Cc: Rafael J. Wysocki <rjw@sisk.pl>
Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Rickard Andersson <rickard.andersson@stericsson.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
[swarren: fixed and simplified error-handling in pinctrl_bind_pins(), to
correctly handle deferred probe. Removed admonition from docs not to use
pinctrl hogs for devices]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
 Documentation/pinctrl.txt       |   18 ++++++++--
 drivers/base/Makefile           |    1 +
 drivers/base/dd.c               |    7 ++++
 drivers/base/pinctrl.c          |   69 +++++++++++++++++++++++++++++++++++++++
 drivers/pinctrl/core.c          |   30 ++++++++++++++---
 drivers/pinctrl/core.h          |    3 ++
 include/linux/device.h          |    7 ++++
 include/linux/pinctrl/devinfo.h |   45 +++++++++++++++++++++++++
 8 files changed, 173 insertions(+), 7 deletions(-)
 create mode 100644 drivers/base/pinctrl.c
 create mode 100644 include/linux/pinctrl/devinfo.h

diff --git a/Documentation/pinctrl.txt b/Documentation/pinctrl.txt
index da40efb..a2b57e0 100644
--- a/Documentation/pinctrl.txt
+++ b/Documentation/pinctrl.txt
@@ -972,6 +972,18 @@ pinmux core.
 Pin control requests from drivers
 =================================
 
+When a device driver is about to probe the device core will automatically
+attempt to issue pinctrl_get_select_default() on these devices.
+This way driver writers do not need to add any of the boilerplate code
+of the type found below. However when doing fine-grained state selection
+and not using the "default" state, you may have to do some device driver
+handling of the pinctrl handles and states.
+
+So if you just want to put the pins for a certain device into the default
+state and be done with it, there is nothing you need to do besides
+providing the proper mapping table. The device core will take care of
+the rest.
+
 Generally it is discouraged to let individual drivers get and enable pin
 control. So if possible, handle the pin control in platform code or some other
 place where you have access to all the affected struct device * pointers. In
@@ -1097,9 +1109,9 @@ situations that can be electrically unpleasant, you will certainly want to
 mux in and bias pins in a certain way before the GPIO subsystems starts to
 deal with them.
 
-The above can be hidden: using pinctrl hogs, the pin control driver may be
-setting up the config and muxing for the pins when it is probing,
-nevertheless orthogonal to the GPIO subsystem.
+The above can be hidden: using the device core, the pinctrl core may be
+setting up the config and muxing for the pins right before the device is
+probing, nevertheless orthogonal to the GPIO subsystem.
 
 But there are also situations where it makes sense for the GPIO subsystem
 to communicate directly with with the pinctrl subsystem, using the latter
diff --git a/drivers/base/Makefile b/drivers/base/Makefile
index 5aa2d70..4e22ce3 100644
--- a/drivers/base/Makefile
+++ b/drivers/base/Makefile
@@ -21,6 +21,7 @@ endif
 obj-$(CONFIG_SYS_HYPERVISOR) += hypervisor.o
 obj-$(CONFIG_REGMAP)	+= regmap/
 obj-$(CONFIG_SOC_BUS) += soc.o
+obj-$(CONFIG_PINCTRL) += pinctrl.o
 
 ccflags-$(CONFIG_DEBUG_DRIVER) := -DDEBUG
 
diff --git a/drivers/base/dd.c b/drivers/base/dd.c
index e3bbed8..65631015 100644
--- a/drivers/base/dd.c
+++ b/drivers/base/dd.c
@@ -24,6 +24,7 @@
 #include <linux/wait.h>
 #include <linux/async.h>
 #include <linux/pm_runtime.h>
+#include <linux/pinctrl/devinfo.h>
 
 #include "base.h"
 #include "power/power.h"
@@ -269,6 +270,12 @@ static int really_probe(struct device *dev, struct device_driver *drv)
 	WARN_ON(!list_empty(&dev->devres_head));
 
 	dev->driver = drv;
+
+	/* If using pinctrl, bind pins now before probing */
+	ret = pinctrl_bind_pins(dev);
+	if (ret)
+		goto probe_failed;
+
 	if (driver_sysfs_add(dev)) {
 		printk(KERN_ERR "%s: driver_sysfs_add(%s) failed\n",
 			__func__, dev_name(dev));
diff --git a/drivers/base/pinctrl.c b/drivers/base/pinctrl.c
new file mode 100644
index 0000000..67a274e
--- /dev/null
+++ b/drivers/base/pinctrl.c
@@ -0,0 +1,69 @@
+/*
+ * Driver core interface to the pinctrl subsystem.
+ *
+ * Copyright (C) 2012 ST-Ericsson SA
+ * Written on behalf of Linaro for ST-Ericsson
+ * Based on bits of regulator core, gpio core and clk core
+ *
+ * Author: Linus Walleij <linus.walleij@linaro.org>
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include <linux/device.h>
+#include <linux/pinctrl/devinfo.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/slab.h>
+
+/**
+ * pinctrl_bind_pins() - called by the device core before probe
+ * @dev: the device that is just about to probe
+ */
+int pinctrl_bind_pins(struct device *dev)
+{
+	int ret;
+
+	dev->pins = devm_kzalloc(dev, sizeof(*(dev->pins)), GFP_KERNEL);
+	if (!dev->pins)
+		return -ENOMEM;
+
+	dev->pins->p = devm_pinctrl_get(dev);
+	if (IS_ERR(dev->pins->p)) {
+		dev_dbg(dev, "no pinctrl handle\n");
+		ret = PTR_ERR(dev->pins->p);
+		goto cleanup_alloc;
+	}
+
+	dev->pins->default_state = pinctrl_lookup_state(dev->pins->p,
+					PINCTRL_STATE_DEFAULT);
+	if (IS_ERR(dev->pins->default_state)) {
+		dev_dbg(dev, "no default pinctrl state\n");
+		ret = 0;
+		goto cleanup_get;
+	}
+
+	ret = pinctrl_select_state(dev->pins->p, dev->pins->default_state);
+	if (ret) {
+		dev_dbg(dev, "failed to activate default pinctrl state\n");
+		goto cleanup_get;
+	}
+
+	return 0;
+
+	/*
+	 * If no pinctrl handle or default state was found for this device,
+	 * let's explicitly free the pin container in the device, there is
+	 * no point in keeping it around.
+	 */
+cleanup_get:
+	devm_pinctrl_put(dev->pins->p);
+cleanup_alloc:
+	devm_kfree(dev, dev->pins);
+	dev->pins = NULL;
+
+	/* Only return deferrals */
+	if (ret != -EPROBE_DEFER)
+		ret = 0;
+
+	return ret;
+}
diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c
index 3611753..0dbbbf3 100644
--- a/drivers/pinctrl/core.c
+++ b/drivers/pinctrl/core.c
@@ -14,6 +14,7 @@
 #define pr_fmt(fmt) "pinctrl core: " fmt
 
 #include <linux/kernel.h>
+#include <linux/kref.h>
 #include <linux/export.h>
 #include <linux/init.h>
 #include <linux/device.h>
@@ -721,6 +722,8 @@ static struct pinctrl *create_pinctrl(struct device *dev)
 		return ERR_PTR(ret);
 	}
 
+	kref_init(&p->users);
+
 	/* Add the pinctrl handle to the global list */
 	list_add_tail(&p->node, &pinctrl_list);
 
@@ -734,9 +737,17 @@ static struct pinctrl *pinctrl_get_locked(struct device *dev)
 	if (WARN_ON(!dev))
 		return ERR_PTR(-EINVAL);
 
+	/*
+	 * See if somebody else (such as the device core) has already
+	 * obtained a handle to the pinctrl for this device. In that case,
+	 * return another pointer to it.
+	 */
 	p = find_pinctrl(dev);
-	if (p != NULL)
-		return ERR_PTR(-EBUSY);
+	if (p != NULL) {
+		dev_dbg(dev, "obtain a copy of previously claimed pinctrl\n");
+		kref_get(&p->users);
+		return p;
+	}
 
 	return create_pinctrl(dev);
 }
@@ -792,13 +803,24 @@ static void pinctrl_put_locked(struct pinctrl *p, bool inlist)
 }
 
 /**
- * pinctrl_put() - release a previously claimed pinctrl handle
+ * pinctrl_release() - release the pinctrl handle
+ * @kref: the kref in the pinctrl being released
+ */
+void pinctrl_release(struct kref *kref)
+{
+	struct pinctrl *p = container_of(kref, struct pinctrl, users);
+
+	pinctrl_put_locked(p, true);
+}
+
+/**
+ * pinctrl_put() - decrease use count on a previously claimed pinctrl handle
  * @p: the pinctrl handle to release
  */
 void pinctrl_put(struct pinctrl *p)
 {
 	mutex_lock(&pinctrl_mutex);
-	pinctrl_put_locked(p, true);
+	kref_put(&p->users, pinctrl_release);
 	mutex_unlock(&pinctrl_mutex);
 }
 EXPORT_SYMBOL_GPL(pinctrl_put);
diff --git a/drivers/pinctrl/core.h b/drivers/pinctrl/core.h
index 232a9f6..fdd350d 100644
--- a/drivers/pinctrl/core.h
+++ b/drivers/pinctrl/core.h
@@ -9,6 +9,7 @@
  * License terms: GNU General Public License (GPL) version 2
  */
 
+#include <linux/kref.h>
 #include <linux/mutex.h>
 #include <linux/radix-tree.h>
 #include <linux/pinctrl/pinconf.h>
@@ -58,6 +59,7 @@ struct pinctrl_dev {
  * @state: the current state
  * @dt_maps: the mapping table chunks dynamically parsed from device tree for
  *	this device, if any
+ * @users: reference count
  */
 struct pinctrl {
 	struct list_head node;
@@ -65,6 +67,7 @@ struct pinctrl {
 	struct list_head states;
 	struct pinctrl_state *state;
 	struct list_head dt_maps;
+	struct kref users;
 };
 
 /**
diff --git a/include/linux/device.h b/include/linux/device.h
index 43dcda9..001f663 100644
--- a/include/linux/device.h
+++ b/include/linux/device.h
@@ -21,6 +21,7 @@
 #include <linux/compiler.h>
 #include <linux/types.h>
 #include <linux/mutex.h>
+#include <linux/pinctrl/devinfo.h>
 #include <linux/pm.h>
 #include <linux/atomic.h>
 #include <linux/ratelimit.h>
@@ -620,6 +621,8 @@ struct acpi_dev_node {
  * @pm_domain:	Provide callbacks that are executed during system suspend,
  * 		hibernation, system resume and during runtime PM transitions
  * 		along with subsystem-level and driver-level callbacks.
+ * @pins:	For device pin management.
+ *		See Documentation/pinctrl.txt for details.
  * @numa_node:	NUMA node this device is close to.
  * @dma_mask:	Dma mask (if dma'ble device).
  * @coherent_dma_mask: Like dma_mask, but for alloc_coherent mapping as not all
@@ -672,6 +675,10 @@ struct device {
 	struct dev_pm_info	power;
 	struct dev_pm_domain	*pm_domain;
 
+#ifdef CONFIG_PINCTRL
+	struct dev_pin_info	*pins;
+#endif
+
 #ifdef CONFIG_NUMA
 	int		numa_node;	/* NUMA node this device is close to */
 #endif
diff --git a/include/linux/pinctrl/devinfo.h b/include/linux/pinctrl/devinfo.h
new file mode 100644
index 0000000..6e5f8a9
--- /dev/null
+++ b/include/linux/pinctrl/devinfo.h
@@ -0,0 +1,45 @@
+/*
+ * Per-device information from the pin control system.
+ * This is the stuff that get included into the device
+ * core.
+ *
+ * Copyright (C) 2012 ST-Ericsson SA
+ * Written on behalf of Linaro for ST-Ericsson
+ * This interface is used in the core to keep track of pins.
+ *
+ * Author: Linus Walleij <linus.walleij@linaro.org>
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#ifndef PINCTRL_DEVINFO_H
+#define PINCTRL_DEVINFO_H
+
+#ifdef CONFIG_PINCTRL
+
+/* The device core acts as a consumer toward pinctrl */
+#include <linux/pinctrl/consumer.h>
+
+/**
+ * struct dev_pin_info - pin state container for devices
+ * @p: pinctrl handle for the containing device
+ * @default_state: the default state for the handle, if found
+ */
+struct dev_pin_info {
+	struct pinctrl *p;
+	struct pinctrl_state *default_state;
+};
+
+extern int pinctrl_bind_pins(struct device *dev);
+
+#else
+
+/* Stubs if we're not using pinctrl */
+
+static inline int pinctrl_bind_pins(struct device *dev)
+{
+	return 0;
+}
+
+#endif /* CONFIG_PINCTRL */
+#endif /* PINCTRL_DEVINFO_H */
-- 
1.7.10.4

^ permalink raw reply related

* [PATCH] clk: Add axi-clkgen driver
From: Mike Turquette @ 2013-01-22 17:55 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1357755120-32735-1-git-send-email-lars@metafoo.de>

Quoting Lars-Peter Clausen (2013-01-09 10:12:00)
<snip>
> +static void axi_clkgen_write(struct axi_clkgen *axi_clkgen,
> +       unsigned int reg, unsigned int val)
> +{
> +       iowrite32(val, axi_clkgen->base + reg);

Silly question: any reason to use this over readl()?  This is more for
my understanding than a real criticism.

> +}
> +
> +static void axi_clkgen_read(struct axi_clkgen *axi_clkgen,
> +       unsigned int reg, unsigned int *val)
> +{
> +       *val = ioread32(axi_clkgen->base + reg);

Same as above, any reason to use this over writel?

<snip>
> +static unsigned long axi_clkgen_recalc_rate(struct clk_hw *clk_hw,
> +       unsigned long parent_rate)
> +{
> +       struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
> +       unsigned int d, m, dout;
> +       unsigned int reg;
> +
> +       axi_clkgen_read(axi_clkgen, AXI_CLKGEN_REG_CLK_OUT1, &reg);
> +       dout = (reg & 0x3f) + ((reg >> 6) & 0x3f);
> +       axi_clkgen_read(axi_clkgen, AXI_CLKGEN_REG_CLK_DIV, &reg);
> +       d = (reg & 0x3f) + ((reg >> 6) & 0x3f);
> +       axi_clkgen_read(axi_clkgen, AXI_CLKGEN_REG_CLK_FB1, &reg);
> +       m = (reg & 0x3f) + ((reg >> 6) & 0x3f);
> +
> +       if (d == 0 || dout == 0)
> +               return 0;
> +
> +       return parent_rate / d * m / dout;

Any chance of overflow here?  Maybe do_div should be used?

Regards,
Mike

^ permalink raw reply

* [PATCH 6/6] ARM: at91/dts: add macb mii pinctrl config for kizbox
From: Nicolas Ferre @ 2013-01-22 17:50 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <cover.1358876553.git.nicolas.ferre@atmel.com>

From: Boris BREZILLON <linux-arm@overkiz.com>

This patch overrides default macb pinctrl config defined in
at91sam9260.dtsi (pinctrl_macb_rmii) with kizbox board config
(pinctrl_macb_rmii + pinctrl_macb_rmii_mii_alt).

Signed-off-by: Boris BREZILLON <linux-arm@overkiz.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
---
 arch/arm/boot/dts/kizbox.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/kizbox.dts b/arch/arm/boot/dts/kizbox.dts
index e8814fe..b4dc3ed 100644
--- a/arch/arm/boot/dts/kizbox.dts
+++ b/arch/arm/boot/dts/kizbox.dts
@@ -48,6 +48,8 @@
 
 			macb0: ethernet at fffc4000 {
 				phy-mode = "mii";
+				pinctrl-0 = <&pinctrl_macb_rmii
+				             &pinctrl_macb_rmii_mii_alt>;
 				status = "okay";
 			};
 
-- 
1.8.0

^ permalink raw reply related

* [PATCH 5/6] ARM: at91: rm9200: remake the BGA as default version
From: Nicolas Ferre @ 2013-01-22 17:50 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <cover.1358876553.git.nicolas.ferre@atmel.com>

From: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

Make BGA as the default version as we are supposed to just have
to specify when we use the PQFP version.

Issue was existing since commit:
3e90772 (ARM: at91: fix at91rm9200 soc subtype handling).

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: stable <stable@vger.kernel.org> [v3.3]
---
 arch/arm/mach-at91/setup.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 9ee866c..4b67847 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -105,6 +105,8 @@ static void __init soc_detect(u32 dbgu_base)
 	switch (socid) {
 	case ARCH_ID_AT91RM9200:
 		at91_soc_initdata.type = AT91_SOC_RM9200;
+		if (at91_soc_initdata.subtype == AT91_SOC_SUBTYPE_NONE)
+			at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
 		at91_boot_soc = at91rm9200_soc;
 		break;
 
-- 
1.8.0

^ permalink raw reply related

* [PATCH 4/6] ARM: at91: fix gpios on i2c-gpio for RM9200 DT
From: Nicolas Ferre @ 2013-01-22 17:50 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <cover.1358876553.git.nicolas.ferre@atmel.com>

From: Joachim Eastwood <manabian@gmail.com>

Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
---
 arch/arm/boot/dts/at91rm9200.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
index e154f24..222047f 100644
--- a/arch/arm/boot/dts/at91rm9200.dtsi
+++ b/arch/arm/boot/dts/at91rm9200.dtsi
@@ -336,8 +336,8 @@
 
 	i2c at 0 {
 		compatible = "i2c-gpio";
-		gpios = <&pioA 23 0 /* sda */
-			 &pioA 24 0 /* scl */
+		gpios = <&pioA 25 0 /* sda */
+			 &pioA 26 0 /* scl */
 			>;
 		i2c-gpio,sda-open-drain;
 		i2c-gpio,scl-open-drain;
-- 
1.8.0

^ permalink raw reply related

* [PATCH 3/6] ARM: at91/at91sam9x5 DTS: add SCK USART pins
From: Nicolas Ferre @ 2013-01-22 17:50 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <cover.1358876553.git.nicolas.ferre@atmel.com>

From: Richard Genoud <richard.genoud@gmail.com>

The SCK pins where missing in usarts pinctrl.

Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
---
 arch/arm/boot/dts/at91sam9x5.dtsi | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index e9c4290..cb711a5 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -143,6 +143,11 @@
 						atmel,pins =
 							<0 3 0x1 0x0>;	/* PA3 periph A */
 					};
+
+					pinctrl_usart0_sck: usart0_sck-0 {
+						atmel,pins =
+							<0 4 0x1 0x0>;	/* PA4 periph A */
+					};
 				};
 
 				usart1 {
@@ -161,6 +166,11 @@
 						atmel,pins =
 							<2 28 0x3 0x0>;	/* PC28 periph C */
 					};
+
+					pinctrl_usart1_sck: usart1_sck-0 {
+						atmel,pins =
+							<2 28 0x3 0x0>;	/* PC29 periph C */
+					};
 				};
 
 				usart2 {
@@ -179,6 +189,11 @@
 						atmel,pins =
 							<1 1 0x2 0x0>;	/* PB1 periph B */
 					};
+
+					pinctrl_usart2_sck: usart2_sck-0 {
+						atmel,pins =
+							<1 2 0x2 0x0>;	/* PB2 periph B */
+					};
 				};
 
 				usart3 {
@@ -197,6 +212,11 @@
 						atmel,pins =
 							<2 25 0x2 0x0>;	/* PC25 periph B */
 					};
+
+					pinctrl_usart3_sck: usart3_sck-0 {
+						atmel,pins =
+							<2 26 0x2 0x0>;	/* PC26 periph B */
+					};
 				};
 
 				uart0 {
-- 
1.8.0

^ permalink raw reply related

* [PATCH 2/6] ARM: at91/at91sam9x5 DTS: correct wrong PIO BANK values on u(s)arts
From: Nicolas Ferre @ 2013-01-22 17:50 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <cover.1358876553.git.nicolas.ferre@atmel.com>

From: Richard Genoud <richard.genoud@gmail.com>

The PIN_BANK 3 is for PDxx pins, not PCxx pins.
And PIN_BANK 1 is for PBxx, not PIN_BANK 0.

Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
---
 arch/arm/boot/dts/at91sam9x5.dtsi | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 3a47cf9..e9c4290 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -154,12 +154,12 @@
 
 					pinctrl_usart1_rts: usart1_rts-0 {
 						atmel,pins =
-							<3 27 0x3 0x0>;	/* PC27 periph C */
+							<2 27 0x3 0x0>;	/* PC27 periph C */
 					};
 
 					pinctrl_usart1_cts: usart1_cts-0 {
 						atmel,pins =
-							<3 28 0x3 0x0>;	/* PC28 periph C */
+							<2 28 0x3 0x0>;	/* PC28 periph C */
 					};
 				};
 
@@ -172,46 +172,46 @@
 
 					pinctrl_uart2_rts: uart2_rts-0 {
 						atmel,pins =
-							<0 0 0x2 0x0>;	/* PB0 periph B */
+							<1 0 0x2 0x0>;	/* PB0 periph B */
 					};
 
 					pinctrl_uart2_cts: uart2_cts-0 {
 						atmel,pins =
-							<0 1 0x2 0x0>;	/* PB1 periph B */
+							<1 1 0x2 0x0>;	/* PB1 periph B */
 					};
 				};
 
 				usart3 {
 					pinctrl_uart3: usart3-0 {
 						atmel,pins =
-							<3 23 0x2 0x1	/* PC22 periph B with pullup */
-							 3 23 0x2 0x0>;	/* PC23 periph B */
+							<2 23 0x2 0x1	/* PC22 periph B with pullup */
+							 2 23 0x2 0x0>;	/* PC23 periph B */
 					};
 
 					pinctrl_usart3_rts: usart3_rts-0 {
 						atmel,pins =
-							<3 24 0x2 0x0>;	/* PC24 periph B */
+							<2 24 0x2 0x0>;	/* PC24 periph B */
 					};
 
 					pinctrl_usart3_cts: usart3_cts-0 {
 						atmel,pins =
-							<3 25 0x2 0x0>;	/* PC25 periph B */
+							<2 25 0x2 0x0>;	/* PC25 periph B */
 					};
 				};
 
 				uart0 {
 					pinctrl_uart0: uart0-0 {
 						atmel,pins =
-							<3 8 0x3 0x0	/* PC8 periph C */
-							 3 9 0x3 0x1>;	/* PC9 periph C with pullup */
+							<2 8 0x3 0x0	/* PC8 periph C */
+							 2 9 0x3 0x1>;	/* PC9 periph C with pullup */
 					};
 				};
 
 				uart1 {
 					pinctrl_uart1: uart1-0 {
 						atmel,pins =
-							<3 16 0x3 0x0	/* PC16 periph C */
-							 3 17 0x3 0x1>;	/* PC17 periph C with pullup */
+							<2 16 0x3 0x0	/* PC16 periph C */
+							 2 17 0x3 0x1>;	/* PC17 periph C with pullup */
 					};
 				};
 
-- 
1.8.0

^ permalink raw reply related

* [PATCH 1/6] ARM: at91/at91-pinctrl documentation: fix typo and add some details
From: Nicolas Ferre @ 2013-01-22 17:50 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <cover.1358876553.git.nicolas.ferre@atmel.com>

From: Richard Genoud <richard.genoud@gmail.com>

The relation between PIN_BANK numbers and pio letters wasn't made very
clear.

Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
---
 Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
index 3a26812..bc50899 100644
--- a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
@@ -81,7 +81,8 @@ PA31	TXD4
 Required properties for pin configuration node:
 - atmel,pins: 4 integers array, represents a group of pins mux and config
   setting. The format is atmel,pins = <PIN_BANK PIN_BANK_NUM PERIPH CONFIG>.
-  The PERIPH 0 means gpio.
+  The PERIPH 0 means gpio, PERIPH 1 is periph A, PERIPH 2 is periph B...
+  PIN_BANK 0 is pioA, PIN_BANK 1 is pioB...
 
 Bits used for CONFIG:
 PULL_UP		(1 << 0): indicate this pin need a pull up.
@@ -126,7 +127,7 @@ pinctrl@fffff400 {
 		pinctrl_dbgu: dbgu-0 {
 			atmel,pins =
 				<1 14 0x1 0x0	/* PB14 periph A */
-				 1 15 0x1 0x1>;	/* PB15 periph with pullup */
+				 1 15 0x1 0x1>;	/* PB15 periph A with pullup */
 		};
 	};
 };
-- 
1.8.0

^ permalink raw reply related

* [PATCH 0/6] at91: some fixes for 3.8-rc5
From: Nicolas Ferre @ 2013-01-22 17:50 UTC (permalink / raw)
  To: linux-arm-kernel

Hi all,

I try to collect fixes for AT91 that can be applied during this development
cycle. Please tell me now if you have more to queue or if some of the proposed
fixes are not targetted to v3.8-final in you opinion...

Thanks, cheers,


Boris BREZILLON (1):
  ARM: at91/dts: add macb mii pinctrl config for kizbox

Jean-Christophe PLAGNIOL-VILLARD (1):
  ARM: at91: rm9200: remake the BGA as default version

Joachim Eastwood (1):
  ARM: at91: fix gpios on i2c-gpio for RM9200 DT

Richard Genoud (3):
  ARM: at91/at91-pinctrl documentation: fix typo and add some details
  ARM: at91/at91sam9x5 DTS: correct wrong PIO BANK values on u(s)arts
  ARM: at91/at91sam9x5 DTS: add SCK USART pins

 .../bindings/pinctrl/atmel,at91-pinctrl.txt        |  5 ++-
 arch/arm/boot/dts/at91rm9200.dtsi                  |  4 +-
 arch/arm/boot/dts/at91sam9x5.dtsi                  | 44 ++++++++++++++++------
 arch/arm/boot/dts/kizbox.dts                       |  2 +
 arch/arm/mach-at91/setup.c                         |  2 +
 5 files changed, 41 insertions(+), 16 deletions(-)

-- 
1.8.0

^ permalink raw reply

* [PATCH 15/15] staging/omapdrm: don't build on multiplatform
From: Arnd Bergmann @ 2013-01-22 17:47 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20130122173013.GA17212@kroah.com>

On Tuesday 22 January 2013, Greg Kroah-Hartman wrote:
> > Ie. I'd prefer to re-enable omapdss on multi-plat rather than
> > disabling omapdrm.  With changes in drm core, it is a bit of a pain
> > to compile test all the arm drivers by doing N different builds, so
> > we've been trying to get to the point of all arm drm drivers
> > supporting multi-plat
> 
> Ok, I'll let you and Arnd fight it out and drop this patch from my
> to-apply queue for now...

If Rob thinks there is no danger in allowing omap2_dss to be built
on all platforms, and Tomi has no objections, I'm fine with that, too.
In general, that is the right solution, I was just trying to be
conservative for the 3.8 cycle.

	Arnd

^ permalink raw reply

* [PATCH 3/6] arm: kconfig: don't select TWD with local timer for Armada 370/XP
From: Arnd Bergmann @ 2013-01-22 17:42 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20130122171817.GM23505@n2100.arm.linux.org.uk>

On Tuesday 22 January 2013, Russell King - ARM Linux wrote:
> > 
> > > >       default y
> > > I am not a kconfig expert, but won't this line set HAVE_ARM_TWD to 'y' whatever
> > > the result of the previous line?
> > 
> > Yes, that was a mistake on my side.
> 
> Sigh.  No.  Wrong.
> 
> config HAVE_ARM_TWD
>         depends on LOCAL_TIMERS
>         default ARCH_MULTIPLATFORM || (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT && !ARMADA_370_XP_TIMER)
>         default y
> 
> This takes the value of the first enabled default.  The first enabled
> default is the first default (it's unconditional).  So, the default y
> will never be used.

Right. I actually know how it works, but didn't think through it this
time. The 'default y' was a mistake on my side and should not have
been in there. I was also missing a 'bool' statement in there, which
makes the whole thing a syntax error.

> Given the above, it's far from clear what the actual behaviour being
> asked for is - it looks totally and utterly screwed to me - and the
> wrong thing to be doing.
> 
> If the desire is to have it enabled if ARCH_MULTIPLATFORM is set, then
> it's easy, and requires just a single line addition:
> 
>  config LOCAL_TIMERS
>         bool "Use local timer interrupts"
>         depends on SMP
>         default y
>         select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
> +       select HAVE_ARM_TWD if ARCH_MULTIPLATFORM

Right. The effect would be the same as what I intended to write:

config LOCAL_TIMERS
        bool "Use local timer interrupts"
        depends on SMP
        default y

config HAVE_ARM_TWD
	def_bool ARCH_MULTIPLATFORM || (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
        depends on LOCAL_TIMERS

but your patch is simpler.

	Arnd

^ permalink raw reply


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