* [PATCH v4] cpufreq: add imx6q-cpufreq driver
From: Shawn Guo @ 2013-01-26 15:31 UTC (permalink / raw)
To: linux-arm-kernel
Add an imx6q-cpufreq driver for Freescale i.MX6Q SoC to handle the
hardware specific frequency and voltage scaling requirements.
The driver supports module build and is instantiated by the platform
device/driver mechanism, so that it will not be instantiated on other
platforms, as IMX is built with multiplatform support.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Rafael J. Wysocki <rjw@sisk.pl>
---
Changes since v3:
* Add RCU lock for OPP pointer
* Handle regulator latency
drivers/cpufreq/Kconfig.arm | 9 ++
drivers/cpufreq/Makefile | 1 +
drivers/cpufreq/imx6q-cpufreq.c | 308 +++++++++++++++++++++++++++++++++++++++
3 files changed, 318 insertions(+)
create mode 100644 drivers/cpufreq/imx6q-cpufreq.c
diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index a0b3661..9e628ba 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -77,6 +77,15 @@ config ARM_EXYNOS5250_CPUFREQ
This adds the CPUFreq driver for Samsung EXYNOS5250
SoC.
+config ARM_IMX6Q_CPUFREQ
+ tristate "Freescale i.MX6Q cpufreq support"
+ depends on SOC_IMX6Q
+ depends on REGULATOR_ANATOP
+ help
+ This adds cpufreq driver support for Freescale i.MX6Q SOC.
+
+ If in doubt, say N.
+
config ARM_SPEAR_CPUFREQ
bool "SPEAr CPUFreq support"
depends on PLAT_SPEAR
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index 1f254ec0..31699a0 100644
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -49,6 +49,7 @@ obj-$(CONFIG_ARM_EXYNOS_CPUFREQ) += exynos-cpufreq.o
obj-$(CONFIG_ARM_EXYNOS4210_CPUFREQ) += exynos4210-cpufreq.o
obj-$(CONFIG_ARM_EXYNOS4X12_CPUFREQ) += exynos4x12-cpufreq.o
obj-$(CONFIG_ARM_EXYNOS5250_CPUFREQ) += exynos5250-cpufreq.o
+obj-$(CONFIG_ARM_IMX6Q_CPUFREQ) += imx6q-cpufreq.o
obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ) += omap-cpufreq.o
obj-$(CONFIG_ARM_SPEAR_CPUFREQ) += spear-cpufreq.o
diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c
new file mode 100644
index 0000000..368b6e7
--- /dev/null
+++ b/drivers/cpufreq/imx6q-cpufreq.c
@@ -0,0 +1,308 @@
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/clk.h>
+#include <linux/cpufreq.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/opp.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+
+#define PU_SOC_VOLTAGE_NORMAL 1250000
+#define PU_SOC_VOLTAGE_HIGH 1275000
+#define FREQ_1P2_GHZ 1200000000
+
+/*
+ * 1275000 mV - 950000 mV = 325 mV, 325 mV / 25 mV = 13 steps
+ * 512 clock cycles at 24 MHz for one step = 21.33 uS
+ * 21.33 us * 13 = ~280 uS
+ */
+#define MAX_REG_LATENCY 280
+
+static struct regulator *arm_reg;
+static struct regulator *pu_reg;
+static struct regulator *soc_reg;
+
+static struct clk *arm_clk;
+static struct clk *pll1_sys_clk;
+static struct clk *pll1_sw_clk;
+static struct clk *step_clk;
+static struct clk *pll2_pfd2_396m_clk;
+
+static struct device *cpu_dev;
+static struct cpufreq_frequency_table *freq_table;
+static unsigned int transition_latency = MAX_REG_LATENCY;
+
+static int imx6q_verify_speed(struct cpufreq_policy *policy)
+{
+ return cpufreq_frequency_table_verify(policy, freq_table);
+}
+
+static unsigned int imx6q_get_speed(unsigned int cpu)
+{
+ return clk_get_rate(arm_clk) / 1000;
+}
+
+static int imx6q_set_target(struct cpufreq_policy *policy,
+ unsigned int target_freq, unsigned int relation)
+{
+ struct cpufreq_freqs freqs;
+ struct opp *opp;
+ unsigned long freq_hz, volt, volt_old;
+ unsigned int index, cpu;
+ int ret;
+
+ ret = cpufreq_frequency_table_target(policy, freq_table, target_freq,
+ relation, &index);
+ if (ret) {
+ dev_err(cpu_dev, "failed to match target frequency %d: %d\n",
+ target_freq, ret);
+ return ret;
+ }
+
+ freqs.new = freq_table[index].frequency;
+ freq_hz = freqs.new * 1000;
+ freqs.old = clk_get_rate(arm_clk) / 1000;
+
+ if (freqs.old == freqs.new)
+ return 0;
+
+ for_each_online_cpu(cpu) {
+ freqs.cpu = cpu;
+ cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
+ }
+
+ rcu_read_lock();
+ opp = opp_find_freq_ceil(cpu_dev, &freq_hz);
+ if (IS_ERR(opp)) {
+ rcu_read_unlock();
+ dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz);
+ return PTR_ERR(opp);
+ }
+
+ volt = opp_get_voltage(opp);
+ rcu_read_unlock();
+ volt_old = regulator_get_voltage(arm_reg);
+
+ dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
+ freqs.old / 1000, volt_old / 1000,
+ freqs.new / 1000, volt / 1000);
+
+ /* scaling up? scale voltage before frequency */
+ if (freqs.new > freqs.old) {
+ ret = regulator_set_voltage_tol(arm_reg, volt, 0);
+ if (ret) {
+ dev_err(cpu_dev, "failed to scale voltage up: %d\n", ret);
+ return ret;
+ }
+
+ /*
+ * Need to increase vddpu and vddsoc for safety
+ * if we are about to run at 1.2 GHz.
+ */
+ if (freqs.new == FREQ_1P2_GHZ / 1000) {
+ regulator_set_voltage_tol(pu_reg,
+ PU_SOC_VOLTAGE_HIGH, 0);
+ regulator_set_voltage_tol(soc_reg,
+ PU_SOC_VOLTAGE_HIGH, 0);
+ }
+
+ /* Wait for LDOs to ramp up */
+ udelay(MAX_REG_LATENCY);
+ }
+
+ /*
+ * The setpoints are selected per PLL/PDF frequencies, so we need to
+ * reprogram PLL for frequency scaling. The procedure of reprogramming
+ * PLL1 is as below.
+ *
+ * - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it
+ * - Disable pll1_sys_clk and reprogram it
+ * - Enable pll1_sys_clk and reparent pll1_sw_clk back to it
+ * - Disable pll2_pfd2_396m_clk
+ */
+ clk_prepare_enable(pll2_pfd2_396m_clk);
+ clk_set_parent(step_clk, pll2_pfd2_396m_clk);
+ clk_set_parent(pll1_sw_clk, step_clk);
+ clk_prepare_enable(pll1_sys_clk);
+ if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) {
+ clk_disable_unprepare(pll1_sys_clk);
+ clk_set_rate(pll1_sys_clk, freqs.new * 1000);
+ clk_prepare_enable(pll1_sys_clk);
+ clk_set_parent(pll1_sw_clk, pll1_sys_clk);
+ clk_disable_unprepare(pll2_pfd2_396m_clk);
+ } else {
+ /*
+ * Disable pll1_sys_clk if pll2_pfd2_396m_clk is sufficient
+ * to provide the frequency.
+ */
+ clk_disable_unprepare(pll1_sys_clk);
+ }
+
+ /* Ensure the arm clock divider is what we expect */
+ ret = clk_set_rate(arm_clk, freqs.new * 1000);
+ if (ret) {
+ dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
+ regulator_set_voltage_tol(arm_reg, volt_old, 0);
+ return ret;
+ }
+
+ /* scaling down? scale voltage after frequency */
+ if (freqs.new < freqs.old) {
+ ret = regulator_set_voltage_tol(arm_reg, volt, 0);
+ if (ret)
+ dev_warn(cpu_dev, "failed to scale voltage down: %d\n", ret);
+
+ if (freqs.old == FREQ_1P2_GHZ / 1000) {
+ regulator_set_voltage_tol(pu_reg,
+ PU_SOC_VOLTAGE_NORMAL, 0);
+ regulator_set_voltage_tol(soc_reg,
+ PU_SOC_VOLTAGE_NORMAL, 0);
+ }
+ }
+
+ for_each_online_cpu(cpu) {
+ freqs.cpu = cpu;
+ cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+ }
+
+ return 0;
+}
+
+static int imx6q_cpufreq_init(struct cpufreq_policy *policy)
+{
+ int ret;
+
+ ret = cpufreq_frequency_table_cpuinfo(policy, freq_table);
+ if (ret) {
+ dev_err(cpu_dev, "invalid frequency table: %d\n", ret);
+ return ret;
+ }
+
+ policy->cpuinfo.transition_latency = transition_latency;
+ policy->cur = clk_get_rate(arm_clk) / 1000;
+ policy->shared_type = CPUFREQ_SHARED_TYPE_ANY;
+ cpumask_setall(policy->cpus);
+ cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
+
+ return 0;
+}
+
+static int imx6q_cpufreq_exit(struct cpufreq_policy *policy)
+{
+ cpufreq_frequency_table_put_attr(policy->cpu);
+ return 0;
+}
+
+static struct freq_attr *imx6q_cpufreq_attr[] = {
+ &cpufreq_freq_attr_scaling_available_freqs,
+ NULL,
+};
+
+static struct cpufreq_driver imx6q_cpufreq_driver = {
+ .verify = imx6q_verify_speed,
+ .target = imx6q_set_target,
+ .get = imx6q_get_speed,
+ .init = imx6q_cpufreq_init,
+ .exit = imx6q_cpufreq_exit,
+ .name = "imx6q-cpufreq",
+ .attr = imx6q_cpufreq_attr,
+};
+
+static int imx6q_cpufreq_probe(struct platform_device *pdev)
+{
+ struct device_node *np;
+ int ret;
+
+ cpu_dev = &pdev->dev;
+
+ np = of_find_node_by_path("/cpus/cpu at 0");
+ if (!np) {
+ dev_err(cpu_dev, "failed to find cpu0 node\n");
+ return -ENOENT;
+ }
+
+ cpu_dev->of_node = np;
+
+ arm_clk = devm_clk_get(cpu_dev, "arm");
+ pll1_sys_clk = devm_clk_get(cpu_dev, "pll1_sys");
+ pll1_sw_clk = devm_clk_get(cpu_dev, "pll1_sw");
+ step_clk = devm_clk_get(cpu_dev, "step");
+ pll2_pfd2_396m_clk = devm_clk_get(cpu_dev, "pll2_pfd2_396m");
+ if (IS_ERR(arm_clk) || IS_ERR(pll1_sys_clk) || IS_ERR(pll1_sw_clk) ||
+ IS_ERR(step_clk) || IS_ERR(pll2_pfd2_396m_clk)) {
+ dev_err(cpu_dev, "failed to get clocks\n");
+ ret = -ENOENT;
+ goto put_node;
+ }
+
+ arm_reg = devm_regulator_get(cpu_dev, "arm");
+ pu_reg = devm_regulator_get(cpu_dev, "pu");
+ soc_reg = devm_regulator_get(cpu_dev, "soc");
+ if (!arm_reg || !pu_reg || !soc_reg) {
+ dev_err(cpu_dev, "failed to get regulators\n");
+ ret = -ENOENT;
+ goto put_node;
+ }
+
+ /* We expect an OPP table supplied by platform */
+ ret = opp_get_opp_count(cpu_dev);
+ if (ret < 0) {
+ dev_err(cpu_dev, "no OPP table is found: %d\n", ret);
+ goto put_node;
+ }
+
+ ret = opp_init_cpufreq_table(cpu_dev, &freq_table);
+ if (ret) {
+ dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
+ goto put_node;
+ }
+
+ if (of_property_read_u32(np, "clock-latency", &transition_latency))
+ transition_latency = CPUFREQ_ETERNAL;
+
+ ret = cpufreq_register_driver(&imx6q_cpufreq_driver);
+ if (ret) {
+ dev_err(cpu_dev, "failed register driver: %d\n", ret);
+ goto free_freq_table;
+ }
+
+ of_node_put(np);
+ return 0;
+
+free_freq_table:
+ opp_free_cpufreq_table(cpu_dev, &freq_table);
+put_node:
+ of_node_put(np);
+ return ret;
+}
+
+static int imx6q_cpufreq_remove(struct platform_device *pdev)
+{
+ cpufreq_unregister_driver(&imx6q_cpufreq_driver);
+ opp_free_cpufreq_table(cpu_dev, &freq_table);
+
+ return 0;
+}
+
+static struct platform_driver imx6q_cpufreq_platdrv = {
+ .driver = {
+ .name = "imx6q-cpufreq",
+ .owner = THIS_MODULE,
+ },
+ .probe = imx6q_cpufreq_probe,
+ .remove = imx6q_cpufreq_remove,
+};
+module_platform_driver(imx6q_cpufreq_platdrv);
+
+MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
+MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver");
+MODULE_LICENSE("GPL");
--
1.7.9.5
^ permalink raw reply related
* [PATCH V3 8/8] ARM: kirkwood: mv643xx_eth dt conversion
From: Andrew Lunn @ 2013-01-26 15:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <a4805edf01c39a374d71fbf4a6b6207dedf6b2bf.1359146831.git.jason@lakedaemon.net>
> -config MACH_LSXL_DT
> - bool "Buffalo Linkstation LS-XHL, LS-CHLv2 (Flattened Device Tree)"
> - select ARCH_KIRKWOOD_DT
> - select POWER_RESET_RESTART
> - help
> - Say 'Y' here if you want your kernel to support the
> - Buffalo Linkstation LS-XHL & LS-CHLv2 devices, using
> - Flattened Device Tree.
Hi Jason
I don't think you add POWER_RESET_RESTART back anywhere. It should
probably be added to ARCH_KIRKWOOD_DT. Otherwise it will not be
possible to shutdown these boxes.
Thanks
Andrew
^ permalink raw reply
* [PATCH V3 8/8] ARM: kirkwood: mv643xx_eth dt conversion
From: Jason Cooper @ 2013-01-26 15:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130126134012.GE29973@lunn.ch>
On Sat, Jan 26, 2013 at 02:40:12PM +0100, Andrew Lunn wrote:
> On Sat, Jan 26, 2013 at 01:50:11PM +0100, Sebastian Hesselbarth wrote:
> > On 01/26/2013 01:38 PM, Andrew Lunn wrote:
> > >>diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
> > >>index 73b76e4..7ab92e5 100644
> > >>--- a/arch/arm/mach-kirkwood/board-dt.c
> > >>+++ b/arch/arm/mach-kirkwood/board-dt.c
> > >>@@ -48,7 +48,7 @@ static void __init kirkwood_legacy_clk_init(void)
> > >> clkspec.args_count = 1;
> > >>
> > >> clkspec.args[0] = CGC_BIT_GE0;
> > >>- orion_clkdev_add(NULL, "mv643xx_eth_port.0",
> > >>+ orion_clkdev_add(NULL, "f1072000.egiga0",
> > >> of_clk_get_from_provider(&clkspec));
> > >>
> > >> clkspec.args[0] = CGC_BIT_PEX0;
> > >>@@ -60,7 +60,7 @@ static void __init kirkwood_legacy_clk_init(void)
> > >> of_clk_get_from_provider(&clkspec));
> > >>
> > >> clkspec.args[0] = CGC_BIT_GE1;
> > >>- orion_clkdev_add(NULL, "mv643xx_eth_port.1",
> > >>+ orion_clkdev_add(NULL, "f1076000.egiga1",
> > >> of_clk_get_from_provider(&clkspec));
> > >> }
> > >>
> > >These changes break any platform not yet converted, eg my QNAP box now
> > >locks up solid.
> > >
> > >Something is not right here, or i'm not understanding something. DT
> > >devices should not need code like this, only devices not yet using
> > >DT....
> >
> > Jason, Andrew,
> >
> > have a look at dove_legacy_clk_init() in arch/arm/mach-dove/common.c.
> > This is how I handled non-DT clock aliases from DT provided clocks.
> > Maybe you can also use it for kirkwood.
>
> Hi Sebastian
>
> The code here is based on dove_legacy_clk_init(). However the change
> made by Jason is in order to make a DT device work, not an non-DT
> device.
>
> The problem is the way the driver is getting the clock.
>
> mp->clk = clk_get(&pdev->dev, (pdev->id ? "1" : "0"));
>
> clk_get() then calls
>
> clk = of_clk_get_by_name(dev->of_node, con_id);
>
> * of_clk_get_by_name() - Parse and lookup a clock referenced by a device node
> * @np: pointer to clock consumer node
> * @name: name of consumer's clock input, or NULL for the first clock reference
>
> So it is looking for a clock called "0" or "1" in the node. This does
> not exist, and so it falls. Jason's change then comes into affect and
> it finds the clkdev entries added above.
Exactly.
> I will change the driver to use of_clk_get() when passed an np.
something like this? (on top of this series):
btw - I just booted this and it is working...
$ cat ge0/clk_prepare_count
1
$ cat ge1/clk_prepare_count
1
$
--8<-------
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index 7ab92e5..620c99f 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -47,10 +47,6 @@ static void __init kirkwood_legacy_clk_init(void)
clkspec.np = np;
clkspec.args_count = 1;
- clkspec.args[0] = CGC_BIT_GE0;
- orion_clkdev_add(NULL, "f1072000.egiga0",
- of_clk_get_from_provider(&clkspec));
-
clkspec.args[0] = CGC_BIT_PEX0;
orion_clkdev_add("0", "pcie",
of_clk_get_from_provider(&clkspec));
@@ -58,10 +54,6 @@ static void __init kirkwood_legacy_clk_init(void)
clkspec.args[0] = CGC_BIT_PEX1;
orion_clkdev_add("1", "pcie",
of_clk_get_from_provider(&clkspec));
-
- clkspec.args[0] = CGC_BIT_GE1;
- orion_clkdev_add(NULL, "f1076000.egiga1",
- of_clk_get_from_provider(&clkspec));
}
static void __init kirkwood_of_clk_init(void)
diff --git a/drivers/net/ethernet/marvell/mv643xx_eth.c b/drivers/net/ethernet/marvell/mv643xx_eth.c
index 7048d7c..8fb92d4 100644
--- a/drivers/net/ethernet/marvell/mv643xx_eth.c
+++ b/drivers/net/ethernet/marvell/mv643xx_eth.c
@@ -2895,6 +2895,7 @@ static int mv643xx_eth_probe(struct platform_device *pdev)
if (pdev->dev.of_node) {
struct device_node *np = NULL;
+ struct clk *clk = NULL;
/* when all users of this driver use FDT, we can remove this */
pd = kzalloc(sizeof(*pd), GFP_KERNEL);
@@ -2912,6 +2913,12 @@ static int mv643xx_eth_probe(struct platform_device *pdev)
else
pd->phy_addr = MV643XX_ETH_PHY_ADDR_DEFAULT;
+ clk = of_clk_get(pdev->dev.of_node, 0);
+ if (!IS_ERR(clk)) {
+ clk_prepare_enable(clk);
+ clk_put(clk);
+ }
+
np = of_parse_phandle(pdev->dev.of_node, "mdio", 0);
if (np) {
pd->shared = of_find_device_by_node(np);
^ permalink raw reply related
* [PATCH v2 0/3] Kirkwoode cpufreq driver
From: Andrew Lunn @ 2013-01-26 15:43 UTC (permalink / raw)
To: linux-arm-kernel
This patchset adds a cpufreq driver for Marvell Kirkwood SoCs.
The changes to kirkwood_defconfig enable it and set the default
governor to ondemand.
Changes since v1:
tabify Kconfig.arm entry
Sort order of include files
Remove some unnecassary include files
Reformat multiline comment to be coding style conform.
Andrew Lunn (3):
cpufreq: kirkwood: Add a cpufreq driver for Marvell Kirkwood SoCs
arm: kirkwood: Instantiate cpufreq driver
arm: kirkwood: Enable cpufreq and ondemand on kirkwood_defconfig
arch/arm/Kconfig | 1 +
arch/arm/configs/kirkwood_defconfig | 3 +
arch/arm/mach-kirkwood/board-dt.c | 3 +-
arch/arm/mach-kirkwood/common.c | 23 ++
arch/arm/mach-kirkwood/common.h | 2 +
arch/arm/mach-kirkwood/include/mach/bridge-regs.h | 2 +
drivers/clk/mvebu/clk-gating-ctrl.c | 1 +
drivers/cpufreq/Kconfig.arm | 6 +
drivers/cpufreq/Makefile | 1 +
drivers/cpufreq/kirkwood-cpufreq.c | 271 +++++++++++++++++++++
10 files changed, 312 insertions(+), 1 deletion(-)
create mode 100644 drivers/cpufreq/kirkwood-cpufreq.c
--
1.7.10.4
^ permalink raw reply
* [PATCH v2 1/3] cpufreq: kirkwood: Add a cpufreq driver for Marvell Kirkwood SoCs
From: Andrew Lunn @ 2013-01-26 15:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359215039-2848-1-git-send-email-andrew@lunn.ch>
The Marvell Kirkwood SoCs have simple cpufreq support in hardware. The
CPU can either use the a high speed cpu clock, or the slower DDR
clock. Add a driver to swap between these two clock sources.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
---
drivers/clk/mvebu/clk-gating-ctrl.c | 1 +
drivers/cpufreq/Kconfig.arm | 6 +
drivers/cpufreq/Makefile | 1 +
drivers/cpufreq/kirkwood-cpufreq.c | 271 +++++++++++++++++++++++++++++++++++
4 files changed, 279 insertions(+)
create mode 100644 drivers/cpufreq/kirkwood-cpufreq.c
diff --git a/drivers/clk/mvebu/clk-gating-ctrl.c b/drivers/clk/mvebu/clk-gating-ctrl.c
index 8fa5408..ebf141d 100644
--- a/drivers/clk/mvebu/clk-gating-ctrl.c
+++ b/drivers/clk/mvebu/clk-gating-ctrl.c
@@ -193,6 +193,7 @@ static const struct mvebu_soc_descr __initconst kirkwood_gating_descr[] = {
{ "runit", NULL, 7 },
{ "xor0", NULL, 8 },
{ "audio", NULL, 9 },
+ { "powersave", "cpuclk", 11 },
{ "sata0", NULL, 14 },
{ "sata1", NULL, 15 },
{ "xor1", NULL, 16 },
diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index a0b3661..80c8229 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -77,6 +77,12 @@ config ARM_EXYNOS5250_CPUFREQ
This adds the CPUFreq driver for Samsung EXYNOS5250
SoC.
+config ARM_KIRKWOOD_CPUFREQ
+ def_bool ARCH_KIRKWOOD && OF
+ help
+ This adds the CPUFreq driver for Marvell Kirkwood
+ SoCs.
+
config ARM_SPEAR_CPUFREQ
bool "SPEAr CPUFreq support"
depends on PLAT_SPEAR
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index fadc4d4..39a0ffe 100644
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -50,6 +50,7 @@ obj-$(CONFIG_ARM_EXYNOS_CPUFREQ) += exynos-cpufreq.o
obj-$(CONFIG_ARM_EXYNOS4210_CPUFREQ) += exynos4210-cpufreq.o
obj-$(CONFIG_ARM_EXYNOS4X12_CPUFREQ) += exynos4x12-cpufreq.o
obj-$(CONFIG_ARM_EXYNOS5250_CPUFREQ) += exynos5250-cpufreq.o
+obj-$(CONFIG_ARM_KIRKWOOD_CPUFREQ) += kirkwood-cpufreq.o
obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ) += omap-cpufreq.o
obj-$(CONFIG_ARM_SPEAR_CPUFREQ) += spear-cpufreq.o
diff --git a/drivers/cpufreq/kirkwood-cpufreq.c b/drivers/cpufreq/kirkwood-cpufreq.c
new file mode 100644
index 0000000..300d01d
--- /dev/null
+++ b/drivers/cpufreq/kirkwood-cpufreq.c
@@ -0,0 +1,271 @@
+/*
+ * kirkwood_freq.c: cpufreq driver for the Marvell kirkwood
+ *
+ * Copyright (C) 2013 Andrew Lunn <andrew@lunn.ch>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/clk.h>
+#include <linux/cpufreq.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <asm/proc-fns.h>
+
+#define CPU_SW_INT_BLK BIT(28)
+
+
+#include <linux/clk-private.h>
+
+static struct priv
+{
+ struct clk *cpu_clk;
+ struct clk *ddr_clk;
+ struct clk *powersave_clk;
+ struct device *dev;
+ void __iomem *base;
+} priv;
+
+#define STATE_CPU_FREQ 0x01
+#define STATE_DDR_FREQ 0x02
+
+/*
+ * Kirkwood can swap the clock to the CPU between two clocks:
+ *
+ * - cpu clk
+ * - ddr clk
+ *
+ * The frequencies are set at runtime before registering this *
+ * table.
+ */
+static struct cpufreq_frequency_table kirkwood_freq_table[] = {
+ {STATE_CPU_FREQ, 0}, /* CPU uses cpuclk */
+ {STATE_DDR_FREQ, 0}, /* CPU uses ddrclk */
+ {0, CPUFREQ_TABLE_END},
+};
+
+static unsigned int kirkwood_cpufreq_get_cpu_frequency(unsigned int cpu)
+{
+ if (__clk_is_enabled(priv.powersave_clk))
+ return kirkwood_freq_table[1].frequency;
+ return kirkwood_freq_table[0].frequency;
+}
+
+static void kirkwood_cpufreq_set_cpu_state(unsigned int index)
+{
+
+ struct cpufreq_freqs freqs;
+ unsigned int state = kirkwood_freq_table[index].index;
+ unsigned long reg;
+
+ freqs.old = kirkwood_cpufreq_get_cpu_frequency(0);
+ freqs.new = kirkwood_freq_table[index].frequency;
+ freqs.cpu = 0; /* Kirkwood is UP */
+
+ cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
+
+ dev_dbg(priv.dev, "Attempting to set frequency to %i KHz\n",
+ kirkwood_freq_table[index].frequency);
+ dev_dbg(priv.dev, "old frequency was %i KHz\n",
+ kirkwood_cpufreq_get_cpu_frequency(0));
+
+ if (freqs.old != freqs.new) {
+ local_irq_disable();
+
+ /* Disable interrupts to the CPU */
+ reg = readl_relaxed(priv.base);
+ reg |= CPU_SW_INT_BLK;
+ writel(reg, priv.base);
+
+ switch (state) {
+ case STATE_CPU_FREQ:
+ clk_disable(priv.powersave_clk);
+ break;
+ case STATE_DDR_FREQ:
+ clk_enable(priv.powersave_clk);
+ break;
+ default:
+ dev_err(priv.dev, "Unexpected cpufreq state");
+ }
+
+ /* Wait-for-Interrupt, which the hardware changes frequency */
+ cpu_do_idle();
+
+ /* Enable interrupts to the CPU */
+ reg = readl_relaxed(priv.base);
+ reg &= ~CPU_SW_INT_BLK;
+ writel(reg, priv.base);
+
+ local_irq_enable();
+ }
+ cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+};
+
+static int kirkwood_cpufreq_verify(struct cpufreq_policy *policy)
+{
+ return cpufreq_frequency_table_verify(policy, &kirkwood_freq_table[0]);
+}
+
+static int kirkwood_cpufreq_target(struct cpufreq_policy *policy,
+ unsigned int target_freq,
+ unsigned int relation)
+{
+ unsigned int index = 0;
+
+ if (cpufreq_frequency_table_target(policy, kirkwood_freq_table,
+ target_freq, relation, &index))
+ return -EINVAL;
+
+ kirkwood_cpufreq_set_cpu_state(index);
+
+ return 0;
+}
+
+/*
+ * Module init and exit code
+ */
+static int kirkwood_cpufreq_cpu_init(struct cpufreq_policy *policy)
+{
+ int result;
+
+ /* cpuinfo and default policy values */
+ policy->cpuinfo.transition_latency = 5000; /* 5uS */
+ policy->cur = kirkwood_cpufreq_get_cpu_frequency(0);
+
+ result = cpufreq_frequency_table_cpuinfo(policy, kirkwood_freq_table);
+ if (result)
+ return result;
+
+ cpufreq_frequency_table_get_attr(kirkwood_freq_table, policy->cpu);
+
+ return 0;
+}
+
+static int kirkwood_cpufreq_cpu_exit(struct cpufreq_policy *policy)
+{
+ cpufreq_frequency_table_put_attr(policy->cpu);
+ return 0;
+}
+
+static struct freq_attr *kirkwood_cpufreq_attr[] = {
+ &cpufreq_freq_attr_scaling_available_freqs,
+ NULL,
+};
+
+
+static struct cpufreq_driver kirkwood_cpufreq_driver = {
+ .get = kirkwood_cpufreq_get_cpu_frequency,
+ .verify = kirkwood_cpufreq_verify,
+ .target = kirkwood_cpufreq_target,
+ .init = kirkwood_cpufreq_cpu_init,
+ .exit = kirkwood_cpufreq_cpu_exit,
+ .name = "kirkwood_freq",
+ .owner = THIS_MODULE,
+ .attr = kirkwood_cpufreq_attr,
+};
+
+static int kirkwood_cpufreq_probe(struct platform_device *pdev)
+{
+ struct device_node *np = of_find_compatible_node(
+ NULL, NULL, "marvell,kirkwood-core-clock");
+
+ struct of_phandle_args clkspec;
+ struct resource *res;
+ int err;
+
+ priv.dev = &pdev->dev;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_err(&pdev->dev, "Cannot get memory resource\n");
+ return -ENODEV;
+ }
+ priv.base = devm_request_and_ioremap(&pdev->dev, res);
+ if (!priv.base) {
+ dev_err(&pdev->dev, "Cannot ioremap\n");
+ return -ENOMEM;
+ }
+
+ clkspec.np = np;
+ clkspec.args_count = 1;
+ clkspec.args[0] = 1;
+
+ priv.cpu_clk = of_clk_get_from_provider(&clkspec);
+ if (IS_ERR(priv.cpu_clk)) {
+ dev_err(priv.dev, "Unable to get cpuclk");
+ return PTR_ERR(priv.cpu_clk);
+ }
+
+ clk_prepare_enable(priv.cpu_clk);
+ kirkwood_freq_table[0].frequency = clk_get_rate(priv.cpu_clk) / 1000;
+
+ clkspec.args[0] = 3;
+ priv.ddr_clk = of_clk_get_from_provider(&clkspec);
+ if (IS_ERR(priv.ddr_clk)) {
+ dev_err(priv.dev, "Unable to get ddrclk");
+ err = PTR_ERR(priv.ddr_clk);
+ goto out_cpu;
+ }
+
+ clk_prepare_enable(priv.ddr_clk);
+ kirkwood_freq_table[1].frequency = clk_get_rate(priv.ddr_clk) / 1000;
+
+ np = of_find_compatible_node(NULL, NULL,
+ "marvell,kirkwood-gating-clock");
+ clkspec.np = np;
+ clkspec.args[0] = 11;
+ priv.powersave_clk = of_clk_get_from_provider(&clkspec);
+ if (IS_ERR(priv.powersave_clk)) {
+ dev_err(priv.dev, "Unable to get powersave");
+ err = PTR_ERR(priv.powersave_clk);
+ goto out_ddr;
+ }
+ clk_prepare(priv.powersave_clk);
+
+ err = cpufreq_register_driver(&kirkwood_cpufreq_driver);
+ if (!err)
+ return 0;
+ dev_err(priv.dev, "Failed to register cpufreq driver");
+
+ clk_disable_unprepare(priv.powersave_clk);
+out_ddr:
+ clk_disable_unprepare(priv.ddr_clk);
+out_cpu:
+ clk_disable_unprepare(priv.cpu_clk);
+
+ return err;
+}
+
+
+static int kirkwood_cpufreq_remove(struct platform_device *pdev)
+{
+ cpufreq_unregister_driver(&kirkwood_cpufreq_driver);
+
+ clk_disable_unprepare(priv.powersave_clk);
+ clk_disable_unprepare(priv.ddr_clk);
+ clk_disable_unprepare(priv.cpu_clk);
+
+ return 0;
+}
+
+static struct platform_driver kirkwood_cpufreq_platform_driver = {
+ .probe = kirkwood_cpufreq_probe,
+ .remove = kirkwood_cpufreq_remove,
+ .driver = {
+ .name = "kirkwood-cpufreq",
+ .owner = THIS_MODULE,
+ },
+};
+
+module_platform_driver(kirkwood_cpufreq_platform_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Andrew Lunn <andrew@lunn.ch");
+MODULE_DESCRIPTION("cpufreq driver for Marvell's kirkwood CPU");
+MODULE_ALIAS("platform:kirkwood-cpufreq");
--
1.7.10.4
^ permalink raw reply related
* [PATCH v2 2/3] arm: kirkwood: Instantiate cpufreq driver
From: Andrew Lunn @ 2013-01-26 15:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359215039-2848-1-git-send-email-andrew@lunn.ch>
Register a platform driver structure for the cpufreq driver.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
---
arch/arm/Kconfig | 1 +
arch/arm/mach-kirkwood/board-dt.c | 3 ++-
arch/arm/mach-kirkwood/common.c | 23 +++++++++++++++++++++
arch/arm/mach-kirkwood/common.h | 2 ++
arch/arm/mach-kirkwood/include/mach/bridge-regs.h | 2 ++
5 files changed, 30 insertions(+), 1 deletion(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 67874b8..830975b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -543,6 +543,7 @@ config ARCH_DOVE
config ARCH_KIRKWOOD
bool "Marvell Kirkwood"
+ select ARCH_HAS_CPUFREQ
select ARCH_REQUIRE_GPIOLIB
select CPU_FEROCEON
select GENERIC_CLOCKEVENTS
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index de4fd2b..fab541d 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -70,7 +70,6 @@ static void __init kirkwood_legacy_clk_init(void)
clkspec.args[0] = CGC_BIT_SDIO;
orion_clkdev_add(NULL, "mvsdio",
of_clk_get_from_provider(&clkspec));
-
}
static void __init kirkwood_of_clk_init(void)
@@ -95,6 +94,8 @@ static void __init kirkwood_dt_init(void)
kirkwood_l2_init();
+ kirkwood_cpufreq_init();
+
/* Setup root of clk tree */
kirkwood_of_clk_init();
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index bac21a5..a3dc21c 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -584,6 +584,29 @@ void __init kirkwood_audio_init(void)
}
/*****************************************************************************
+ * CPU Frequency
+ ****************************************************************************/
+static struct resource kirkwood_cpufreq_resources[] = {
+ [0] = {
+ .start = CPU_CONTROL_PHYS,
+ .end = CPU_CONTROL_PHYS + 3,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device kirkwood_cpufreq_device = {
+ .name = "kirkwood-cpufreq",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(kirkwood_cpufreq_resources),
+ .resource = kirkwood_cpufreq_resources,
+};
+
+void __init kirkwood_cpufreq_init(void)
+{
+ platform_device_register(&kirkwood_cpufreq_device);
+}
+
+/*****************************************************************************
* General
****************************************************************************/
/*
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 5ffa57f..9ede04b 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -50,6 +50,8 @@ void kirkwood_nand_init(struct mtd_partition *parts, int nr_parts, int delay);
void kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts,
int (*dev_ready)(struct mtd_info *));
void kirkwood_audio_init(void);
+void kirkwood_cpufreq_init(void);
+
void kirkwood_restart(char, const char *);
void kirkwood_clk_init(void);
diff --git a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
index 5c82b7d..d4cbe5e 100644
--- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
+++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
@@ -17,6 +17,7 @@
#define CPU_CONFIG_ERROR_PROP 0x00000004
#define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104)
+#define CPU_CONTROL_PHYS (BRIDGE_PHYS_BASE + 0x0104)
#define CPU_RESET 0x00000002
#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108)
@@ -69,6 +70,7 @@
#define CGC_RUNIT (1 << 7)
#define CGC_XOR0 (1 << 8)
#define CGC_AUDIO (1 << 9)
+#define CGC_POWERSAVE (1 << 11)
#define CGC_SATA0 (1 << 14)
#define CGC_SATA1 (1 << 15)
#define CGC_XOR1 (1 << 16)
--
1.7.10.4
^ permalink raw reply related
* [PATCH v2 3/3] arm: kirkwood: Enable cpufreq and ondemand on kirkwood_defconfig
From: Andrew Lunn @ 2013-01-26 15:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359215039-2848-1-git-send-email-andrew@lunn.ch>
Now that we have a cpufreq driver for kirkwood, enable it in
kirkwood_defconfig and set the default governer to ondemand.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
---
arch/arm/configs/kirkwood_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig
index 93f3794..6ecb7de 100644
--- a/arch/arm/configs/kirkwood_defconfig
+++ b/arch/arm/configs/kirkwood_defconfig
@@ -55,6 +55,9 @@ CONFIG_AEABI=y
# CONFIG_OABI_COMPAT is not set
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_STAT_DETAILS=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
CONFIG_CPU_IDLE=y
CONFIG_NET=y
CONFIG_PACKET=y
--
1.7.10.4
^ permalink raw reply related
* [PATCH 0/3] atmel_lcdfb: fix 16-bpp regression
From: Johan Hovold @ 2013-01-26 15:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1355142530-10366-1-git-send-email-jhovold@gmail.com>
On Mon, Dec 10, 2012 at 01:28:47PM +0100, Johan Hovold wrote:
> These patches fix a regression in 16-bpp support for older SOCs which use
> IBGR:555 rather than BGR:565 pixel layout. Use SOC-type to determine if the
> controller uses the intensity-bit and restore the old layout in that case.
I understand the maintainer's been busy lately, but could someone pick
these regression fixes up so we can get them into v3.8-rc and the stable
trees?
Thanks,
Johan
^ permalink raw reply
* [PATCH V3 8/8] ARM: kirkwood: mv643xx_eth dt conversion
From: Jason Cooper @ 2013-01-26 15:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130126153357.GG29973@lunn.ch>
On Sat, Jan 26, 2013 at 04:33:57PM +0100, Andrew Lunn wrote:
> > -config MACH_LSXL_DT
> > - bool "Buffalo Linkstation LS-XHL, LS-CHLv2 (Flattened Device Tree)"
> > - select ARCH_KIRKWOOD_DT
> > - select POWER_RESET_RESTART
> > - help
> > - Say 'Y' here if you want your kernel to support the
> > - Buffalo Linkstation LS-XHL & LS-CHLv2 devices, using
> > - Flattened Device Tree.
>
> Hi Jason
>
> I don't think you add POWER_RESET_RESTART back anywhere. It should
> probably be added to ARCH_KIRKWOOD_DT. Otherwise it will not be
> possible to shutdown these boxes.
Good catch, I'll add that in.
thx,
Jason.
^ permalink raw reply
* [PATCH 1/3] NET: mv643xx: Get clk from device tree.
From: Jason Cooper @ 2013-01-26 15:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359213030-18588-2-git-send-email-andrew@lunn.ch>
On Sat, Jan 26, 2013 at 04:10:28PM +0100, Andrew Lunn wrote:
> If we are passed a device tree node pointer, get the clock from it.
> This avoids problems with con_id when using clk_get().
>
> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
> ---
> drivers/net/ethernet/marvell/mv643xx_eth.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
I like this much better than what I hacked together, thanks.
Jason.
> diff --git a/drivers/net/ethernet/marvell/mv643xx_eth.c b/drivers/net/ethernet/marvell/mv643xx_eth.c
> index 7048d7c..296beec 100644
> --- a/drivers/net/ethernet/marvell/mv643xx_eth.c
> +++ b/drivers/net/ethernet/marvell/mv643xx_eth.c
> @@ -2955,7 +2955,10 @@ static int mv643xx_eth_probe(struct platform_device *pdev)
> */
> mp->t_clk = 133000000;
> #if defined(CONFIG_HAVE_CLK)
> - mp->clk = clk_get(&pdev->dev, (pdev->id ? "1" : "0"));
> + if (pdev->dev.of_node)
> + mp->clk = of_clk_get(pdev->dev.of_node, 0);
> + else
> + mp->clk = clk_get(&pdev->dev, (pdev->id ? "1" : "0"));
> if (!IS_ERR(mp->clk)) {
> clk_prepare_enable(mp->clk);
> mp->t_clk = clk_get_rate(mp->clk);
> --
> 1.7.10.4
>
^ permalink raw reply
* [PATCH] arm: dts: Add uart1 and uart2 to igep boards.
From: Javier Martinez Canillas @ 2013-01-26 15:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CABuKBeJsHCq98Pe-BwPajbQ+2OLQpwrbtVTJe=j9thPDQCCBrg@mail.gmail.com>
On Sat, Jan 26, 2013 at 4:16 PM, Matthias Brugger
<matthias.bgg@gmail.com<javascript:;>>
wrote:
> Hi Benoit,
>
> 2012/12/12 Benoit Cousson <b-cousson@ti.com <javascript:;>>:
>> Hi Matthias,
>>
>> On 12/12/2012 04:33 PM, Matthias Brugger wrote:
>>> This patch is a follow-up patch for Javier Martinez effort adding
initial
>>> device tree support to IGEP technology devices. [1]
>>>
>>> It adds uart1 and uart2 bindings to the generic dtsi for the IGEP
boards.
>>>
>>> [1] http://www.spinics.net/lists/linux-omap/msg83409.html
>>>
>>> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com <javascript:;>>
>>> ---
>>> arch/arm/boot/dts/omap3-igep.dtsi | 24 ++++++++++++++++++++++++
>>> 1 file changed, 24 insertions(+)
>>>
>>> diff --git a/arch/arm/boot/dts/omap3-igep.dtsi
b/arch/arm/boot/dts/omap3-igep.dtsi
>>> index 125fe00..c02e3c0 100644
>>> --- a/arch/arm/boot/dts/omap3-igep.dtsi
>>> +++ b/arch/arm/boot/dts/omap3-igep.dtsi
>>> @@ -27,6 +27,20 @@
>>> };
>>>
>>> &omap3_pmx_core {
>>> + uart1_pins: pinmux_uart1_pins {
>>> + pinctrl-single,pins = <
>>> + 0x152 0x100 /* uart1_rx.uart1_rx INPUT |
MODE0 */
>>> + 0x14c 0 /* uart1_tx.uart1_tx OUTPUT |
MODE0 */
>>> + >;
>>> + };
>>> +
>>> + uart2_pins: pinmux_uart2_pins {
>>> + pinctrl-single,pins = <
>>> + 0x14a 0x100 /* uart2_rx.uart2_rx INPUT |
MODE0 */
>>> + 0x148 0 /* uart2_tx.uart2_tx OUTPUT |
MODE0 */
>>> + >;
>>> + };
>>> +
>>> uart3_pins: pinmux_uart3_pins {
>>> pinctrl-single,pins = <
>>> 0x16e 0x100 /* uart3_rx.uart3_rx INPUT |
MODE0 */
>>> @@ -77,6 +91,16 @@
>>> status = "disabled";
>>> };
>>>
>>> +&uart1 {
>>> + pinctrl-names = "default";
>>> + pinctrl-0 = <&uart1_pins>;
>>> +};
>>> +
>>> +&uart2 {
>>> + pinctrl-names = "default";
>>> + pinctrl-0 = <&uart2_pins>;
>>> +};
>>> +
>>> &uart3 {
>>> pinctrl-names = "default";
>>> pinctrl-0 = <&uart3_pins>;
>>>
>>
>> That looks good to me. I'll apply it on top of javier's series for 3.9.
>
> Can you pin-point me to the repository where this patches are in right
> now? I tried to figure it out these days, but didn't found where to
> clone the repository from.
>
> Thanks,
> Matthias
>
Hi Matthias,
OMAP DT tree is: git://
git.kernel.org/pub/scm/linux/kernel/git/bcousson/linux-omap-dt.git
Hope it helps,
Javier
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^ permalink raw reply
* [PATCH V3 1/8] ARM: kirkwood: topkick: init mvsdio via DT
From: Andrew Lunn @ 2013-01-26 16:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <e99a647c7c1eae5dfee3b1ccf9f6803c3c859962.1359146831.git.jason@lakedaemon.net>
On Fri, Jan 25, 2013 at 08:53:53PM +0000, Jason Cooper wrote:
> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
> ---
> arch/arm/boot/dts/kirkwood-topkick.dts | 7 +++++++
> arch/arm/mach-kirkwood/board-usi_topkick.c | 6 ------
> 2 files changed, 7 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/boot/dts/kirkwood-topkick.dts b/arch/arm/boot/dts/kirkwood-topkick.dts
> index cd15452..23c2ddc 100644
> --- a/arch/arm/boot/dts/kirkwood-topkick.dts
> +++ b/arch/arm/boot/dts/kirkwood-topkick.dts
> @@ -54,6 +54,13 @@
> status = "okay";
> nr-ports = <1>;
> };
> +
> + mvsdio at 90000 {
> + pinctrl-0 = <&pmx_sdio>;
> + pinctrl-names = "default";
> + status = "okay";
> + /* No CD or WP GPIOs */
> + };
> };
>
> gpio-leds {
> diff --git a/arch/arm/mach-kirkwood/board-usi_topkick.c b/arch/arm/mach-kirkwood/board-usi_topkick.c
> index 23d2dd1..95f0711 100644
> --- a/arch/arm/mach-kirkwood/board-usi_topkick.c
> +++ b/arch/arm/mach-kirkwood/board-usi_topkick.c
> @@ -14,7 +14,6 @@
> #include <linux/init.h>
> #include <linux/mv643xx_eth.h>
> #include <linux/gpio.h>
> -#include <linux/platform_data/mmc-mvsdio.h>
> #include "common.h"
> #include "mpp.h"
>
> @@ -22,10 +21,6 @@ static struct mv643xx_eth_platform_data topkick_ge00_data = {
> .phy_addr = MV643XX_ETH_PHY_ADDR(0),
> };
>
> -static struct mvsdio_platform_data topkick_mvsdio_data = {
> - /* unfortunately the CD signal has not been connected */
> -};
> -
> /*
> * GPIO LED layout
> *
> @@ -73,5 +68,4 @@ void __init usi_topkick_init(void)
>
>
> kirkwood_ge00_init(&topkick_ge00_data);
> - kirkwood_sdio_init(&topkick_mvsdio_data);
> }
> --
> 1.8.1.1
>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Andrew
^ permalink raw reply
* [PATCH 1/2] ARM: Kirkwood: topkick: Fix SoC type and add missing pins
From: Andrew Lunn @ 2013-01-26 16:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <f6d483f3fb83826bce16f956afa013f0bcf11f52.1359146831.git.jason@lakedaemon.net>
Topkick contains a Marvell 6282, not an 6281 as included in the
kirkwood-topkick.dts file.
Also, add pinhogs for the serial port and nand devices.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
---
arch/arm/boot/dts/kirkwood-topkick.dts | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/kirkwood-topkick.dts b/arch/arm/boot/dts/kirkwood-topkick.dts
index edefbb5..c8e8a64 100644
--- a/arch/arm/boot/dts/kirkwood-topkick.dts
+++ b/arch/arm/boot/dts/kirkwood-topkick.dts
@@ -1,7 +1,7 @@
/dts-v1/;
/include/ "kirkwood.dtsi"
-/include/ "kirkwood-6281.dtsi"
+/include/ "kirkwood-6282.dtsi"
/ {
model = "Univeral Scientific Industrial Co. Topkick-1281P2";
@@ -50,7 +50,9 @@
&pmx_sw_right
&pmx_sw_idle
&pmx_sw_left2
- &pmx_led_wifi_yellow >;
+ &pmx_led_wifi_yellow
+ &pmx_uart0
+ &pmx_nand >;
pinctrl-names = "default";
pmx_led_disk_yellow: pmx-led-disk-yellow {
--
1.7.10.4
^ permalink raw reply related
* [PATCH 2/2] ARM: Kirkwood: topkick: Enable i2c bus.
From: Andrew Lunn @ 2013-01-26 16:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359219326-5927-1-git-send-email-andrew@lunn.ch>
Add a DT node for I2C and pinctrl hog for the pins. There appears to
be an i2c bus on topkick with a device on it:
i2cdetect 0
WARNING! This program can confuse your I2C bus, cause data loss and worse!
I will probe file /dev/i2c-0.
I will probe address range 0x03-0x77.
Continue? [Y/n] y
0 1 2 3 4 5 6 7 8 9 a b c d e f
00: -- -- -- -- -- -- -- -- -- -- -- -- --
10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
30: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
40: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
60: -- -- -- -- 64 -- -- -- -- -- -- -- -- -- -- --
70: -- -- -- -- -- -- -- --
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
---
arch/arm/boot/dts/kirkwood-topkick.dts | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/kirkwood-topkick.dts b/arch/arm/boot/dts/kirkwood-topkick.dts
index c8e8a64..75fc1dd 100644
--- a/arch/arm/boot/dts/kirkwood-topkick.dts
+++ b/arch/arm/boot/dts/kirkwood-topkick.dts
@@ -52,7 +52,8 @@
&pmx_sw_left2
&pmx_led_wifi_yellow
&pmx_uart0
- &pmx_nand >;
+ &pmx_nand
+ &pmx_twsi0 >;
pinctrl-names = "default";
pmx_led_disk_yellow: pmx-led-disk-yellow {
@@ -159,6 +160,9 @@
egiga0 {
status = "ok";
};
+ i2c at 11000 {
+ status = "ok";
+ };
};
gpio-leds {
--
1.7.10.4
^ permalink raw reply related
* [PATCH] dma: mv_xor: remove minimal offload length threshold
From: Mario Schuknecht @ 2013-01-26 17:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1356639358.28655.7.camel@sakura.staff.proxad.net>
Maxime Bizon <mbizon <at> freebox.fr> writes:
>
> On Thu, 2012-12-27 at 20:20 +0100, Lubomir Rintel wrote:
> >
> > of memory condition and retries indefinitelly, causing a soft lockup.
> > The threshold does not seem to be enforced by hardware (couldn't find
> > anything like that in a datasheet)
>
> page 212
>
> Table 63: Descriptor Byte Count Word
>
> 3:0 ByteCount
>
> XOR mode: Size of source and destination blocks in bytes.
> CRC mode: Size of source block part represented by the descriptor.
> DMA mode: Size of source and destination block in bytes.
> Minimum blocks' size: 16B.
> Maximum blocks' size: 16MB-1
>
> > and things seems to work fine without it. If there's a
>
> my guess is that it transfers 16B so it seems to work but actually
> corrupts data.
>
> maybe we should teach net_dma_find_channel() about that limitation
>
I observe the same error with the Marvell SoC 88F6282. The patch works. It is
sufficient to just change the #define MV_XOR_MIN_BYTE_COUNT of 128 to 16. But
I'm not very familiar with the code and Marvell xor/dma engine.
Therefore the questions: Is the patch correctly for the SoC 88F6282? Is the
error still in work? And is there an offical solution soon?
Kind regards,
Mario Schuknecht
^ permalink raw reply
* [PATCH 2/2] ARM: Kirkwood: topkick: Enable i2c bus.
From: Sebastian Hesselbarth @ 2013-01-26 17:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359219326-5927-2-git-send-email-andrew@lunn.ch>
On 01/26/2013 05:55 PM, Andrew Lunn wrote:
> Add a DT node for I2C and pinctrl hog for the pins. There appears to
> be an i2c bus on topkick with a device on it:
>
> 60: -- -- -- -- 64 -- -- -- -- -- -- -- -- -- -- --
Andrew,
this could be a Nuvoton NCT3012S ACPI PMIC. It is located right next to
Wifi/BT. There is i2c address should be 6c but officially it
only supports 100kHz bus frequency. Can you post i2cdetect and
i2cdump with 100kHz?
Sebastian
[1] http://www.catagle.com/29-11/NCT3012S.htm
^ permalink raw reply
* [PATCH 09/13] ARM: spear: make clock driver independent of headers
From: Mike Turquette @ 2013-01-26 17:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359156956-32404-10-git-send-email-arnd@arndb.de>
Quoting Arnd Bergmann (2013-01-25 15:35:52)
> Device drivers should not access MMIO registers through hardcoded
> platform specific address constants. Instead, we can pass the
> MMIO token to the spear clock driver in the initialization routine
> to contain that knowledge in the platform code itself.
>
> Ideally, the clock driver would use of_iomap() or similar to
> get the address, and that can be used later, but for now, this
> is the minimal change.
>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Hi Arnd,
This change appears good to me (but needs testing).
Regards,
Mike
^ permalink raw reply
* [PATCH 2/2] ARM: Kirkwood: topkick: Enable i2c bus.
From: Andrew Lunn @ 2013-01-26 18:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <510414B3.6000207@gmail.com>
On Sat, Jan 26, 2013 at 06:38:59PM +0100, Sebastian Hesselbarth wrote:
> On 01/26/2013 05:55 PM, Andrew Lunn wrote:
> >Add a DT node for I2C and pinctrl hog for the pins. There appears to
> >be an i2c bus on topkick with a device on it:
> >
> >60: -- -- -- -- 64 -- -- -- -- -- -- -- -- -- -- --
>
> Andrew,
>
> this could be a Nuvoton NCT3012S ACPI PMIC. It is located right next to
> Wifi/BT. There is i2c address should be 6c but officially it
> only supports 100kHz bus frequency. Can you post i2cdetect and
> i2cdump with 100kHz?
Hi Sebastian
100KHz is the default in the kirkwood.dtsi file.
Just to be paranoid, i dropped it to 10KHz. No difference, still at
address 0x64.
Probing just 0x6c does not help:
# i2cdetect 0 0x6c 0x6c
WARNING! This program can confuse your I2C bus, cause data loss and worse!
I will probe file /dev/i2c-0.
I will probe address range 0x6c-0x6c.
Continue? [Y/n] y
0 1 2 3 4 5 6 7 8 9 a b c d e f
00:
10:
20:
30:
40:
50:
60: --
70:
However, there are some issues at other addresses, both at 100KHz and
10KHz:
# i2cdetect 0
WARNING! This program can confuse your I2C bus, cause data loss and worse!
I will probe file /dev/i2c-0.
I will probe address range 0x03-0x77.
Continue? [Y/n] y
0 1 2 3 4 5 6 7 8 9 a b c d e f
00: -- -- -- -- --i2c i2c-0: mv64xxx_i2c_fsm: Ctlr Error -- state: 0x71
-- -- -- -- -- -- -- --
10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
30: -- -- -- -- -- -- -- i2c i2c-0: mv64xxx_i2c_fsm: Ctlr Error -- state: 0x2, 1
-- -- -- -- -- -- -- -- --
40: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
60: -- -- -- -- 64 -- -- -- -- -- -- -- -- -- -- --
70: -- -- -- -- -- -- -- --
Full message is:
[ 215.514562] i2c i2c-0: mv64xxx_i2c_fsm: Ctlr Error -- state: 0x7, status: 0x38, addr: 0x36, flags: 0x1
[ 215.545791] i2c i2c-0: mv64xxx_i2c_fsm: Ctlr Error -- state: 0x2, status: 0x0, addr: 0x37, flags: 0x1
So maybe there is something at 0x36 and 0x37 as well?
# i2cdump 0 0x36
No size specified (using byte-data access)
WARNING! This program can confuse your I2C bus, cause data loss and worse!
I will probe file /dev/i2c-0, address 0x36, mode byte
Continue? [Y/n] y
0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef
00: 3d 00 00 87 47 0c 00 08 00 13 00 00 10 00 00 00 =..?G?.?.?..?...
10: ff ff 00 6c 09 02 ff ff ff ff ff ff ff ff ff ff ...l??..........
20: 88 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ?...............
30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
# i2cdump 0 0x37
No size specified (using byte-data access)
WARNING! This program can confuse your I2C bus, cause data loss and worse!
I will probe file /dev/i2c-0, address 0x37, mode byte
Continue? [Y/n] y
0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef
00: XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XXXXXXXXXXXXXXXX
10: XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XXXXXXXXXXXXXXXX
20: XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XXXXXXXXXXXXXXXX
30: XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XXXXXXXXXXXXXXXX
40: XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XXXXXXXXXXXXXXXX
50: XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XXXXXXXXXXXXXXXX
60: XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XXXXXXXXXXXXXXXX
70: XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XXXXXXXXXXXXXXXX
80: XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XXXXXXXXXXXXXXXX
90: XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XXXXXXXXXXXXXXXX
a0: XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XXXXXXXXXXXXXXXX
b0: XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XXXXXXXXXXXXXXXX
c0: XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XXXXXXXXXXXXXXXX
d0: XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XXXXXXXXXXXXXXXX
e0: XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XXXXXXXXXXXXXXXX
f0: XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XXXXXXXXXXXXXXXX
Nothing interesting at 0x64:
# i2cdump 0 0x64
No size specified (using byte-data access)
WARNING! This program can confuse your I2C bus, cause data loss and worse!
I will probe file /dev/i2c-0, address 0x64, mode byte
Continue? [Y/n] y
0 1 2 3 i2c i2c-0: mv64xxx_i2c_fsm: Ctlr Error -- state: 0x2, status: 0x0, addr: 0x64, flags: 0x0
4 5 6 7 8 9 a b c d e f 0123456789abcdef
00: XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XXXXXXXXXXXXXXXX
10: XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XXXXXXXXXXXXXXXX
20: XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XXXXXXXXXXXXXXXX
30: XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XXXXXXXXXXXXXXXX
40: XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XXXXXXXXXXXXXXXX
50: XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XXXXXXXXXXXXXXXX
60: XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XXXXXXXXXXXXXXXX
70: XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XXXXXXXXXXXXXXXX
80: XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XXXXXXXXXXXXXXXX
90: XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XXXXXXXXXXXXXXXX
a0: XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XXXXXXXXXXXXXXXX
b0: XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XXXXXXXXXXXXXXXX
c0: XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XXXXXXXXXXXXXXXX
d0: XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XXXXXXXXXXXXXXXX
e0: XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XXXXXXXXXXXXXXXX
f0: XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XXXXXXXXXXXXXXXX
Humm. A thought. 6282 has two i2c busses. I had noticed that uboot had
configured the pin multiplexer such that they could be used for
i2c. But maybe the NCT3012S is on the other i2c bus? Need to go look
and see, but that will probably happen tomorrow....
Andrew
^ permalink raw reply
* [PATCH 2/2] ARM: Kirkwood: topkick: Enable i2c bus.
From: Sebastian Hesselbarth @ 2013-01-26 18:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130126182454.GM17242@lunn.ch>
On 01/26/2013 07:24 PM, Andrew Lunn wrote:
> # i2cdump 0 0x36
> No size specified (using byte-data access)
> WARNING! This program can confuse your I2C bus, cause data loss and worse!
> I will probe file /dev/i2c-0, address 0x36, mode byte
> Continue? [Y/n] y
> 0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef
> 00: 3d 00 00 87 47 0c 00 08 00 13 00 00 10 00 00 00 =..?G?.?.?..?...
> 10: ff ff 00 6c 09 02 ff ff ff ff ff ff ff ff ff ff ...l??..........
> 20: 88 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ?...............
>
> ...
>
> Humm. A thought. 6282 has two i2c busses. I had noticed that uboot had
> configured the pin multiplexer such that they could be used for
> i2c. But maybe the NCT3012S is on the other i2c bus? Need to go look
> and see, but that will probably happen tomorrow....
0x36 (=0x6c >> 1) is the nuvoton pmic. Register values match what is
written in that very short datasheet.
Sebastian
^ permalink raw reply
* [PATCH] clk: mvebu: Do not gate ge0/1 and runit clocks on Kirkwood
From: Simon Baatz @ 2013-01-26 19:01 UTC (permalink / raw)
To: linux-arm-kernel
Commits f479db "ARM: Kirkwood: Ensure runit clock always ticks." and
128789 "ARM: Kirkwood: Fix clk problems modular ethernet driver"
ensured that the ge and runit clocks always tick on Kirkwood. This
prevents the device from locking up and from forgetting the MAC addresses
which are usually set by the boot loader.
When moving the clock gating control to this driver for DT devices, these
changes were disabled. Ensure that the respective clocks have the
CLK_IGNORE_UNUSED flag set.
Signed-off-by: Simon Baatz <gmbnomis@gmail.com>
---
Hi,
kernel 3.8-rc5 will hang on kirkwood DT if the Ethernet driver is built
as a module or when no driver claiming the runit clock is built in.
(Usually, at least the serial driver is built in, but it won't request
the clock if "clock-frequency" is given in DT.)
In the past, we fixed this by keeping the clocks ticking (which
probably is not be the nicest solution for the ge clocks).
The patch creates much noise, but is hopefully obvious. I have tested
it on IB-NAS6210 (kirkwood, single Ethernet port). The other platforms
are only compile tested. I don't know whether something similar is
required for other platforms as well; I left them untouched.
- Simon
drivers/clk/mvebu/clk-gating-ctrl.c | 159 +++++++++++++++++------------------
1 file changed, 79 insertions(+), 80 deletions(-)
diff --git a/drivers/clk/mvebu/clk-gating-ctrl.c b/drivers/clk/mvebu/clk-gating-ctrl.c
index 8fa5408..917049c 100644
--- a/drivers/clk/mvebu/clk-gating-ctrl.c
+++ b/drivers/clk/mvebu/clk-gating-ctrl.c
@@ -28,6 +28,7 @@ struct mvebu_soc_descr {
const char *name;
const char *parent;
int bit_idx;
+ unsigned long flags;
};
#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
@@ -88,21 +89,12 @@ static void __init mvebu_clk_gating_setup(
}
for (n = 0; n < ctrl->num_gates; n++) {
- u8 flags = 0;
const char *parent =
(descr[n].parent) ? descr[n].parent : default_parent;
-
- /*
- * On Armada 370, the DDR clock is a special case: it
- * isn't taken by any driver, but should anyway be
- * kept enabled, so we mark it as IGNORE_UNUSED for
- * now.
- */
- if (!strcmp(descr[n].name, "ddr"))
- flags |= CLK_IGNORE_UNUSED;
-
ctrl->gates[n] = clk_register_gate(NULL, descr[n].name, parent,
- flags, base, descr[n].bit_idx, 0, &ctrl->lock);
+ descr[n].flags, base,
+ descr[n].bit_idx,
+ 0, &ctrl->lock);
WARN_ON(IS_ERR(ctrl->gates[n]));
}
of_clk_add_provider(np, mvebu_clk_gating_get_src, ctrl);
@@ -114,92 +106,99 @@ static void __init mvebu_clk_gating_setup(
#ifdef CONFIG_MACH_ARMADA_370
static const struct mvebu_soc_descr __initconst armada_370_gating_descr[] = {
- { "audio", NULL, 0 },
- { "pex0_en", NULL, 1 },
- { "pex1_en", NULL, 2 },
- { "ge1", NULL, 3 },
- { "ge0", NULL, 4 },
- { "pex0", NULL, 5 },
- { "pex1", NULL, 9 },
- { "sata0", NULL, 15 },
- { "sdio", NULL, 17 },
- { "tdm", NULL, 25 },
- { "ddr", NULL, 28 },
- { "sata1", NULL, 30 },
+ { .name = "audio", .bit_idx = 0 },
+ { .name = "pex0_en", .bit_idx = 1 },
+ { .name = "pex1_en", .bit_idx = 2 },
+ { .name = "ge1", .bit_idx = 3 },
+ { .name = "ge0", .bit_idx = 4 },
+ { .name = "pex0", .bit_idx = 5 },
+ { .name = "pex1", .bit_idx = 9 },
+ { .name = "sata0", .bit_idx = 15 },
+ { .name = "sdio", .bit_idx = 17 },
+ { .name = "tdm", .bit_idx = 25 },
+ /* The DDR clock is a special case: it isn't taken by
+ * any driver, but should anyway be kept enabled.
+ */
+ { .name = "ddr", .bit_idx = 28, .flags = CLK_IGNORE_UNUSED },
+ { .name = "sata1", .bit_idx = 30 },
{ }
};
#endif
#ifdef CONFIG_MACH_ARMADA_XP
static const struct mvebu_soc_descr __initconst armada_xp_gating_descr[] = {
- { "audio", NULL, 0 },
- { "ge3", NULL, 1 },
- { "ge2", NULL, 2 },
- { "ge1", NULL, 3 },
- { "ge0", NULL, 4 },
- { "pex0", NULL, 5 },
- { "pex1", NULL, 6 },
- { "pex2", NULL, 7 },
- { "pex3", NULL, 8 },
- { "bp", NULL, 13 },
- { "sata0lnk", NULL, 14 },
- { "sata0", "sata0lnk", 15 },
- { "lcd", NULL, 16 },
- { "sdio", NULL, 17 },
- { "usb0", NULL, 18 },
- { "usb1", NULL, 19 },
- { "usb2", NULL, 20 },
- { "xor0", NULL, 22 },
- { "crypto", NULL, 23 },
- { "tdm", NULL, 25 },
- { "xor1", NULL, 28 },
- { "sata1lnk", NULL, 29 },
- { "sata1", "sata1lnk", 30 },
+ { .name = "audio", .bit_idx = 0 },
+ { .name = "ge3", .bit_idx = 1 },
+ { .name = "ge2", .bit_idx = 2 },
+ { .name = "ge1", .bit_idx = 3 },
+ { .name = "ge0", .bit_idx = 4 },
+ { .name = "pex0", .bit_idx = 5 },
+ { .name = "pex1", .bit_idx = 6 },
+ { .name = "pex2", .bit_idx = 7 },
+ { .name = "pex3", .bit_idx = 8 },
+ { .name = "bp", .bit_idx = 13 },
+ { .name = "sata0lnk", .bit_idx = 14 },
+ { .name = "sata0", .bit_idx = 15, .parent = "sata0lnk" },
+ { .name = "lcd", .bit_idx = 16 },
+ { .name = "sdio", .bit_idx = 17 },
+ { .name = "usb0", .bit_idx = 18 },
+ { .name = "usb1", .bit_idx = 19 },
+ { .name = "usb2", .bit_idx = 20 },
+ { .name = "xor0", .bit_idx = 22 },
+ { .name = "crypto", .bit_idx = 23 },
+ { .name = "tdm", .bit_idx = 25 },
+ { .name = "xor1", .bit_idx = 28 },
+ { .name = "sata1lnk", .bit_idx = 29 },
+ { .name = "sata1", .bit_idx = 30, .parent = "sata1lnk" },
{ }
};
#endif
#ifdef CONFIG_ARCH_DOVE
static const struct mvebu_soc_descr __initconst dove_gating_descr[] = {
- { "usb0", NULL, 0 },
- { "usb1", NULL, 1 },
- { "ge", "gephy", 2 },
- { "sata", NULL, 3 },
- { "pex0", NULL, 4 },
- { "pex1", NULL, 5 },
- { "sdio0", NULL, 8 },
- { "sdio1", NULL, 9 },
- { "nand", NULL, 10 },
- { "camera", NULL, 11 },
- { "i2s0", NULL, 12 },
- { "i2s1", NULL, 13 },
- { "crypto", NULL, 15 },
- { "ac97", NULL, 21 },
- { "pdma", NULL, 22 },
- { "xor0", NULL, 23 },
- { "xor1", NULL, 24 },
- { "gephy", NULL, 30 },
+ { .name = "usb0", .bit_idx = 0 },
+ { .name = "usb1", .bit_idx = 1 },
+ { .name = "ge", .bit_idx = 2, .parent = "gephy" },
+ { .name = "sata", .bit_idx = 3 },
+ { .name = "pex0", .bit_idx = 4 },
+ { .name = "pex1", .bit_idx = 5 },
+ { .name = "sdio0", .bit_idx = 8 },
+ { .name = "sdio1", .bit_idx = 9 },
+ { .name = "nand", .bit_idx = 10 },
+ { .name = "camera", .bit_idx = 11 },
+ { .name = "i2s0", .bit_idx = 12 },
+ { .name = "i2s1", .bit_idx = 13 },
+ { .name = "crypto", .bit_idx = 15 },
+ { .name = "ac97", .bit_idx = 21 },
+ { .name = "pdma", .bit_idx = 22 },
+ { .name = "xor0", .bit_idx = 23 },
+ { .name = "xor1", .bit_idx = 24 },
+ { .name = "gephy", .bit_idx = 30 },
{ }
};
#endif
#ifdef CONFIG_ARCH_KIRKWOOD
static const struct mvebu_soc_descr __initconst kirkwood_gating_descr[] = {
- { "ge0", NULL, 0 },
- { "pex0", NULL, 2 },
- { "usb0", NULL, 3 },
- { "sdio", NULL, 4 },
- { "tsu", NULL, 5 },
- { "runit", NULL, 7 },
- { "xor0", NULL, 8 },
- { "audio", NULL, 9 },
- { "sata0", NULL, 14 },
- { "sata1", NULL, 15 },
- { "xor1", NULL, 16 },
- { "crypto", NULL, 17 },
- { "pex1", NULL, 18 },
- { "ge1", NULL, 19 },
- { "tdm", NULL, 20 },
+ /* Prevent that the Ethernet interfaces will forget their
+ * MAC addresses by keeping the "ge0/1" clocks running.
+ */
+ { .name = "ge0", .bit_idx = 0, .flags = CLK_IGNORE_UNUSED },
+ { .name = "pex0", .bit_idx = 2 },
+ { .name = "usb0", .bit_idx = 3 },
+ { .name = "sdio", .bit_idx = 4 },
+ { .name = "tsu", .bit_idx = 5 },
+ /* Devices will lock hard if the "runit" clock is gated. */
+ { .name = "runit", .bit_idx = 7, .flags = CLK_IGNORE_UNUSED },
+ { .name = "xor0", .bit_idx = 8 },
+ { .name = "audio", .bit_idx = 9 },
+ { .name = "sata0", .bit_idx = 14 },
+ { .name = "sata1", .bit_idx = 15 },
+ { .name = "xor1", .bit_idx = 16 },
+ { .name = "crypto", .bit_idx = 17 },
+ { .name = "pex1", .bit_idx = 18 },
+ { .name = "ge1", .bit_idx = 19, .flags = CLK_IGNORE_UNUSED },
+ { .name = "tdm", .bit_idx = 20 },
{ }
};
#endif
--
1.7.9.5
^ permalink raw reply related
* [PATCH v2 4/6] ARM: dts: omap5: add dwc3 omap dt data
From: Sergei Shtylyov @ 2013-01-26 19:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359112312-6918-5-git-send-email-kishon@ti.com>
Hello.
On 25-01-2013 15:11, Kishon Vijay Abraham I wrote:
> Add dwc3 omap glue data to the omap5 dt data file. The information about
> the dt node added here is available @
> Documentation/devicetree/bindings/usb/omap-usb.txt
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
> arch/arm/boot/dts/omap5.dtsi | 11 +++++++++++
> 1 file changed, 11 insertions(+)
> diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
> index 5f59bf2..1703a72 100644
> --- a/arch/arm/boot/dts/omap5.dtsi
> +++ b/arch/arm/boot/dts/omap5.dtsi
> @@ -513,6 +513,17 @@
> ti,type = <2>;
> };
>
> + omap_dwc3 at 4a020000 {
> + compatible = "ti,dwc3";
> + ti,hwmods = "usb_otg_ss";
> + reg = <0x4a020000 0x1ff>;
Shoudn't the "reg" length be 0x200 here? It's length, not limit.
WBR, Sergei
^ permalink raw reply
* [PATCH v2 5/6] ARM: dts: omap5: add dwc3 core dt data
From: Sergei Shtylyov @ 2013-01-26 19:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359112312-6918-6-git-send-email-kishon@ti.com>
On 25-01-2013 15:11, Kishon Vijay Abraham I wrote:
> Add dwc3 core dt data as a subnode to dwc3 omap glue data in omap5 dt
> data file. The information for the entered data node is available @
> Documentation/devicetree/bindings/usb/dwc3.txt
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
> arch/arm/boot/dts/omap5.dtsi | 7 +++++++
> 1 file changed, 7 insertions(+)
> diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
> index 1703a72..58118c4 100644
> --- a/arch/arm/boot/dts/omap5.dtsi
> +++ b/arch/arm/boot/dts/omap5.dtsi
> @@ -522,6 +522,13 @@
> #size-cells = <1>;
> utmi-mode = <2>;
> ranges;
> + dwc3 at 4a030000 {
> + compatible = "synopsys,dwc3";
> + reg = <0x4a030000 0xcfff>;
Same question here.
WBR, Sergei
^ permalink raw reply
* [PATCH 2/3] ARM: Kirkwood: Revert clkdev changes.
From: Jason Cooper @ 2013-01-26 19:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359213030-18588-3-git-send-email-andrew@lunn.ch>
On Sat, Jan 26, 2013 at 04:10:29PM +0100, Andrew Lunn wrote:
> Now that the Ethernet driver can get its clock from device tree,
> revert this change which broken non-DT probing of the ethernet device.
>
> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
> ---
> arch/arm/mach-kirkwood/board-dt.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Squashed in,
thx,
Jason.
^ permalink raw reply
* [RFC V2 PATCH 3/8] ARM: kirkwood: nsa310: cleanup includes and unneeded code
From: Sergei Shtylyov @ 2013-01-26 20:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <31142087d93c2713d067f4ccf470810e6e71f17b.1359091286.git.jason@lakedaemon.net>
Hello.
On 25-01-2013 9:32, Jason Cooper wrote:
> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
> ---
> arch/arm/mach-kirkwood/board-nsa310.c | 9 +--------
> 1 file changed, 1 insertion(+), 8 deletions(-)
> diff --git a/arch/arm/mach-kirkwood/board-nsa310.c b/arch/arm/mach-kirkwood/board-nsa310.c
> index 1bd328d..0b99533 100644
> --- a/arch/arm/mach-kirkwood/board-nsa310.c
> +++ b/arch/arm/mach-kirkwood/board-nsa310.c
> @@ -10,11 +10,8 @@
>
> #include <linux/kernel.h>
> #include <linux/init.h>
> -#include <linux/i2c.h>
> -
> -#include <asm/mach-types.h>
> -#include <asm/mach/arch.h>
> #include <mach/kirkwood.h>
> +#include <linux/of.h>
You also add an #include and don't mention it anywhere. Or is that part of
the cleanup?
WBR, Sergei
^ permalink raw reply
* [PATCH 3/3] ARM: Kirkwood: Convert QNAP TS219 Ethernet to DT.
From: Jason Cooper @ 2013-01-26 20:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359213030-18588-4-git-send-email-andrew@lunn.ch>
On Sat, Jan 26, 2013 at 04:10:30PM +0100, Andrew Lunn wrote:
> Add DT nodes for the Ethernet ports and remove the C code. The PHY
> addresses depends on which SoC is used, so place the nodes into the
> SoC specific DTS files.
>
> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
> ---
> arch/arm/boot/dts/kirkwood-ts219-6281.dts | 9 +++++++
> arch/arm/boot/dts/kirkwood-ts219-6282.dts | 10 ++++++++
> arch/arm/mach-kirkwood/Kconfig | 17 ++-----------
> arch/arm/mach-kirkwood/Makefile | 1 -
> arch/arm/mach-kirkwood/board-dt.c | 3 ---
> arch/arm/mach-kirkwood/board-ts219.c | 37 -----------------------------
> arch/arm/mach-kirkwood/common.h | 6 -----
> 7 files changed, 21 insertions(+), 62 deletions(-)
> delete mode 100644 arch/arm/mach-kirkwood/board-ts219.c
Pulled into the series. Thanks.
fyi - I also converted keymile. The only one left is the iomega_ix2_200
board. Which only inits ge01.
thx,
Jason.
^ permalink raw reply
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