* [arm-soc:next/soc 4/8] arch/arm/mach-prima2/platsmp.c:20:30: fatal error: asm/hardware/gic.h: No such file or directory
From: Barry Song @ 2013-02-04 5:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130130003908.GA12315@quad.lixom.net>
Hi Olof,
2013/1/30 Olof Johansson <olof@lixom.net>
>
> On Wed, Jan 30, 2013 at 08:29:05AM +0800, Xie ChanglongX wrote:
> >
> > Hi Olof,
> >
> > FYI, kernel build failed on
> >
> > tree: git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git
> > next/soc
> > head: 6ed05a2aab3763b58922247543d7079106b254dc
> > commit: af70fdc947dbe835acc26c6ee9e8e930f38935f8 [4/8] Merge branch
> > 'marco-timer-cleanup-rebase' of
> > git://gitorious.org/sirfprima2-kernel/sirfprima2-kernel into next/soc
> > config: make ARCH=arm prima2_defconfig
>
> Thanks! Yes, this is a known issue as of this morning, I didn't catch it
> before
> I merged in so I asked Barry to follow up with a fix.
done by "[PATCH] ARM: MARCO: fix the build issue due to
gic-vic-to-irqchip move".
i'll not send a pull request for it, would you apply it separately?
>
>
> -Olof
-barry
^ permalink raw reply
* linux-next: manual merge of the arm-soc tree with the mfd tree
From: Stephen Rothwell @ 2013-02-04 6:04 UTC (permalink / raw)
To: linux-arm-kernel
Hi all,
Today's linux-next merge of the arm-soc tree got a conflict in
drivers/mfd/db8500-prcmu.c between commit 5073e7b57041 ("mfd:
db8500-prcmu: Add ux500_wdt mfd_cell") from the mfd tree and commit
520f7bd73354 ("irqchip: Move ARM gic.h to
include/linux/irqchip/arm-gic.h") from the arm-soc tree.
I fixed it up (see below) and can carry the fix as necessary (no action
is required).
--
Cheers,
Stephen Rothwell sfr at canb.auug.org.au
diff --cc drivers/mfd/db8500-prcmu.c
index e42a417,42f3afc..0000000
--- a/drivers/mfd/db8500-prcmu.c
+++ b/drivers/mfd/db8500-prcmu.c
@@@ -32,8 -33,6 +33,7 @@@
#include <linux/regulator/db8500-prcmu.h>
#include <linux/regulator/machine.h>
#include <linux/cpufreq.h>
+#include <linux/platform_data/ux500_wdt.h>
- #include <asm/hardware/gic.h>
#include <mach/hardware.h>
#include <mach/irqs.h>
#include <mach/db8500-regs.h>
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^ permalink raw reply
* [PATCH v5 01/10] clk: tegra: Refactor PLL programming code
From: Prashant Gaikwad @ 2013-02-04 6:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359713962-16822-2-git-send-email-pdeschrijver@nvidia.com>
On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:
> Refactor the PLL programming code to make it useable by the new PLL types
> introduced by Tegra114.
>
> The following changes were done:
>
> * Split programming the PLL into updating m,n,p and updating cpcon
> * Move locking from _update_pll_cpcon() to clk_pll_set_rate()
> * Introduce _get_pll_mnp() helper
> * Move check for identical m,n,p values to clk_pll_set_rate()
> * struct tegra_clk_pll_freq_table will always contain the values as defined
> by the hardware.
> * Simplify the arguments to clk_pll_wait_for_lock()
>
> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> ---
> drivers/clk/tegra/clk-pll.c | 178 +++++++++++++++++------------
> drivers/clk/tegra/clk-tegra20.c | 144 ++++++++++++------------
> drivers/clk/tegra/clk-tegra30.c | 234 +++++++++++++++++++-------------------
> 3 files changed, 294 insertions(+), 262 deletions(-)
>
> diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
> index 165f247..912c977 100644
> --- a/drivers/clk/tegra/clk-pll.c
> +++ b/drivers/clk/tegra/clk-pll.c
> @@ -1,5 +1,5 @@
> /*
> - * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
> + * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
> *
> * This program is free software; you can redistribute it and/or modify it
> * under the terms and conditions of the GNU General Public License,
> @@ -113,20 +113,23 @@ static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
> pll_writel_misc(val, pll);
> }
>
> -static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll,
> - void __iomem *lock_addr, u32 lock_bit_idx)
> +static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll)
> {
> int i;
> - u32 val;
> + u32 val, lock_bit;
> + void __iomem *lock_addr;
>
> if (!(pll->flags & TEGRA_PLL_USE_LOCK)) {
> udelay(pll->params->lock_delay);
> return 0;
> }
>
> + lock_addr = pll->clk_base + pll->params->base_reg;
This will not work for PLLE. Lock bit for PLLE is in misc register.
> + lock_bit = BIT(pll->params->lock_bit_idx);
> +
> for (i = 0; i < pll->params->lock_delay; i++) {
> val = readl_relaxed(lock_addr);
> - if (val & BIT(lock_bit_idx)) {
> + if (val & lock_bit) {
Need to change the lock bit idx parameter for Tegra20 and Tegra30 PLLs
else this patch will break those.
> udelay(PLL_POST_LOCK_DELAY);
> return 0;
> }
> @@ -155,7 +158,7 @@ static int clk_pll_is_enabled(struct clk_hw *hw)
> return val & PLL_BASE_ENABLE ? 1 : 0;
> }
<snip>
> @@ -538,8 +570,8 @@ static int clk_plle_enable(struct clk_hw *hw)
> val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE);
> pll_writel_base(val, pll);
>
> - clk_pll_wait_for_lock(pll, pll->clk_base + pll->params->misc_reg,
> - pll->params->lock_bit_idx);
> + clk_pll_wait_for_lock(pll);
> +
> return 0;
> }
<snip>
> static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
> /* 1.7 GHz */
> - { 12000000, 1700000000, 850, 6, 1, 8},
> - { 13000000, 1700000000, 915, 7, 1, 8}, /* actual: 1699.2 MHz */
> - { 16800000, 1700000000, 708, 7, 1, 8}, /* actual: 1699.2 MHz */
> - { 19200000, 1700000000, 885, 10, 1, 8}, /* actual: 1699.2 MHz */
> - { 26000000, 1700000000, 850, 13, 1, 8},
> + { 12000000, 1700000000, 850, 6, 0, 8},
> + { 13000000, 1700000000, 915, 7, 0, 8}, /* actual: 1699.2 MHz */
> + { 16800000, 1700000000, 708, 7, 0, 8}, /* actual: 1699.2 MHz */
> + { 19200000, 1700000000, 885, 10, 0, 8}, /* actual: 1699.2 MHz */
> + { 26000000, 1700000000, 850, 13, 0, 8},
>
> /* 1.6 GHz */
> - { 12000000, 1600000000, 800, 6, 1, 8},
> - { 13000000, 1600000000, 738, 6, 1, 8}, /* actual: 1599.0 MHz */
> - { 16800000, 1600000000, 857, 9, 1, 8}, /* actual: 1599.7 MHz */
> - { 19200000, 1600000000, 500, 6, 1, 8},
> - { 26000000, 1600000000, 800, 13, 1, 8},
> + { 12000000, 1600000000, 800, 6, 0, 8},
> + { 13000000, 1600000000, 738, 6, 0, 8}, /* actual: 1599.0 MHz */
> + { 16800000, 1600000000, 857, 9, 0, 8}, /* actual: 1599.7 MHz */
> + { 19200000, 1600000000, 500, 6, 0, 8},
> + { 26000000, 1600000000, 800, 13, 0, 8},
>
> /* 1.5 GHz */
> - { 12000000, 1500000000, 750, 6, 1, 8},
> - { 13000000, 1500000000, 923, 8, 1, 8}, /* actual: 1499.8 MHz */
> - { 16800000, 1500000000, 625, 7, 1, 8},
> - { 19200000, 1500000000, 625, 8, 1, 8},
> - { 26000000, 1500000000, 750, 13, 1, 8},
> + { 12000000, 1500000000, 750, 6, 0, 8},
> + { 13000000, 1500000000, 923, 8, 0, 8}, /* actual: 1499.8 MHz */
> + { 16800000, 1500000000, 625, 7, 0, 8},
> + { 19200000, 1500000000, 625, 8, 0, 8},
> + { 26000000, 1500000000, 750, 13, 0, 8},
>
> /* 1.4 GHz */
> - { 12000000, 1400000000, 700, 6, 1, 8},
> - { 13000000, 1400000000, 969, 9, 1, 8}, /* actual: 1399.7 MHz */
> - { 16800000, 1400000000, 1000, 12, 1, 8},
> - { 19200000, 1400000000, 875, 12, 1, 8},
> - { 26000000, 1400000000, 700, 13, 1, 8},
> + { 12000000, 1400000000, 700, 6, 0, 8},
> + { 13000000, 1400000000, 969, 9, 0, 8}, /* actual: 1399.7 MHz */
> + { 16800000, 1400000000, 1000, 12, 0, 8},
> + { 19200000, 1400000000, 875, 12, 0, 8},
> + { 26000000, 1400000000, 700, 13, 0, 8},
>
> /* 1.3 GHz */
> - { 12000000, 1300000000, 975, 9, 1, 8},
> - { 13000000, 1300000000, 1000, 10, 1, 8},
> - { 16800000, 1300000000, 928, 12, 1, 8}, /* actual: 1299.2 MHz */
> - { 19200000, 1300000000, 812, 12, 1, 8}, /* actual: 1299.2 MHz */
> - { 26000000, 1300000000, 650, 13, 1, 8},
> + { 12000000, 1300000000, 975, 9, 0, 8},
> + { 13000000, 1300000000, 1000, 10, 0, 8},
> + { 16800000, 1300000000, 928, 12, 0, 8}, /* actual: 1299.2 MHz */
> + { 19200000, 1300000000, 812, 12, 0, 8}, /* actual: 1299.2 MHz */
> + { 26000000, 1300000000, 650, 13, 0, 8},
>
> /* 1.2 GHz */
> - { 12000000, 1200000000, 1000, 10, 1, 8},
> - { 13000000, 1200000000, 923, 10, 1, 8}, /* actual: 1199.9 MHz */
> - { 16800000, 1200000000, 1000, 14, 1, 8},
> - { 19200000, 1200000000, 1000, 16, 1, 8},
> - { 26000000, 1200000000, 600, 13, 1, 8},
> + { 12000000, 1200000000, 1000, 10, 0, 8},
> + { 13000000, 1200000000, 923, 10, 0, 8}, /* actual: 1199.9 MHz */
> + { 16800000, 1200000000, 1000, 14, 0, 8},
> + { 19200000, 1200000000, 1000, 16, 0, 8},
> + { 26000000, 1200000000, 600, 13, 0, 8},
>
> /* 1.1 GHz */
> - { 12000000, 1100000000, 825, 9, 1, 8},
> - { 13000000, 1100000000, 846, 10, 1, 8}, /* actual: 1099.8 MHz */
> - { 16800000, 1100000000, 982, 15, 1, 8}, /* actual: 1099.8 MHz */
> - { 19200000, 1100000000, 859, 15, 1, 8}, /* actual: 1099.5 MHz */
> - { 26000000, 1100000000, 550, 13, 1, 8},
> + { 12000000, 1100000000, 825, 9, 0, 8},
> + { 13000000, 1100000000, 846, 10, 0, 8}, /* actual: 1099.8 MHz */
> + { 16800000, 1100000000, 982, 15, 0, 8}, /* actual: 1099.8 MHz */
> + { 19200000, 1100000000, 859, 15, 0, 8}, /* actual: 1099.5 MHz */
> + { 26000000, 1100000000, 550, 13, 0, 8},
>
> /* 1 GHz */
> - { 12000000, 1000000000, 1000, 12, 1, 8},
> - { 13000000, 1000000000, 1000, 13, 1, 8},
> - { 16800000, 1000000000, 833, 14, 1, 8}, /* actual: 999.6 MHz */
> - { 19200000, 1000000000, 625, 12, 1, 8},
> - { 26000000, 1000000000, 1000, 26, 1, 8},
> + { 12000000, 1000000000, 1000, 12, 0, 8},
> + { 13000000, 1000000000, 1000, 13, 0, 8},
> + { 16800000, 1000000000, 833, 14, 0, 8}, /* actual: 999.6 MHz */
> + { 19200000, 1000000000, 625, 12, 0, 8},
> + { 26000000, 1000000000, 1000, 26, 0, 8},
>
> { 0, 0, 0, 0, 0, 0 },
> };
>
^ permalink raw reply
* [PATCH v5 02/10] clk: tegra: Add TEGRA_PLL_BYPASS flag
From: Prashant Gaikwad @ 2013-02-04 6:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359713962-16822-3-git-send-email-pdeschrijver@nvidia.com>
On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:
> Not all PLLs in Tegra114 have a bypass bit. Adapt the common code to only use
> this bit when available.
>
> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> ---
Looks good to me.
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
> drivers/clk/tegra/clk-pll.c | 15 ++++++++++-----
> drivers/clk/tegra/clk.h | 8 +++++---
> 2 files changed, 15 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
> index 912c977..3c3a25e 100644
> --- a/drivers/clk/tegra/clk-pll.c
> +++ b/drivers/clk/tegra/clk-pll.c
> @@ -166,7 +166,8 @@ static void _clk_pll_enable(struct clk_hw *hw)
> clk_pll_enable_lock(pll);
>
> val = pll_readl_base(pll);
> - val &= ~PLL_BASE_BYPASS;
> + if (pll->flags & TEGRA_PLL_BYPASS)
> + val &= ~PLL_BASE_BYPASS;
> val |= PLL_BASE_ENABLE;
> pll_writel_base(val, pll);
>
> @@ -183,7 +184,9 @@ static void _clk_pll_disable(struct clk_hw *hw)
> u32 val;
>
> val = pll_readl_base(pll);
> - val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
> + if (pll->flags & TEGRA_PLL_BYPASS)
> + val &= ~PLL_BASE_BYPASS;
> + val &= ~PLL_BASE_ENABLE;
> pll_writel_base(val, pll);
>
> if (pll->flags & TEGRA_PLLM) {
> @@ -454,7 +457,7 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
>
> val = pll_readl_base(pll);
>
> - if (val & PLL_BASE_BYPASS)
> + if ((pll->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS))
> return parent_rate;
>
> if ((pll->flags & TEGRA_PLL_FIXED) && !(val & PLL_BASE_OVERRIDE)) {
> @@ -660,9 +663,10 @@ static struct clk *_tegra_clk_register_pll(const char *name,
> struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
> void __iomem *clk_base, void __iomem *pmc,
> unsigned long flags, unsigned long fixed_rate,
> - struct tegra_clk_pll_params *pll_params, u8 pll_flags,
> + struct tegra_clk_pll_params *pll_params, u32 pll_flags,
> struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock)
> {
> + pll_flags |= TEGRA_PLL_BYPASS;
> return _tegra_clk_register_pll(name, parent_name, clk_base, pmc,
> flags, fixed_rate, pll_params, pll_flags, freq_table,
> lock, &tegra_clk_pll_ops);
> @@ -671,9 +675,10 @@ struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
> struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
> void __iomem *clk_base, void __iomem *pmc,
> unsigned long flags, unsigned long fixed_rate,
> - struct tegra_clk_pll_params *pll_params, u8 pll_flags,
> + struct tegra_clk_pll_params *pll_params, u32 pll_flags,
> struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock)
> {
> + pll_flags |= TEGRA_PLL_BYPASS;
> return _tegra_clk_register_pll(name, parent_name, clk_base, pmc,
> flags, fixed_rate, pll_params, pll_flags, freq_table,
> lock, &tegra_clk_plle_ops);
> diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
> index a09d7dc..3cff1df 100644
> --- a/drivers/clk/tegra/clk.h
> +++ b/drivers/clk/tegra/clk.h
> @@ -182,12 +182,13 @@ struct tegra_clk_pll_params {
> * TEGRA_PLL_FIXED - We are not supposed to change output frequency
> * of some plls.
> * TEGRA_PLLE_CONFIGURE - Configure PLLE when enabling.
> + * TEGRA_PLL_BYPASS - PLL has bypass bit
> */
> struct tegra_clk_pll {
> struct clk_hw hw;
> void __iomem *clk_base;
> void __iomem *pmc;
> - u8 flags;
> + u32 flags;
> unsigned long fixed_rate;
> spinlock_t *lock;
> u8 divn_shift;
> @@ -210,18 +211,19 @@ struct tegra_clk_pll {
> #define TEGRA_PLLM BIT(5)
> #define TEGRA_PLL_FIXED BIT(6)
> #define TEGRA_PLLE_CONFIGURE BIT(7)
> +#define TEGRA_PLL_BYPASS BIT(8)
>
> extern const struct clk_ops tegra_clk_pll_ops;
> extern const struct clk_ops tegra_clk_plle_ops;
> struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
> void __iomem *clk_base, void __iomem *pmc,
> unsigned long flags, unsigned long fixed_rate,
> - struct tegra_clk_pll_params *pll_params, u8 pll_flags,
> + struct tegra_clk_pll_params *pll_params, u32 pll_flags,
> struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock);
> struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
> void __iomem *clk_base, void __iomem *pmc,
> unsigned long flags, unsigned long fixed_rate,
> - struct tegra_clk_pll_params *pll_params, u8 pll_flags,
> + struct tegra_clk_pll_params *pll_params, u32 pll_flags,
> struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock);
>
> /**
^ permalink raw reply
* [PATCH] rtc: rtc-mv: Add support for clk to avoid lockups
From: Jason Gunthorpe @ 2013-02-04 6:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130203111415.GE27791@lunn.ch>
On Sun, Feb 03, 2013 at 12:14:15PM +0100, Andrew Lunn wrote:
> > > + pdata->clk = devm_clk_get(&pdev->dev, NULL);
> > > + /* Not all SoCs require a clock.*/
> > > + if (!IS_ERR(pdata->clk))
> > > + clk_prepare_enable(pdata->clk);
> > > +
> >
> > There are already I/O accesses to the RTC above this. Thus, you
> > probably need to move this up.
>
> Doh!
>
> I was trying to keep the cleanup on error simple....
Why is this stuff in the drivers anyhow? All the other kernel power
management seems to be done by the device core prior to probing the
device, why is clk different?
Jason
^ permalink raw reply
* [PATCH v5 03/10] clk: tegra: Add PLL post divider table
From: Prashant Gaikwad @ 2013-02-04 6:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359713962-16822-4-git-send-email-pdeschrijver@nvidia.com>
On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:
> Some PLLs in Tegra114 don't use a power of 2 mapping for the post divider.
> Introduce a table based approach and switch PLLU to it.
>
> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> ---
Looks good to me.
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
> drivers/clk/tegra/clk-pll.c | 38 ++++++++++++++++++++++++++++++++------
> drivers/clk/tegra/clk-tegra20.c | 7 +++++++
> drivers/clk/tegra/clk-tegra30.c | 7 +++++++
> drivers/clk/tegra/clk.h | 13 +++++++++++++
> 4 files changed, 59 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
> index 3c3a25e..87d2f34 100644
> --- a/drivers/clk/tegra/clk-pll.c
> +++ b/drivers/clk/tegra/clk-pll.c
> @@ -258,6 +258,7 @@ static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
> unsigned long rate, unsigned long parent_rate)
> {
> struct tegra_clk_pll *pll = to_clk_pll(hw);
> + struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
> unsigned long cfreq;
> u32 p_div = 0;
>
> @@ -291,7 +292,6 @@ static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
> cfg->output_rate <<= 1)
> p_div++;
>
> - cfg->p = p_div;
> cfg->m = parent_rate / cfreq;
> cfg->n = cfg->output_rate / cfreq;
> cfg->cpcon = OUT_OF_TABLE_CPCON;
> @@ -304,8 +304,19 @@ static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
> return -EINVAL;
> }
>
> - if (pll->flags & TEGRA_PLLU)
> - cfg->p ^= 1;
> + if (p_tohw) {
> + p_div = 1 << p_div;
> + while (p_tohw->pdiv) {
> + if (p_div <= p_tohw->pdiv) {
> + cfg->p = p_tohw->hw_val;
> + break;
> + }
> + p_tohw++;
> + }
> + if (!p_tohw->pdiv)
> + return -EINVAL;
> + } else
> + cfg->p = p_div;
>
> return 0;
> }
> @@ -452,8 +463,10 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
> {
> struct tegra_clk_pll *pll = to_clk_pll(hw);
> struct tegra_clk_pll_freq_table cfg;
> + struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
> u32 val;
> u64 rate = parent_rate;
> + int pdiv;
>
> val = pll_readl_base(pll);
>
> @@ -472,10 +485,23 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
>
> _get_pll_mnp(pll, &cfg);
>
> - if (pll->flags & TEGRA_PLLU)
> - cfg.p ^= 1;
> + if (p_tohw) {
> + while (p_tohw->pdiv) {
> + if (cfg.p == p_tohw->hw_val) {
> + pdiv = p_tohw->pdiv;
> + break;
> + }
> + p_tohw++;
> + }
> +
> + if (!p_tohw->pdiv) {
> + WARN_ON(1);
> + pdiv = 1;
> + }
> + } else
> + pdiv = 1 << cfg.p;
>
> - cfg.m *= 1 << cfg.p;
> + cfg.m *= pdiv;
>
> rate *= cfg.n;
> do_div(rate, cfg.m);
> diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
> index 30bd3fd..54c6777 100644
> --- a/drivers/clk/tegra/clk-tegra20.c
> +++ b/drivers/clk/tegra/clk-tegra20.c
> @@ -440,6 +440,12 @@ static struct tegra_clk_pll_params pll_d_params = {
> .lock_delay = 1000,
> };
>
> +static struct pdiv_map pllu_p[] = {
> + { .pdiv = 1, .hw_val = 1 },
> + { .pdiv = 2, .hw_val = 0 },
> + { .pdiv = 0, .hw_val = 0 },
> +};
> +
> static struct tegra_clk_pll_params pll_u_params = {
> .input_min = 2000000,
> .input_max = 40000000,
> @@ -452,6 +458,7 @@ static struct tegra_clk_pll_params pll_u_params = {
> .lock_bit_idx = PLL_BASE_LOCK,
> .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
> .lock_delay = 1000,
> + .pdiv_tohw = pllu_p,
> };
>
> static struct tegra_clk_pll_params pll_x_params = {
> diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
> index 28a2997..078f9b8 100644
> --- a/drivers/clk/tegra/clk-tegra30.c
> +++ b/drivers/clk/tegra/clk-tegra30.c
> @@ -466,6 +466,12 @@ static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
> { 0, 0, 0, 0, 0, 0 },
> };
>
> +static struct pdiv_map pllu_p[] = {
> + { .pdiv = 1, .hw_val = 1 },
> + { .pdiv = 2, .hw_val = 0 },
> + { .pdiv = 0, .hw_val = 0 },
> +};
> +
> static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
> { 12000000, 480000000, 960, 12, 0, 12},
> { 13000000, 480000000, 960, 13, 0, 12},
> @@ -639,6 +645,7 @@ static struct tegra_clk_pll_params pll_u_params = {
> .lock_bit_idx = PLL_BASE_LOCK,
> .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
> .lock_delay = 1000,
> + .pdiv_tohw = pllu_p,
> };
>
> static struct tegra_clk_pll_params pll_x_params = {
> diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
> index 3cff1df..1b9cbcd 100644
> --- a/drivers/clk/tegra/clk.h
> +++ b/drivers/clk/tegra/clk.h
> @@ -117,6 +117,17 @@ struct tegra_clk_pll_freq_table {
> };
>
> /**
> + * struct pdiv_map - map post divider to hw value
> + *
> + * @pdiv: post divider
> + * @hw_val: value to be written to the PLL hw
> + */
> +struct pdiv_map {
> + u8 pdiv;
> + u8 hw_val;
> +};
> +
> +/**
> * struct clk_pll_params - PLL parameters
> *
> * @input_min: Minimum input frequency
> @@ -146,6 +157,8 @@ struct tegra_clk_pll_params {
> u32 lock_bit_idx;
> u32 lock_enable_bit_idx;
> int lock_delay;
> + int max_p;
> + struct pdiv_map *pdiv_tohw;
> };
>
> /**
>
^ permalink raw reply
* [PATCH 1/1] net: fec: fix miss init spinlock
From: Frank Li @ 2013-02-04 6:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130204.002410.508273179967651174.davem@davemloft.net>
>>> This breaks the build, tmreg_lock is only present in certain
>>> configurations.
>>
>> No, FEC have changed to check dramatically instead of static config.
>> You can look fec.h. tmreg_lock is always defined.
>
> Not in the 'net' tree or you don't want this bug fixed there at all?
Sorry, I forget mask tree.
This patch is for net-next.
best regards
Frank Li
^ permalink raw reply
* [PATCH v5 05/10] clk: tegra: Add flags to tegra_clk_periph()
From: Prashant Gaikwad @ 2013-02-04 6:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359713962-16822-6-git-send-email-pdeschrijver@nvidia.com>
On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:
> We will need some tegra peripheral clocks with the CLK_IGNORE_UNUSED flag,
> most notably mselect, which is a bridge between AXI and most peripherals.
>
> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> ---
Looks good to me.
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
> drivers/clk/tegra/clk-periph.c | 11 ++++++-----
> drivers/clk/tegra/clk-tegra20.c | 2 +-
> drivers/clk/tegra/clk-tegra30.c | 2 +-
> drivers/clk/tegra/clk.h | 9 ++++++---
> 4 files changed, 14 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/clk/tegra/clk-periph.c b/drivers/clk/tegra/clk-periph.c
> index 788486e..067abb3 100644
> --- a/drivers/clk/tegra/clk-periph.c
> +++ b/drivers/clk/tegra/clk-periph.c
> @@ -170,14 +170,15 @@ const struct clk_ops tegra_clk_periph_nodiv_ops = {
> static struct clk *_tegra_clk_register_periph(const char *name,
> const char **parent_names, int num_parents,
> struct tegra_clk_periph *periph,
> - void __iomem *clk_base, u32 offset, bool div)
> + void __iomem *clk_base, u32 offset, bool div,
> + unsigned long flags)
> {
> struct clk *clk;
> struct clk_init_data init;
>
> init.name = name;
> init.ops = div ? &tegra_clk_periph_ops : &tegra_clk_periph_nodiv_ops;
> - init.flags = div ? 0 : CLK_SET_RATE_PARENT;
> + init.flags = flags;
> init.parent_names = parent_names;
> init.num_parents = num_parents;
>
> @@ -202,10 +203,10 @@ static struct clk *_tegra_clk_register_periph(const char *name,
> struct clk *tegra_clk_register_periph(const char *name,
> const char **parent_names, int num_parents,
> struct tegra_clk_periph *periph, void __iomem *clk_base,
> - u32 offset)
> + u32 offset, unsigned long flags)
> {
> return _tegra_clk_register_periph(name, parent_names, num_parents,
> - periph, clk_base, offset, true);
> + periph, clk_base, offset, true, flags);
> }
>
> struct clk *tegra_clk_register_periph_nodiv(const char *name,
> @@ -214,5 +215,5 @@ struct clk *tegra_clk_register_periph_nodiv(const char *name,
> u32 offset)
> {
> return _tegra_clk_register_periph(name, parent_names, num_parents,
> - periph, clk_base, offset, false);
> + periph, clk_base, offset, false, CLK_SET_RATE_PARENT);
> }
> diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
> index 54c6777..870349e 100644
> --- a/drivers/clk/tegra/clk-tegra20.c
> +++ b/drivers/clk/tegra/clk-tegra20.c
> @@ -1048,7 +1048,7 @@ static void __init tegra20_periph_clk_init(void)
> data = &tegra_periph_clk_list[i];
> clk = tegra_clk_register_periph(data->name, data->parent_names,
> data->num_parents, &data->periph,
> - clk_base, data->offset);
> + clk_base, data->offset, data->flags);
> clk_register_clkdev(clk, data->con_id, data->dev_id);
> clks[data->clk_id] = clk;
> }
> diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
> index 078f9b8..126747b 100644
> --- a/drivers/clk/tegra/clk-tegra30.c
> +++ b/drivers/clk/tegra/clk-tegra30.c
> @@ -1665,7 +1665,7 @@ static void __init tegra30_periph_clk_init(void)
> data = &tegra_periph_clk_list[i];
> clk = tegra_clk_register_periph(data->name, data->parent_names,
> data->num_parents, &data->periph,
> - clk_base, data->offset);
> + clk_base, data->offset, data->flags);
> clk_register_clkdev(clk, data->con_id, data->dev_id);
> clks[data->clk_id] = clk;
> }
> diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
> index 4d0f556..79f5e2a 100644
> --- a/drivers/clk/tegra/clk.h
> +++ b/drivers/clk/tegra/clk.h
> @@ -411,7 +411,7 @@ extern const struct clk_ops tegra_clk_periph_ops;
> struct clk *tegra_clk_register_periph(const char *name,
> const char **parent_names, int num_parents,
> struct tegra_clk_periph *periph, void __iomem *clk_base,
> - u32 offset);
> + u32 offset, unsigned long flags);
> struct clk *tegra_clk_register_periph_nodiv(const char *name,
> const char **parent_names, int num_parents,
> struct tegra_clk_periph *periph, void __iomem *clk_base,
> @@ -454,12 +454,14 @@ struct tegra_periph_init_data {
> u32 offset;
> const char *con_id;
> const char *dev_id;
> + unsigned long flags;
> };
>
> #define TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\
> _mux_shift, _mux_mask, _mux_flags, _div_shift, \
> _div_width, _div_frac_width, _div_flags, _regs, \
> - _clk_num, _enb_refcnt, _gate_flags, _clk_id, _table) \
> + _clk_num, _enb_refcnt, _gate_flags, _clk_id, _table,\
> + _flags) \
> { \
> .name = _name, \
> .clk_id = _clk_id, \
> @@ -474,6 +476,7 @@ struct tegra_periph_init_data {
> .offset = _offset, \
> .con_id = _con_id, \
> .dev_id = _dev_id, \
> + .flags = _flags \
> }
>
> #define TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parent_names, _offset,\
> @@ -484,7 +487,7 @@ struct tegra_periph_init_data {
> _mux_shift, BIT(_mux_width) - 1, _mux_flags, \
> _div_shift, _div_width, _div_frac_width, _div_flags, \
> _regs, _clk_num, _enb_refcnt, _gate_flags, _clk_id,\
> - NULL)
> + NULL, 0)
>
> /**
> * struct clk_super_mux - super clock
>
^ permalink raw reply
* [PATCH v5 04/10] clk: tegra: Add new fields and PLL types for Tegra114
From: Prashant Gaikwad @ 2013-02-04 6:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <510C1A2E.5010408@nvidia.com>
On Saturday 02 February 2013 01:10 AM, Rhyland Klein wrote:
> On 2/1/2013 5:18 AM, Peter De Schrijver wrote:
>> Tegra114 introduces new PLL types. This requires new clocktypes as well
>> as some new fields in the pll structure.
>>
>> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
>> ---
>> drivers/clk/tegra/clk-pll.c | 719 +++++++++++++++++++++++++++++++++++++++++++
>> drivers/clk/tegra/clk.h | 47 +++
>> 2 files changed, 766 insertions(+), 0 deletions(-)
>>
>> diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
>> index 87d2f34..50114b7 100644
>> --- a/drivers/clk/tegra/clk-pll.c
>> +++ b/drivers/clk/tegra/clk-pll.c
>> [snip]
>> +struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
>> + void __iomem *clk_base, void __iomem *pmc,
>> + unsigned long flags, unsigned long fixed_rate,
>> + struct tegra_clk_pll_params *pll_params,
>> + u32 pll_flags,
>> + struct tegra_clk_pll_freq_table *freq_table,
>> + spinlock_t *lock)
>> +{
>> + if (!pll_params->pdiv_tohw)
>> + return -EINVAL;
>> +
> This will cause the following warning:
> warning: return makes pointer from integer without a cast
>
> Same with occurrences in tegra_clk_register_pllm and
> tegra_clk_register_pllc.
>
> Should this instead be returning NULL?
return ERR_PTR(-EINVAL)
>
> -rhyland
>
^ permalink raw reply
* [PATCH v5 06/10] clk: tegra: Workaround for Tegra114 MSENC problem
From: Prashant Gaikwad @ 2013-02-04 6:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359713962-16822-7-git-send-email-pdeschrijver@nvidia.com>
On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:
> Workaround a hardware bug in MSENC during clock enable.
>
> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> ---
> drivers/clk/tegra/clk-periph-gate.c | 9 +++++++++
> drivers/clk/tegra/clk.h | 1 +
> 2 files changed, 10 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/clk/tegra/clk-periph-gate.c b/drivers/clk/tegra/clk-periph-gate.c
> index 6dd5332..c9083fb 100644
> --- a/drivers/clk/tegra/clk-periph-gate.c
> +++ b/drivers/clk/tegra/clk-periph-gate.c
> @@ -43,6 +43,8 @@ static DEFINE_SPINLOCK(periph_ref_lock);
>
> #define periph_clk_to_bit(periph) (1 << (gate->clk_num % 32))
>
> +#define LVL2_CLK_GATE_OVRE 0x554
> +
> /* Peripheral gate clock ops */
> static int clk_periph_is_enabled(struct clk_hw *hw)
> {
> @@ -83,6 +85,13 @@ static int clk_periph_enable(struct clk_hw *hw)
> }
> }
>
> + if (gate->flags & TEGRA_PERIPH_WAR_1005168) {
> + writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE);
> + writel_relaxed(BIT(22), gate->clk_base + LVL2_CLK_GATE_OVRE);
> + udelay(1);
> + writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE);
> + }
> +
> spin_unlock_irqrestore(&periph_ref_lock, flags);
>
> return 0;
> diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
> index 79f5e2a..8756d9f 100644
> --- a/drivers/clk/tegra/clk.h
> +++ b/drivers/clk/tegra/clk.h
> @@ -371,6 +371,7 @@ struct tegra_clk_periph_gate {
> #define TEGRA_PERIPH_NO_RESET BIT(0)
> #define TEGRA_PERIPH_MANUAL_RESET BIT(1)
> #define TEGRA_PERIPH_ON_APB BIT(2)
> +#define TEGRA_PERIPH_WAR_1005168 BIT(3)
>
Comment for this flag, otherwise
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
> void tegra_periph_reset(struct tegra_clk_periph_gate *gate, bool assert);
> extern const struct clk_ops tegra_clk_periph_gate_ops;
>
^ permalink raw reply
* [PATCH v5 08/10] ARM: dt: Add references to tegra_car clocks
From: Prashant Gaikwad @ 2013-02-04 6:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359713962-16822-9-git-send-email-pdeschrijver@nvidia.com>
On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:
> Add references to tegra_car clocks for the basic device nodes.
>
> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> ---
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
> arch/arm/boot/dts/tegra114.dtsi | 7 ++++++-
> 1 files changed, 6 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
> index 96a8235..1dec620 100644
> --- a/arch/arm/boot/dts/tegra114.dtsi
> +++ b/arch/arm/boot/dts/tegra114.dtsi
> @@ -27,7 +27,7 @@
> };
>
> tegra_car: clock {
> - compatible = "nvidia,tegra114-car, nvidia,tegra30-car";
> + compatible = "nvidia,tegra114-car";
> reg = <0x60006000 0x1000>;
> #clock-cells = <1>;
> };
> @@ -43,6 +43,7 @@
> reg-shift = <2>;
> interrupts = <0 36 0x04>;
> status = "disabled";
> + clocks = <&tegra_car 6>;
> };
>
> serial at 70006040 {
> @@ -51,6 +52,7 @@
> reg-shift = <2>;
> interrupts = <0 37 0x04>;
> status = "disabled";
> + clocks = <&tegra_car 192>;
> };
>
> serial at 70006200 {
> @@ -59,6 +61,7 @@
> reg-shift = <2>;
> interrupts = <0 46 0x04>;
> status = "disabled";
> + clocks = <&tegra_car 55>;
> };
>
> serial at 70006300 {
> @@ -67,12 +70,14 @@
> reg-shift = <2>;
> interrupts = <0 90 0x04>;
> status = "disabled";
> + clocks = <&tegra_car 65>;
> };
>
> rtc {
> compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
> reg = <0x7000e000 0x100>;
> interrupts = <0 2 0x04>;
> + clocks = <&tegra_car 4>;
> };
>
> pmc {
>
^ permalink raw reply
* [PATCH 05/11 v2] ARM: nomadik: add FSMC NAND
From: Artem Bityutskiy @ 2013-02-04 7:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358607204-24264-1-git-send-email-linus.walleij@linaro.org>
On Sat, 2013-01-19 at 15:53 +0100, Linus Walleij wrote:
> This adds the FSMC NAND driver and flash partitions to the Nomadik
> device tree.
>
> The only compatible string accepted by this driver is currently
> "st,spear600-fsmc-nand" which is inappropriate for this system, so
> this patch adds the compatible value "stericsson,fsmc-nand" as
> well.
>
> Cc: linux-mtd at vger.kernel.org
> Cc: David Woodhouse <dwmw2@infradead.org>
> Cc: Artem Bityutskiy <dedekind1@gmail.com>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
> I'm requesting an ACK from the MTD maintainers to be able to apply
> this patch through the ARM SoC tree.
Acked-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
--
Best Regards,
Artem Bityutskiy
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^ permalink raw reply
* [PATCH v5 09/10] clk: tegra: Implement clocks for Tegra114
From: Prashant Gaikwad @ 2013-02-04 7:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359713962-16822-10-git-send-email-pdeschrijver@nvidia.com>
On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:
> Implement most clocks for Tegra114. The super clocks for the CPU complex
> are still missing and will be implemented in a future version.
>
> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> ---
> drivers/clk/tegra/Makefile | 1 +
> drivers/clk/tegra/clk-tegra114.c | 2002 ++++++++++++++++++++++++++++++++++++++
> 2 files changed, 2003 insertions(+), 0 deletions(-)
> create mode 100644 drivers/clk/tegra/clk-tegra114.c
>
> diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile
> index 2b41b0f..f49fac2 100644
> --- a/drivers/clk/tegra/Makefile
> +++ b/drivers/clk/tegra/Makefile
> @@ -9,3 +9,4 @@ obj-y += clk-super.o
>
> obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clk-tegra20.o
> obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += clk-tegra30.o
> +obj-$(CONFIG_ARCH_TEGRA_114_SOC) += clk-tegra114.o
> diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
> new file mode 100644
> index 0000000..f8165d2
> --- /dev/null
> +++ b/drivers/clk/tegra/clk-tegra114.c
> @@ -0,0 +1,2002 @@
> +/*
> + * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <linux/io.h>
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/clkdev.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/delay.h>
> +#include <linux/clk/tegra.h>
> +
> +#include "clk.h"
> +
> +#define RST_DEVICES_L 0x004
> +#define RST_DEVICES_H 0x008
> +#define RST_DEVICES_U 0x00C
> +#define RST_DEVICES_V 0x358
> +#define RST_DEVICES_W 0x35C
> +#define RST_DEVICES_X 0x28C
> +#define RST_DEVICES_SET_L 0x300
> +#define RST_DEVICES_CLR_L 0x304
> +#define RST_DEVICES_SET_H 0x308
> +#define RST_DEVICES_CLR_H 0x30c
> +#define RST_DEVICES_SET_U 0x310
> +#define RST_DEVICES_CLR_U 0x314
> +#define RST_DEVICES_SET_V 0x430
> +#define RST_DEVICES_CLR_V 0x434
> +#define RST_DEVICES_SET_W 0x438
> +#define RST_DEVICES_CLR_W 0x43c
> +#define RST_DEVICES_NUM 5
RST_DEVICES_SET/CLR_X?
> +
> +#define CLK_OUT_ENB_L 0x010
> +#define CLK_OUT_ENB_H 0x014
> +#define CLK_OUT_ENB_U 0x018
> +#define CLK_OUT_ENB_V 0x360
> +#define CLK_OUT_ENB_W 0x364
> +#define CLK_OUT_ENB_X 0x280
> +#define CLK_OUT_ENB_SET_L 0x320
> +#define CLK_OUT_ENB_CLR_L 0x324
> +#define CLK_OUT_ENB_SET_H 0x328
> +#define CLK_OUT_ENB_CLR_H 0x32c
> +#define CLK_OUT_ENB_SET_U 0x330
> +#define CLK_OUT_ENB_CLR_U 0x334
> +#define CLK_OUT_ENB_SET_V 0x440
> +#define CLK_OUT_ENB_CLR_V 0x444
> +#define CLK_OUT_ENB_SET_W 0x448
> +#define CLK_OUT_ENB_CLR_W 0x44c
> +#define CLK_OUT_ENB_SET_X 0x284
> +#define CLK_OUT_ENB_CLR_X 0x288
> +#define CLK_OUT_ENB_NUM 6
<snip>
> +
> + /* dsia */
> + clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0,
> + ARRAY_SIZE(mux_plld_out0_plld2_out0), 0,
> + clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock);
> + clks[dsia_mux] = clk;
> + clk = tegra_clk_register_periph_gate("dsia", "dsia_mux", 0, clk_base,
> + 0, 48, &periph_h_regs,
> + periph_clk_enb_refcnt);
> + clk_register_clkdev(clk, "dsia", "tegradc.0");
> + clks[dsia] = clk;
> +
> + /* dsib */
> + clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0,
> + ARRAY_SIZE(mux_plld_out0_plld2_out0), 0,
> + clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock);
> + clks[dsib_mux] = clk;
> + clk = tegra_clk_register_periph_gate("dsib", "dsib_mux", 0, clk_base,
> + 0, 82, &periph_u_regs,
> + periph_clk_enb_refcnt);
> + clk_register_clkdev(clk, "dsib", "tegradc.1");
> + clks[dsib] = clk;
> +
Can we use periph no div clock here for dsia and dsib?
> + /* xusb_hs_src */
> + val = readl(clk_base + CLK_SOURCE_XUSB_SS_SRC);
> + val |= BIT(25); /* always select PLLU_60M */
> + writel(val, clk_base + CLK_SOURCE_XUSB_SS_SRC);
> +
> + clk = clk_register_fixed_factor(NULL, "xusb_hs_src", "pll_u_60M", 0,
> + 1, 1);
> + clks[xusb_hs_src] = clk;
> +
With device tree we can directly use pll_u_60M, no need to register
clock with fixed factor 1.
Same comment for dis1-fixed, dsi2-fixed and mipi-cal-fast clocks.
> + /* xusb_host */
> + clk = tegra_clk_register_periph_gate("xusb_host", "xusb_host_src", 0,
> + clk_base, 0, 89, &periph_u_regs,
> + periph_clk_enb_refcnt);
> + clk_register_clkdev(clk, "tegra_xhci", "host");
> + clks[xusb_host] = clk;
> +
> + /* xusb_ss */
> + clk = tegra_clk_register_periph_gate("xusb_ss", "xusb_ss_src", 0,
> + clk_base, 0, 156, &periph_w_regs,
> + periph_clk_enb_refcnt);
> + clk_register_clkdev(clk, "tegra_xhci", "ss");
> + clks[xusb_host] = clk;
> +
> + /* xusb_dev */
> + clk = tegra_clk_register_periph_gate("xusb_dev", "xusb_dev_src", 0,
> + clk_base, 0, 95, &periph_u_regs,
> + periph_clk_enb_refcnt);
> + clk_register_clkdev(clk, "tegra_xhci", "dev");
clks[xusb_dev] = clk;
> +
> + for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
> + data = &tegra_periph_clk_list[i];
> + clk = tegra_clk_register_periph(data->name, data->parent_names,
> + data->num_parents, &data->periph,
> + clk_base, data->offset, data->flags);
> + clk_register_clkdev(clk, data->con_id, data->dev_id);
> + clks[data->clk_id] = clk;
> + }
> +
> + for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) {
> + data = &tegra_periph_nodiv_clk_list[i];
> + clk = tegra_clk_register_periph_nodiv(data->name,
> + data->parent_names, data->num_parents,
> + &data->periph, clk_base, data->offset);
> + clk_register_clkdev(clk, data->con_id, data->dev_id);
> + clks[data->clk_id] = clk;
> + }
> +}
> +
> +static struct tegra_cpu_car_ops tegra114_cpu_car_ops;
> +
> +static const struct of_device_id pmc_match[] __initconst = {
> + { .compatible = "nvidia,tegra114-pmc" },
> + {},
> +};
> +
> +static __initdata struct tegra_clk_init_table init_table[] = {
> + {uartd, pll_p, 408000000, 1},
> + {clk_max, clk_max, 0, 0}, /* This MUST be the last entry. */
> +};
> +
> +void __init tegra114_clock_init(struct device_node *np)
> +{
> + struct device_node *node;
> + int i;
> +
> + clk_base = of_iomap(np, 0);
> + if (!clk_base) {
> + pr_err("ioremap tegra114 CAR failed\n");
> + return;
> + }
> +
> + node = of_find_matching_node(NULL, pmc_match);
> + if (!node) {
> + pr_err("Failed to find pmc node\n");
> + WARN_ON(1);
> + return;
> + }
> +
> + pmc_base = of_iomap(node, 0);
> + if (!pmc_base) {
> + pr_err("Can't map pmc registers\n");
> + WARN_ON(1);
> + return;
> + }
> +
> + if (tegra114_osc_clk_init(clk_base) < 0)
> + return;
> +
> + tegra114_fixed_clk_init(clk_base);
> + tegra114_pll_init(clk_base, pmc_base);
> + tegra114_periph_clk_init(clk_base);
> + tegra114_audio_clk_init(clk_base);
> + tegra114_pmc_clk_init(pmc_base);
> +
> + for (i = 0; i < ARRAY_SIZE(clks); i++) {
> + if (IS_ERR(clks[i])) {
> + pr_err
> + ("Tegra114 clk %d: register failed with %ld\n",
> + i, PTR_ERR(clks[i]));
> + }
> + if (!clks[i])
> + clks[i] = ERR_PTR(-EINVAL);
> + }
> +
> + clk_data.clks = clks;
> + clk_data.clk_num = ARRAY_SIZE(clks);
> + of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
> +
> + tegra_init_from_table(init_table, clks, clk_max);
> +
> + tegra_cpu_car_ops = &tegra114_cpu_car_ops;
> +}
>
^ permalink raw reply
* [PATCH v5 10/10] clk: tegra: devicetree match for nvidia, tegra114-car
From: Prashant Gaikwad @ 2013-02-04 7:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359713962-16822-11-git-send-email-pdeschrijver@nvidia.com>
On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:
> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> ---
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
> drivers/clk/tegra/clk.c | 1 +
> drivers/clk/tegra/clk.h | 7 +++++++
> 2 files changed, 8 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c
> index a603b9a..a328365 100644
> --- a/drivers/clk/tegra/clk.c
> +++ b/drivers/clk/tegra/clk.c
> @@ -76,6 +76,7 @@ void __init tegra_init_from_table(struct tegra_clk_init_table *tbl,
> static const struct of_device_id tegra_dt_clk_match[] = {
> { .compatible = "nvidia,tegra20-car", .data = tegra20_clock_init },
> { .compatible = "nvidia,tegra30-car", .data = tegra30_clock_init },
> + { .compatible = "nvidia,tegra114-car", .data = tegra114_clock_init },
> { }
> };
>
> diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
> index 8756d9f..8097850 100644
> --- a/drivers/clk/tegra/clk.h
> +++ b/drivers/clk/tegra/clk.h
> @@ -576,4 +576,11 @@ void tegra30_clock_init(struct device_node *np);
> static inline void tegra30_clock_init(struct device_node *np) {}
> #endif /* CONFIG_ARCH_TEGRA_3x_SOC */
>
> +#ifdef CONFIG_ARCH_TEGRA_114_SOC
> +void tegra114_clock_init(struct device_node *np);
> +#else
> +static inline void tegra114_clock_init(struct device_node *np) {}
> +#endif /* CONFIG_ARCH_TEGRA114_SOC */
> +
> +
> #endif /* TEGRA_CLK_H */
>
^ permalink raw reply
* [PATCH] mtd: gpmi: fix a dereferencing freed memory error
From: Artem Bityutskiy @ 2013-02-04 8:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1358929253-29143-1-git-send-email-b32955@freescale.com>
On Wed, 2013-01-23 at 16:20 +0800, Huang Shijie wrote:
> The patch "490e280 mtd: gpmi-nand: Convert to module_platform_driver()"
> introduced a "dereferencing freed memory" error.
>
> This patch fixes it.
>
> Signed-off-by: Huang Shijie <b32955@freescale.com>
Pushed to l2-mtd.git, thanks!
--
Best Regards,
Artem Bityutskiy
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^ permalink raw reply
* [PATCH V2] clk: Add composite clock type
From: Prashant Gaikwad @ 2013-02-04 8:11 UTC (permalink / raw)
To: linux-arm-kernel
Not all clocks are required to be decomposed into basic clock
types but at the same time want to use the functionality
provided by these basic clock types instead of duplicating.
For example, Tegra SoC has ~100 clocks which can be decomposed
into Mux -> Div -> Gate clock types making the clock count to
~300. Also, parent change operation can not be performed on gate
clock which forces to use mux clock in driver if want to change
the parent.
Instead aggregate the basic clock types functionality into one
clock and just use this clock for all operations. This clock
type re-uses the functionality of basic clock types and not
limited to basic clock types but any hardware-specific
implementation.
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
---
Changes from V1:
- 2nd patch dropped as the concept is acked by Mike.
- Fixed comments from Stephen.
---
drivers/clk/Makefile | 1 +
drivers/clk/clk-composite.c | 208 ++++++++++++++++++++++++++++++++++++++++++
include/linux/clk-provider.h | 30 ++++++
3 files changed, 239 insertions(+), 0 deletions(-)
create mode 100644 drivers/clk/clk-composite.c
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index ce77077..2287848 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_COMMON_CLK) += clk-fixed-factor.o
obj-$(CONFIG_COMMON_CLK) += clk-fixed-rate.o
obj-$(CONFIG_COMMON_CLK) += clk-gate.o
obj-$(CONFIG_COMMON_CLK) += clk-mux.o
+obj-$(CONFIG_COMMON_CLK) += clk-composite.o
# SoCs specific
obj-$(CONFIG_ARCH_BCM2835) += clk-bcm2835.o
diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
new file mode 100644
index 0000000..5a6587f
--- /dev/null
+++ b/drivers/clk/clk-composite.c
@@ -0,0 +1,208 @@
+/*
+ * Copyright (c) 2013 NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+
+#define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
+
+static u8 clk_composite_get_parent(struct clk_hw *hw)
+{
+ struct clk_composite *composite = to_clk_composite(hw);
+ const struct clk_ops *mux_ops = composite->mux_ops;
+ struct clk_hw *mux_hw = composite->mux_hw;
+
+ mux_hw->clk = hw->clk;
+
+ return mux_ops->get_parent(mux_hw);
+}
+
+static int clk_composite_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct clk_composite *composite = to_clk_composite(hw);
+ const struct clk_ops *mux_ops = composite->mux_ops;
+ struct clk_hw *mux_hw = composite->mux_hw;
+
+ mux_hw->clk = hw->clk;
+
+ return mux_ops->set_parent(mux_hw, index);
+}
+
+static unsigned long clk_composite_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_composite *composite = to_clk_composite(hw);
+ const struct clk_ops *div_ops = composite->div_ops;
+ struct clk_hw *div_hw = composite->div_hw;
+
+ div_hw->clk = hw->clk;
+
+ return div_ops->recalc_rate(div_hw, parent_rate);
+}
+
+static long clk_composite_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ struct clk_composite *composite = to_clk_composite(hw);
+ const struct clk_ops *div_ops = composite->div_ops;
+ struct clk_hw *div_hw = composite->div_hw;
+
+ div_hw->clk = hw->clk;
+
+ return div_ops->round_rate(div_hw, rate, prate);
+}
+
+static int clk_composite_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_composite *composite = to_clk_composite(hw);
+ const struct clk_ops *div_ops = composite->div_ops;
+ struct clk_hw *div_hw = composite->div_hw;
+
+ div_hw->clk = hw->clk;
+
+ return div_ops->set_rate(div_hw, rate, parent_rate);
+}
+
+static int clk_composite_is_enabled(struct clk_hw *hw)
+{
+ struct clk_composite *composite = to_clk_composite(hw);
+ const struct clk_ops *gate_ops = composite->gate_ops;
+ struct clk_hw *gate_hw = composite->gate_hw;
+
+ gate_hw->clk = hw->clk;
+
+ return gate_ops->is_enabled(gate_hw);
+}
+
+static int clk_composite_enable(struct clk_hw *hw)
+{
+ struct clk_composite *composite = to_clk_composite(hw);
+ const struct clk_ops *gate_ops = composite->gate_ops;
+ struct clk_hw *gate_hw = composite->gate_hw;
+
+ gate_hw->clk = hw->clk;
+
+ return gate_ops->enable(gate_hw);
+}
+
+static void clk_composite_disable(struct clk_hw *hw)
+{
+ struct clk_composite *composite = to_clk_composite(hw);
+ const struct clk_ops *gate_ops = composite->gate_ops;
+ struct clk_hw *gate_hw = composite->gate_hw;
+
+ gate_hw->clk = hw->clk;
+
+ gate_ops->disable(gate_hw);
+}
+
+struct clk *clk_register_composite(struct device *dev, const char *name,
+ const char **parent_names, int num_parents,
+ struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
+ struct clk_hw *div_hw, const struct clk_ops *div_ops,
+ struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
+ unsigned long flags)
+{
+ struct clk *clk;
+ struct clk_init_data init;
+ struct clk_composite *composite;
+ struct clk_ops *clk_composite_ops;
+
+ composite = kzalloc(sizeof(*composite), GFP_KERNEL);
+ if (!composite) {
+ pr_err("%s: could not allocate composite clk\n", __func__);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ init.name = name;
+ init.flags = flags | CLK_IS_BASIC;
+ init.parent_names = parent_names;
+ init.num_parents = num_parents;
+
+ /* allocate the clock ops */
+ clk_composite_ops = kzalloc(sizeof(*clk_composite_ops), GFP_KERNEL);
+ if (!clk_composite_ops) {
+ pr_err("%s: could not allocate clk ops\n", __func__);
+ kfree(composite);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ if (mux_hw && mux_ops) {
+ if (!mux_ops->get_parent || !mux_ops->set_parent) {
+ clk = ERR_PTR(-EINVAL);
+ goto err;
+ }
+
+ composite->mux_hw = mux_hw;
+ composite->mux_ops = mux_ops;
+ clk_composite_ops->get_parent = clk_composite_get_parent;
+ clk_composite_ops->set_parent = clk_composite_set_parent;
+ }
+
+ if (div_hw && div_ops) {
+ if (!div_ops->recalc_rate || !div_ops->round_rate ||
+ !div_ops->set_rate) {
+ clk = ERR_PTR(-EINVAL);
+ goto err;
+ }
+
+ composite->div_hw = div_hw;
+ composite->div_ops = div_ops;
+ clk_composite_ops->recalc_rate = clk_composite_recalc_rate;
+ clk_composite_ops->round_rate = clk_composite_round_rate;
+ clk_composite_ops->set_rate = clk_composite_set_rate;
+ }
+
+ if (gate_hw && gate_ops) {
+ if (!gate_ops->is_enabled || !gate_ops->enable ||
+ !gate_ops->disable) {
+ clk = ERR_PTR(-EINVAL);
+ goto err;
+ }
+
+ composite->gate_hw = gate_hw;
+ composite->gate_ops = gate_ops;
+ clk_composite_ops->is_enabled = clk_composite_is_enabled;
+ clk_composite_ops->enable = clk_composite_enable;
+ clk_composite_ops->disable = clk_composite_disable;
+ }
+
+ init.ops = clk_composite_ops;
+ composite->hw.init = &init;
+
+ clk = clk_register(dev, &composite->hw);
+ if (IS_ERR(clk))
+ goto err;
+
+ if (composite->mux_hw)
+ composite->mux_hw->clk = clk;
+
+ if (composite->div_hw)
+ composite->div_hw->clk = clk;
+
+ if (composite->gate_hw)
+ composite->gate_hw->clk = clk;
+
+ return clk;
+
+err:
+ kfree(clk_composite_ops);
+ kfree(composite);
+ return clk;
+}
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 7f197d7..f1a36aa 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -325,6 +325,36 @@ struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
const char *parent_name, unsigned long flags,
unsigned int mult, unsigned int div);
+/***
+ * struct clk_composite - aggregate clock of mux, divider and gate clocks
+ *
+ * @hw: handle between common and hardware-specific interfaces
+ * @mux_hw: handle between composite and hardware-specifix mux clock
+ * @div_hw: handle between composite and hardware-specifix divider clock
+ * @gate_hw: handle between composite and hardware-specifix gate clock
+ * @mux_ops: clock ops for mux
+ * @div_ops: clock ops for divider
+ * @gate_ops: clock ops for gate
+ */
+struct clk_composite {
+ struct clk_hw hw;
+
+ struct clk_hw *mux_hw;
+ struct clk_hw *div_hw;
+ struct clk_hw *gate_hw;
+
+ const struct clk_ops *mux_ops;
+ const struct clk_ops *div_ops;
+ const struct clk_ops *gate_ops;
+};
+
+struct clk *clk_register_composite(struct device *dev, const char *name,
+ const char **parent_names, int num_parents,
+ struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
+ struct clk_hw *div_hw, const struct clk_ops *div_ops,
+ struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
+ unsigned long flags);
+
/**
* clk_register - allocate a new clock, register it and return an opaque cookie
* @dev: device that is registering this clock
--
1.7.4.1
^ permalink raw reply related
* [GIT PULL 0/4] ARM: mvebu: changes for v3.9
From: Gregory CLEMENT @ 2013-02-04 8:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359733918.Bf7ecc0.22262@triton>
Hi Jason,
On 02/01/2013 04:51 PM, Jason Cooper wrote:
> The following changes since commit 19d23dac1b8f95e4a960fcbbb5687c33b9a2cd01:
>
> Merge branch 'fixes' into for-next
>
> are available in the git repository at:
>
> git://git.infradead.org/users/jcooper/linux.git mvebu/for-next
>
> for you to fetch changes up to 7d8a7dce24f76242daf1c469878597b8acc4f78f:
>
> Merge tag 'tags/dt_for_v3.9' into mvebu/for-next
>
> Jason Cooper (5):
> Merge tag 'tags/mvebu_fixes_for_v3.8-rc6' into mvebu/for-next
> Merge tag 'tags/cleanup_for_v3.9_round2' into mvebu/for-next
> Merge tag 'tags/drivers_for_v3.9' into mvebu/for-next
> Merge tag 'tags/boards_for_v3.9' into mvebu/for-next
> Merge tag 'tags/dt_for_v3.9' into mvebu/for-next
I didn't see anything about the USB support for Armada370/XP sent
by Ezequiel. Is there any reason to not have it? Or do you plan
to send a new pull request soon with his patch set?
Thanks,
PS: I noticed that there are a some files not related to mvebu at all
(such as the arch/parisc/... for example), but I guess it is due to some
dependencies.
>
> .../bindings/mmc/brcm,bcm2835-sdhci.txt | 18 ++
> .../devicetree/bindings/mmc/orion-sdio.txt | 17 ++
> Documentation/filesystems/f2fs.txt | 18 +-
> MAINTAINERS | 2 +-
> Makefile | 4 +-
> arch/arm/boot/dts/Makefile | 2 +
> arch/arm/boot/dts/armada-370-db.dts | 15 +
> arch/arm/boot/dts/armada-370-mirabox.dts | 10 +
> arch/arm/boot/dts/armada-370-rd.dts | 61 ++++
> arch/arm/boot/dts/armada-370-xp.dtsi | 14 +
> arch/arm/boot/dts/armada-370.dtsi | 12 +
> arch/arm/boot/dts/armada-xp-db.dts | 7 +
> arch/arm/boot/dts/armada-xp-mv78230.dtsi | 6 +
> arch/arm/boot/dts/armada-xp-mv78260.dtsi | 6 +
> arch/arm/boot/dts/armada-xp-mv78460.dtsi | 6 +
> .../arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 12 +
> arch/arm/boot/dts/armada-xp.dtsi | 2 +-
> arch/arm/boot/dts/dove-cubox.dts | 28 +-
> arch/arm/boot/dts/dove.dtsi | 2 +
> arch/arm/boot/dts/kirkwood-6282.dtsi | 17 ++
> arch/arm/boot/dts/kirkwood-dreamplug.dts | 7 +
> .../boot/dts/kirkwood-guruplug-server-plus.dts | 94 +++++++
> arch/arm/boot/dts/kirkwood-mplcec4.dts | 11 +-
> arch/arm/boot/dts/kirkwood-ns2-common.dtsi | 6 +
> arch/arm/boot/dts/kirkwood-nsa310.dts | 27 ++
> arch/arm/boot/dts/kirkwood-openblocks_a6.dts | 116 ++++++++
> arch/arm/boot/dts/kirkwood.dtsi | 8 +
> arch/arm/configs/dove_defconfig | 28 +-
> arch/arm/configs/kirkwood_defconfig | 1 +
> arch/arm/configs/mvebu_defconfig | 16 ++
> arch/arm/kernel/head.S | 5 +-
> arch/arm/kernel/hyp-stub.S | 18 +-
> arch/arm/mach-dove/Kconfig | 7 +
> arch/arm/mach-dove/Makefile | 4 +-
> arch/arm/mach-dove/board-dt.c | 102 +++++++
> arch/arm/mach-dove/common.c | 114 +-------
> arch/arm/mach-imx/clk-imx25.c | 6 +-
> arch/arm/mach-imx/clk-imx27.c | 6 +-
> arch/arm/mach-imx/clk-imx31.c | 6 +-
> arch/arm/mach-imx/clk-imx35.c | 6 +-
> arch/arm/mach-imx/clk-imx51-imx53.c | 6 +-
> arch/arm/mach-imx/devices/devices-common.h | 1 +
> .../mach-imx/devices/platform-fsl-usb2-udc.c | 15 +-
> arch/arm/mach-kirkwood/Kconfig | 7 +
> arch/arm/mach-kirkwood/Makefile | 2 +-
> arch/arm/mach-kirkwood/board-dreamplug.c | 6 -
> arch/arm/mach-kirkwood/board-dt.c | 15 +-
> arch/arm/mach-kirkwood/board-guruplug.c | 39 +++
> arch/arm/mach-kirkwood/board-ib62x0.c | 1 -
> arch/arm/mach-kirkwood/board-mplcec4.c | 8 -
> arch/arm/mach-kirkwood/board-ns2.c | 14 -
> arch/arm/mach-kirkwood/board-nsa310.c | 51 +---
> arch/arm/mach-kirkwood/board-openblocks_a6.c | 44 ---
> arch/arm/mach-kirkwood/common.c | 23 ++
> arch/arm/mach-kirkwood/common.h | 6 +
> arch/arm/mach-kirkwood/dockstar-setup.c | 1 -
> arch/arm/mach-kirkwood/include/mach/kirkwood.h | 3 +-
> arch/arm/mach-kirkwood/pcie.c | 10 +-
> arch/arm/mach-mvebu/irq-armada-370-xp.c | 72 +++++
> arch/arm/mm/dma-mapping.c | 18 +-
> arch/arm/mm/mmu.c | 2 +-
> arch/arm/plat-orion/mpp.c | 2 +-
> arch/arm/vfp/entry.S | 6 +-
> arch/arm/vfp/vfphw.S | 4 +-
> arch/arm64/include/asm/elf.h | 5 +-
> arch/ia64/kernel/ptrace.c | 27 --
> arch/m68k/include/asm/dma-mapping.h | 16 ++
> arch/m68k/include/asm/pgtable_no.h | 2 +
> arch/m68k/include/asm/unistd.h | 2 +-
> arch/m68k/include/uapi/asm/unistd.h | 1 +
> arch/m68k/kernel/syscalltable.S | 1 +
> arch/m68k/mm/init.c | 8 +-
> arch/parisc/kernel/entry.S | 18 +-
> arch/parisc/kernel/irq.c | 6 +-
> arch/parisc/kernel/ptrace.c | 2 +-
> arch/parisc/kernel/signal.c | 4 +-
> arch/parisc/math-emu/cnv_float.h | 11 +-
> arch/powerpc/kvm/emulate.c | 2 +
> arch/x86/kernel/cpu/perf_event.c | 6 -
> arch/x86/kernel/entry_32.S | 1 -
> arch/x86/kernel/step.c | 9 +-
> arch/x86/xen/smp.c | 7 -
> drivers/acpi/apei/apei-base.c | 3 +
> drivers/acpi/processor_idle.c | 4 +
> drivers/acpi/processor_perflib.c | 7 +
> drivers/ata/ahci.c | 8 +-
> drivers/ata/libahci.c | 6 +-
> drivers/ata/libata-core.c | 22 +-
> drivers/ata/libata-eh.c | 2 +-
> drivers/base/regmap/regmap-debugfs.c | 2 -
> drivers/base/regmap/regmap.c | 2 +-
> drivers/block/virtio_blk.c | 7 +-
> drivers/cpufreq/Kconfig.x86 | 2 +-
> drivers/cpufreq/acpi-cpufreq.c | 7 +
> drivers/cpufreq/cpufreq-cpu0.c | 5 +
> drivers/cpufreq/omap-cpufreq.c | 3 +
> drivers/cpuidle/Kconfig | 6 +
> drivers/cpuidle/Makefile | 1 +
> .../cpuidle/cpuidle-kirkwood.c | 45 ++-
> drivers/devfreq/devfreq.c | 5 +
> drivers/devfreq/exynos4_bus.c | 94 +++++--
> drivers/dma/imx-dma.c | 5 +-
> drivers/dma/ioat/dma_v3.c | 2 +-
> drivers/dma/tegra20-apb-dma.c | 8 +-
> drivers/gpio/gpio-mvebu.c | 6 -
> drivers/gpio/gpio-samsung.c | 14 +-
> drivers/gpu/drm/i915/i915_debugfs.c | 3 +
> drivers/gpu/drm/i915/i915_drv.h | 3 +
> drivers/gpu/drm/i915/i915_gem_execbuffer.c | 21 ++
> drivers/gpu/drm/i915/i915_irq.c | 11 +
> drivers/gpu/drm/i915/i915_reg.h | 2 +
> drivers/gpu/drm/i915/intel_dp.c | 47 +++-
> drivers/gpu/drm/i915/intel_pm.c | 17 +-
> drivers/gpu/drm/radeon/evergreen.c | 6 +
> drivers/gpu/drm/radeon/ni.c | 6 +
> drivers/gpu/drm/radeon/r600.c | 6 +
> drivers/gpu/drm/radeon/radeon.h | 3 +-
> drivers/gpu/drm/radeon/radeon_drv.c | 3 +-
> drivers/gpu/drm/radeon/radeon_object.c | 18 +-
> drivers/gpu/drm/radeon/radeon_ring.c | 2 +
> drivers/gpu/drm/radeon/radeon_semaphore.c | 4 +
> drivers/gpu/drm/radeon/reg_srcs/rv515 | 2 +
> drivers/gpu/drm/radeon/si.c | 6 +
> drivers/gpu/drm/ttm/ttm_bo.c | 1 +
> drivers/gpu/drm/ttm/ttm_bo_util.c | 11 +-
> drivers/hv/hv_balloon.c | 35 ++-
> drivers/i2c/busses/i2c-designware-core.c | 4 +
> drivers/i2c/busses/i2c-mxs.c | 6 +-
> drivers/i2c/busses/i2c-omap.c | 6 +-
> drivers/i2c/busses/i2c-sirf.c | 4 +
> drivers/i2c/muxes/i2c-mux-pinctrl.c | 2 +-
> drivers/idle/intel_idle.c | 3 +-
> drivers/media/i2c/m5mols/m5mols_core.c | 2 +-
> drivers/media/platform/omap3isp/ispvideo.c | 3 -
> drivers/media/platform/s5p-fimc/fimc-mdevice.c | 2 +-
> drivers/media/platform/s5p-mfc/s5p_mfc.c | 88 +++---
> drivers/media/usb/gspca/kinect.c | 1 +
> drivers/media/usb/gspca/sonixb.c | 13 +-
> drivers/media/usb/gspca/sonixj.c | 1 +
> drivers/media/usb/uvc/uvc_ctrl.c | 4 +-
> drivers/media/usb/uvc/uvc_v4l2.c | 6 +-
> drivers/media/v4l2-core/videobuf2-core.c | 4 +-
> drivers/misc/ti-st/st_kim.c | 37 ++-
> drivers/mmc/card/block.c | 30 +-
> drivers/mmc/card/queue.c | 32 ++-
> drivers/mmc/card/queue.h | 3 +
> drivers/mmc/core/bus.c | 1 +
> drivers/mmc/core/core.c | 121 +++++++-
> drivers/mmc/core/core.h | 1 +
> drivers/mmc/core/sdio.c | 33 ++-
> drivers/mmc/core/slot-gpio.c | 57 +++-
> drivers/mmc/host/Kconfig | 11 +
> drivers/mmc/host/Makefile | 1 +
> drivers/mmc/host/mvsdio.c | 131 +++++----
> drivers/mmc/host/sdhci-bcm2835.c | 227 +++++++++++++++
> drivers/mmc/host/sdhci-esdhc-imx.c | 59 +---
> drivers/mmc/host/sdhci-pxav3.c | 12 +-
> drivers/mmc/host/sdhci.c | 117 +++++---
> drivers/mmc/host/sh_mmcif.c | 280 +++++++++++--------
> drivers/mmc/host/tmio_mmc_pio.c | 8 -
> drivers/pci/hotplug/pciehp.h | 2 +-
> drivers/pci/hotplug/pciehp_core.c | 11 +-
> drivers/pci/hotplug/pciehp_ctrl.c | 8 +-
> drivers/pci/hotplug/pciehp_hpc.c | 11 +-
> drivers/pci/hotplug/shpchp.h | 3 +-
> drivers/pci/hotplug/shpchp_core.c | 36 +--
> drivers/pci/hotplug/shpchp_ctrl.c | 6 +-
> drivers/pci/pcie/Kconfig | 2 +-
> drivers/pci/pcie/aer/aerdrv_core.c | 1 +
> drivers/pci/pcie/aspm.c | 3 +
> drivers/rtc/Kconfig | 2 +-
> drivers/staging/iio/adc/mxs-lradc.c | 2 +-
> drivers/staging/iio/gyro/adis16080_core.c | 2 +-
> drivers/staging/sb105x/sb_pci_mp.c | 2 +-
> drivers/staging/vt6656/bssdb.h | 1 -
> drivers/staging/vt6656/int.h | 1 -
> drivers/staging/vt6656/iocmd.h | 33 ++-
> drivers/staging/vt6656/iowpa.h | 8 +-
> drivers/staging/wlan-ng/prism2mgmt.c | 2 +-
> drivers/tty/pty.c | 2 +
> drivers/tty/serial/8250/8250.c | 11 +
> drivers/tty/serial/8250/8250.h | 1 +
> drivers/tty/serial/8250/8250_dw.c | 2 +-
> drivers/tty/serial/8250/8250_pci.c | 42 ++-
> drivers/tty/serial/ifx6x60.c | 4 +-
> drivers/tty/serial/mxs-auart.c | 6 +-
> drivers/tty/serial/samsung.c | 1 -
> drivers/tty/serial/vt8500_serial.c | 2 +-
> drivers/usb/dwc3/gadget.c | 1 +
> drivers/usb/gadget/f_fs.c | 6 +-
> drivers/usb/gadget/fsl_mxc_udc.c | 40 ++-
> drivers/usb/gadget/fsl_udc_core.c | 42 +--
> drivers/usb/gadget/fsl_usb2_udc.h | 5 +-
> drivers/usb/host/Kconfig | 2 +-
> drivers/usb/host/Makefile | 1 +
> drivers/usb/host/ehci-hcd.c | 12 +-
> drivers/usb/host/ehci-mxc.c | 120 ++++----
> drivers/usb/host/ehci.h | 7 +
> drivers/usb/host/uhci-hcd.c | 15 +-
> drivers/usb/musb/cppi_dma.c | 4 +-
> drivers/usb/serial/io_ti.c | 3 +
> drivers/usb/serial/option.c | 9 +-
> drivers/vfio/pci/vfio_pci_rdwr.c | 4 +-
> drivers/xen/cpu_hotplug.c | 4 +-
> drivers/xen/gntdev.c | 130 ++++++---
> drivers/xen/grant-table.c | 48 ++--
> drivers/xen/privcmd.c | 89 +++---
> drivers/xen/xen-pciback/pciback.h | 2 +-
> fs/Kconfig | 10 -
> fs/btrfs/extent-tree.c | 6 +-
> fs/btrfs/extent_map.c | 13 +-
> fs/btrfs/extent_map.h | 1 +
> fs/btrfs/file-item.c | 4 +-
> fs/btrfs/file.c | 10 +-
> fs/btrfs/free-space-cache.c | 20 +-
> fs/btrfs/inode.c | 137 ++++++---
> fs/btrfs/ioctl.c | 129 ++++++---
> fs/btrfs/qgroup.c | 20 +-
> fs/btrfs/send.c | 4 +-
> fs/btrfs/super.c | 2 +-
> fs/btrfs/transaction.c | 19 +-
> fs/btrfs/tree-log.c | 10 +-
> fs/btrfs/volumes.c | 23 +-
> fs/cifs/cifs_dfs_ref.c | 2 +
> fs/cifs/connect.c | 2 +-
> fs/f2fs/acl.c | 13 +-
> fs/f2fs/checkpoint.c | 3 +-
> fs/f2fs/data.c | 17 +-
> fs/f2fs/debug.c | 50 ++--
> fs/f2fs/dir.c | 2 +-
> fs/f2fs/f2fs.h | 18 +-
> fs/f2fs/file.c | 16 +-
> fs/f2fs/gc.c | 68 ++---
> fs/f2fs/inode.c | 3 +
> fs/f2fs/node.c | 19 +-
> fs/f2fs/recovery.c | 10 +-
> fs/f2fs/segment.c | 2 +-
> fs/f2fs/super.c | 97 +++++--
> fs/f2fs/xattr.c | 2 +
> fs/fuse/Kconfig | 16 +-
> fs/fuse/cuse.c | 36 ++-
> fs/fuse/dev.c | 5 -
> fs/fuse/file.c | 5 +-
> include/asm-generic/dma-mapping-broken.h | 16 ++
> include/asm-generic/pgtable.h | 6 +-
> include/asm-generic/syscalls.h | 2 +
> include/linux/ata.h | 8 +-
> include/linux/libata.h | 4 +-
> include/linux/mmc/card.h | 12 +
> include/linux/mmc/core.h | 3 +-
> include/linux/mmc/host.h | 25 ++
> include/linux/module.h | 10 +-
> include/linux/ptrace.h | 1 -
> include/linux/sched.h | 11 +-
> include/uapi/linux/serial_core.h | 3 +-
> init/do_mounts_initrd.c | 4 +
> init/main.c | 4 +-
> kernel/async.c | 27 +-
> kernel/compat.c | 23 +-
> kernel/debug/kdb/kdb_main.c | 2 +
> kernel/fork.c | 6 +-
> kernel/module.c | 154 +++++++---
> kernel/ptrace.c | 74 ++++-
> kernel/sched/core.c | 3 +-
> kernel/signal.c | 24 +-
> kernel/trace/ftrace.c | 2 +-
> lib/bug.c | 1 +
> security/device_cgroup.c | 2 +
> security/integrity/evm/evm_crypto.c | 4 +-
> sound/pci/hda/hda_codec.c | 5 +-
> sound/pci/hda/patch_conexant.c | 9 +
> sound/pci/hda/patch_realtek.c | 2 +
> tools/perf/MANIFEST | 10 +
> tools/perf/Makefile | 2 +-
> 274 files changed, 3501 insertions(+), 1617 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/mmc/brcm,bcm2835-sdhci.txt
> create mode 100644 Documentation/devicetree/bindings/mmc/orion-sdio.txt
> create mode 100644 arch/arm/boot/dts/armada-370-rd.dts
> create mode 100644 arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
> create mode 100644 arch/arm/mach-dove/board-dt.c
> create mode 100644 arch/arm/mach-kirkwood/board-guruplug.c
> rename arch/arm/mach-kirkwood/cpuidle.c => drivers/cpuidle/cpuidle-kirkwood.c (61%)
> create mode 100644 drivers/mmc/host/sdhci-bcm2835.c
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply
* [PATCH 1/2] mtd: gpmi: set the Golois Field bit for mx6q's BCH
From: Artem Bityutskiy @ 2013-02-04 8:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359093848-22301-1-git-send-email-b32955@freescale.com>
On Fri, 2013-01-25 at 14:04 +0800, Huang Shijie wrote:
> +#define BF_BCH_FLASH0LAYOUT0_GF(v, x) \
> + ((GPMI_IS_MX6Q(x) && ((v) == 14)) \
> + ? (((1) << MX6Q_BP_BCH_FLASH0LAYOUT0_GF_13_14) \
> + & MX6Q_BM_BCH_FLASH0LAYOUT0_GF_13_14) \
> + : 0 \
> + )
Did you consider using static inline functions instead of macro
definitions? The added value would be at least type-checking. You would
also probably use names better than "v" and "x", you could even have
commentaries. Please, consider doing this.
Anyway, pushed to l2-mtd.git, thanks!
--
Best Regards,
Artem Bityutskiy
-------------- next part --------------
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^ permalink raw reply
* [PATCH] ARM: SAMSUNG: dma: Remove unnecessary code
From: Padmavathi Venna @ 2013-02-04 8:47 UTC (permalink / raw)
To: linux-arm-kernel
This patch removes the usage of DMACH_DT_PROP and dt_dmach_prop
from dma code as the new generic dma dt binding support has been
added.
Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
---
The functionality of this patch is dependent on following patches in the link.
http://www.mail-archive.com/linux-samsung-soc at vger.kernel.org/msg15402.html
This patch is made based on Mark Brown next branch.
arch/arm/mach-s3c24xx/include/mach/dma.h | 1 -
arch/arm/mach-s3c64xx/include/mach/dma.h | 1 -
arch/arm/plat-samsung/dma-ops.c | 10 +---------
arch/arm/plat-samsung/include/plat/dma-ops.h | 1 -
arch/arm/plat-samsung/include/plat/dma-pl330.h | 1 -
5 files changed, 1 insertions(+), 13 deletions(-)
diff --git a/arch/arm/mach-s3c24xx/include/mach/dma.h b/arch/arm/mach-s3c24xx/include/mach/dma.h
index 6b72d5a..b55da1d 100644
--- a/arch/arm/mach-s3c24xx/include/mach/dma.h
+++ b/arch/arm/mach-s3c24xx/include/mach/dma.h
@@ -24,7 +24,6 @@
*/
enum dma_ch {
- DMACH_DT_PROP = -1, /* not yet supported, do not use */
DMACH_XD0 = 0,
DMACH_XD1,
DMACH_SDI,
diff --git a/arch/arm/mach-s3c64xx/include/mach/dma.h b/arch/arm/mach-s3c64xx/include/mach/dma.h
index 57b1ff4..fe1a98c 100644
--- a/arch/arm/mach-s3c64xx/include/mach/dma.h
+++ b/arch/arm/mach-s3c64xx/include/mach/dma.h
@@ -21,7 +21,6 @@
*/
enum dma_ch {
/* DMA0/SDMA0 */
- DMACH_DT_PROP = -1, /* not yet supported, do not use */
DMACH_UART0 = 0,
DMACH_UART0_SRC2,
DMACH_UART1,
diff --git a/arch/arm/plat-samsung/dma-ops.c b/arch/arm/plat-samsung/dma-ops.c
index 71d58dd..ec0d731 100644
--- a/arch/arm/plat-samsung/dma-ops.c
+++ b/arch/arm/plat-samsung/dma-ops.c
@@ -23,23 +23,15 @@ static unsigned samsung_dmadev_request(enum dma_ch dma_ch,
struct device *dev, char *ch_name)
{
dma_cap_mask_t mask;
- void *filter_param;
dma_cap_zero(mask);
dma_cap_set(param->cap, mask);
- /*
- * If a dma channel property of a device node from device tree is
- * specified, use that as the fliter parameter.
- */
- filter_param = (dma_ch == DMACH_DT_PROP) ?
- (void *)param->dt_dmach_prop : (void *)dma_ch;
-
if (dev->of_node)
return (unsigned)dma_request_slave_channel(dev, ch_name);
else
return (unsigned)dma_request_channel(mask, pl330_filter,
- filter_param);
+ (void *)dma_ch);
}
static int samsung_dmadev_release(unsigned ch, void *param)
diff --git a/arch/arm/plat-samsung/include/plat/dma-ops.h b/arch/arm/plat-samsung/include/plat/dma-ops.h
index 1141782..ce6d763 100644
--- a/arch/arm/plat-samsung/include/plat/dma-ops.h
+++ b/arch/arm/plat-samsung/include/plat/dma-ops.h
@@ -18,7 +18,6 @@
struct samsung_dma_req {
enum dma_transaction_type cap;
- struct property *dt_dmach_prop;
struct s3c2410_dma_client *client;
};
diff --git a/arch/arm/plat-samsung/include/plat/dma-pl330.h b/arch/arm/plat-samsung/include/plat/dma-pl330.h
index d384a80..abe07fa 100644
--- a/arch/arm/plat-samsung/include/plat/dma-pl330.h
+++ b/arch/arm/plat-samsung/include/plat/dma-pl330.h
@@ -21,7 +21,6 @@
* use these just as IDs.
*/
enum dma_ch {
- DMACH_DT_PROP = -1,
DMACH_UART0_RX = 0,
DMACH_UART0_TX,
DMACH_UART1_RX,
--
1.7.4.4
^ permalink raw reply related
* [PATCHv2 0/2] add omap mcspi device tree data
From: Sourav Poddar @ 2013-02-04 8:51 UTC (permalink / raw)
To: linux-arm-kernel
Patch series adds omap5 evm mcspi nodes and pinctrl
data in omap5.dtsi and omap5-evm.dts files.
Felipe Balbi (1):
arm: dts: omap5: add SPI devices to OMAP5 DeviceTree file
Sourav Poddar (1):
arm: dts: omap5-evm: Add mcspi data
arch/arm/boot/dts/omap5-evm.dts | 46 +++++++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/omap5.dtsi | 40 +++++++++++++++++++++++++++++++++
2 files changed, 86 insertions(+), 0 deletions(-)
^ permalink raw reply
* [PATCHv2 1/2] arm: dts: omap5: add SPI devices to OMAP5 DeviceTree file
From: Sourav Poddar @ 2013-02-04 8:52 UTC (permalink / raw)
To: linux-arm-kernel
From: Felipe Balbi <balbi@ti.com>
Add all 4 mcspi instances to omap5.dtsi file.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
---
arch/arm/boot/dts/omap5.dtsi | 40 ++++++++++++++++++++++++++++++++++++++++
1 files changed, 40 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 790bb2a..9e182a9 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -241,6 +241,46 @@
ti,hwmods = "i2c5";
};
+ mcspi1: spi at 48098000 {
+ compatible = "ti,omap4-mcspi";
+ reg = <0x48098000 0x200>;
+ interrupts = <0 65 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "mcspi1";
+ ti,spi-num-cs = <4>;
+ };
+
+ mcspi2: spi at 4809a000 {
+ compatible = "ti,omap4-mcspi";
+ reg = <0x4809a000 0x200>;
+ interrupts = <0 66 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "mcspi2";
+ ti,spi-num-cs = <2>;
+ };
+
+ mcspi3: spi at 480b8000 {
+ compatible = "ti,omap4-mcspi";
+ reg = <0x480b8000 0x200>;
+ interrupts = <0 91 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "mcspi3";
+ ti,spi-num-cs = <2>;
+ };
+
+ mcspi4: spi at 480ba000 {
+ compatible = "ti,omap4-mcspi";
+ reg = <0x480ba000 0x200>;
+ interrupts = <0 48 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "mcspi4";
+ ti,spi-num-cs = <1>;
+ };
+
uart1: serial at 4806a000 {
compatible = "ti,omap4-uart";
reg = <0x4806a000 0x100>;
--
1.7.1
^ permalink raw reply related
* [PATCHv2 2/2] arm: dts: omap5-evm: Add mcspi data
From: Sourav Poddar @ 2013-02-04 8:52 UTC (permalink / raw)
To: linux-arm-kernel
Add mcspi node and pinmux data for omap5 mcspi controller.
Tested on omap5430 evm with 3.8-rc4 custom kernel.
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
---
v1->v2
Pinctrl nodes were pointing to a different parent.
Fixing the same.
arch/arm/boot/dts/omap5-evm.dts | 46 +++++++++++++++++++++++++++++++++++++++
1 files changed, 46 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts
index 8722c15..3625c5c 100644
--- a/arch/arm/boot/dts/omap5-evm.dts
+++ b/arch/arm/boot/dts/omap5-evm.dts
@@ -80,6 +80,33 @@
0x15a 0x100 /* abemcbsp2_clkx.abemcbsp2_clkx INPUT | MODE0 */
>;
};
+
+ mcspi2_pins: pinmux_mcspi2_pins {
+ pinctrl-single,pins = <
+ 0xbc 0x100
+ 0xbe 0x100
+ 0xc0 0x118
+ 0xc2 0x0
+ >;
+ };
+
+ mcspi3_pins: pinmux_mcspi3_pins {
+ pinctrl-single,pins = <
+ 0x78 0x101
+ 0x7a 0x101
+ 0x7c 0x101
+ 0x7e 0x101
+ >;
+ };
+
+ mcspi4_pins: pinmux_mcspi4_pins {
+ pinctrl-single,pins = <
+ 0x164 0x101
+ 0x168 0x101
+ 0x16a 0x101
+ 0x16c 0x101
+ >;
+ };
};
&mmc1 {
@@ -151,3 +178,22 @@
cs1-used;
device-handle = <&samsung_K3PE0E000B>;
};
+
+&mcspi1 {
+
+};
+
+&mcspi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcspi2_pins>;
+};
+
+&mcspi3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcspi3_pins>;
+};
+
+&mcspi4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcspi4_pins>;
+};
--
1.7.1
^ permalink raw reply related
* [PATCH v3 3/3] leds: leds-pwm: Defer led_pwm_set() if PWM can sleep
From: Florian Vaussard @ 2013-02-04 8:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20130130081728.GC13568@avionic-0098.mockup.avionic-design.de>
On 01/30/2013 09:17 AM, Thierry Reding wrote:
> On Mon, Jan 28, 2013 at 03:00:59PM +0100, Florian Vaussard wrote:
>> Call to led_pwm_set() can happen inside atomic context, like triggers.
>> If the PWM call can sleep, defer using a worker.
>>
>> Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
>> Signed-off-by: Florian Vaussard <florian.vaussard@epfl.ch>
>> ---
>> drivers/leds/leds-pwm.c | 50 +++++++++++++++++++++++++++++++++++++++-------
>> 1 files changed, 42 insertions(+), 8 deletions(-)
>
> Bryan, I assume that you'll be taking this? It doesn't apply cleanly to
> my tree, probably because of Peter's recent changes that you took
> through your tree and Florian based his patches on top of that. The
> conflict resolution should be trivial, though.
>
Thank you Thierry. Indeed, this patchset was based on linux-leds due to the
dependancy with Peter's patches.
Bryan, can you take this patch?
Regards,
Florian
^ permalink raw reply
* [PATCH] ARM:omap2: using strlcpy instead of strncpy
From: Peter Ujfalusi @ 2013-02-04 8:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <51090829.1010109@asianux.com>
On 01/30/2013 12:46 PM, Chen Gang wrote:
>
> the fields must be null-terminated:
> the caller may use it as null-terminted string, next.
>
> Signed-off-by: Chen Gang <gang.chen@asianux.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
> ---
> arch/arm/mach-omap2/twl-common.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c
> index e49b40b..6a7aec6 100644
> --- a/arch/arm/mach-omap2/twl-common.c
> +++ b/arch/arm/mach-omap2/twl-common.c
> @@ -23,6 +23,7 @@
> #include <linux/i2c.h>
> #include <linux/i2c/twl.h>
> #include <linux/gpio.h>
> +#include <linux/string.h>
> #include <linux/regulator/machine.h>
> #include <linux/regulator/fixed.h>
>
> @@ -56,7 +57,7 @@ void __init omap_pmic_init(int bus, u32 clkrate,
> struct twl4030_platform_data *pmic_data)
> {
> omap_mux_init_signal("sys_nirq", OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE);
> - strncpy(pmic_i2c_board_info.type, pmic_type,
> + strlcpy(pmic_i2c_board_info.type, pmic_type,
> sizeof(pmic_i2c_board_info.type));
> pmic_i2c_board_info.irq = pmic_irq;
> pmic_i2c_board_info.platform_data = pmic_data;
>
--
P?ter
^ permalink raw reply
* [PATCHv2 0/2] add omap mcspi device tree data
From: Santosh Shilimkar @ 2013-02-04 8:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1359967907-26645-1-git-send-email-sourav.poddar@ti.com>
On Monday 04 February 2013 02:21 PM, Sourav Poddar wrote:
> Patch series adds omap5 evm mcspi nodes and pinctrl
> data in omap5.dtsi and omap5-evm.dts files.
>
> Felipe Balbi (1):
> arm: dts: omap5: add SPI devices to OMAP5 DeviceTree file
>
> Sourav Poddar (1):
> arm: dts: omap5-evm: Add mcspi data
>
> arch/arm/boot/dts/omap5-evm.dts | 46 +++++++++++++++++++++++++++++++++++++++
> arch/arm/boot/dts/omap5.dtsi | 40 +++++++++++++++++++++++++++++++++
> 2 files changed, 86 insertions(+), 0 deletions(-)
>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
^ permalink raw reply
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